include/asm-powerpc/bitops.h

   1 /*
   2  * PowerPC atomic bit operations.
   3  *
   4  * Merged version by David Gibson <david@gibson.dropbear.id.au>.
   5  * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
   6  * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
   7  * originally took it from the ppc32 code.
   8  *
   9  * Within a word, bits are numbered LSB first.  Lot's of places make
  10  * this assumption by directly testing bits with (val & (1<<nr)).
  11  * This can cause confusion for large (> 1 word) bitmaps on a
  12  * big-endian system because, unlike little endian, the number of each
  13  * bit depends on the word size.
  14  *
  15  * The bitop functions are defined to work on unsigned longs, so for a
  16  * ppc64 system the bits end up numbered:
  17  *   |63..............0|127............64|191...........128|255...........196|
  18  * and on ppc32:
  19  *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
  20  *
  21  * There are a few little-endian macros used mostly for filesystem
  22  * bitmaps, these work on similar bit arrays layouts, but
  23  * byte-oriented:
  24  *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
  25  *
  26  * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
  27  * number field needs to be reversed compared to the big-endian bit
  28  * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
  29  *
  30  * This program is free software; you can redistribute it and/or
  31  * modify it under the terms of the GNU General Public License
  32  * as published by the Free Software Foundation; either version
  33  * 2 of the License, or (at your option) any later version.
  34  */
  35
  36 #ifndef _ASM_POWERPC_BITOPS_H
  37 #define _ASM_POWERPC_BITOPS_H
  38
  39 #ifdef __KERNEL__
  40
  41 #include <linux/compiler.h>
  42 #include <asm/asm-compat.h>
  43 #include <asm/synch.h>
  44
  45 /*
  46  * clear_bit doesn't imply a memory barrier
  47  */
  48 #define smp_mb__before_clear_bit()      smp_mb()
  49 #define smp_mb__after_clear_bit()       smp_mb()
  50
  51 #define BITOP_MASK(nr)          (1UL << ((nr) % BITS_PER_LONG))
  52 #define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
  53 #define BITOP_LE_SWIZZLE        ((BITS_PER_LONG-1) & ~0x7)
  54
  55 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
  56 {
  57         unsigned long old;
  58         unsigned long mask = BITOP_MASK(nr);
  59         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
  60
  61         __asm__ __volatile__(
  62 "1:"    PPC_LLARX "%0,0,%3      # set_bit\n"
  63         "or     %0,%0,%2\n"
  64         PPC405_ERR77(0,%3)
  65         PPC_STLCX "%0,0,%3\n"
  66         "bne-   1b"
  67         : "=&r" (old), "+m" (*p)
  68         : "r" (mask), "r" (p)
  69         : "cc" );
  70 }
  71
  72 static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
  73 {
  74         unsigned long old;
  75         unsigned long mask = BITOP_MASK(nr);
  76         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
  77
  78         __asm__ __volatile__(
  79 "1:"    PPC_LLARX "%0,0,%3      # clear_bit\n"
  80         "andc   %0,%0,%2\n"
  81         PPC405_ERR77(0,%3)
  82         PPC_STLCX "%0,0,%3\n"
  83         "bne-   1b"
  84         : "=&r" (old), "+m" (*p)
  85         : "r" (mask), "r" (p)
  86         : "cc" );
  87 }
  88
  89 static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
  90 {
  91         unsigned long old;
  92         unsigned long mask = BITOP_MASK(nr);
  93         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
  94
  95         __asm__ __volatile__(
  96         LWSYNC_ON_SMP
  97 "1:"    PPC_LLARX "%0,0,%3      # clear_bit_unlock\n"
  98         "andc   %0,%0,%2\n"
  99         PPC405_ERR77(0,%3)
 100         PPC_STLCX "%0,0,%3\n"
 101         "bne-   1b"
 102         : "=&r" (old), "+m" (*p)
 103         : "r" (mask), "r" (p)
 104         : "cc", "memory");
 105 }
 106
 107 static __inline__ void change_bit(int nr, volatile unsigned long *addr)
 108 {
 109         unsigned long old;
 110         unsigned long mask = BITOP_MASK(nr);
 111         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
 112
 113         __asm__ __volatile__(
 114 "1:"    PPC_LLARX "%0,0,%3      # change_bit\n"
 115         "xor    %0,%0,%2\n"
 116         PPC405_ERR77(0,%3)
 117         PPC_STLCX "%0,0,%3\n"
 118         "bne-   1b"
 119         : "=&r" (old), "+m" (*p)
 120         : "r" (mask), "r" (p)
 121         : "cc" );
 122 }
 123
 124 static __inline__ int test_and_set_bit(unsigned long nr,
 125                                        volatile unsigned long *addr)
 126 {
 127         unsigned long old, t;
 128         unsigned long mask = BITOP_MASK(nr);
 129         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
 130
 131         __asm__ __volatile__(
 132         LWSYNC_ON_SMP
 133 "1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit\n"
 134         "or     %1,%0,%2 \n"
 135         PPC405_ERR77(0,%3)
 136         PPC_STLCX "%1,0,%3 \n"
 137         "bne-   1b"
 138         ISYNC_ON_SMP
 139         : "=&r" (old), "=&r" (t)
 140         : "r" (mask), "r" (p)
 141         : "cc", "memory");
 142
 143         return (old & mask) != 0;
 144 }
 145
 146 static __inline__ int test_and_set_bit_lock(unsigned long nr,
 147                                        volatile unsigned long *addr)
 148 {
 149         unsigned long old, t;
 150         unsigned long mask = BITOP_MASK(nr);
 151         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
 152
 153         __asm__ __volatile__(
 154 "1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit_lock\n"
 155         "or     %1,%0,%2 \n"
 156         PPC405_ERR77(0,%3)
 157         PPC_STLCX "%1,0,%3 \n"
 158         "bne-   1b"
 159         ISYNC_ON_SMP
 160         : "=&r" (old), "=&r" (t)
 161         : "r" (mask), "r" (p)
 162         : "cc", "memory");
 163
 164         return (old & mask) != 0;
 165 }
 166
 167 static __inline__ int test_and_clear_bit(unsigned long nr,
 168                                          volatile unsigned long *addr)
 169 {
 170         unsigned long old, t;
 171         unsigned long mask = BITOP_MASK(nr);
 172         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
 173
 174         __asm__ __volatile__(
 175         LWSYNC_ON_SMP
 176 "1:"    PPC_LLARX "%0,0,%3              # test_and_clear_bit\n"
 177         "andc   %1,%0,%2 \n"
 178         PPC405_ERR77(0,%3)
 179         PPC_STLCX "%1,0,%3 \n"
 180         "bne-   1b"
 181         ISYNC_ON_SMP
 182         : "=&r" (old), "=&r" (t)
 183         : "r" (mask), "r" (p)
 184         : "cc", "memory");
 185
 186         return (old & mask) != 0;
 187 }
 188
 189 static __inline__ int test_and_change_bit(unsigned long nr,
 190                                           volatile unsigned long *addr)
 191 {
 192         unsigned long old, t;
 193         unsigned long mask = BITOP_MASK(nr);
 194         unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
 195
 196         __asm__ __volatile__(
 197         LWSYNC_ON_SMP
 198 "1:"    PPC_LLARX "%0,0,%3              # test_and_change_bit\n"
 199         "xor    %1,%0,%2 \n"
 200         PPC405_ERR77(0,%3)
 201         PPC_STLCX "%1,0,%3 \n"
 202         "bne-   1b"
 203         ISYNC_ON_SMP
 204         : "=&r" (old), "=&r" (t)
 205         : "r" (mask), "r" (p)
 206         : "cc", "memory");
 207
 208         return (old & mask) != 0;
 209 }
 210
 211 static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
 212 {
 213         unsigned long old;
 214
 215         __asm__ __volatile__(
 216 "1:"    PPC_LLARX "%0,0,%3         # set_bits\n"
 217         "or     %0,%0,%2\n"
 218         PPC_STLCX "%0,0,%3\n"
 219         "bne-   1b"
 220         : "=&r" (old), "+m" (*addr)
 221         : "r" (mask), "r" (addr)
 222         : "cc");
 223 }
 224
 225 #include <asm-generic/bitops/non-atomic.h>
 226
 227 static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
 228 {
 229         __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory");
 230         __clear_bit(nr, addr);
 231 }
 232
 233 /*
 234  * Return the zero-based bit position (LE, not IBM bit numbering) of
 235  * the most significant 1-bit in a double word.
 236  */
 237 static __inline__ __attribute__((const))
 238 int __ilog2(unsigned long x)
 239 {
 240         int lz;
 241
 242         asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
 243         return BITS_PER_LONG - 1 - lz;
 244 }
 245
 246 static inline __attribute__((const))
 247 int __ilog2_u32(u32 n)
 248 {
 249         int bit;
 250         asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
 251         return 31 - bit;
 252 }
 253
 254 #ifdef __powerpc64__
 255 static inline __attribute__((const))
 256 int __ilog2_u64(u64 n)
 257 {
 258         int bit;
 259         asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
 260         return 63 - bit;
 261 }
 262 #endif
 263
 264 /*
 265  * Determines the bit position of the least significant 0 bit in the
 266  * specified double word. The returned bit position will be
 267  * zero-based, starting from the right side (63/31 - 0).
 268  */
 269 static __inline__ unsigned long ffz(unsigned long x)
 270 {
 271         /* no zero exists anywhere in the 8 byte area. */
 272         if ((x = ~x) == 0)
 273                 return BITS_PER_LONG;
 274
 275         /*
 276          * Calculate the bit position of the least signficant '1' bit in x
 277          * (since x has been changed this will actually be the least signficant
 278          * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
 279          * is the least significant * (RIGHT-most) 1-bit of the value in x.
 280          */
 281         return __ilog2(x & -x);
 282 }
 283
 284 static __inline__ int __ffs(unsigned long x)
 285 {
 286         return __ilog2(x & -x);
 287 }
 288
 289 /*
 290  * ffs: find first bit set. This is defined the same way as
 291  * the libc and compiler builtin ffs routines, therefore
 292  * differs in spirit from the above ffz (man ffs).
 293  */
 294 static __inline__ int ffs(int x)
 295 {
 296         unsigned long i = (unsigned long)x;
 297         return __ilog2(i & -i) + 1;
 298 }
 299
 300 /*
 301  * fls: find last (most-significant) bit set.
 302  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
 303  */
 304 static __inline__ int fls(unsigned int x)
 305 {
 306         int lz;
 307
 308         asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
 309         return 32 - lz;
 310 }
 311 #include <asm-generic/bitops/fls64.h>
 312
 313 #include <asm-generic/bitops/hweight.h>
 314
 315 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
 316 unsigned long find_next_zero_bit(const unsigned long *addr,
 317                                  unsigned long size, unsigned long offset);
 318 /**
 319  * find_first_bit - find the first set bit in a memory region
 320  * @addr: The address to start the search at
 321  * @size: The maximum size to search
 322  *
 323  * Returns the bit-number of the first set bit, not the number of the byte
 324  * containing a bit.
 325  */
 326 #define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
 327 unsigned long find_next_bit(const unsigned long *addr,
 328                             unsigned long size, unsigned long offset);
 329
 330 /* Little-endian versions */
 331
 332 static __inline__ int test_le_bit(unsigned long nr,
 333                                   __const__ unsigned long *addr)
 334 {
 335         __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
 336         return (tmp[nr >> 3] >> (nr & 7)) & 1;
 337 }
 338
 339 #define __set_le_bit(nr, addr) \
 340         __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 341 #define __clear_le_bit(nr, addr) \
 342         __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 343
 344 #define test_and_set_le_bit(nr, addr) \
 345         test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 346 #define test_and_clear_le_bit(nr, addr) \
 347         test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 348
 349 #define __test_and_set_le_bit(nr, addr) \
 350         __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 351 #define __test_and_clear_le_bit(nr, addr) \
 352         __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 353
 354 #define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
 355 unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
 356                                     unsigned long size, unsigned long offset);
 357
 358 /* Bitmap functions for the ext2 filesystem */
 359
 360 #define ext2_set_bit(nr,addr) \
 361         __test_and_set_le_bit((nr), (unsigned long*)addr)
 362 #define ext2_clear_bit(nr, addr) \
 363         __test_and_clear_le_bit((nr), (unsigned long*)addr)
 364
 365 #define ext2_set_bit_atomic(lock, nr, addr) \
 366         test_and_set_le_bit((nr), (unsigned long*)addr)
 367 #define ext2_clear_bit_atomic(lock, nr, addr) \
 368         test_and_clear_le_bit((nr), (unsigned long*)addr)
 369
 370 #define ext2_test_bit(nr, addr)      test_le_bit((nr),(unsigned long*)addr)
 371
 372 #define ext2_find_first_zero_bit(addr, size) \
 373         find_first_zero_le_bit((unsigned long*)addr, size)
 374 #define ext2_find_next_zero_bit(addr, size, off) \
 375         generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
 376
 377 /* Bitmap functions for the minix filesystem.  */
 378
 379 #define minix_test_and_set_bit(nr,addr) \
 380         __test_and_set_le_bit(nr, (unsigned long *)addr)
 381 #define minix_set_bit(nr,addr) \
 382         __set_le_bit(nr, (unsigned long *)addr)
 383 #define minix_test_and_clear_bit(nr,addr) \
 384         __test_and_clear_le_bit(nr, (unsigned long *)addr)
 385 #define minix_test_bit(nr,addr) \
 386         test_le_bit(nr, (unsigned long *)addr)
 387
 388 #define minix_find_first_zero_bit(addr,size) \
 389         find_first_zero_le_bit((unsigned long *)addr, size)
 390
 391 #include <asm-generic/bitops/sched.h>
 392
 393 #endif /* __KERNEL__ */
 394
 395 #endif /* _ASM_POWERPC_BITOPS_H */