include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <asm/hazards.h>
  18
  19 /*
  20  * The following macros are especially useful for __asm__
  21  * inline assembler.
  22  */
  23 #ifndef __STR
  24 #define __STR(x) #x
  25 #endif
  26 #ifndef STR
  27 #define STR(x) __STR(x)
  28 #endif
  29
  30 /*
  31  *  Configure language
  32  */
  33 #ifdef __ASSEMBLY__
  34 #define _ULCAST_
  35 #else
  36 #define _ULCAST_ (unsigned long)
  37 #endif
  38
  39 /*
  40  * Coprocessor 0 register names
  41  */
  42 #define CP0_INDEX $0
  43 #define CP0_RANDOM $1
  44 #define CP0_ENTRYLO0 $2
  45 #define CP0_ENTRYLO1 $3
  46 #define CP0_CONF $3
  47 #define CP0_CONTEXT $4
  48 #define CP0_PAGEMASK $5
  49 #define CP0_WIRED $6
  50 #define CP0_INFO $7
  51 #define CP0_BADVADDR $8
  52 #define CP0_COUNT $9
  53 #define CP0_ENTRYHI $10
  54 #define CP0_COMPARE $11
  55 #define CP0_STATUS $12
  56 #define CP0_CAUSE $13
  57 #define CP0_EPC $14
  58 #define CP0_PRID $15
  59 #define CP0_CONFIG $16
  60 #define CP0_LLADDR $17
  61 #define CP0_WATCHLO $18
  62 #define CP0_WATCHHI $19
  63 #define CP0_XCONTEXT $20
  64 #define CP0_FRAMEMASK $21
  65 #define CP0_DIAGNOSTIC $22
  66 #define CP0_DEBUG $23
  67 #define CP0_DEPC $24
  68 #define CP0_PERFORMANCE $25
  69 #define CP0_ECC $26
  70 #define CP0_CACHEERR $27
  71 #define CP0_TAGLO $28
  72 #define CP0_TAGHI $29
  73 #define CP0_ERROREPC $30
  74 #define CP0_DESAVE $31
  75
  76 /*
  77  * R4640/R4650 cp0 register names.  These registers are listed
  78  * here only for completeness; without MMU these CPUs are not useable
  79  * by Linux.  A future ELKS port might take make Linux run on them
  80  * though ...
  81  */
  82 #define CP0_IBASE $0
  83 #define CP0_IBOUND $1
  84 #define CP0_DBASE $2
  85 #define CP0_DBOUND $3
  86 #define CP0_CALG $17
  87 #define CP0_IWATCH $18
  88 #define CP0_DWATCH $19
  89
  90 /*
  91  * Coprocessor 0 Set 1 register names
  92  */
  93 #define CP0_S1_DERRADDR0  $26
  94 #define CP0_S1_DERRADDR1  $27
  95 #define CP0_S1_INTCONTROL $20
  96
  97 /*
  98  * Coprocessor 0 Set 2 register names
  99  */
 100 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 101
 102 /*
 103  * Coprocessor 0 Set 3 register names
 104  */
 105 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 106
 107 /*
 108  *  TX39 Series
 109  */
 110 #define CP0_TX39_CACHE  $7
 111
 112 /*
 113  * Coprocessor 1 (FPU) register names
 114  */
 115 #define CP1_REVISION   $0
 116 #define CP1_STATUS     $31
 117
 118 /*
 119  * FPU Status Register Values
 120  */
 121 /*
 122  * Status Register Values
 123  */
 124
 125 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 126 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 127 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 128 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 129 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 130 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 131 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 132 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 133 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 134 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 135
 136 /*
 137  * X the exception cause indicator
 138  * E the exception enable
 139  * S the sticky/flag bit
 140 */
 141 #define FPU_CSR_ALL_X   0x0003f000
 142 #define FPU_CSR_UNI_X   0x00020000
 143 #define FPU_CSR_INV_X   0x00010000
 144 #define FPU_CSR_DIV_X   0x00008000
 145 #define FPU_CSR_OVF_X   0x00004000
 146 #define FPU_CSR_UDF_X   0x00002000
 147 #define FPU_CSR_INE_X   0x00001000
 148
 149 #define FPU_CSR_ALL_E   0x00000f80
 150 #define FPU_CSR_INV_E   0x00000800
 151 #define FPU_CSR_DIV_E   0x00000400
 152 #define FPU_CSR_OVF_E   0x00000200
 153 #define FPU_CSR_UDF_E   0x00000100
 154 #define FPU_CSR_INE_E   0x00000080
 155
 156 #define FPU_CSR_ALL_S   0x0000007c
 157 #define FPU_CSR_INV_S   0x00000040
 158 #define FPU_CSR_DIV_S   0x00000020
 159 #define FPU_CSR_OVF_S   0x00000010
 160 #define FPU_CSR_UDF_S   0x00000008
 161 #define FPU_CSR_INE_S   0x00000004
 162
 163 /* rounding mode */
 164 #define FPU_CSR_RN      0x0     /* nearest */
 165 #define FPU_CSR_RZ      0x1     /* towards zero */
 166 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 167 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 168
 169
 170 /*
 171  * Values for PageMask register
 172  */
 173 #ifdef CONFIG_CPU_VR41XX
 174
 175 /* Why doesn't stupidity hurt ... */
 176
 177 #define PM_1K           0x00000000
 178 #define PM_4K           0x00001800
 179 #define PM_16K          0x00007800
 180 #define PM_64K          0x0001f800
 181 #define PM_256K         0x0007f800
 182
 183 #else
 184
 185 #define PM_4K           0x00000000
 186 #define PM_16K          0x00006000
 187 #define PM_64K          0x0001e000
 188 #define PM_256K         0x0007e000
 189 #define PM_1M           0x001fe000
 190 #define PM_4M           0x007fe000
 191 #define PM_16M          0x01ffe000
 192 #define PM_64M          0x07ffe000
 193 #define PM_256M         0x1fffe000
 194
 195 #endif
 196
 197 /*
 198  * Default page size for a given kernel configuration
 199  */
 200 #ifdef CONFIG_PAGE_SIZE_4KB
 201 #define PM_DEFAULT_MASK PM_4K
 202 #elif defined(CONFIG_PAGE_SIZE_16KB)
 203 #define PM_DEFAULT_MASK PM_16K
 204 #elif defined(CONFIG_PAGE_SIZE_64KB)
 205 #define PM_DEFAULT_MASK PM_64K
 206 #else
 207 #error Bad page size configuration!
 208 #endif
 209
 210
 211 /*
 212  * Values used for computation of new tlb entries
 213  */
 214 #define PL_4K           12
 215 #define PL_16K          14
 216 #define PL_64K          16
 217 #define PL_256K         18
 218 #define PL_1M           20
 219 #define PL_4M           22
 220 #define PL_16M          24
 221 #define PL_64M          26
 222 #define PL_256M         28
 223
 224 /*
 225  * R4x00 interrupt enable / cause bits
 226  */
 227 #define IE_SW0          (_ULCAST_(1) <<  8)
 228 #define IE_SW1          (_ULCAST_(1) <<  9)
 229 #define IE_IRQ0         (_ULCAST_(1) << 10)
 230 #define IE_IRQ1         (_ULCAST_(1) << 11)
 231 #define IE_IRQ2         (_ULCAST_(1) << 12)
 232 #define IE_IRQ3         (_ULCAST_(1) << 13)
 233 #define IE_IRQ4         (_ULCAST_(1) << 14)
 234 #define IE_IRQ5         (_ULCAST_(1) << 15)
 235
 236 /*
 237  * R4x00 interrupt cause bits
 238  */
 239 #define C_SW0           (_ULCAST_(1) <<  8)
 240 #define C_SW1           (_ULCAST_(1) <<  9)
 241 #define C_IRQ0          (_ULCAST_(1) << 10)
 242 #define C_IRQ1          (_ULCAST_(1) << 11)
 243 #define C_IRQ2          (_ULCAST_(1) << 12)
 244 #define C_IRQ3          (_ULCAST_(1) << 13)
 245 #define C_IRQ4          (_ULCAST_(1) << 14)
 246 #define C_IRQ5          (_ULCAST_(1) << 15)
 247
 248 /*
 249  * Bitfields in the R4xx0 cp0 status register
 250  */
 251 #define ST0_IE                  0x00000001
 252 #define ST0_EXL                 0x00000002
 253 #define ST0_ERL                 0x00000004
 254 #define ST0_KSU                 0x00000018
 255 #  define KSU_USER              0x00000010
 256 #  define KSU_SUPERVISOR        0x00000008
 257 #  define KSU_KERNEL            0x00000000
 258 #define ST0_UX                  0x00000020
 259 #define ST0_SX                  0x00000040
 260 #define ST0_KX                  0x00000080
 261 #define ST0_DE                  0x00010000
 262 #define ST0_CE                  0x00020000
 263
 264 /*
 265  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 266  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 267  * processors.
 268  */
 269 #define ST0_CO                  0x08000000
 270
 271 /*
 272  * Bitfields in the R[23]000 cp0 status register.
 273  */
 274 #define ST0_IEC                 0x00000001
 275 #define ST0_KUC                 0x00000002
 276 #define ST0_IEP                 0x00000004
 277 #define ST0_KUP                 0x00000008
 278 #define ST0_IEO                 0x00000010
 279 #define ST0_KUO                 0x00000020
 280 /* bits 6 & 7 are reserved on R[23]000 */
 281 #define ST0_ISC                 0x00010000
 282 #define ST0_SWC                 0x00020000
 283 #define ST0_CM                  0x00080000
 284
 285 /*
 286  * Bits specific to the R4640/R4650
 287  */
 288 #define ST0_UM                  (_ULCAST_(1) <<  4)
 289 #define ST0_IL                  (_ULCAST_(1) << 23)
 290 #define ST0_DL                  (_ULCAST_(1) << 24)
 291
 292 /*
 293  * Enable the MIPS MDMX and DSP ASEs
 294  */
 295 #define ST0_MX                  0x01000000
 296
 297 /*
 298  * Bitfields in the TX39 family CP0 Configuration Register 3
 299  */
 300 #define TX39_CONF_ICS_SHIFT     19
 301 #define TX39_CONF_ICS_MASK      0x00380000
 302 #define TX39_CONF_ICS_1KB       0x00000000
 303 #define TX39_CONF_ICS_2KB       0x00080000
 304 #define TX39_CONF_ICS_4KB       0x00100000
 305 #define TX39_CONF_ICS_8KB       0x00180000
 306 #define TX39_CONF_ICS_16KB      0x00200000
 307
 308 #define TX39_CONF_DCS_SHIFT     16
 309 #define TX39_CONF_DCS_MASK      0x00070000
 310 #define TX39_CONF_DCS_1KB       0x00000000
 311 #define TX39_CONF_DCS_2KB       0x00010000
 312 #define TX39_CONF_DCS_4KB       0x00020000
 313 #define TX39_CONF_DCS_8KB       0x00030000
 314 #define TX39_CONF_DCS_16KB      0x00040000
 315
 316 #define TX39_CONF_CWFON         0x00004000
 317 #define TX39_CONF_WBON          0x00002000
 318 #define TX39_CONF_RF_SHIFT      10
 319 #define TX39_CONF_RF_MASK       0x00000c00
 320 #define TX39_CONF_DOZE          0x00000200
 321 #define TX39_CONF_HALT          0x00000100
 322 #define TX39_CONF_LOCK          0x00000080
 323 #define TX39_CONF_ICE           0x00000020
 324 #define TX39_CONF_DCE           0x00000010
 325 #define TX39_CONF_IRSIZE_SHIFT  2
 326 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 327 #define TX39_CONF_DRSIZE_SHIFT  0
 328 #define TX39_CONF_DRSIZE_MASK   0x00000003
 329
 330 /*
 331  * Status register bits available in all MIPS CPUs.
 332  */
 333 #define ST0_IM                  0x0000ff00
 334 #define  STATUSB_IP0            8
 335 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 336 #define  STATUSB_IP1            9
 337 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 338 #define  STATUSB_IP2            10
 339 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 340 #define  STATUSB_IP3            11
 341 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 342 #define  STATUSB_IP4            12
 343 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 344 #define  STATUSB_IP5            13
 345 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 346 #define  STATUSB_IP6            14
 347 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 348 #define  STATUSB_IP7            15
 349 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 350 #define  STATUSB_IP8            0
 351 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 352 #define  STATUSB_IP9            1
 353 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 354 #define  STATUSB_IP10           2
 355 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 356 #define  STATUSB_IP11           3
 357 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 358 #define  STATUSB_IP12           4
 359 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 360 #define  STATUSB_IP13           5
 361 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 362 #define  STATUSB_IP14           6
 363 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 364 #define  STATUSB_IP15           7
 365 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 366 #define ST0_CH                  0x00040000
 367 #define ST0_SR                  0x00100000
 368 #define ST0_TS                  0x00200000
 369 #define ST0_BEV                 0x00400000
 370 #define ST0_RE                  0x02000000
 371 #define ST0_FR                  0x04000000
 372 #define ST0_CU                  0xf0000000
 373 #define ST0_CU0                 0x10000000
 374 #define ST0_CU1                 0x20000000
 375 #define ST0_CU2                 0x40000000
 376 #define ST0_CU3                 0x80000000
 377 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 378
 379 /*
 380  * Bitfields and bit numbers in the coprocessor 0 cause register.
 381  *
 382  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 383  */
 384 #define  CAUSEB_EXCCODE         2
 385 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 386 #define  CAUSEB_IP              8
 387 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 388 #define  CAUSEB_IP0             8
 389 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 390 #define  CAUSEB_IP1             9
 391 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 392 #define  CAUSEB_IP2             10
 393 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 394 #define  CAUSEB_IP3             11
 395 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 396 #define  CAUSEB_IP4             12
 397 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 398 #define  CAUSEB_IP5             13
 399 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 400 #define  CAUSEB_IP6             14
 401 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 402 #define  CAUSEB_IP7             15
 403 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 404 #define  CAUSEB_IV              23
 405 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 406 #define  CAUSEB_CE              28
 407 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 408 #define  CAUSEB_BD              31
 409 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 410
 411 /*
 412  * Bits in the coprocessor 0 config register.
 413  */
 414 /* Generic bits.  */
 415 #define CONF_CM_CACHABLE_NO_WA          0
 416 #define CONF_CM_CACHABLE_WA             1
 417 #define CONF_CM_UNCACHED                2
 418 #define CONF_CM_CACHABLE_NONCOHERENT    3
 419 #define CONF_CM_CACHABLE_CE             4
 420 #define CONF_CM_CACHABLE_COW            5
 421 #define CONF_CM_CACHABLE_CUW            6
 422 #define CONF_CM_CACHABLE_ACCELERATED    7
 423 #define CONF_CM_CMASK                   7
 424 #define CONF_BE                 (_ULCAST_(1) << 15)
 425
 426 /* Bits common to various processors.  */
 427 #define CONF_CU                 (_ULCAST_(1) <<  3)
 428 #define CONF_DB                 (_ULCAST_(1) <<  4)
 429 #define CONF_IB                 (_ULCAST_(1) <<  5)
 430 #define CONF_DC                 (_ULCAST_(7) <<  6)
 431 #define CONF_IC                 (_ULCAST_(7) <<  9)
 432 #define CONF_EB                 (_ULCAST_(1) << 13)
 433 #define CONF_EM                 (_ULCAST_(1) << 14)
 434 #define CONF_SM                 (_ULCAST_(1) << 16)
 435 #define CONF_SC                 (_ULCAST_(1) << 17)
 436 #define CONF_EW                 (_ULCAST_(3) << 18)
 437 #define CONF_EP                 (_ULCAST_(15)<< 24)
 438 #define CONF_EC                 (_ULCAST_(7) << 28)
 439 #define CONF_CM                 (_ULCAST_(1) << 31)
 440
 441 /* Bits specific to the R4xx0.  */
 442 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 443 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 444 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 445
 446 /* Bits specific to the R5000.  */
 447 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 448 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 449
 450 /* Bits specific to the RM7000.  */
 451 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 452 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 453 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 454 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 455 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 456 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 457
 458 /* Bits specific to the R10000.  */
 459 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 460 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 461 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 462 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 463 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 464 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 465 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 466 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 467 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 468 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 469 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 470
 471 /* Bits specific to the VR41xx.  */
 472 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 473 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 474 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 475 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 476 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 477
 478 /* Bits specific to the R30xx.  */
 479 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 480 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 481 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 482 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 483 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 484 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 485 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 486 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 487 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 488
 489 /* Bits specific to the TX49.  */
 490 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 491 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 492 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 493 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 494
 495 /* Bits specific to the MIPS32/64 PRA.  */
 496 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 497 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 498 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 499 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 500
 501 /*
 502  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 503  */
 504 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 505 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 506 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 507 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 508 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 509 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 510 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 511 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 512 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 513 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 514 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 515 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 516 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 517 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
 518
 519 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 520 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 521 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 522 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 523 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 524 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 525 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 526 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 527
 528 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 529 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 530 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 531 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 532 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 533 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 534 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 535 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 536
 537 /*
 538  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 539  */
 540 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 541 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 542 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 543 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 544 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 545 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 546 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 547
 548 /*
 549  * R10000 performance counter definitions.
 550  *
 551  * FIXME: The R10000 performance counter opens a nice way to implement CPU
 552  *        time accounting with a precission of one cycle.  I don't have
 553  *        R10000 silicon but just a manual, so ...
 554  */
 555
 556 /*
 557  * Events counted by counter #0
 558  */
 559 #define CE0_CYCLES                      0
 560 #define CE0_INSN_ISSUED                 1
 561 #define CE0_LPSC_ISSUED                 2
 562 #define CE0_S_ISSUED                    3
 563 #define CE0_SC_ISSUED                   4
 564 #define CE0_SC_FAILED                   5
 565 #define CE0_BRANCH_DECODED              6
 566 #define CE0_QW_WB_SECONDARY             7
 567 #define CE0_CORRECTED_ECC_ERRORS        8
 568 #define CE0_ICACHE_MISSES               9
 569 #define CE0_SCACHE_I_MISSES             10
 570 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
 571 #define CE0_EXT_INTERVENTIONS_REQ       12
 572 #define CE0_EXT_INVALIDATE_REQ          13
 573 #define CE0_VIRTUAL_COHERENCY_COND      14
 574 #define CE0_INSN_GRADUATED              15
 575
 576 /*
 577  * Events counted by counter #1
 578  */
 579 #define CE1_CYCLES                      0
 580 #define CE1_INSN_GRADUATED              1
 581 #define CE1_LPSC_GRADUATED              2
 582 #define CE1_S_GRADUATED                 3
 583 #define CE1_SC_GRADUATED                4
 584 #define CE1_FP_INSN_GRADUATED           5
 585 #define CE1_QW_WB_PRIMARY               6
 586 #define CE1_TLB_REFILL                  7
 587 #define CE1_BRANCH_MISSPREDICTED        8
 588 #define CE1_DCACHE_MISS                 9
 589 #define CE1_SCACHE_D_MISSES             10
 590 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
 591 #define CE1_EXT_INTERVENTION_HITS       12
 592 #define CE1_EXT_INVALIDATE_REQ          13
 593 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
 594 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 595
 596 /*
 597  * These flags define in which privilege mode the counters count events
 598  */
 599 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
 600 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
 601 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
 602 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
 603
 604 #ifndef __ASSEMBLY__
 605
 606 /*
 607  * Functions to access the R10000 performance counters.  These are basically
 608  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 609  * performance counter number encoded into bits 1 ... 5 of the instruction.
 610  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 611  * disassembler these will look like an access to sel 0 or 1.
 612  */
 613 #define read_r10k_perf_cntr(counter)                            \
 614 ({                                                              \
 615         unsigned int __res;                                     \
 616         __asm__ __volatile__(                                   \
 617         "mfpc\t%0, %1"                                          \
 618         : "=r" (__res)                                          \
 619         : "i" (counter));                                       \
 620                                                                 \
 621         __res;                                                  \
 622 })
 623
 624 #define write_r10k_perf_cntr(counter,val)                       \
 625 do {                                                            \
 626         __asm__ __volatile__(                                   \
 627         "mtpc\t%0, %1"                                          \
 628         :                                                       \
 629         : "r" (val), "i" (counter));                            \
 630 } while (0)
 631
 632 #define read_r10k_perf_event(counter)                           \
 633 ({                                                              \
 634         unsigned int __res;                                     \
 635         __asm__ __volatile__(                                   \
 636         "mfps\t%0, %1"                                          \
 637         : "=r" (__res)                                          \
 638         : "i" (counter));                                       \
 639                                                                 \
 640         __res;                                                  \
 641 })
 642
 643 #define write_r10k_perf_cntl(counter,val)                       \
 644 do {                                                            \
 645         __asm__ __volatile__(                                   \
 646         "mtps\t%0, %1"                                          \
 647         :                                                       \
 648         : "r" (val), "i" (counter));                            \
 649 } while (0)
 650
 651
 652 /*
 653  * Macros to access the system control coprocessor
 654  */
 655
 656 #define __read_32bit_c0_register(source, sel)                           \
 657 ({ int __res;                                                           \
 658         if (sel == 0)                                                   \
 659                 __asm__ __volatile__(                                   \
 660                         "mfc0\t%0, " #source "\n\t"                     \
 661                         : "=r" (__res));                                \
 662         else                                                            \
 663                 __asm__ __volatile__(                                   \
 664                         ".set\tmips32\n\t"                              \
 665                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 666                         ".set\tmips0\n\t"                               \
 667                         : "=r" (__res));                                \
 668         __res;                                                          \
 669 })
 670
 671 #define __read_64bit_c0_register(source, sel)                           \
 672 ({ unsigned long long __res;                                            \
 673         if (sizeof(unsigned long) == 4)                                 \
 674                 __res = __read_64bit_c0_split(source, sel);             \
 675         else if (sel == 0)                                              \
 676                 __asm__ __volatile__(                                   \
 677                         ".set\tmips3\n\t"                               \
 678                         "dmfc0\t%0, " #source "\n\t"                    \
 679                         ".set\tmips0"                                   \
 680                         : "=r" (__res));                                \
 681         else                                                            \
 682                 __asm__ __volatile__(                                   \
 683                         ".set\tmips64\n\t"                              \
 684                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 685                         ".set\tmips0"                                   \
 686                         : "=r" (__res));                                \
 687         __res;                                                          \
 688 })
 689
 690 #define __write_32bit_c0_register(register, sel, value)                 \
 691 do {                                                                    \
 692         if (sel == 0)                                                   \
 693                 __asm__ __volatile__(                                   \
 694                         "mtc0\t%z0, " #register "\n\t"                  \
 695                         : : "Jr" ((unsigned int)(value)));              \
 696         else                                                            \
 697                 __asm__ __volatile__(                                   \
 698                         ".set\tmips32\n\t"                              \
 699                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 700                         ".set\tmips0"                                   \
 701                         : : "Jr" ((unsigned int)(value)));              \
 702 } while (0)
 703
 704 #define __write_64bit_c0_register(register, sel, value)                 \
 705 do {                                                                    \
 706         if (sizeof(unsigned long) == 4)                                 \
 707                 __write_64bit_c0_split(register, sel, value);           \
 708         else if (sel == 0)                                              \
 709                 __asm__ __volatile__(                                   \
 710                         ".set\tmips3\n\t"                               \
 711                         "dmtc0\t%z0, " #register "\n\t"                 \
 712                         ".set\tmips0"                                   \
 713                         : : "Jr" (value));                              \
 714         else                                                            \
 715                 __asm__ __volatile__(                                   \
 716                         ".set\tmips64\n\t"                              \
 717                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 718                         ".set\tmips0"                                   \
 719                         : : "Jr" (value));                              \
 720 } while (0)
 721
 722 #define __read_ulong_c0_register(reg, sel)                              \
 723         ((sizeof(unsigned long) == 4) ?                                 \
 724         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 725         (unsigned long) __read_64bit_c0_register(reg, sel))
 726
 727 #define __write_ulong_c0_register(reg, sel, val)                        \
 728 do {                                                                    \
 729         if (sizeof(unsigned long) == 4)                                 \
 730                 __write_32bit_c0_register(reg, sel, val);               \
 731         else                                                            \
 732                 __write_64bit_c0_register(reg, sel, val);               \
 733 } while (0)
 734
 735 /*
 736  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 737  */
 738 #define __read_32bit_c0_ctrl_register(source)                           \
 739 ({ int __res;                                                           \
 740         __asm__ __volatile__(                                           \
 741                 "cfc0\t%0, " #source "\n\t"                             \
 742                 : "=r" (__res));                                        \
 743         __res;                                                          \
 744 })
 745
 746 #define __write_32bit_c0_ctrl_register(register, value)                 \
 747 do {                                                                    \
 748         __asm__ __volatile__(                                           \
 749                 "ctc0\t%z0, " #register "\n\t"                          \
 750                 : : "Jr" ((unsigned int)(value)));                      \
 751 } while (0)
 752
 753 /*
 754  * These versions are only needed for systems with more than 38 bits of
 755  * physical address space running the 32-bit kernel.  That's none atm :-)
 756  */
 757 #define __read_64bit_c0_split(source, sel)                              \
 758 ({                                                                      \
 759         unsigned long long val;                                         \
 760         unsigned long flags;                                            \
 761                                                                         \
 762         local_irq_save(flags);                                          \
 763         if (sel == 0)                                                   \
 764                 __asm__ __volatile__(                                   \
 765                         ".set\tmips64\n\t"                              \
 766                         "dmfc0\t%M0, " #source "\n\t"                   \
 767                         "dsll\t%L0, %M0, 32\n\t"                        \
 768                         "dsrl\t%M0, %M0, 32\n\t"                        \
 769                         "dsrl\t%L0, %L0, 32\n\t"                        \
 770                         ".set\tmips0"                                   \
 771                         : "=r" (val));                                  \
 772         else                                                            \
 773                 __asm__ __volatile__(                                   \
 774                         ".set\tmips64\n\t"                              \
 775                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 776                         "dsll\t%L0, %M0, 32\n\t"                        \
 777                         "dsrl\t%M0, %M0, 32\n\t"                        \
 778                         "dsrl\t%L0, %L0, 32\n\t"                        \
 779                         ".set\tmips0"                                   \
 780                         : "=r" (val));                                  \
 781         local_irq_restore(flags);                                       \
 782                                                                         \
 783         val;                                                            \
 784 })
 785
 786 #define __write_64bit_c0_split(source, sel, val)                        \
 787 do {                                                                    \
 788         unsigned long flags;                                            \
 789                                                                         \
 790         local_irq_save(flags);                                          \
 791         if (sel == 0)                                                   \
 792                 __asm__ __volatile__(                                   \
 793                         ".set\tmips64\n\t"                              \
 794                         "dsll\t%L0, %L0, 32\n\t"                        \
 795                         "dsrl\t%L0, %L0, 32\n\t"                        \
 796                         "dsll\t%M0, %M0, 32\n\t"                        \
 797                         "or\t%L0, %L0, %M0\n\t"                         \
 798                         "dmtc0\t%L0, " #source "\n\t"                   \
 799                         ".set\tmips0"                                   \
 800                         : : "r" (val));                                 \
 801         else                                                            \
 802                 __asm__ __volatile__(                                   \
 803                         ".set\tmips64\n\t"                              \
 804                         "dsll\t%L0, %L0, 32\n\t"                        \
 805                         "dsrl\t%L0, %L0, 32\n\t"                        \
 806                         "dsll\t%M0, %M0, 32\n\t"                        \
 807                         "or\t%L0, %L0, %M0\n\t"                         \
 808                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 809                         ".set\tmips0"                                   \
 810                         : : "r" (val));                                 \
 811         local_irq_restore(flags);                                       \
 812 } while (0)
 813
 814 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 815 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 816
 817 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 818 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 819
 820 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 821 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 822
 823 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 824 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 825
 826 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 827 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 828
 829 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 830 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 831
 832 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 833 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 834
 835 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 836
 837 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 838 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 839
 840 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
 841 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
 842
 843 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 844 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 845
 846 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
 847 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
 848
 849 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
 850 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 851
 852 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 853 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 854
 855 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 856 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 857
 858 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
 859 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
 860
 861 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
 862 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 863
 864 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 865 #ifdef CONFIG_MIPS_MT_SMTC
 866 #define write_c0_status(val)                                            \
 867 do {                                                                    \
 868         __write_32bit_c0_register($12, 0, val);                         \
 869         __ehb();                                                        \
 870 } while (0)
 871 #else
 872 /*
 873  * Legacy non-SMTC code, which may be hazardous
 874  * but which might not support EHB
 875  */
 876 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 877 #endif /* CONFIG_MIPS_MT_SMTC */
 878
 879 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 880 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 881
 882 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 883 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 884
 885 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 886
 887 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 888 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 889 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 890 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 891 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
 892 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
 893 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
 894 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
 895 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 896 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 897 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 898 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 899 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 900 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 901 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 902 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 903
 904 /*
 905  * The WatchLo register.  There may be upto 8 of them.
 906  */
 907 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 908 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 909 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
 910 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
 911 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
 912 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
 913 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
 914 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
 915 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
 916 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
 917 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
 918 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
 919 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
 920 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
 921 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
 922 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 923
 924 /*
 925  * The WatchHi register.  There may be upto 8 of them.
 926  */
 927 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 928 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
 929 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
 930 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
 931 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
 932 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
 933 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
 934 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
 935
 936 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
 937 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
 938 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
 939 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
 940 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
 941 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
 942 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
 943 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 944
 945 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
 946 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 947
 948 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
 949 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 950
 951 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 952 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 953
 954 /* RM9000 PerfControl performance counter control register */
 955 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
 956 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
 957
 958 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 959 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 960
 961 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
 962 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
 963
 964 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
 965 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
 966
 967 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
 968 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
 969
 970 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
 971 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
 972
 973 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
 974 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
 975
 976 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
 977 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
 978
 979 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
 980 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
 981
 982 /*
 983  * MIPS32 / MIPS64 performance counters
 984  */
 985 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
 986 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 987 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 988 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
 989 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 990 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 991 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 992 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
 993 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 994 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 995 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 996 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
 997 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 998 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 999 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1000 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1001
1002 /* RM9000 PerfCount performance counter register */
1003 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
1004 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1005
1006 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1007 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1008
1009 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1010 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1011
1012 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1013
1014 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1015 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1016
1017 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1018 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1019
1020 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1021 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1022
1023 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1024 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1025
1026 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1027 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1028
1029 /* MIPSR2 */
1030 #define read_c0_hwrena()        __read_32bit_c0_register($7,0)
1031 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1032
1033 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1034 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1035
1036 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1037 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1038
1039 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1040 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1041
1042 #define read_c0_ebase()         __read_32bit_c0_register($15,1)
1043 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1044
1045 /*
1046  * Macros to access the floating point coprocessor control registers
1047  */
1048 #define read_32bit_cp1_register(source)                         \
1049 ({ int __res;                                                   \
1050         __asm__ __volatile__(                                   \
1051         ".set\tpush\n\t"                                        \
1052         ".set\treorder\n\t"                                     \
1053         "cfc1\t%0,"STR(source)"\n\t"                            \
1054         ".set\tpop"                                             \
1055         : "=r" (__res));                                        \
1056         __res;})
1057
1058 #define rddsp(mask)                                                     \
1059 ({                                                                      \
1060         unsigned int __res;                                             \
1061                                                                         \
1062         __asm__ __volatile__(                                           \
1063         "       .set    push                            \n"             \
1064         "       .set    noat                            \n"             \
1065         "       # rddsp $1, %x1                         \n"             \
1066         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1067         "       move    %0, $1                          \n"             \
1068         "       .set    pop                             \n"             \
1069         : "=r" (__res)                                                  \
1070         : "i" (mask));                                                  \
1071         __res;                                                          \
1072 })
1073
1074 #define wrdsp(val, mask)                                                \
1075 do {                                                                    \
1076         __asm__ __volatile__(                                           \
1077         "       .set    push                                    \n"     \
1078         "       .set    noat                                    \n"     \
1079         "       move    $1, %0                                  \n"     \
1080         "       # wrdsp $1, %x1                                 \n"     \
1081         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1082         "       .set    pop                                     \n"     \
1083         :                                                               \
1084         : "r" (val), "i" (mask));                                       \
1085 } while (0)
1086
1087 #if 0   /* Need DSP ASE capable assembler ... */
1088 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1089 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1090 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1091 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1092
1093 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1094 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1095 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1096 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1097
1098 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1099 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1100 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1101 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1102
1103 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1104 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1105 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1106 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1107
1108 #else
1109
1110 #define mfhi0()                                                         \
1111 ({                                                                      \
1112         unsigned long __treg;                                           \
1113                                                                         \
1114         __asm__ __volatile__(                                           \
1115         "       .set    push                    \n"                     \
1116         "       .set    noat                    \n"                     \
1117         "       # mfhi  %0, $ac0                \n"                     \
1118         "       .word   0x00000810              \n"                     \
1119         "       move    %0, $1                  \n"                     \
1120         "       .set    pop                     \n"                     \
1121         : "=r" (__treg));                                               \
1122         __treg;                                                         \
1123 })
1124
1125 #define mfhi1()                                                         \
1126 ({                                                                      \
1127         unsigned long __treg;                                           \
1128                                                                         \
1129         __asm__ __volatile__(                                           \
1130         "       .set    push                    \n"                     \
1131         "       .set    noat                    \n"                     \
1132         "       # mfhi  %0, $ac1                \n"                     \
1133         "       .word   0x00200810              \n"                     \
1134         "       move    %0, $1                  \n"                     \
1135         "       .set    pop                     \n"                     \
1136         : "=r" (__treg));                                               \
1137         __treg;                                                         \
1138 })
1139
1140 #define mfhi2()                                                         \
1141 ({                                                                      \
1142         unsigned long __treg;                                           \
1143                                                                         \
1144         __asm__ __volatile__(                                           \
1145         "       .set    push                    \n"                     \
1146         "       .set    noat                    \n"                     \
1147         "       # mfhi  %0, $ac2                \n"                     \
1148         "       .word   0x00400810              \n"                     \
1149         "       move    %0, $1                  \n"                     \
1150         "       .set    pop                     \n"                     \
1151         : "=r" (__treg));                                               \
1152         __treg;                                                         \
1153 })
1154
1155 #define mfhi3()                                                         \
1156 ({                                                                      \
1157         unsigned long __treg;                                           \
1158                                                                         \
1159         __asm__ __volatile__(                                           \
1160         "       .set    push                    \n"                     \
1161         "       .set    noat                    \n"                     \
1162         "       # mfhi  %0, $ac3                \n"                     \
1163         "       .word   0x00600810              \n"                     \
1164         "       move    %0, $1                  \n"                     \
1165         "       .set    pop                     \n"                     \
1166         : "=r" (__treg));                                               \
1167         __treg;                                                         \
1168 })
1169
1170 #define mflo0()                                                         \
1171 ({                                                                      \
1172         unsigned long __treg;                                           \
1173                                                                         \
1174         __asm__ __volatile__(                                           \
1175         "       .set    push                    \n"                     \
1176         "       .set    noat                    \n"                     \
1177         "       # mflo  %0, $ac0                \n"                     \
1178         "       .word   0x00000812              \n"                     \
1179         "       move    %0, $1                  \n"                     \
1180         "       .set    pop                     \n"                     \
1181         : "=r" (__treg));                                               \
1182         __treg;                                                         \
1183 })
1184
1185 #define mflo1()                                                         \
1186 ({                                                                      \
1187         unsigned long __treg;                                           \
1188                                                                         \
1189         __asm__ __volatile__(                                           \
1190         "       .set    push                    \n"                     \
1191         "       .set    noat                    \n"                     \
1192         "       # mflo  %0, $ac1                \n"                     \
1193         "       .word   0x00200812              \n"                     \
1194         "       move    %0, $1                  \n"                     \
1195         "       .set    pop                     \n"                     \
1196         : "=r" (__treg));                                               \
1197         __treg;                                                         \
1198 })
1199
1200 #define mflo2()                                                         \
1201 ({                                                                      \
1202         unsigned long __treg;                                           \
1203                                                                         \
1204         __asm__ __volatile__(                                           \
1205         "       .set    push                    \n"                     \
1206         "       .set    noat                    \n"                     \
1207         "       # mflo  %0, $ac2                \n"                     \
1208         "       .word   0x00400812              \n"                     \
1209         "       move    %0, $1                  \n"                     \
1210         "       .set    pop                     \n"                     \
1211         : "=r" (__treg));                                               \
1212         __treg;                                                         \
1213 })
1214
1215 #define mflo3()                                                         \
1216 ({                                                                      \
1217         unsigned long __treg;                                           \
1218                                                                         \
1219         __asm__ __volatile__(                                           \
1220         "       .set    push                    \n"                     \
1221         "       .set    noat                    \n"                     \
1222         "       # mflo  %0, $ac3                \n"                     \
1223         "       .word   0x00600812              \n"                     \
1224         "       move    %0, $1                  \n"                     \
1225         "       .set    pop                     \n"                     \
1226         : "=r" (__treg));                                               \
1227         __treg;                                                         \
1228 })
1229
1230 #define mthi0(x)                                                        \
1231 do {                                                                    \
1232         __asm__ __volatile__(                                           \
1233         "       .set    push                                    \n"     \
1234         "       .set    noat                                    \n"     \
1235         "       move    $1, %0                                  \n"     \
1236         "       # mthi  $1, $ac0                                \n"     \
1237         "       .word   0x00200011                              \n"     \
1238         "       .set    pop                                     \n"     \
1239         :                                                               \
1240         : "r" (x));                                                     \
1241 } while (0)
1242
1243 #define mthi1(x)                                                        \
1244 do {                                                                    \
1245         __asm__ __volatile__(                                           \
1246         "       .set    push                                    \n"     \
1247         "       .set    noat                                    \n"     \
1248         "       move    $1, %0                                  \n"     \
1249         "       # mthi  $1, $ac1                                \n"     \
1250         "       .word   0x00200811                              \n"     \
1251         "       .set    pop                                     \n"     \
1252         :                                                               \
1253         : "r" (x));                                                     \
1254 } while (0)
1255
1256 #define mthi2(x)                                                        \
1257 do {                                                                    \
1258         __asm__ __volatile__(                                           \
1259         "       .set    push                                    \n"     \
1260         "       .set    noat                                    \n"     \
1261         "       move    $1, %0                                  \n"     \
1262         "       # mthi  $1, $ac2                                \n"     \
1263         "       .word   0x00201011                              \n"     \
1264         "       .set    pop                                     \n"     \
1265         :                                                               \
1266         : "r" (x));                                                     \
1267 } while (0)
1268
1269 #define mthi3(x)                                                        \
1270 do {                                                                    \
1271         __asm__ __volatile__(                                           \
1272         "       .set    push                                    \n"     \
1273         "       .set    noat                                    \n"     \
1274         "       move    $1, %0                                  \n"     \
1275         "       # mthi  $1, $ac3                                \n"     \
1276         "       .word   0x00201811                              \n"     \
1277         "       .set    pop                                     \n"     \
1278         :                                                               \
1279         : "r" (x));                                                     \
1280 } while (0)
1281
1282 #define mtlo0(x)                                                        \
1283 do {                                                                    \
1284         __asm__ __volatile__(                                           \
1285         "       .set    push                                    \n"     \
1286         "       .set    noat                                    \n"     \
1287         "       move    $1, %0                                  \n"     \
1288         "       # mtlo  $1, $ac0                                \n"     \
1289         "       .word   0x00200013                              \n"     \
1290         "       .set    pop                                     \n"     \
1291         :                                                               \
1292         : "r" (x));                                                     \
1293 } while (0)
1294
1295 #define mtlo1(x)                                                        \
1296 do {                                                                    \
1297         __asm__ __volatile__(                                           \
1298         "       .set    push                                    \n"     \
1299         "       .set    noat                                    \n"     \
1300         "       move    $1, %0                                  \n"     \
1301         "       # mtlo  $1, $ac1                                \n"     \
1302         "       .word   0x00200813                              \n"     \
1303         "       .set    pop                                     \n"     \
1304         :                                                               \
1305         : "r" (x));                                                     \
1306 } while (0)
1307
1308 #define mtlo2(x)                                                        \
1309 do {                                                                    \
1310         __asm__ __volatile__(                                           \
1311         "       .set    push                                    \n"     \
1312         "       .set    noat                                    \n"     \
1313         "       move    $1, %0                                  \n"     \
1314         "       # mtlo  $1, $ac2                                \n"     \
1315         "       .word   0x00201013                              \n"     \
1316         "       .set    pop                                     \n"     \
1317         :                                                               \
1318         : "r" (x));                                                     \
1319 } while (0)
1320
1321 #define mtlo3(x)                                                        \
1322 do {                                                                    \
1323         __asm__ __volatile__(                                           \
1324         "       .set    push                                    \n"     \
1325         "       .set    noat                                    \n"     \
1326         "       move    $1, %0                                  \n"     \
1327         "       # mtlo  $1, $ac3                                \n"     \
1328         "       .word   0x00201813                              \n"     \
1329         "       .set    pop                                     \n"     \
1330         :                                                               \
1331         : "r" (x));                                                     \
1332 } while (0)
1333
1334 #endif
1335
1336 /*
1337  * TLB operations.
1338  *
1339  * It is responsibility of the caller to take care of any TLB hazards.
1340  */
1341 static inline void tlb_probe(void)
1342 {
1343         __asm__ __volatile__(
1344                 ".set noreorder\n\t"
1345                 "tlbp\n\t"
1346                 ".set reorder");
1347 }
1348
1349 static inline void tlb_read(void)
1350 {
1351         __asm__ __volatile__(
1352                 ".set noreorder\n\t"
1353                 "tlbr\n\t"
1354                 ".set reorder");
1355 }
1356
1357 static inline void tlb_write_indexed(void)
1358 {
1359         __asm__ __volatile__(
1360                 ".set noreorder\n\t"
1361                 "tlbwi\n\t"
1362                 ".set reorder");
1363 }
1364
1365 static inline void tlb_write_random(void)
1366 {
1367         __asm__ __volatile__(
1368                 ".set noreorder\n\t"
1369                 "tlbwr\n\t"
1370                 ".set reorder");
1371 }
1372
1373 /*
1374  * Manipulate bits in a c0 register.
1375  */
1376 #ifndef CONFIG_MIPS_MT_SMTC
1377 /*
1378  * SMTC Linux requires shutting-down microthread scheduling
1379  * during CP0 register read-modify-write sequences.
1380  */
1381 #define __BUILD_SET_C0(name)                                    \
1382 static inline unsigned int                                      \
1383 set_c0_##name(unsigned int set)                                 \
1384 {                                                               \
1385         unsigned int res;                                       \
1386                                                                 \
1387         res = read_c0_##name();                                 \
1388         res |= set;                                             \
1389         write_c0_##name(res);                                   \
1390                                                                 \
1391         return res;                                             \
1392 }                                                               \
1393                                                                 \
1394 static inline unsigned int                                      \
1395 clear_c0_##name(unsigned int clear)                             \
1396 {                                                               \
1397         unsigned int res;                                       \
1398                                                                 \
1399         res = read_c0_##name();                                 \
1400         res &= ~clear;                                          \
1401         write_c0_##name(res);                                   \
1402                                                                 \
1403         return res;                                             \
1404 }                                                               \
1405                                                                 \
1406 static inline unsigned int                                      \
1407 change_c0_##name(unsigned int change, unsigned int new)         \
1408 {                                                               \
1409         unsigned int res;                                       \
1410                                                                 \
1411         res = read_c0_##name();                                 \
1412         res &= ~change;                                         \
1413         res |= (new & change);                                  \
1414         write_c0_##name(res);                                   \
1415                                                                 \
1416         return res;                                             \
1417 }
1418
1419 #else /* SMTC versions that manage MT scheduling */
1420
1421 #include <linux/irqflags.h>
1422
1423 /*
1424  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1425  * header file recursion.
1426  */
1427 static inline unsigned int __dmt(void)
1428 {
1429         int res;
1430
1431         __asm__ __volatile__(
1432         "       .set    push                                            \n"
1433         "       .set    mips32r2                                        \n"
1434         "       .set    noat                                            \n"
1435         "       .word   0x41610BC1                      # dmt $1        \n"
1436         "       ehb                                                     \n"
1437         "       move    %0, $1                                          \n"
1438         "       .set    pop                                             \n"
1439         : "=r" (res));
1440
1441         instruction_hazard();
1442
1443         return res;
1444 }
1445
1446 #define __VPECONTROL_TE_SHIFT   15
1447 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1448
1449 #define __EMT_ENABLE            __VPECONTROL_TE
1450
1451 static inline void __emt(unsigned int previous)
1452 {
1453         if ((previous & __EMT_ENABLE))
1454                 __asm__ __volatile__(
1455                 "       .set    mips32r2                                \n"
1456                 "       .word   0x41600be1              # emt           \n"
1457                 "       ehb                                             \n"
1458                 "       .set    mips0                                   \n");
1459 }
1460
1461 static inline void __ehb(void)
1462 {
1463         __asm__ __volatile__(
1464         "       .set    mips32r2                                        \n"
1465         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1466 }
1467
1468 /*
1469  * Note that local_irq_save/restore affect TC-specific IXMT state,
1470  * not Status.IE as in non-SMTC kernel.
1471  */
1472
1473 #define __BUILD_SET_C0(name)                                    \
1474 static inline unsigned int                                      \
1475 set_c0_##name(unsigned int set)                                 \
1476 {                                                               \
1477         unsigned int res;                                       \
1478         unsigned int omt;                                       \
1479         unsigned int flags;                                     \
1480                                                                 \
1481         local_irq_save(flags);                                  \
1482         omt = __dmt();                                          \
1483         res = read_c0_##name();                                 \
1484         res |= set;                                             \
1485         write_c0_##name(res);                                   \
1486         __emt(omt);                                             \
1487         local_irq_restore(flags);                               \
1488                                                                 \
1489         return res;                                             \
1490 }                                                               \
1491                                                                 \
1492 static inline unsigned int                                      \
1493 clear_c0_##name(unsigned int clear)                             \
1494 {                                                               \
1495         unsigned int res;                                       \
1496         unsigned int omt;                                       \
1497         unsigned int flags;                                     \
1498                                                                 \
1499         local_irq_save(flags);                                  \
1500         omt = __dmt();                                          \
1501         res = read_c0_##name();                                 \
1502         res &= ~clear;                                          \
1503         write_c0_##name(res);                                   \
1504         __emt(omt);                                             \
1505         local_irq_restore(flags);                               \
1506                                                                 \
1507         return res;                                             \
1508 }                                                               \
1509                                                                 \
1510 static inline unsigned int                                      \
1511 change_c0_##name(unsigned int change, unsigned int new)         \
1512 {                                                               \
1513         unsigned int res;                                       \
1514         unsigned int omt;                                       \
1515         unsigned int flags;                                     \
1516                                                                 \
1517         local_irq_save(flags);                                  \
1518                                                                 \
1519         omt = __dmt();                                          \
1520         res = read_c0_##name();                                 \
1521         res &= ~change;                                         \
1522         res |= (new & change);                                  \
1523         write_c0_##name(res);                                   \
1524         __emt(omt);                                             \
1525         local_irq_restore(flags);                               \
1526                                                                 \
1527         return res;                                             \
1528 }
1529 #endif
1530
1531 __BUILD_SET_C0(status)
1532 __BUILD_SET_C0(cause)
1533 __BUILD_SET_C0(config)
1534 __BUILD_SET_C0(intcontrol)
1535 __BUILD_SET_C0(intctl)
1536 __BUILD_SET_C0(srsmap)
1537
1538 #endif /* !__ASSEMBLY__ */
1539
1540 #endif /* _ASM_MIPSREGS_H */