include/asm-m68knommu/mcftimer.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcftimer.h -- ColdFire internal TIMER support defines.
   5  *
   6  *      (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcftimer_h
  12 #define mcftimer_h
  13 /****************************************************************************/
  14
  15
  16 /*
  17  *      Get address specific defines for this ColdFire member.
  18  */
  19 #if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
  20 #define MCFTIMER_BASE1          0x100           /* Base address of TIMER1 */
  21 #define MCFTIMER_BASE2          0x120           /* Base address of TIMER2 */
  22 #elif defined(CONFIG_M5272)
  23 #define MCFTIMER_BASE1          0x200           /* Base address of TIMER1 */
  24 #define MCFTIMER_BASE2          0x220           /* Base address of TIMER2 */
  25 #define MCFTIMER_BASE3          0x240           /* Base address of TIMER4 */
  26 #define MCFTIMER_BASE4          0x260           /* Base address of TIMER3 */
  27 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
  28 #define MCFTIMER_BASE1          0x140           /* Base address of TIMER1 */
  29 #define MCFTIMER_BASE2          0x180           /* Base address of TIMER2 */
  30 #endif
  31
  32
  33 /*
  34  *      Define the TIMER register set addresses.
  35  */
  36 #define MCFTIMER_TMR            0x00            /* Timer Mode reg (r/w) */
  37 #define MCFTIMER_TRR            0x02            /* Timer Reference (r/w) */
  38 #define MCFTIMER_TCR            0x04            /* Timer Capture reg (r/w) */
  39 #define MCFTIMER_TCN            0x06            /* Timer Counter reg (r/w) */
  40 #define MCFTIMER_TER            0x11            /* Timer Event reg (r/w) */
  41
  42 struct mcftimer {
  43         unsigned short  tmr;                    /* Timer Mode reg (r/w) */
  44         unsigned short  reserved1;
  45         unsigned short  trr;                    /* Timer Reference (r/w) */
  46         unsigned short  reserved2;
  47         unsigned short  tcr;                    /* Timer Capture reg (r/w) */
  48         unsigned short  reserved3;
  49         unsigned short  tcn;                    /* Timer Counter reg (r/w) */
  50         unsigned short  reserved4;
  51         unsigned char   reserved5;
  52         unsigned char   ter;                    /* Timer Event reg (r/w) */
  53 } __attribute__((packed));
  54
  55 /*
  56  *      Bit definitions for the Timer Mode Register (TMR).
  57  *      Register bit flags are common accross ColdFires.
  58  */
  59 #define MCFTIMER_TMR_PREMASK    0xff00          /* Prescalar mask */
  60 #define MCFTIMER_TMR_DISCE      0x0000          /* Disable capture */
  61 #define MCFTIMER_TMR_ANYCE      0x00c0          /* Capture any edge */
  62 #define MCFTIMER_TMR_FALLCE     0x0080          /* Capture fallingedge */
  63 #define MCFTIMER_TMR_RISECE     0x0040          /* Capture rising edge */
  64 #define MCFTIMER_TMR_ENOM       0x0020          /* Enable output toggle */
  65 #define MCFTIMER_TMR_DISOM      0x0000          /* Do single output pulse  */
  66 #define MCFTIMER_TMR_ENORI      0x0010          /* Enable ref interrupt */
  67 #define MCFTIMER_TMR_DISORI     0x0000          /* Disable ref interrupt */
  68 #define MCFTIMER_TMR_RESTART    0x0008          /* Restart counter */
  69 #define MCFTIMER_TMR_FREERUN    0x0000          /* Free running counter */
  70 #define MCFTIMER_TMR_CLKTIN     0x0006          /* Input clock is TIN */
  71 #define MCFTIMER_TMR_CLK16      0x0004          /* Input clock is /16 */
  72 #define MCFTIMER_TMR_CLK1       0x0002          /* Input clock is /1 */
  73 #define MCFTIMER_TMR_CLKSTOP    0x0000          /* Stop counter */
  74 #define MCFTIMER_TMR_ENABLE     0x0001          /* Enable timer */
  75 #define MCFTIMER_TMR_DISABLE    0x0000          /* Disable timer */
  76
  77 /*
  78  *      Bit definitions for the Timer Event Registers (TER).
  79  */
  80 #define MCFTIMER_TER_CAP        0x01            /* Capture event */
  81 #define MCFTIMER_TER_REF        0x02            /* Refernece event */
  82
  83 /****************************************************************************/
  84 #endif  /* mcftimer_h */