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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee13...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-ia64 / processor.h
1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
3
4 /*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16
17 #include <asm/intrinsics.h>
18 #include <asm/kregs.h>
19 #include <asm/ptrace.h>
20 #include <asm/ustack.h>
21
22 #define IA64_NUM_DBG_REGS 8
23
24 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
25 #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
26
27 /*
28 * TASK_SIZE really is a mis-named. It really is the maximum user
29 * space address (plus one). On IA-64, there are five regions of 2TB
30 * each (assuming 8KB page size), for a total of 8TB of user virtual
31 * address space.
32 */
33 #define TASK_SIZE (current->thread.task_size)
34
35 /*
36 * This decides where the kernel will search for a free chunk of vm
37 * space during mmap's.
38 */
39 #define TASK_UNMAPPED_BASE (current->thread.map_base)
40
41 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
42 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
43 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
44 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
45 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
46 #define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
47 sync at ctx sw */
48 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
49 #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
50
51 #define IA64_THREAD_UAC_SHIFT 3
52 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
53 #define IA64_THREAD_FPEMU_SHIFT 6
54 #define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
55
56
57 /*
58 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
59 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
60 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
61 */
62 #define IA64_NSEC_PER_CYC_SHIFT 30
63
64 #ifndef __ASSEMBLY__
65
66 #include <linux/cache.h>
67 #include <linux/compiler.h>
68 #include <linux/threads.h>
69 #include <linux/types.h>
70
71 #include <asm/fpu.h>
72 #include <asm/page.h>
73 #include <asm/percpu.h>
74 #include <asm/rse.h>
75 #include <asm/unwind.h>
76 #include <asm/atomic.h>
77 #ifdef CONFIG_NUMA
78 #include <asm/nodedata.h>
79 #endif
80
81 /* like above but expressed as bitfields for more efficient access: */
82 struct ia64_psr {
83 __u64 reserved0 : 1;
84 __u64 be : 1;
85 __u64 up : 1;
86 __u64 ac : 1;
87 __u64 mfl : 1;
88 __u64 mfh : 1;
89 __u64 reserved1 : 7;
90 __u64 ic : 1;
91 __u64 i : 1;
92 __u64 pk : 1;
93 __u64 reserved2 : 1;
94 __u64 dt : 1;
95 __u64 dfl : 1;
96 __u64 dfh : 1;
97 __u64 sp : 1;
98 __u64 pp : 1;
99 __u64 di : 1;
100 __u64 si : 1;
101 __u64 db : 1;
102 __u64 lp : 1;
103 __u64 tb : 1;
104 __u64 rt : 1;
105 __u64 reserved3 : 4;
106 __u64 cpl : 2;
107 __u64 is : 1;
108 __u64 mc : 1;
109 __u64 it : 1;
110 __u64 id : 1;
111 __u64 da : 1;
112 __u64 dd : 1;
113 __u64 ss : 1;
114 __u64 ri : 2;
115 __u64 ed : 1;
116 __u64 bn : 1;
117 __u64 reserved4 : 19;
118 };
119
120 /*
121 * CPU type, hardware bug flags, and per-CPU state. Frequently used
122 * state comes earlier:
123 */
124 struct cpuinfo_ia64 {
125 __u32 softirq_pending;
126 __u64 itm_delta; /* # of clock cycles between clock ticks */
127 __u64 itm_next; /* interval timer mask value to use for next clock tick */
128 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
129 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
130 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
131 __u64 itc_freq; /* frequency of ITC counter */
132 __u64 proc_freq; /* frequency of processor */
133 __u64 cyc_per_usec; /* itc_freq/1000000 */
134 __u64 ptce_base;
135 __u32 ptce_count[2];
136 __u32 ptce_stride[2];
137 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
138
139 #ifdef CONFIG_SMP
140 __u64 loops_per_jiffy;
141 int cpu;
142 __u32 socket_id; /* physical processor socket id */
143 __u16 core_id; /* core id */
144 __u16 thread_id; /* thread id */
145 __u16 num_log; /* Total number of logical processors on
146 * this socket that were successfully booted */
147 __u8 cores_per_socket; /* Cores per processor socket */
148 __u8 threads_per_core; /* Threads per core */
149 #endif
150
151 /* CPUID-derived information: */
152 __u64 ppn;
153 __u64 features;
154 __u8 number;
155 __u8 revision;
156 __u8 model;
157 __u8 family;
158 __u8 archrev;
159 char vendor[16];
160 char *model_name;
161
162 #ifdef CONFIG_NUMA
163 struct ia64_node_data *node_data;
164 #endif
165 };
166
167 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
168
169 /*
170 * The "local" data variable. It refers to the per-CPU data of the currently executing
171 * CPU, much like "current" points to the per-task data of the currently executing task.
172 * Do not use the address of local_cpu_data, since it will be different from
173 * cpu_data(smp_processor_id())!
174 */
175 #define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
176 #define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
177
178 extern void print_cpu_info (struct cpuinfo_ia64 *);
179
180 typedef struct {
181 unsigned long seg;
182 } mm_segment_t;
183
184 #define SET_UNALIGN_CTL(task,value) \
185 ({ \
186 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
187 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
188 0; \
189 })
190 #define GET_UNALIGN_CTL(task,addr) \
191 ({ \
192 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
193 (int __user *) (addr)); \
194 })
195
196 #define SET_FPEMU_CTL(task,value) \
197 ({ \
198 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
199 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
200 0; \
201 })
202 #define GET_FPEMU_CTL(task,addr) \
203 ({ \
204 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
205 (int __user *) (addr)); \
206 })
207
208 #ifdef CONFIG_IA32_SUPPORT
209 struct desc_struct {
210 unsigned int a, b;
211 };
212
213 #define desc_empty(desc) (!((desc)->a + (desc)->b))
214 #define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
215
216 #define GDT_ENTRY_TLS_ENTRIES 3
217 #define GDT_ENTRY_TLS_MIN 6
218 #define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
219
220 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
221
222 struct partial_page_list;
223 #endif
224
225 struct thread_struct {
226 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
227 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
228 __u8 on_ustack; /* executing on user-stacks? */
229 __u8 pad[3];
230 __u64 ksp; /* kernel stack pointer */
231 __u64 map_base; /* base address for get_unmapped_area() */
232 __u64 task_size; /* limit for task size */
233 __u64 rbs_bot; /* the base address for the RBS */
234 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
235
236 #ifdef CONFIG_IA32_SUPPORT
237 __u64 eflag; /* IA32 EFLAGS reg */
238 __u64 fsr; /* IA32 floating pt status reg */
239 __u64 fcr; /* IA32 floating pt control reg */
240 __u64 fir; /* IA32 fp except. instr. reg */
241 __u64 fdr; /* IA32 fp except. data reg */
242 __u64 old_k1; /* old value of ar.k1 */
243 __u64 old_iob; /* old IOBase value */
244 struct partial_page_list *ppl; /* partial page list for 4K page size issue */
245 /* cached TLS descriptors. */
246 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
247
248 # define INIT_THREAD_IA32 .eflag = 0, \
249 .fsr = 0, \
250 .fcr = 0x17800000037fULL, \
251 .fir = 0, \
252 .fdr = 0, \
253 .old_k1 = 0, \
254 .old_iob = 0, \
255 .ppl = NULL,
256 #else
257 # define INIT_THREAD_IA32
258 #endif /* CONFIG_IA32_SUPPORT */
259 #ifdef CONFIG_PERFMON
260 void *pfm_context; /* pointer to detailed PMU context */
261 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
262 # define INIT_THREAD_PM .pfm_context = NULL, \
263 .pfm_needs_checking = 0UL,
264 #else
265 # define INIT_THREAD_PM
266 #endif
267 __u64 dbr[IA64_NUM_DBG_REGS];
268 __u64 ibr[IA64_NUM_DBG_REGS];
269 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
270 };
271
272 #define INIT_THREAD { \
273 .flags = 0, \
274 .on_ustack = 0, \
275 .ksp = 0, \
276 .map_base = DEFAULT_MAP_BASE, \
277 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
278 .task_size = DEFAULT_TASK_SIZE, \
279 .last_fph_cpu = -1, \
280 INIT_THREAD_IA32 \
281 INIT_THREAD_PM \
282 .dbr = {0, }, \
283 .ibr = {0, }, \
284 .fph = {{{{0}}}, } \
285 }
286
287 #define start_thread(regs,new_ip,new_sp) do { \
288 set_fs(USER_DS); \
289 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
290 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
291 regs->cr_iip = new_ip; \
292 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
293 regs->ar_rnat = 0; \
294 regs->ar_bspstore = current->thread.rbs_bot; \
295 regs->ar_fpsr = FPSR_DEFAULT; \
296 regs->loadrs = 0; \
297 regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \
298 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
299 if (unlikely(!current->mm->dumpable)) { \
300 /* \
301 * Zap scratch regs to avoid leaking bits between processes with different \
302 * uid/privileges. \
303 */ \
304 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
305 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
306 } \
307 } while (0)
308
309 /* Forward declarations, a strange C thing... */
310 struct mm_struct;
311 struct task_struct;
312
313 /*
314 * Free all resources held by a thread. This is called after the
315 * parent of DEAD_TASK has collected the exit status of the task via
316 * wait().
317 */
318 #define release_thread(dead_task)
319
320 /* Prepare to copy thread state - unlazy all lazy status */
321 #define prepare_to_copy(tsk) do { } while (0)
322
323 /*
324 * This is the mechanism for creating a new kernel thread.
325 *
326 * NOTE 1: Only a kernel-only process (ie the swapper or direct
327 * descendants who haven't done an "execve()") should use this: it
328 * will work within a system call from a "real" process, but the
329 * process memory space will not be free'd until both the parent and
330 * the child have exited.
331 *
332 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
333 * into trouble in init/main.c when the child thread returns to
334 * do_basic_setup() and the timing is such that free_initmem() has
335 * been called already.
336 */
337 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
338
339 /* Get wait channel for task P. */
340 extern unsigned long get_wchan (struct task_struct *p);
341
342 /* Return instruction pointer of blocked task TSK. */
343 #define KSTK_EIP(tsk) \
344 ({ \
345 struct pt_regs *_regs = task_pt_regs(tsk); \
346 _regs->cr_iip + ia64_psr(_regs)->ri; \
347 })
348
349 /* Return stack pointer of blocked task TSK. */
350 #define KSTK_ESP(tsk) ((tsk)->thread.ksp)
351
352 extern void ia64_getreg_unknown_kr (void);
353 extern void ia64_setreg_unknown_kr (void);
354
355 #define ia64_get_kr(regnum) \
356 ({ \
357 unsigned long r = 0; \
358 \
359 switch (regnum) { \
360 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
361 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
362 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
363 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
364 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
365 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
366 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
367 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
368 default: ia64_getreg_unknown_kr(); break; \
369 } \
370 r; \
371 })
372
373 #define ia64_set_kr(regnum, r) \
374 ({ \
375 switch (regnum) { \
376 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
377 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
378 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
379 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
380 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
381 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
382 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
383 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
384 default: ia64_setreg_unknown_kr(); break; \
385 } \
386 })
387
388 /*
389 * The following three macros can't be inline functions because we don't have struct
390 * task_struct at this point.
391 */
392
393 /*
394 * Return TRUE if task T owns the fph partition of the CPU we're running on.
395 * Must be called from code that has preemption disabled.
396 */
397 #define ia64_is_local_fpu_owner(t) \
398 ({ \
399 struct task_struct *__ia64_islfo_task = (t); \
400 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
401 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
402 })
403
404 /*
405 * Mark task T as owning the fph partition of the CPU we're running on.
406 * Must be called from code that has preemption disabled.
407 */
408 #define ia64_set_local_fpu_owner(t) do { \
409 struct task_struct *__ia64_slfo_task = (t); \
410 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
411 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
412 } while (0)
413
414 /* Mark the fph partition of task T as being invalid on all CPUs. */
415 #define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
416
417 extern void __ia64_init_fpu (void);
418 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
419 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
420 extern void ia64_save_debug_regs (unsigned long *save_area);
421 extern void ia64_load_debug_regs (unsigned long *save_area);
422
423 #ifdef CONFIG_IA32_SUPPORT
424 extern void ia32_save_state (struct task_struct *task);
425 extern void ia32_load_state (struct task_struct *task);
426 #endif
427
428 #define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
429 #define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
430
431 /* load fp 0.0 into fph */
432 static inline void
433 ia64_init_fpu (void) {
434 ia64_fph_enable();
435 __ia64_init_fpu();
436 ia64_fph_disable();
437 }
438
439 /* save f32-f127 at FPH */
440 static inline void
441 ia64_save_fpu (struct ia64_fpreg *fph) {
442 ia64_fph_enable();
443 __ia64_save_fpu(fph);
444 ia64_fph_disable();
445 }
446
447 /* load f32-f127 from FPH */
448 static inline void
449 ia64_load_fpu (struct ia64_fpreg *fph) {
450 ia64_fph_enable();
451 __ia64_load_fpu(fph);
452 ia64_fph_disable();
453 }
454
455 static inline __u64
456 ia64_clear_ic (void)
457 {
458 __u64 psr;
459 psr = ia64_getreg(_IA64_REG_PSR);
460 ia64_stop();
461 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
462 ia64_srlz_i();
463 return psr;
464 }
465
466 /*
467 * Restore the psr.
468 */
469 static inline void
470 ia64_set_psr (__u64 psr)
471 {
472 ia64_stop();
473 ia64_setreg(_IA64_REG_PSR_L, psr);
474 ia64_srlz_d();
475 }
476
477 /*
478 * Insert a translation into an instruction and/or data translation
479 * register.
480 */
481 static inline void
482 ia64_itr (__u64 target_mask, __u64 tr_num,
483 __u64 vmaddr, __u64 pte,
484 __u64 log_page_size)
485 {
486 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
487 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
488 ia64_stop();
489 if (target_mask & 0x1)
490 ia64_itri(tr_num, pte);
491 if (target_mask & 0x2)
492 ia64_itrd(tr_num, pte);
493 }
494
495 /*
496 * Insert a translation into the instruction and/or data translation
497 * cache.
498 */
499 static inline void
500 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
501 __u64 log_page_size)
502 {
503 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
504 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
505 ia64_stop();
506 /* as per EAS2.6, itc must be the last instruction in an instruction group */
507 if (target_mask & 0x1)
508 ia64_itci(pte);
509 if (target_mask & 0x2)
510 ia64_itcd(pte);
511 }
512
513 /*
514 * Purge a range of addresses from instruction and/or data translation
515 * register(s).
516 */
517 static inline void
518 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
519 {
520 if (target_mask & 0x1)
521 ia64_ptri(vmaddr, (log_size << 2));
522 if (target_mask & 0x2)
523 ia64_ptrd(vmaddr, (log_size << 2));
524 }
525
526 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */
527 static inline void
528 ia64_set_iva (void *ivt_addr)
529 {
530 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
531 ia64_srlz_i();
532 }
533
534 /* Set the page table address and control bits. */
535 static inline void
536 ia64_set_pta (__u64 pta)
537 {
538 /* Note: srlz.i implies srlz.d */
539 ia64_setreg(_IA64_REG_CR_PTA, pta);
540 ia64_srlz_i();
541 }
542
543 static inline void
544 ia64_eoi (void)
545 {
546 ia64_setreg(_IA64_REG_CR_EOI, 0);
547 ia64_srlz_d();
548 }
549
550 #define cpu_relax() ia64_hint(ia64_hint_pause)
551
552 static inline int
553 ia64_get_irr(unsigned int vector)
554 {
555 unsigned int reg = vector / 64;
556 unsigned int bit = vector % 64;
557 u64 irr;
558
559 switch (reg) {
560 case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
561 case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
562 case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
563 case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
564 }
565
566 return test_bit(bit, &irr);
567 }
568
569 static inline void
570 ia64_set_lrr0 (unsigned long val)
571 {
572 ia64_setreg(_IA64_REG_CR_LRR0, val);
573 ia64_srlz_d();
574 }
575
576 static inline void
577 ia64_set_lrr1 (unsigned long val)
578 {
579 ia64_setreg(_IA64_REG_CR_LRR1, val);
580 ia64_srlz_d();
581 }
582
583
584 /*
585 * Given the address to which a spill occurred, return the unat bit
586 * number that corresponds to this address.
587 */
588 static inline __u64
589 ia64_unat_pos (void *spill_addr)
590 {
591 return ((__u64) spill_addr >> 3) & 0x3f;
592 }
593
594 /*
595 * Set the NaT bit of an integer register which was spilled at address
596 * SPILL_ADDR. UNAT is the mask to be updated.
597 */
598 static inline void
599 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
600 {
601 __u64 bit = ia64_unat_pos(spill_addr);
602 __u64 mask = 1UL << bit;
603
604 *unat = (*unat & ~mask) | (nat << bit);
605 }
606
607 /*
608 * Return saved PC of a blocked thread.
609 * Note that the only way T can block is through a call to schedule() -> switch_to().
610 */
611 static inline unsigned long
612 thread_saved_pc (struct task_struct *t)
613 {
614 struct unw_frame_info info;
615 unsigned long ip;
616
617 unw_init_from_blocked_task(&info, t);
618 if (unw_unwind(&info) < 0)
619 return 0;
620 unw_get_ip(&info, &ip);
621 return ip;
622 }
623
624 /*
625 * Get the current instruction/program counter value.
626 */
627 #define current_text_addr() \
628 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
629
630 static inline __u64
631 ia64_get_ivr (void)
632 {
633 __u64 r;
634 ia64_srlz_d();
635 r = ia64_getreg(_IA64_REG_CR_IVR);
636 ia64_srlz_d();
637 return r;
638 }
639
640 static inline void
641 ia64_set_dbr (__u64 regnum, __u64 value)
642 {
643 __ia64_set_dbr(regnum, value);
644 #ifdef CONFIG_ITANIUM
645 ia64_srlz_d();
646 #endif
647 }
648
649 static inline __u64
650 ia64_get_dbr (__u64 regnum)
651 {
652 __u64 retval;
653
654 retval = __ia64_get_dbr(regnum);
655 #ifdef CONFIG_ITANIUM
656 ia64_srlz_d();
657 #endif
658 return retval;
659 }
660
661 static inline __u64
662 ia64_rotr (__u64 w, __u64 n)
663 {
664 return (w >> n) | (w << (64 - n));
665 }
666
667 #define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
668
669 /*
670 * Take a mapped kernel address and return the equivalent address
671 * in the region 7 identity mapped virtual area.
672 */
673 static inline void *
674 ia64_imva (void *addr)
675 {
676 void *result;
677 result = (void *) ia64_tpa(addr);
678 return __va(result);
679 }
680
681 #define ARCH_HAS_PREFETCH
682 #define ARCH_HAS_PREFETCHW
683 #define ARCH_HAS_SPINLOCK_PREFETCH
684 #define PREFETCH_STRIDE L1_CACHE_BYTES
685
686 static inline void
687 prefetch (const void *x)
688 {
689 ia64_lfetch(ia64_lfhint_none, x);
690 }
691
692 static inline void
693 prefetchw (const void *x)
694 {
695 ia64_lfetch_excl(ia64_lfhint_none, x);
696 }
697
698 #define spin_lock_prefetch(x) prefetchw(x)
699
700 extern unsigned long boot_option_idle_override;
701
702 #endif /* !__ASSEMBLY__ */
703
704 #endif /* _ASM_IA64_PROCESSOR_H */
kernel source for telekom puls (alcatel/mediatek)