1 #ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
2 #define _ASM_GENERIC_BITOPS_ATOMIC_H_
6 #define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
7 #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
10 #include <asm/spinlock.h>
11 #include <asm/cache.h> /* we use L1_CACHE_BYTES */
13 /* Use an array of spinlocks for our atomic_ts.
14 * Hash function to index into a different SPINLOCK.
15 * Since "a" is usually an address, use one spinlock per cacheline.
17 # define ATOMIC_HASH_SIZE 4
18 # define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
20 extern raw_spinlock_t __atomic_hash
[ATOMIC_HASH_SIZE
] __lock_aligned
;
22 /* Can't use raw_spin_lock_irq because of #include problems, so
23 * this is the substitute */
24 #define _atomic_spin_lock_irqsave(l,f) do { \
25 raw_spinlock_t *s = ATOMIC_HASH(l); \
30 #define _atomic_spin_unlock_irqrestore(l,f) do { \
31 raw_spinlock_t *s = ATOMIC_HASH(l); \
32 __raw_spin_unlock(s); \
33 local_irq_restore(f); \
38 # define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
39 # define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
43 * NMI events can occur at any time, including when interrupts have been
44 * disabled by *_irqsave(). So you can get NMI events occurring while a
45 * *_bit function is holding a spin lock. If the NMI handler also wants
46 * to do bit manipulation (and they do) then you can get a deadlock
47 * between the original caller of *_bit() and the NMI handler.
53 * set_bit - Atomically set a bit in memory
55 * @addr: the address to start counting from
57 * This function is atomic and may not be reordered. See __set_bit()
58 * if you do not require the atomic guarantees.
60 * Note: there are no guarantees that this function will not be reordered
61 * on non x86 architectures, so if you are writing portable code,
62 * make sure not to rely on its reordering guarantees.
64 * Note that @nr may be almost arbitrarily large; this function is not
65 * restricted to acting on a single-word quantity.
67 static inline void set_bit(int nr
, volatile unsigned long *addr
)
69 unsigned long mask
= BITOP_MASK(nr
);
70 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
73 _atomic_spin_lock_irqsave(p
, flags
);
75 _atomic_spin_unlock_irqrestore(p
, flags
);
79 * clear_bit - Clears a bit in memory
81 * @addr: Address to start counting from
83 * clear_bit() is atomic and may not be reordered. However, it does
84 * not contain a memory barrier, so if it is used for locking purposes,
85 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
86 * in order to ensure changes are visible on other processors.
88 static inline void clear_bit(int nr
, volatile unsigned long *addr
)
90 unsigned long mask
= BITOP_MASK(nr
);
91 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
94 _atomic_spin_lock_irqsave(p
, flags
);
96 _atomic_spin_unlock_irqrestore(p
, flags
);
100 * change_bit - Toggle a bit in memory
102 * @addr: Address to start counting from
104 * change_bit() is atomic and may not be reordered. It may be
105 * reordered on other architectures than x86.
106 * Note that @nr may be almost arbitrarily large; this function is not
107 * restricted to acting on a single-word quantity.
109 static inline void change_bit(int nr
, volatile unsigned long *addr
)
111 unsigned long mask
= BITOP_MASK(nr
);
112 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
115 _atomic_spin_lock_irqsave(p
, flags
);
117 _atomic_spin_unlock_irqrestore(p
, flags
);
121 * test_and_set_bit - Set a bit and return its old value
123 * @addr: Address to count from
125 * This operation is atomic and cannot be reordered.
126 * It may be reordered on other architectures than x86.
127 * It also implies a memory barrier.
129 static inline int test_and_set_bit(int nr
, volatile unsigned long *addr
)
131 unsigned long mask
= BITOP_MASK(nr
);
132 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
136 _atomic_spin_lock_irqsave(p
, flags
);
139 _atomic_spin_unlock_irqrestore(p
, flags
);
141 return (old
& mask
) != 0;
145 * test_and_clear_bit - Clear a bit and return its old value
147 * @addr: Address to count from
149 * This operation is atomic and cannot be reordered.
150 * It can be reorderdered on other architectures other than x86.
151 * It also implies a memory barrier.
153 static inline int test_and_clear_bit(int nr
, volatile unsigned long *addr
)
155 unsigned long mask
= BITOP_MASK(nr
);
156 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
160 _atomic_spin_lock_irqsave(p
, flags
);
163 _atomic_spin_unlock_irqrestore(p
, flags
);
165 return (old
& mask
) != 0;
169 * test_and_change_bit - Change a bit and return its old value
171 * @addr: Address to count from
173 * This operation is atomic and cannot be reordered.
174 * It also implies a memory barrier.
176 static inline int test_and_change_bit(int nr
, volatile unsigned long *addr
)
178 unsigned long mask
= BITOP_MASK(nr
);
179 unsigned long *p
= ((unsigned long *)addr
) + BITOP_WORD(nr
);
183 _atomic_spin_lock_irqsave(p
, flags
);
186 _atomic_spin_unlock_irqrestore(p
, flags
);
188 return (old
& mask
) != 0;
191 #endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */