include/asm-arm/arch-pxa/regs-lcd.h

   1 #ifndef __ASM_ARCH_REGS_LCD_H
   2 #define __ASM_ARCH_REGS_LCD_H
   3
   4 #include <asm/arch/bitfield.h>
   5
   6 /*
   7  * LCD Controller Registers and Bits Definitions
   8  */
   9 #define LCCR0           (0x000) /* LCD Controller Control Register 0 */
  10 #define LCCR1           (0x004) /* LCD Controller Control Register 1 */
  11 #define LCCR2           (0x008) /* LCD Controller Control Register 2 */
  12 #define LCCR3           (0x00C) /* LCD Controller Control Register 3 */
  13 #define LCCR4           (0x010) /* LCD Controller Control Register 4 */
  14 #define LCCR5           (0x014) /* LCD Controller Control Register 5 */
  15 #define DFBR0           (0x020) /* DMA Channel 0 Frame Branch Register */
  16 #define DFBR1           (0x024) /* DMA Channel 1 Frame Branch Register */
  17 #define LCSR            (0x038) /* LCD Controller Status Register */
  18 #define LIIDR           (0x03C) /* LCD Controller Interrupt ID Register */
  19 #define TMEDRGBR        (0x040) /* TMED RGB Seed Register */
  20 #define TMEDCR          (0x044) /* TMED Control Register */
  21
  22 #define CMDCR           (0x100) /* Command Control Register */
  23 #define PRSR            (0x104) /* Panel Read Status Register */
  24
  25 #define LCCR3_1BPP      (0 << 24)
  26 #define LCCR3_2BPP      (1 << 24)
  27 #define LCCR3_4BPP      (2 << 24)
  28 #define LCCR3_8BPP      (3 << 24)
  29 #define LCCR3_16BPP     (4 << 24)
  30 #define LCCR3_18BPP     (5 << 24)
  31 #define LCCR3_18BPP_P   (6 << 24)
  32 #define LCCR3_19BPP     (7 << 24)
  33 #define LCCR3_19BPP_P   (1 << 29)
  34 #define LCCR3_24BPP     ((1 << 29) | (1 << 24))
  35 #define LCCR3_25BPP     ((1 << 29) | (2 << 24))
  36
  37 #define LCCR3_PDFOR_0   (0 << 30)
  38 #define LCCR3_PDFOR_1   (1 << 30)
  39 #define LCCR3_PDFOR_2   (2 << 30)
  40 #define LCCR3_PDFOR_3   (3 << 30)
  41
  42 #define LCCR4_PAL_FOR_0 (0 << 15)
  43 #define LCCR4_PAL_FOR_1 (1 << 15)
  44 #define LCCR4_PAL_FOR_2 (2 << 15)
  45 #define LCCR4_PAL_FOR_MASK      (3 << 15)
  46
  47 #define FDADR0          (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
  48 #define FSADR0          (0x204) /* DMA Channel 0 Frame Source Address Register */
  49 #define FIDR0           (0x208) /* DMA Channel 0 Frame ID Register */
  50 #define LDCMD0          (0x20C) /* DMA Channel 0 Command Register */
  51 #define FDADR1          (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
  52 #define FSADR1          (0x214) /* DMA Channel 1 Frame Source Address Register */
  53 #define FIDR1           (0x218) /* DMA Channel 1 Frame ID Register */
  54 #define LDCMD1          (0x21C) /* DMA Channel 1 Command Register */
  55 #define FDADR6          (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
  56 #define FSADR6          (0x264) /* DMA Channel 6 Frame Source Address Register */
  57 #define FIDR6           (0x268) /* DMA Channel 6 Frame ID Register */
  58
  59 #define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
  60 #define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
  61 #define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display */
  62 #define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display */
  63 #define LCCR0_SDS       (1 << 2)        /* Single/Dual Panel Display Select */
  64 #define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display */
  65 #define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display */
  66
  67 #define LCCR0_LDM       (1 << 3)        /* LCD Disable Done Mask */
  68 #define LCCR0_SFM       (1 << 4)        /* Start of frame mask */
  69 #define LCCR0_IUM       (1 << 5)        /* Input FIFO underrun mask */
  70 #define LCCR0_EFM       (1 << 6)        /* End of Frame mask */
  71 #define LCCR0_PAS       (1 << 7)        /* Passive/Active display Select */
  72 #define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN) */
  73 #define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT) */
  74 #define LCCR0_DPD       (1 << 9)        /* Double Pixel Data (monochrome) */
  75 #define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome display */
  76 #define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome display */
  77 #define LCCR0_DIS       (1 << 10)       /* LCD Disable */
  78 #define LCCR0_QDM       (1 << 11)       /* LCD Quick Disable mask */
  79 #define LCCR0_PDD       (0xff << 12)    /* Palette DMA request delay */
  80 #define LCCR0_PDD_S     12
  81 #define LCCR0_BM        (1 << 20)       /* Branch mask */
  82 #define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
  83 #define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
  84 #define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
  85 #define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
  86 #define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
  87 #define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
  88
  89 #define LCCR1_PPL       Fld (10, 0)     /* Pixels Per Line - 1 */
  90 #define LCCR1_DisWdth(Pixel)    (((Pixel) - 1) << FShft (LCCR1_PPL))
  91
  92 #define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization */
  93 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
  94
  95 #define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait - 1 */
  96 #define LCCR1_EndLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_ELW))
  97
  98 #define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock */
  99 #define LCCR1_BegLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_BLW))
 100
 101 #define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1 */
 102 #define LCCR2_DisHght(Line)     (((Line) - 1) << FShft (LCCR2_LPP))
 103
 104 #define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse - 1 */
 105 #define LCCR2_VrtSnchWdth(Tln)  (((Tln) - 1) << FShft (LCCR2_VSW))
 106
 107 #define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait */
 108 #define LCCR2_EndFrmDel(Tln)    ((Tln) << FShft (LCCR2_EFW))
 109
 110 #define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock */
 111 #define LCCR2_BegFrmDel(Tln)    ((Tln) << FShft (LCCR2_BFW))
 112
 113 #define LCCR3_API       (0xf << 16)     /* AC Bias pin trasitions per interrupt */
 114 #define LCCR3_API_S     16
 115 #define LCCR3_VSP       (1 << 20)       /* vertical sync polarity */
 116 #define LCCR3_HSP       (1 << 21)       /* horizontal sync polarity */
 117 #define LCCR3_PCP       (1 << 22)       /* Pixel Clock Polarity (L_PCLK) */
 118 #define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge */
 119 #define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge */
 120
 121 #define LCCR3_OEP       (1 << 23)       /* Output Enable Polarity */
 122 #define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High */
 123 #define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low */
 124
 125 #define LCCR3_DPC       (1 << 27)       /* double pixel clock mode */
 126 #define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
 127 #define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
 128
 129 #define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
 130 #define LCCR3_Bpp(Bpp)  (((Bpp) << FShft (LCCR3_BPP)))
 131
 132 #define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
 133 #define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
 134
 135 #define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  HSP Active High */
 136 #define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  HSP Active Low */
 137
 138 #define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  VSP Active High */
 139 #define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  VSP Active Low */
 140
 141 #define LCCR5_IUM(x)    (1 << ((x) + 23)) /* input underrun mask */
 142 #define LCCR5_BSM(x)    (1 << ((x) + 15)) /* branch mask */
 143 #define LCCR5_EOFM(x)   (1 << ((x) + 7))  /* end of frame mask */
 144 #define LCCR5_SOFM(x)   (1 << ((x) + 0))  /* start of frame mask */
 145
 146 #define LCSR_LDD        (1 << 0)        /* LCD Disable Done */
 147 #define LCSR_SOF        (1 << 1)        /* Start of frame */
 148 #define LCSR_BER        (1 << 2)        /* Bus error */
 149 #define LCSR_ABC        (1 << 3)        /* AC Bias count */
 150 #define LCSR_IUL        (1 << 4)        /* input FIFO underrun Lower panel */
 151 #define LCSR_IUU        (1 << 5)        /* input FIFO underrun Upper panel */
 152 #define LCSR_OU         (1 << 6)        /* output FIFO underrun */
 153 #define LCSR_QD         (1 << 7)        /* quick disable */
 154 #define LCSR_EOF        (1 << 8)        /* end of frame */
 155 #define LCSR_BS         (1 << 9)        /* branch status */
 156 #define LCSR_SINT       (1 << 10)       /* subsequent interrupt */
 157 #define LCSR_RD_ST      (1 << 11)       /* read status */
 158 #define LCSR_CMD_INT    (1 << 12)       /* command interrupt */
 159
 160 #define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
 161
 162 /* smartpanel related */
 163 #define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
 164 #define PRSR_A0         (1 << 8)        /* Read Data Source */
 165 #define PRSR_ST_OK      (1 << 9)        /* Status OK */
 166 #define PRSR_CON_NT     (1 << 10)       /* Continue to Next Command */
 167
 168 #define SMART_CMD_A0                     (0x1 << 8)
 169 #define SMART_CMD_READ_STATUS_REG        (0x0 << 9)
 170 #define SMART_CMD_READ_FRAME_BUFFER     ((0x0 << 9) | SMART_CMD_A0)
 171 #define SMART_CMD_WRITE_COMMAND          (0x1 << 9)
 172 #define SMART_CMD_WRITE_DATA            ((0x1 << 9) | SMART_CMD_A0)
 173 #define SMART_CMD_WRITE_FRAME           ((0x2 << 9) | SMART_CMD_A0)
 174 #define SMART_CMD_WAIT_FOR_VSYNC         (0x3 << 9)
 175 #define SMART_CMD_NOOP                   (0x4 << 9)
 176 #define SMART_CMD_INTERRUPT              (0x5 << 9)
 177
 178 #define SMART_CMD(x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
 179 #define SMART_DAT(x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))
 180 #endif /* __ASM_ARCH_REGS_LCD_H */