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tridentfb: improve check_var function
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / tridentfb.c
1 /*
2 * Frame buffer driver for Trident Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
17 */
18
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
27
28 #define VERSION "0.7.9-NEWAPI"
29
30 struct tridentfb_par {
31 void __iomem *io_virt; /* iospace virtual memory address */
32 u32 pseudo_pal[16];
33 int chip_id;
34 int flatpanel;
35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
37 void (*fill_rect)
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
39 void (*copy_rect)
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
41 };
42
43 static unsigned char eng_oper; /* engine operation... */
44 static struct fb_ops tridentfb_ops;
45
46 static struct fb_fix_screeninfo tridentfb_fix = {
47 .id = "Trident",
48 .type = FB_TYPE_PACKED_PIXELS,
49 .ypanstep = 1,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
52 };
53
54 /* defaults which are normally overriden by user values */
55
56 /* video mode */
57 static char *mode_option __devinitdata = "640x480";
58 static int bpp __devinitdata = 8;
59
60 static int noaccel __devinitdata;
61
62 static int center;
63 static int stretch;
64
65 static int fp __devinitdata;
66 static int crt __devinitdata;
67
68 static int memsize __devinitdata;
69 static int memdiff __devinitdata;
70 static int nativex;
71
72 module_param(mode_option, charp, 0);
73 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
74 module_param_named(mode, mode_option, charp, 0);
75 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
76 module_param(bpp, int, 0);
77 module_param(center, int, 0);
78 module_param(stretch, int, 0);
79 module_param(noaccel, int, 0);
80 module_param(memsize, int, 0);
81 module_param(memdiff, int, 0);
82 module_param(nativex, int, 0);
83 module_param(fp, int, 0);
84 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
85 module_param(crt, int, 0);
86 MODULE_PARM_DESC(crt, "Define if CRT is connected");
87
88 static int is_oldclock(int id)
89 {
90 return (id == TGUI9440) ||
91 (id == TGUI9660) ||
92 (id == CYBER9320);
93 }
94
95 static int is_oldprotect(int id)
96 {
97 return (id == TGUI9440) ||
98 (id == TGUI9660) ||
99 (id == PROVIDIA9685) ||
100 (id == CYBER9320) ||
101 (id == CYBER9382) ||
102 (id == CYBER9385);
103 }
104
105 static int is_blade(int id)
106 {
107 return (id == BLADE3D) ||
108 (id == CYBERBLADEE4) ||
109 (id == CYBERBLADEi7) ||
110 (id == CYBERBLADEi7D) ||
111 (id == CYBERBLADEi1) ||
112 (id == CYBERBLADEi1D) ||
113 (id == CYBERBLADEAi1) ||
114 (id == CYBERBLADEAi1D);
115 }
116
117 static int is_xp(int id)
118 {
119 return (id == CYBERBLADEXPAi1) ||
120 (id == CYBERBLADEXPm8) ||
121 (id == CYBERBLADEXPm16);
122 }
123
124 static int is3Dchip(int id)
125 {
126 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
127 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
128 (id == CYBER9397) || (id == CYBER9397DVD) ||
129 (id == CYBER9520) || (id == CYBER9525DVD) ||
130 (id == IMAGE975) || (id == IMAGE985) ||
131 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
132 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
133 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
134 (id == CYBERBLADEXPAi1));
135 }
136
137 static int iscyber(int id)
138 {
139 switch (id) {
140 case CYBER9388:
141 case CYBER9382:
142 case CYBER9385:
143 case CYBER9397:
144 case CYBER9397DVD:
145 case CYBER9520:
146 case CYBER9525DVD:
147 case CYBERBLADEE4:
148 case CYBERBLADEi7D:
149 case CYBERBLADEi1:
150 case CYBERBLADEi1D:
151 case CYBERBLADEAi1:
152 case CYBERBLADEAi1D:
153 case CYBERBLADEXPAi1:
154 return 1;
155
156 case CYBER9320:
157 case TGUI9660:
158 case PROVIDIA9685:
159 case IMAGE975:
160 case IMAGE985:
161 case BLADE3D:
162 case CYBERBLADEi7: /* VIA MPV4 integrated version */
163
164 default:
165 /* case CYBERBLDAEXPm8: Strange */
166 /* case CYBERBLDAEXPm16: Strange */
167 return 0;
168 }
169 }
170
171 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
172 {
173 fb_writeb(val, p->io_virt + reg);
174 }
175
176 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
177 {
178 return fb_readb(p->io_virt + reg);
179 }
180
181 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
182 {
183 fb_writel(v, par->io_virt + r);
184 }
185
186 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
187 {
188 return fb_readl(par->io_virt + r);
189 }
190
191 /*
192 * Blade specific acceleration.
193 */
194
195 #define point(x, y) ((y) << 16 | (x))
196 #define STA 0x2120
197 #define CMD 0x2144
198 #define ROP 0x2148
199 #define CLR 0x2160
200 #define SR1 0x2100
201 #define SR2 0x2104
202 #define DR1 0x2108
203 #define DR2 0x210C
204
205 #define ROP_S 0xCC
206
207 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
208 {
209 int v1 = (pitch >> 3) << 20;
210 int tmp = 0, v2;
211 switch (bpp) {
212 case 8:
213 tmp = 0;
214 break;
215 case 15:
216 tmp = 5;
217 break;
218 case 16:
219 tmp = 1;
220 break;
221 case 24:
222 case 32:
223 tmp = 2;
224 break;
225 }
226 v2 = v1 | (tmp << 29);
227 writemmr(par, 0x21C0, v2);
228 writemmr(par, 0x21C4, v2);
229 writemmr(par, 0x21B8, v2);
230 writemmr(par, 0x21BC, v2);
231 writemmr(par, 0x21D0, v1);
232 writemmr(par, 0x21D4, v1);
233 writemmr(par, 0x21C8, v1);
234 writemmr(par, 0x21CC, v1);
235 writemmr(par, 0x216C, 0);
236 }
237
238 static void blade_wait_engine(struct tridentfb_par *par)
239 {
240 while (readmmr(par, STA) & 0xFA800000) ;
241 }
242
243 static void blade_fill_rect(struct tridentfb_par *par,
244 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
245 {
246 writemmr(par, CLR, c);
247 writemmr(par, ROP, rop ? 0x66 : ROP_S);
248 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
249
250 writemmr(par, DR1, point(x, y));
251 writemmr(par, DR2, point(x + w - 1, y + h - 1));
252 }
253
254 static void blade_copy_rect(struct tridentfb_par *par,
255 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
256 {
257 u32 s1, s2, d1, d2;
258 int direction = 2;
259 s1 = point(x1, y1);
260 s2 = point(x1 + w - 1, y1 + h - 1);
261 d1 = point(x2, y2);
262 d2 = point(x2 + w - 1, y2 + h - 1);
263
264 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
265 direction = 0;
266
267 writemmr(par, ROP, ROP_S);
268 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
269
270 writemmr(par, SR1, direction ? s2 : s1);
271 writemmr(par, SR2, direction ? s1 : s2);
272 writemmr(par, DR1, direction ? d2 : d1);
273 writemmr(par, DR2, direction ? d1 : d2);
274 }
275
276 /*
277 * BladeXP specific acceleration functions
278 */
279
280 #define ROP_P 0xF0
281 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
282
283 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
284 {
285 int tmp = 0, v1;
286 unsigned char x = 0;
287
288 switch (bpp) {
289 case 8:
290 x = 0;
291 break;
292 case 16:
293 x = 1;
294 break;
295 case 24:
296 x = 3;
297 break;
298 case 32:
299 x = 2;
300 break;
301 }
302
303 switch (pitch << (bpp >> 3)) {
304 case 8192:
305 case 512:
306 x |= 0x00;
307 break;
308 case 1024:
309 x |= 0x04;
310 break;
311 case 2048:
312 x |= 0x08;
313 break;
314 case 4096:
315 x |= 0x0C;
316 break;
317 }
318
319 t_outb(par, x, 0x2125);
320
321 eng_oper = x | 0x40;
322
323 switch (bpp) {
324 case 8:
325 tmp = 18;
326 break;
327 case 15:
328 case 16:
329 tmp = 19;
330 break;
331 case 24:
332 case 32:
333 tmp = 20;
334 break;
335 }
336
337 v1 = pitch << tmp;
338
339 writemmr(par, 0x2154, v1);
340 writemmr(par, 0x2150, v1);
341 t_outb(par, 3, 0x2126);
342 }
343
344 static void xp_wait_engine(struct tridentfb_par *par)
345 {
346 int busy;
347 int count, timeout;
348
349 count = 0;
350 timeout = 0;
351 for (;;) {
352 busy = t_inb(par, STA) & 0x80;
353 if (busy != 0x80)
354 return;
355 count++;
356 if (count == 10000000) {
357 /* Timeout */
358 count = 9990000;
359 timeout++;
360 if (timeout == 8) {
361 /* Reset engine */
362 t_outb(par, 0x00, 0x2120);
363 return;
364 }
365 }
366 }
367 }
368
369 static void xp_fill_rect(struct tridentfb_par *par,
370 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
371 {
372 writemmr(par, 0x2127, ROP_P);
373 writemmr(par, 0x2158, c);
374 writemmr(par, 0x2128, 0x4000);
375 writemmr(par, 0x2140, masked_point(h, w));
376 writemmr(par, 0x2138, masked_point(y, x));
377 t_outb(par, 0x01, 0x2124);
378 t_outb(par, eng_oper, 0x2125);
379 }
380
381 static void xp_copy_rect(struct tridentfb_par *par,
382 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
383 {
384 int direction;
385 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
386
387 direction = 0x0004;
388
389 if ((x1 < x2) && (y1 == y2)) {
390 direction |= 0x0200;
391 x1_tmp = x1 + w - 1;
392 x2_tmp = x2 + w - 1;
393 } else {
394 x1_tmp = x1;
395 x2_tmp = x2;
396 }
397
398 if (y1 < y2) {
399 direction |= 0x0100;
400 y1_tmp = y1 + h - 1;
401 y2_tmp = y2 + h - 1;
402 } else {
403 y1_tmp = y1;
404 y2_tmp = y2;
405 }
406
407 writemmr(par, 0x2128, direction);
408 t_outb(par, ROP_S, 0x2127);
409 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
410 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
411 writemmr(par, 0x2140, masked_point(h, w));
412 t_outb(par, 0x01, 0x2124);
413 }
414
415 /*
416 * Image specific acceleration functions
417 */
418 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
419 {
420 int tmp = 0;
421 switch (bpp) {
422 case 8:
423 tmp = 0;
424 break;
425 case 15:
426 tmp = 5;
427 break;
428 case 16:
429 tmp = 1;
430 break;
431 case 24:
432 case 32:
433 tmp = 2;
434 break;
435 }
436 writemmr(par, 0x2120, 0xF0000000);
437 writemmr(par, 0x2120, 0x40000000 | tmp);
438 writemmr(par, 0x2120, 0x80000000);
439 writemmr(par, 0x2144, 0x00000000);
440 writemmr(par, 0x2148, 0x00000000);
441 writemmr(par, 0x2150, 0x00000000);
442 writemmr(par, 0x2154, 0x00000000);
443 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
444 writemmr(par, 0x216C, 0x00000000);
445 writemmr(par, 0x2170, 0x00000000);
446 writemmr(par, 0x217C, 0x00000000);
447 writemmr(par, 0x2120, 0x10000000);
448 writemmr(par, 0x2130, (2047 << 16) | 2047);
449 }
450
451 static void image_wait_engine(struct tridentfb_par *par)
452 {
453 while (readmmr(par, 0x2164) & 0xF0000000) ;
454 }
455
456 static void image_fill_rect(struct tridentfb_par *par,
457 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
458 {
459 writemmr(par, 0x2120, 0x80000000);
460 writemmr(par, 0x2120, 0x90000000 | ROP_S);
461
462 writemmr(par, 0x2144, c);
463
464 writemmr(par, DR1, point(x, y));
465 writemmr(par, DR2, point(x + w - 1, y + h - 1));
466
467 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
468 }
469
470 static void image_copy_rect(struct tridentfb_par *par,
471 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
472 {
473 u32 s1, s2, d1, d2;
474 int direction = 2;
475 s1 = point(x1, y1);
476 s2 = point(x1 + w - 1, y1 + h - 1);
477 d1 = point(x2, y2);
478 d2 = point(x2 + w - 1, y2 + h - 1);
479
480 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
481 direction = 0;
482
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2120, 0x90000000 | ROP_S);
485
486 writemmr(par, SR1, direction ? s2 : s1);
487 writemmr(par, SR2, direction ? s1 : s2);
488 writemmr(par, DR1, direction ? d2 : d1);
489 writemmr(par, DR2, direction ? d1 : d2);
490 writemmr(par, 0x2124,
491 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
492 }
493
494 /*
495 * Accel functions called by the upper layers
496 */
497 #ifdef CONFIG_FB_TRIDENT_ACCEL
498 static void tridentfb_fillrect(struct fb_info *info,
499 const struct fb_fillrect *fr)
500 {
501 struct tridentfb_par *par = info->par;
502 int bpp = info->var.bits_per_pixel;
503 int col = 0;
504
505 switch (bpp) {
506 default:
507 case 8:
508 col |= fr->color;
509 col |= col << 8;
510 col |= col << 16;
511 break;
512 case 16:
513 col = ((u32 *)(info->pseudo_palette))[fr->color];
514 break;
515 case 32:
516 col = ((u32 *)(info->pseudo_palette))[fr->color];
517 break;
518 }
519
520 par->fill_rect(par, fr->dx, fr->dy, fr->width,
521 fr->height, col, fr->rop);
522 par->wait_engine(par);
523 }
524 static void tridentfb_copyarea(struct fb_info *info,
525 const struct fb_copyarea *ca)
526 {
527 struct tridentfb_par *par = info->par;
528
529 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
530 ca->width, ca->height);
531 par->wait_engine(par);
532 }
533 #else /* !CONFIG_FB_TRIDENT_ACCEL */
534 #define tridentfb_fillrect cfb_fillrect
535 #define tridentfb_copyarea cfb_copyarea
536 #endif /* CONFIG_FB_TRIDENT_ACCEL */
537
538
539 /*
540 * Hardware access functions
541 */
542
543 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
544 {
545 return vga_mm_rcrt(par->io_virt, reg);
546 }
547
548 static inline void write3X4(struct tridentfb_par *par, int reg,
549 unsigned char val)
550 {
551 vga_mm_wcrt(par->io_virt, reg, val);
552 }
553
554 static inline unsigned char read3CE(struct tridentfb_par *par,
555 unsigned char reg)
556 {
557 return vga_mm_rgfx(par->io_virt, reg);
558 }
559
560 static inline void writeAttr(struct tridentfb_par *par, int reg,
561 unsigned char val)
562 {
563 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
564 vga_mm_wattr(par->io_virt, reg, val);
565 }
566
567 static inline void write3CE(struct tridentfb_par *par, int reg,
568 unsigned char val)
569 {
570 vga_mm_wgfx(par->io_virt, reg, val);
571 }
572
573 static void enable_mmio(void)
574 {
575 /* Goto New Mode */
576 vga_io_rseq(0x0B);
577
578 /* Unprotect registers */
579 vga_io_wseq(NewMode1, 0x80);
580
581 /* Enable MMIO */
582 outb(PCIReg, 0x3D4);
583 outb(inb(0x3D5) | 0x01, 0x3D5);
584 }
585
586 static void disable_mmio(struct tridentfb_par *par)
587 {
588 /* Goto New Mode */
589 vga_mm_rseq(par->io_virt, 0x0B);
590
591 /* Unprotect registers */
592 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
593
594 /* Disable MMIO */
595 t_outb(par, PCIReg, 0x3D4);
596 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
597 }
598
599 static void crtc_unlock(struct tridentfb_par *par)
600 {
601 write3X4(par, VGA_CRTC_V_SYNC_END,
602 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
603 }
604
605 /* Return flat panel's maximum x resolution */
606 static int __devinit get_nativex(struct tridentfb_par *par)
607 {
608 int x, y, tmp;
609
610 if (nativex)
611 return nativex;
612
613 tmp = (read3CE(par, VertStretch) >> 4) & 3;
614
615 switch (tmp) {
616 case 0:
617 x = 1280; y = 1024;
618 break;
619 case 2:
620 x = 1024; y = 768;
621 break;
622 case 3:
623 x = 800; y = 600;
624 break;
625 case 4:
626 x = 1400; y = 1050;
627 break;
628 case 1:
629 default:
630 x = 640; y = 480;
631 break;
632 }
633
634 output("%dx%d flat panel found\n", x, y);
635 return x;
636 }
637
638 /* Set pitch */
639 static void set_lwidth(struct tridentfb_par *par, int width)
640 {
641 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
642 write3X4(par, AddColReg,
643 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
644 }
645
646 /* For resolutions smaller than FP resolution stretch */
647 static void screen_stretch(struct tridentfb_par *par)
648 {
649 if (par->chip_id != CYBERBLADEXPAi1)
650 write3CE(par, BiosReg, 0);
651 else
652 write3CE(par, BiosReg, 8);
653 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
654 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
655 }
656
657 /* For resolutions smaller than FP resolution center */
658 static void screen_center(struct tridentfb_par *par)
659 {
660 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
661 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
662 }
663
664 /* Address of first shown pixel in display memory */
665 static void set_screen_start(struct tridentfb_par *par, int base)
666 {
667 u8 tmp;
668 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
669 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
670 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
671 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
672 tmp = read3X4(par, CRTHiOrd) & 0xF8;
673 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
674 }
675
676 /* Set dotclock frequency */
677 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
678 {
679 int m, n, k;
680 unsigned long fi, d, di;
681 unsigned char best_m = 0, best_n = 0, best_k = 0;
682 unsigned char hi, lo;
683
684 d = 20000;
685 for (k = 1; k >= 0; k--)
686 for (m = 0; m < 32; m++)
687 for (n = 0; n < 122; n++) {
688 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
689 if ((di = abs(fi - freq)) < d) {
690 d = di;
691 best_n = n;
692 best_m = m;
693 best_k = k;
694 }
695 if (fi > freq)
696 break;
697 }
698
699 if (is_oldclock(par->chip_id)) {
700 lo = best_n | (best_m << 7);
701 hi = (best_m >> 1) | (best_k << 4);
702 } else {
703 lo = best_n;
704 hi = best_m | (best_k << 6);
705 }
706
707 if (is3Dchip(par->chip_id)) {
708 vga_mm_wseq(par->io_virt, ClockHigh, hi);
709 vga_mm_wseq(par->io_virt, ClockLow, lo);
710 } else {
711 t_outb(par, lo, 0x43C8);
712 t_outb(par, hi, 0x43C9);
713 }
714 debug("VCLK = %X %X\n", hi, lo);
715 }
716
717 /* Set number of lines for flat panels*/
718 static void set_number_of_lines(struct tridentfb_par *par, int lines)
719 {
720 int tmp = read3CE(par, CyberEnhance) & 0x8F;
721 if (lines > 1024)
722 tmp |= 0x50;
723 else if (lines > 768)
724 tmp |= 0x30;
725 else if (lines > 600)
726 tmp |= 0x20;
727 else if (lines > 480)
728 tmp |= 0x10;
729 write3CE(par, CyberEnhance, tmp);
730 }
731
732 /*
733 * If we see that FP is active we assume we have one.
734 * Otherwise we have a CRT display. User can override.
735 */
736 static int __devinit is_flatpanel(struct tridentfb_par *par)
737 {
738 if (fp)
739 return 1;
740 if (crt || !iscyber(par->chip_id))
741 return 0;
742 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
743 }
744
745 /* Try detecting the video memory size */
746 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
747 {
748 unsigned char tmp, tmp2;
749 unsigned int k;
750
751 /* If memory size provided by user */
752 if (memsize)
753 k = memsize * Kb;
754 else
755 switch (par->chip_id) {
756 case CYBER9525DVD:
757 k = 2560 * Kb;
758 break;
759 default:
760 tmp = read3X4(par, SPR) & 0x0F;
761 switch (tmp) {
762
763 case 0x01:
764 k = 512 * Kb;
765 break;
766 case 0x02:
767 k = 6 * Mb; /* XP */
768 break;
769 case 0x03:
770 k = 1 * Mb;
771 break;
772 case 0x04:
773 k = 8 * Mb;
774 break;
775 case 0x06:
776 k = 10 * Mb; /* XP */
777 break;
778 case 0x07:
779 k = 2 * Mb;
780 break;
781 case 0x08:
782 k = 12 * Mb; /* XP */
783 break;
784 case 0x0A:
785 k = 14 * Mb; /* XP */
786 break;
787 case 0x0C:
788 k = 16 * Mb; /* XP */
789 break;
790 case 0x0E: /* XP */
791
792 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
793 switch (tmp2) {
794 case 0x00:
795 k = 20 * Mb;
796 break;
797 case 0x01:
798 k = 24 * Mb;
799 break;
800 case 0x10:
801 k = 28 * Mb;
802 break;
803 case 0x11:
804 k = 32 * Mb;
805 break;
806 default:
807 k = 1 * Mb;
808 break;
809 }
810 break;
811
812 case 0x0F:
813 k = 4 * Mb;
814 break;
815 default:
816 k = 1 * Mb;
817 break;
818 }
819 }
820
821 k -= memdiff * Kb;
822 output("framebuffer size = %d Kb\n", k / Kb);
823 return k;
824 }
825
826 /* See if we can handle the video mode described in var */
827 static int tridentfb_check_var(struct fb_var_screeninfo *var,
828 struct fb_info *info)
829 {
830 struct tridentfb_par *par = info->par;
831 int bpp = var->bits_per_pixel;
832 int ramdac = 230000; /* 230MHz for most 3D chips */
833 debug("enter\n");
834
835 /* check color depth */
836 if (bpp == 24)
837 bpp = var->bits_per_pixel = 32;
838 /* check whether resolution fits on panel and in memory */
839 if (par->flatpanel && nativex && var->xres > nativex)
840 return -EINVAL;
841 /* various resolution checks */
842 var->xres = (var->xres + 7) & ~0x7;
843 if (var->xres != var->xres_virtual)
844 var->xres_virtual = var->xres;
845 if (var->yres > var->yres_virtual)
846 var->yres_virtual = var->yres;
847 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
848 return -EINVAL;
849
850 switch (bpp) {
851 case 8:
852 var->red.offset = 0;
853 var->green.offset = 0;
854 var->blue.offset = 0;
855 var->red.length = 6;
856 var->green.length = 6;
857 var->blue.length = 6;
858 break;
859 case 16:
860 var->red.offset = 11;
861 var->green.offset = 5;
862 var->blue.offset = 0;
863 var->red.length = 5;
864 var->green.length = 6;
865 var->blue.length = 5;
866 break;
867 case 32:
868 var->red.offset = 16;
869 var->green.offset = 8;
870 var->blue.offset = 0;
871 var->red.length = 8;
872 var->green.length = 8;
873 var->blue.length = 8;
874 break;
875 default:
876 return -EINVAL;
877 }
878
879 if (is_xp(par->chip_id))
880 ramdac = 350000;
881
882 switch (par->chip_id) {
883 case TGUI9440:
884 ramdac = 90000;
885 break;
886 case CYBER9320:
887 case TGUI9660:
888 ramdac = 135000;
889 break;
890 case PROVIDIA9685:
891 case CYBER9388:
892 case CYBER9382:
893 case CYBER9385:
894 ramdac = 170000;
895 break;
896 }
897
898 /* The clock is doubled for 32 bpp */
899 if (bpp == 32)
900 ramdac /= 2;
901
902 if (PICOS2KHZ(var->pixclock) > ramdac)
903 return -EINVAL;
904
905 debug("exit\n");
906
907 return 0;
908
909 }
910
911 /* Pan the display */
912 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
913 struct fb_info *info)
914 {
915 struct tridentfb_par *par = info->par;
916 unsigned int offset;
917
918 debug("enter\n");
919 offset = (var->xoffset + (var->yoffset * var->xres))
920 * var->bits_per_pixel / 32;
921 info->var.xoffset = var->xoffset;
922 info->var.yoffset = var->yoffset;
923 set_screen_start(par, offset);
924 debug("exit\n");
925 return 0;
926 }
927
928 static void shadowmode_on(struct tridentfb_par *par)
929 {
930 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
931 }
932
933 static void shadowmode_off(struct tridentfb_par *par)
934 {
935 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
936 }
937
938 /* Set the hardware to the requested video mode */
939 static int tridentfb_set_par(struct fb_info *info)
940 {
941 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
942 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
943 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
944 struct fb_var_screeninfo *var = &info->var;
945 int bpp = var->bits_per_pixel;
946 unsigned char tmp;
947 unsigned long vclk;
948
949 debug("enter\n");
950 hdispend = var->xres / 8 - 1;
951 hsyncstart = (var->xres + var->right_margin) / 8 - 1;
952 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1;
953 htotal = (var->xres + var->left_margin + var->right_margin +
954 var->hsync_len) / 8 - 5;
955 hblankstart = hdispend + 1;
956 hblankend = htotal + 3;
957
958 vdispend = var->yres - 1;
959 vsyncstart = var->yres + var->lower_margin;
960 vsyncend = vsyncstart + var->vsync_len;
961 vtotal = var->upper_margin + vsyncend - 2;
962 vblankstart = vdispend + 1;
963 vblankend = vtotal;
964
965 crtc_unlock(par);
966 write3CE(par, CyberControl, 8);
967
968 if (par->flatpanel && var->xres < nativex) {
969 /*
970 * on flat panels with native size larger
971 * than requested resolution decide whether
972 * we stretch or center
973 */
974 t_outb(par, 0xEB, VGA_MIS_W);
975
976 shadowmode_on(par);
977
978 if (center)
979 screen_center(par);
980 else if (stretch)
981 screen_stretch(par);
982
983 } else {
984 t_outb(par, 0x2B, VGA_MIS_W);
985 write3CE(par, CyberControl, 8);
986 }
987
988 /* vertical timing values */
989 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
990 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
991 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
992 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
993 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
994 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
995
996 /* horizontal timing values */
997 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
998 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
999 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1000 write3X4(par, VGA_CRTC_H_SYNC_END,
1001 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1002 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1003 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1004
1005 /* higher bits of vertical timing values */
1006 tmp = 0x10;
1007 if (vtotal & 0x100) tmp |= 0x01;
1008 if (vdispend & 0x100) tmp |= 0x02;
1009 if (vsyncstart & 0x100) tmp |= 0x04;
1010 if (vblankstart & 0x100) tmp |= 0x08;
1011
1012 if (vtotal & 0x200) tmp |= 0x20;
1013 if (vdispend & 0x200) tmp |= 0x40;
1014 if (vsyncstart & 0x200) tmp |= 0x80;
1015 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1016
1017 tmp = read3X4(par, CRTHiOrd) & 0x07;
1018 tmp |= 0x08; /* line compare bit 10 */
1019 if (vtotal & 0x400) tmp |= 0x80;
1020 if (vblankstart & 0x400) tmp |= 0x40;
1021 if (vsyncstart & 0x400) tmp |= 0x20;
1022 if (vdispend & 0x400) tmp |= 0x10;
1023 write3X4(par, CRTHiOrd, tmp);
1024
1025 tmp = (htotal >> 8) & 0x01;
1026 tmp |= (hdispend >> 7) & 0x02;
1027 tmp |= (hsyncstart >> 5) & 0x08;
1028 tmp |= (hblankstart >> 4) & 0x10;
1029 write3X4(par, HorizOverflow, tmp);
1030
1031 tmp = 0x40;
1032 if (vblankstart & 0x200) tmp |= 0x20;
1033 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1034 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1035
1036 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1037 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1038 write3X4(par, VGA_CRTC_MODE, 0xC3);
1039
1040 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1041
1042 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1043 /* enable access extended memory */
1044 write3X4(par, CRTCModuleTest, tmp);
1045
1046 /* enable GE for text acceleration */
1047 write3X4(par, GraphEngReg, 0x80);
1048
1049 #ifdef CONFIG_FB_TRIDENT_ACCEL
1050 par->init_accel(par, info->var.xres, bpp);
1051 #endif
1052
1053 switch (bpp) {
1054 case 8:
1055 tmp = 0x00;
1056 break;
1057 case 16:
1058 tmp = 0x05;
1059 break;
1060 case 24:
1061 tmp = 0x29;
1062 break;
1063 case 32:
1064 tmp = 0x09;
1065 break;
1066 }
1067
1068 write3X4(par, PixelBusReg, tmp);
1069
1070 tmp = read3X4(par, DRAMControl);
1071 if (!is_oldprotect(par->chip_id))
1072 tmp |= 0x10;
1073 if (iscyber(par->chip_id))
1074 tmp |= 0x20;
1075 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1076
1077 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1078 if (!is_xp(par->chip_id))
1079 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1080 /* MMIO & PCI read and write burst enable */
1081 if (par->chip_id != TGUI9440)
1082 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1083
1084 /* convert from picoseconds to kHz */
1085 vclk = PICOS2KHZ(info->var.pixclock);
1086 if (bpp == 32)
1087 vclk *= 2;
1088 set_vclk(par, vclk);
1089
1090 vga_mm_wseq(par->io_virt, 0, 3);
1091 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1092 /* enable 4 maps because needed in chain4 mode */
1093 vga_mm_wseq(par->io_virt, 2, 0x0F);
1094 vga_mm_wseq(par->io_virt, 3, 0);
1095 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1096
1097 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1098 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1099 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1100 write3CE(par, 0x6, 0x05); /* graphics mode */
1101 write3CE(par, 0x7, 0x0F); /* planes? */
1102
1103 if (par->chip_id == CYBERBLADEXPAi1) {
1104 /* This fixes snow-effect in 32 bpp */
1105 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1106 }
1107
1108 /* graphics mode and support 256 color modes */
1109 writeAttr(par, 0x10, 0x41);
1110 writeAttr(par, 0x12, 0x0F); /* planes */
1111 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1112
1113 /* colors */
1114 for (tmp = 0; tmp < 0x10; tmp++)
1115 writeAttr(par, tmp, tmp);
1116 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1117 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1118
1119 switch (bpp) {
1120 case 8:
1121 tmp = 0;
1122 break;
1123 case 15:
1124 tmp = 0x10;
1125 break;
1126 case 16:
1127 tmp = 0x30;
1128 break;
1129 case 24:
1130 case 32:
1131 tmp = 0xD0;
1132 break;
1133 }
1134
1135 t_inb(par, VGA_PEL_IW);
1136 t_inb(par, VGA_PEL_MSK);
1137 t_inb(par, VGA_PEL_MSK);
1138 t_inb(par, VGA_PEL_MSK);
1139 t_inb(par, VGA_PEL_MSK);
1140 t_outb(par, tmp, VGA_PEL_MSK);
1141 t_inb(par, VGA_PEL_IW);
1142
1143 if (par->flatpanel)
1144 set_number_of_lines(par, info->var.yres);
1145 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1146 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1147 info->fix.line_length = info->var.xres * (bpp >> 3);
1148 info->cmap.len = (bpp == 8) ? 256 : 16;
1149 debug("exit\n");
1150 return 0;
1151 }
1152
1153 /* Set one color register */
1154 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1155 unsigned blue, unsigned transp,
1156 struct fb_info *info)
1157 {
1158 int bpp = info->var.bits_per_pixel;
1159 struct tridentfb_par *par = info->par;
1160
1161 if (regno >= info->cmap.len)
1162 return 1;
1163
1164 if (bpp == 8) {
1165 t_outb(par, 0xFF, VGA_PEL_MSK);
1166 t_outb(par, regno, VGA_PEL_IW);
1167
1168 t_outb(par, red >> 10, VGA_PEL_D);
1169 t_outb(par, green >> 10, VGA_PEL_D);
1170 t_outb(par, blue >> 10, VGA_PEL_D);
1171
1172 } else if (regno < 16) {
1173 if (bpp == 16) { /* RGB 565 */
1174 u32 col;
1175
1176 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1177 ((blue & 0xF800) >> 11);
1178 col |= col << 16;
1179 ((u32 *)(info->pseudo_palette))[regno] = col;
1180 } else if (bpp == 32) /* ARGB 8888 */
1181 ((u32*)info->pseudo_palette)[regno] =
1182 ((transp & 0xFF00) << 16) |
1183 ((red & 0xFF00) << 8) |
1184 ((green & 0xFF00)) |
1185 ((blue & 0xFF00) >> 8);
1186 }
1187
1188 /* debug("exit\n"); */
1189 return 0;
1190 }
1191
1192 /* Try blanking the screen.For flat panels it does nothing */
1193 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1194 {
1195 unsigned char PMCont, DPMSCont;
1196 struct tridentfb_par *par = info->par;
1197
1198 debug("enter\n");
1199 if (par->flatpanel)
1200 return 0;
1201 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1202 PMCont = t_inb(par, 0x83C6) & 0xFC;
1203 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1204 switch (blank_mode) {
1205 case FB_BLANK_UNBLANK:
1206 /* Screen: On, HSync: On, VSync: On */
1207 case FB_BLANK_NORMAL:
1208 /* Screen: Off, HSync: On, VSync: On */
1209 PMCont |= 0x03;
1210 DPMSCont |= 0x00;
1211 break;
1212 case FB_BLANK_HSYNC_SUSPEND:
1213 /* Screen: Off, HSync: Off, VSync: On */
1214 PMCont |= 0x02;
1215 DPMSCont |= 0x01;
1216 break;
1217 case FB_BLANK_VSYNC_SUSPEND:
1218 /* Screen: Off, HSync: On, VSync: Off */
1219 PMCont |= 0x02;
1220 DPMSCont |= 0x02;
1221 break;
1222 case FB_BLANK_POWERDOWN:
1223 /* Screen: Off, HSync: Off, VSync: Off */
1224 PMCont |= 0x00;
1225 DPMSCont |= 0x03;
1226 break;
1227 }
1228
1229 write3CE(par, PowerStatus, DPMSCont);
1230 t_outb(par, 4, 0x83C8);
1231 t_outb(par, PMCont, 0x83C6);
1232
1233 debug("exit\n");
1234
1235 /* let fbcon do a softblank for us */
1236 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1237 }
1238
1239 static struct fb_ops tridentfb_ops = {
1240 .owner = THIS_MODULE,
1241 .fb_setcolreg = tridentfb_setcolreg,
1242 .fb_pan_display = tridentfb_pan_display,
1243 .fb_blank = tridentfb_blank,
1244 .fb_check_var = tridentfb_check_var,
1245 .fb_set_par = tridentfb_set_par,
1246 .fb_fillrect = tridentfb_fillrect,
1247 .fb_copyarea = tridentfb_copyarea,
1248 .fb_imageblit = cfb_imageblit,
1249 };
1250
1251 static int __devinit trident_pci_probe(struct pci_dev *dev,
1252 const struct pci_device_id *id)
1253 {
1254 int err;
1255 unsigned char revision;
1256 struct fb_info *info;
1257 struct tridentfb_par *default_par;
1258 int defaultaccel;
1259 int chip3D;
1260 int chip_id;
1261
1262 err = pci_enable_device(dev);
1263 if (err)
1264 return err;
1265
1266 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1267 if (!info)
1268 return -ENOMEM;
1269 default_par = info->par;
1270
1271 chip_id = id->device;
1272
1273 if (chip_id == CYBERBLADEi1)
1274 output("*** Please do use cyblafb, Cyberblade/i1 support "
1275 "will soon be removed from tridentfb!\n");
1276
1277
1278 /* If PCI id is 0x9660 then further detect chip type */
1279
1280 if (chip_id == TGUI9660) {
1281 revision = vga_io_rseq(RevisionID);
1282
1283 switch (revision) {
1284 case 0x21:
1285 chip_id = PROVIDIA9685;
1286 break;
1287 case 0x22:
1288 case 0x23:
1289 chip_id = CYBER9397;
1290 break;
1291 case 0x2A:
1292 chip_id = CYBER9397DVD;
1293 break;
1294 case 0x30:
1295 case 0x33:
1296 case 0x34:
1297 case 0x35:
1298 case 0x38:
1299 case 0x3A:
1300 case 0xB3:
1301 chip_id = CYBER9385;
1302 break;
1303 case 0x40 ... 0x43:
1304 chip_id = CYBER9382;
1305 break;
1306 case 0x4A:
1307 chip_id = CYBER9388;
1308 break;
1309 default:
1310 break;
1311 }
1312 }
1313
1314 chip3D = is3Dchip(chip_id);
1315
1316 if (is_xp(chip_id)) {
1317 default_par->init_accel = xp_init_accel;
1318 default_par->wait_engine = xp_wait_engine;
1319 default_par->fill_rect = xp_fill_rect;
1320 default_par->copy_rect = xp_copy_rect;
1321 } else if (is_blade(chip_id)) {
1322 default_par->init_accel = blade_init_accel;
1323 default_par->wait_engine = blade_wait_engine;
1324 default_par->fill_rect = blade_fill_rect;
1325 default_par->copy_rect = blade_copy_rect;
1326 } else {
1327 default_par->init_accel = image_init_accel;
1328 default_par->wait_engine = image_wait_engine;
1329 default_par->fill_rect = image_fill_rect;
1330 default_par->copy_rect = image_copy_rect;
1331 }
1332
1333 default_par->chip_id = chip_id;
1334
1335 /* acceleration is on by default for 3D chips */
1336 defaultaccel = chip3D && !noaccel;
1337
1338 /* setup MMIO region */
1339 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1340 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1341
1342 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1343 debug("request_region failed!\n");
1344 framebuffer_release(info);
1345 return -1;
1346 }
1347
1348 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1349 tridentfb_fix.mmio_len);
1350
1351 if (!default_par->io_virt) {
1352 debug("ioremap failed\n");
1353 err = -1;
1354 goto out_unmap1;
1355 }
1356
1357 /* setup framebuffer memory */
1358 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1359 tridentfb_fix.smem_len = get_memsize(default_par);
1360
1361 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1362 debug("request_mem_region failed!\n");
1363 disable_mmio(info->par);
1364 err = -1;
1365 goto out_unmap1;
1366 }
1367
1368 enable_mmio();
1369
1370 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1371 tridentfb_fix.smem_len);
1372
1373 if (!info->screen_base) {
1374 debug("ioremap failed\n");
1375 err = -1;
1376 goto out_unmap2;
1377 }
1378
1379 output("%s board found\n", pci_name(dev));
1380 default_par->flatpanel = is_flatpanel(default_par);
1381
1382 if (default_par->flatpanel)
1383 nativex = get_nativex(default_par);
1384
1385 info->fix = tridentfb_fix;
1386 info->fbops = &tridentfb_ops;
1387 info->pseudo_palette = default_par->pseudo_pal;
1388
1389 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1390 #ifdef CONFIG_FB_TRIDENT_ACCEL
1391 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1392 #endif
1393 if (!fb_find_mode(&info->var, info,
1394 mode_option, NULL, 0, NULL, bpp)) {
1395 err = -EINVAL;
1396 goto out_unmap2;
1397 }
1398 err = fb_alloc_cmap(&info->cmap, 256, 0);
1399 if (err < 0)
1400 goto out_unmap2;
1401
1402 if (defaultaccel && default_par->init_accel)
1403 info->var.accel_flags |= FB_ACCELF_TEXT;
1404 else
1405 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1406 info->var.activate |= FB_ACTIVATE_NOW;
1407 info->device = &dev->dev;
1408 if (register_framebuffer(info) < 0) {
1409 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1410 fb_dealloc_cmap(&info->cmap);
1411 err = -EINVAL;
1412 goto out_unmap2;
1413 }
1414 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1415 info->node, info->fix.id, info->var.xres,
1416 info->var.yres, info->var.bits_per_pixel);
1417
1418 pci_set_drvdata(dev, info);
1419 return 0;
1420
1421 out_unmap2:
1422 if (info->screen_base)
1423 iounmap(info->screen_base);
1424 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1425 disable_mmio(info->par);
1426 out_unmap1:
1427 if (default_par->io_virt)
1428 iounmap(default_par->io_virt);
1429 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1430 framebuffer_release(info);
1431 return err;
1432 }
1433
1434 static void __devexit trident_pci_remove(struct pci_dev *dev)
1435 {
1436 struct fb_info *info = pci_get_drvdata(dev);
1437 struct tridentfb_par *par = info->par;
1438
1439 unregister_framebuffer(info);
1440 iounmap(par->io_virt);
1441 iounmap(info->screen_base);
1442 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1443 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1444 pci_set_drvdata(dev, NULL);
1445 framebuffer_release(info);
1446 }
1447
1448 /* List of boards that we are trying to support */
1449 static struct pci_device_id trident_devices[] = {
1450 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1451 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1452 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1453 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1454 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1455 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1456 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1457 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1458 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1459 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1460 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1461 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1462 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1463 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1464 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1465 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1466 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1467 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1468 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1469 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1470 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1471 {0,}
1472 };
1473
1474 MODULE_DEVICE_TABLE(pci, trident_devices);
1475
1476 static struct pci_driver tridentfb_pci_driver = {
1477 .name = "tridentfb",
1478 .id_table = trident_devices,
1479 .probe = trident_pci_probe,
1480 .remove = __devexit_p(trident_pci_remove)
1481 };
1482
1483 /*
1484 * Parse user specified options (`video=trident:')
1485 * example:
1486 * video=trident:800x600,bpp=16,noaccel
1487 */
1488 #ifndef MODULE
1489 static int __init tridentfb_setup(char *options)
1490 {
1491 char *opt;
1492 if (!options || !*options)
1493 return 0;
1494 while ((opt = strsep(&options, ",")) != NULL) {
1495 if (!*opt)
1496 continue;
1497 if (!strncmp(opt, "noaccel", 7))
1498 noaccel = 1;
1499 else if (!strncmp(opt, "fp", 2))
1500 fp = 1;
1501 else if (!strncmp(opt, "crt", 3))
1502 fp = 0;
1503 else if (!strncmp(opt, "bpp=", 4))
1504 bpp = simple_strtoul(opt + 4, NULL, 0);
1505 else if (!strncmp(opt, "center", 6))
1506 center = 1;
1507 else if (!strncmp(opt, "stretch", 7))
1508 stretch = 1;
1509 else if (!strncmp(opt, "memsize=", 8))
1510 memsize = simple_strtoul(opt + 8, NULL, 0);
1511 else if (!strncmp(opt, "memdiff=", 8))
1512 memdiff = simple_strtoul(opt + 8, NULL, 0);
1513 else if (!strncmp(opt, "nativex=", 8))
1514 nativex = simple_strtoul(opt + 8, NULL, 0);
1515 else
1516 mode_option = opt;
1517 }
1518 return 0;
1519 }
1520 #endif
1521
1522 static int __init tridentfb_init(void)
1523 {
1524 #ifndef MODULE
1525 char *option = NULL;
1526
1527 if (fb_get_options("tridentfb", &option))
1528 return -ENODEV;
1529 tridentfb_setup(option);
1530 #endif
1531 output("Trident framebuffer %s initializing\n", VERSION);
1532 return pci_register_driver(&tridentfb_pci_driver);
1533 }
1534
1535 static void __exit tridentfb_exit(void)
1536 {
1537 pci_unregister_driver(&tridentfb_pci_driver);
1538 }
1539
1540 module_init(tridentfb_init);
1541 module_exit(tridentfb_exit);
1542
1543 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1544 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1545 MODULE_LICENSE("GPL");
1546
kernel source for telekom puls (alcatel/mediatek)