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tridentfb: acceleration constants change
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / tridentfb.c
1 /*
2 * Frame buffer driver for Trident TGUI, Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 */
17
18 #include <linux/module.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
26
27 #define VERSION "0.7.9-NEWAPI"
28
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
31 u32 pseudo_pal[16];
32 int chip_id;
33 int flatpanel;
34 void (*init_accel) (struct tridentfb_par *, int, int);
35 void (*wait_engine) (struct tridentfb_par *);
36 void (*fill_rect)
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 void (*copy_rect)
39 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 };
41
42 static unsigned char eng_oper; /* engine operation... */
43 static struct fb_ops tridentfb_ops;
44
45 static struct fb_fix_screeninfo tridentfb_fix = {
46 .id = "Trident",
47 .type = FB_TYPE_PACKED_PIXELS,
48 .ypanstep = 1,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
51 };
52
53 /* defaults which are normally overriden by user values */
54
55 /* video mode */
56 static char *mode_option __devinitdata = "640x480";
57 static int bpp __devinitdata = 8;
58
59 static int noaccel __devinitdata;
60
61 static int center;
62 static int stretch;
63
64 static int fp __devinitdata;
65 static int crt __devinitdata;
66
67 static int memsize __devinitdata;
68 static int memdiff __devinitdata;
69 static int nativex;
70
71 module_param(mode_option, charp, 0);
72 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
73 module_param_named(mode, mode_option, charp, 0);
74 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
75 module_param(bpp, int, 0);
76 module_param(center, int, 0);
77 module_param(stretch, int, 0);
78 module_param(noaccel, int, 0);
79 module_param(memsize, int, 0);
80 module_param(memdiff, int, 0);
81 module_param(nativex, int, 0);
82 module_param(fp, int, 0);
83 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
84 module_param(crt, int, 0);
85 MODULE_PARM_DESC(crt, "Define if CRT is connected");
86
87 static int is_oldclock(int id)
88 {
89 return (id == TGUI9440) ||
90 (id == TGUI9660) ||
91 (id == CYBER9320);
92 }
93
94 static int is_oldprotect(int id)
95 {
96 return (id == TGUI9440) ||
97 (id == TGUI9660) ||
98 (id == PROVIDIA9685) ||
99 (id == CYBER9320) ||
100 (id == CYBER9382) ||
101 (id == CYBER9385);
102 }
103
104 static int is_blade(int id)
105 {
106 return (id == BLADE3D) ||
107 (id == CYBERBLADEE4) ||
108 (id == CYBERBLADEi7) ||
109 (id == CYBERBLADEi7D) ||
110 (id == CYBERBLADEi1) ||
111 (id == CYBERBLADEi1D) ||
112 (id == CYBERBLADEAi1) ||
113 (id == CYBERBLADEAi1D);
114 }
115
116 static int is_xp(int id)
117 {
118 return (id == CYBERBLADEXPAi1) ||
119 (id == CYBERBLADEXPm8) ||
120 (id == CYBERBLADEXPm16);
121 }
122
123 static int is3Dchip(int id)
124 {
125 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
126 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
127 (id == CYBER9397) || (id == CYBER9397DVD) ||
128 (id == CYBER9520) || (id == CYBER9525DVD) ||
129 (id == IMAGE975) || (id == IMAGE985) ||
130 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
131 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
132 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
133 (id == CYBERBLADEXPAi1));
134 }
135
136 static int iscyber(int id)
137 {
138 switch (id) {
139 case CYBER9388:
140 case CYBER9382:
141 case CYBER9385:
142 case CYBER9397:
143 case CYBER9397DVD:
144 case CYBER9520:
145 case CYBER9525DVD:
146 case CYBERBLADEE4:
147 case CYBERBLADEi7D:
148 case CYBERBLADEi1:
149 case CYBERBLADEi1D:
150 case CYBERBLADEAi1:
151 case CYBERBLADEAi1D:
152 case CYBERBLADEXPAi1:
153 return 1;
154
155 case CYBER9320:
156 case TGUI9660:
157 case PROVIDIA9685:
158 case IMAGE975:
159 case IMAGE985:
160 case BLADE3D:
161 case CYBERBLADEi7: /* VIA MPV4 integrated version */
162
163 default:
164 /* case CYBERBLDAEXPm8: Strange */
165 /* case CYBERBLDAEXPm16: Strange */
166 return 0;
167 }
168 }
169
170 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
171 {
172 fb_writeb(val, p->io_virt + reg);
173 }
174
175 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
176 {
177 return fb_readb(p->io_virt + reg);
178 }
179
180 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
181 {
182 fb_writel(v, par->io_virt + r);
183 }
184
185 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
186 {
187 return fb_readl(par->io_virt + r);
188 }
189
190 /*
191 * Blade specific acceleration.
192 */
193
194 #define point(x, y) ((y) << 16 | (x))
195
196 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
197 {
198 int v1 = (pitch >> 3) << 20;
199 int tmp = bpp == 24 ? 2 : (bpp >> 4);
200 int v2 = v1 | (tmp << 29);
201
202 writemmr(par, 0x21C0, v2);
203 writemmr(par, 0x21C4, v2);
204 writemmr(par, 0x21B8, v2);
205 writemmr(par, 0x21BC, v2);
206 writemmr(par, 0x21D0, v1);
207 writemmr(par, 0x21D4, v1);
208 writemmr(par, 0x21C8, v1);
209 writemmr(par, 0x21CC, v1);
210 writemmr(par, 0x216C, 0);
211 }
212
213 static void blade_wait_engine(struct tridentfb_par *par)
214 {
215 while (readmmr(par, STATUS) & 0xFA800000)
216 cpu_relax();
217 }
218
219 static void blade_fill_rect(struct tridentfb_par *par,
220 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
221 {
222 writemmr(par, COLOR, c);
223 writemmr(par, ROP, rop ? ROP_X : ROP_S);
224 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
225
226 writemmr(par, DST1, point(x, y));
227 writemmr(par, DST2, point(x + w - 1, y + h - 1));
228 }
229
230 static void blade_copy_rect(struct tridentfb_par *par,
231 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
232 {
233 int direction = 2;
234 u32 s1 = point(x1, y1);
235 u32 s2 = point(x1 + w - 1, y1 + h - 1);
236 u32 d1 = point(x2, y2);
237 u32 d2 = point(x2 + w - 1, y2 + h - 1);
238
239 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
240 direction = 0;
241
242 writemmr(par, ROP, ROP_S);
243 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
244
245 writemmr(par, SRC1, direction ? s2 : s1);
246 writemmr(par, SRC2, direction ? s1 : s2);
247 writemmr(par, DST1, direction ? d2 : d1);
248 writemmr(par, DST2, direction ? d1 : d2);
249 }
250
251 /*
252 * BladeXP specific acceleration functions
253 */
254
255 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
256 {
257 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
258 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
259
260 switch (pitch << (bpp >> 3)) {
261 case 8192:
262 case 512:
263 x |= 0x00;
264 break;
265 case 1024:
266 x |= 0x04;
267 break;
268 case 2048:
269 x |= 0x08;
270 break;
271 case 4096:
272 x |= 0x0C;
273 break;
274 }
275
276 t_outb(par, x, 0x2125);
277
278 eng_oper = x | 0x40;
279
280 writemmr(par, 0x2154, v1);
281 writemmr(par, 0x2150, v1);
282 t_outb(par, 3, 0x2126);
283 }
284
285 static void xp_wait_engine(struct tridentfb_par *par)
286 {
287 int count, timeout;
288
289 count = 0;
290 timeout = 0;
291 while (t_inb(par, STATUS) & 0x80) {
292 count++;
293 if (count == 10000000) {
294 /* Timeout */
295 count = 9990000;
296 timeout++;
297 if (timeout == 8) {
298 /* Reset engine */
299 t_outb(par, 0x00, STATUS);
300 return;
301 }
302 }
303 cpu_relax();
304 }
305 }
306
307 static void xp_fill_rect(struct tridentfb_par *par,
308 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
309 {
310 writemmr(par, 0x2127, ROP_P);
311 writemmr(par, 0x2158, c);
312 writemmr(par, DRAWFL, 0x4000);
313 writemmr(par, OLDDIM, point(h, w));
314 writemmr(par, OLDDST, point(y, x));
315 t_outb(par, 0x01, OLDCMD);
316 t_outb(par, eng_oper, 0x2125);
317 }
318
319 static void xp_copy_rect(struct tridentfb_par *par,
320 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
321 {
322 int direction;
323 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
324
325 direction = 0x0004;
326
327 if ((x1 < x2) && (y1 == y2)) {
328 direction |= 0x0200;
329 x1_tmp = x1 + w - 1;
330 x2_tmp = x2 + w - 1;
331 } else {
332 x1_tmp = x1;
333 x2_tmp = x2;
334 }
335
336 if (y1 < y2) {
337 direction |= 0x0100;
338 y1_tmp = y1 + h - 1;
339 y2_tmp = y2 + h - 1;
340 } else {
341 y1_tmp = y1;
342 y2_tmp = y2;
343 }
344
345 writemmr(par, DRAWFL, direction);
346 t_outb(par, ROP_S, 0x2127);
347 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
348 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
349 writemmr(par, OLDDIM, point(h, w));
350 t_outb(par, 0x01, OLDCMD);
351 }
352
353 /*
354 * Image specific acceleration functions
355 */
356 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
357 {
358 int tmp = bpp == 24 ? 2: (bpp >> 4);
359
360 writemmr(par, 0x2120, 0xF0000000);
361 writemmr(par, 0x2120, 0x40000000 | tmp);
362 writemmr(par, 0x2120, 0x80000000);
363 writemmr(par, 0x2144, 0x00000000);
364 writemmr(par, 0x2148, 0x00000000);
365 writemmr(par, 0x2150, 0x00000000);
366 writemmr(par, 0x2154, 0x00000000);
367 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
368 writemmr(par, 0x216C, 0x00000000);
369 writemmr(par, 0x2170, 0x00000000);
370 writemmr(par, 0x217C, 0x00000000);
371 writemmr(par, 0x2120, 0x10000000);
372 writemmr(par, 0x2130, (2047 << 16) | 2047);
373 }
374
375 static void image_wait_engine(struct tridentfb_par *par)
376 {
377 while (readmmr(par, 0x2164) & 0xF0000000)
378 cpu_relax();
379 }
380
381 static void image_fill_rect(struct tridentfb_par *par,
382 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
383 {
384 writemmr(par, 0x2120, 0x80000000);
385 writemmr(par, 0x2120, 0x90000000 | ROP_S);
386
387 writemmr(par, 0x2144, c);
388
389 writemmr(par, DST1, point(x, y));
390 writemmr(par, DST2, point(x + w - 1, y + h - 1));
391
392 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
393 }
394
395 static void image_copy_rect(struct tridentfb_par *par,
396 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
397 {
398 int direction = 0x4;
399 u32 s1 = point(x1, y1);
400 u32 s2 = point(x1 + w - 1, y1 + h - 1);
401 u32 d1 = point(x2, y2);
402 u32 d2 = point(x2 + w - 1, y2 + h - 1);
403
404 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
405 direction = 0;
406
407 writemmr(par, 0x2120, 0x80000000);
408 writemmr(par, 0x2120, 0x90000000 | ROP_S);
409
410 writemmr(par, SRC1, direction ? s2 : s1);
411 writemmr(par, SRC2, direction ? s1 : s2);
412 writemmr(par, DST1, direction ? d2 : d1);
413 writemmr(par, DST2, direction ? d1 : d2);
414 writemmr(par, 0x2124,
415 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
416 }
417
418 /*
419 * TGUI 9440/96XX acceleration
420 */
421
422 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
423 {
424 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
425
426 /* disable clipping */
427 writemmr(par, 0x2148, 0);
428 writemmr(par, 0x214C, point(4095, 2047));
429
430 switch ((pitch * bpp) / 8) {
431 case 8192:
432 case 512:
433 x |= 0x00;
434 break;
435 case 1024:
436 x |= 0x04;
437 break;
438 case 2048:
439 x |= 0x08;
440 break;
441 case 4096:
442 x |= 0x0C;
443 break;
444 }
445
446 fb_writew(x, par->io_virt + 0x2122);
447 }
448
449 static void tgui_fill_rect(struct tridentfb_par *par,
450 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
451 {
452 t_outb(par, ROP_P, 0x2127);
453 writemmr(par, OLDCLR, c);
454 writemmr(par, DRAWFL, 0x4020);
455 writemmr(par, OLDDIM, point(w - 1, h - 1));
456 writemmr(par, OLDDST, point(x, y));
457 t_outb(par, 1, OLDCMD);
458 }
459
460 static void tgui_copy_rect(struct tridentfb_par *par,
461 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
462 {
463 int flags = 0;
464 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
465
466 if ((x1 < x2) && (y1 == y2)) {
467 flags |= 0x0200;
468 x1_tmp = x1 + w - 1;
469 x2_tmp = x2 + w - 1;
470 } else {
471 x1_tmp = x1;
472 x2_tmp = x2;
473 }
474
475 if (y1 < y2) {
476 flags |= 0x0100;
477 y1_tmp = y1 + h - 1;
478 y2_tmp = y2 + h - 1;
479 } else {
480 y1_tmp = y1;
481 y2_tmp = y2;
482 }
483
484 writemmr(par, DRAWFL, 0x4 | flags);
485 t_outb(par, ROP_S, 0x2127);
486 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
487 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
488 writemmr(par, OLDDIM, point(w - 1, h - 1));
489 t_outb(par, 1, OLDCMD);
490 }
491
492 /*
493 * Accel functions called by the upper layers
494 */
495 #ifdef CONFIG_FB_TRIDENT_ACCEL
496 static void tridentfb_fillrect(struct fb_info *info,
497 const struct fb_fillrect *fr)
498 {
499 struct tridentfb_par *par = info->par;
500 int col;
501
502 if (info->flags & FBINFO_HWACCEL_DISABLED) {
503 cfb_fillrect(info, fr);
504 return;
505 }
506 if (info->var.bits_per_pixel == 8) {
507 col = fr->color;
508 col |= col << 8;
509 col |= col << 16;
510 } else
511 col = ((u32 *)(info->pseudo_palette))[fr->color];
512
513 par->wait_engine(par);
514 par->fill_rect(par, fr->dx, fr->dy, fr->width,
515 fr->height, col, fr->rop);
516 }
517
518 static void tridentfb_copyarea(struct fb_info *info,
519 const struct fb_copyarea *ca)
520 {
521 struct tridentfb_par *par = info->par;
522
523 if (info->flags & FBINFO_HWACCEL_DISABLED) {
524 cfb_copyarea(info, ca);
525 return;
526 }
527 par->wait_engine(par);
528 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
529 ca->width, ca->height);
530 }
531
532 static int tridentfb_sync(struct fb_info *info)
533 {
534 struct tridentfb_par *par = info->par;
535
536 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
537 par->wait_engine(par);
538 return 0;
539 }
540 #else
541 #define tridentfb_fillrect cfb_fillrect
542 #define tridentfb_copyarea cfb_copyarea
543 #endif /* CONFIG_FB_TRIDENT_ACCEL */
544
545 /*
546 * Hardware access functions
547 */
548
549 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
550 {
551 return vga_mm_rcrt(par->io_virt, reg);
552 }
553
554 static inline void write3X4(struct tridentfb_par *par, int reg,
555 unsigned char val)
556 {
557 vga_mm_wcrt(par->io_virt, reg, val);
558 }
559
560 static inline unsigned char read3CE(struct tridentfb_par *par,
561 unsigned char reg)
562 {
563 return vga_mm_rgfx(par->io_virt, reg);
564 }
565
566 static inline void writeAttr(struct tridentfb_par *par, int reg,
567 unsigned char val)
568 {
569 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
570 vga_mm_wattr(par->io_virt, reg, val);
571 }
572
573 static inline void write3CE(struct tridentfb_par *par, int reg,
574 unsigned char val)
575 {
576 vga_mm_wgfx(par->io_virt, reg, val);
577 }
578
579 static void enable_mmio(void)
580 {
581 /* Goto New Mode */
582 vga_io_rseq(0x0B);
583
584 /* Unprotect registers */
585 vga_io_wseq(NewMode1, 0x80);
586
587 /* Enable MMIO */
588 outb(PCIReg, 0x3D4);
589 outb(inb(0x3D5) | 0x01, 0x3D5);
590 }
591
592 static void disable_mmio(struct tridentfb_par *par)
593 {
594 /* Goto New Mode */
595 vga_mm_rseq(par->io_virt, 0x0B);
596
597 /* Unprotect registers */
598 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
599
600 /* Disable MMIO */
601 t_outb(par, PCIReg, 0x3D4);
602 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
603 }
604
605 static void crtc_unlock(struct tridentfb_par *par)
606 {
607 write3X4(par, VGA_CRTC_V_SYNC_END,
608 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
609 }
610
611 /* Return flat panel's maximum x resolution */
612 static int __devinit get_nativex(struct tridentfb_par *par)
613 {
614 int x, y, tmp;
615
616 if (nativex)
617 return nativex;
618
619 tmp = (read3CE(par, VertStretch) >> 4) & 3;
620
621 switch (tmp) {
622 case 0:
623 x = 1280; y = 1024;
624 break;
625 case 2:
626 x = 1024; y = 768;
627 break;
628 case 3:
629 x = 800; y = 600;
630 break;
631 case 4:
632 x = 1400; y = 1050;
633 break;
634 case 1:
635 default:
636 x = 640; y = 480;
637 break;
638 }
639
640 output("%dx%d flat panel found\n", x, y);
641 return x;
642 }
643
644 /* Set pitch */
645 static void set_lwidth(struct tridentfb_par *par, int width)
646 {
647 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
648 write3X4(par, AddColReg,
649 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
650 }
651
652 /* For resolutions smaller than FP resolution stretch */
653 static void screen_stretch(struct tridentfb_par *par)
654 {
655 if (par->chip_id != CYBERBLADEXPAi1)
656 write3CE(par, BiosReg, 0);
657 else
658 write3CE(par, BiosReg, 8);
659 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
660 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
661 }
662
663 /* For resolutions smaller than FP resolution center */
664 static void screen_center(struct tridentfb_par *par)
665 {
666 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
667 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
668 }
669
670 /* Address of first shown pixel in display memory */
671 static void set_screen_start(struct tridentfb_par *par, int base)
672 {
673 u8 tmp;
674 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
675 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
676 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
677 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
678 tmp = read3X4(par, CRTHiOrd) & 0xF8;
679 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
680 }
681
682 /* Set dotclock frequency */
683 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
684 {
685 int m, n, k;
686 unsigned long fi, d, di;
687 unsigned char best_m = 0, best_n = 0, best_k = 0;
688 unsigned char hi, lo;
689
690 d = 20000;
691 for (k = 1; k >= 0; k--)
692 for (m = 0; m < 32; m++) {
693 n = 2 * (m + 2) - 8;
694 for (n = (n < 0 ? 0 : n); n < 122; n++) {
695 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
696 di = abs(fi - freq);
697 if (di <= d) {
698 d = di;
699 best_n = n;
700 best_m = m;
701 best_k = k;
702 }
703 if (fi > freq)
704 break;
705 }
706 }
707
708 if (is_oldclock(par->chip_id)) {
709 lo = best_n | (best_m << 7);
710 hi = (best_m >> 1) | (best_k << 4);
711 } else {
712 lo = best_n;
713 hi = best_m | (best_k << 6);
714 }
715
716 if (is3Dchip(par->chip_id)) {
717 vga_mm_wseq(par->io_virt, ClockHigh, hi);
718 vga_mm_wseq(par->io_virt, ClockLow, lo);
719 } else {
720 t_outb(par, lo, 0x43C8);
721 t_outb(par, hi, 0x43C9);
722 }
723 debug("VCLK = %X %X\n", hi, lo);
724 }
725
726 /* Set number of lines for flat panels*/
727 static void set_number_of_lines(struct tridentfb_par *par, int lines)
728 {
729 int tmp = read3CE(par, CyberEnhance) & 0x8F;
730 if (lines > 1024)
731 tmp |= 0x50;
732 else if (lines > 768)
733 tmp |= 0x30;
734 else if (lines > 600)
735 tmp |= 0x20;
736 else if (lines > 480)
737 tmp |= 0x10;
738 write3CE(par, CyberEnhance, tmp);
739 }
740
741 /*
742 * If we see that FP is active we assume we have one.
743 * Otherwise we have a CRT display. User can override.
744 */
745 static int __devinit is_flatpanel(struct tridentfb_par *par)
746 {
747 if (fp)
748 return 1;
749 if (crt || !iscyber(par->chip_id))
750 return 0;
751 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
752 }
753
754 /* Try detecting the video memory size */
755 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
756 {
757 unsigned char tmp, tmp2;
758 unsigned int k;
759
760 /* If memory size provided by user */
761 if (memsize)
762 k = memsize * Kb;
763 else
764 switch (par->chip_id) {
765 case CYBER9525DVD:
766 k = 2560 * Kb;
767 break;
768 default:
769 tmp = read3X4(par, SPR) & 0x0F;
770 switch (tmp) {
771
772 case 0x01:
773 k = 512 * Kb;
774 break;
775 case 0x02:
776 k = 6 * Mb; /* XP */
777 break;
778 case 0x03:
779 k = 1 * Mb;
780 break;
781 case 0x04:
782 k = 8 * Mb;
783 break;
784 case 0x06:
785 k = 10 * Mb; /* XP */
786 break;
787 case 0x07:
788 k = 2 * Mb;
789 break;
790 case 0x08:
791 k = 12 * Mb; /* XP */
792 break;
793 case 0x0A:
794 k = 14 * Mb; /* XP */
795 break;
796 case 0x0C:
797 k = 16 * Mb; /* XP */
798 break;
799 case 0x0E: /* XP */
800
801 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
802 switch (tmp2) {
803 case 0x00:
804 k = 20 * Mb;
805 break;
806 case 0x01:
807 k = 24 * Mb;
808 break;
809 case 0x10:
810 k = 28 * Mb;
811 break;
812 case 0x11:
813 k = 32 * Mb;
814 break;
815 default:
816 k = 1 * Mb;
817 break;
818 }
819 break;
820
821 case 0x0F:
822 k = 4 * Mb;
823 break;
824 default:
825 k = 1 * Mb;
826 break;
827 }
828 }
829
830 k -= memdiff * Kb;
831 output("framebuffer size = %d Kb\n", k / Kb);
832 return k;
833 }
834
835 /* See if we can handle the video mode described in var */
836 static int tridentfb_check_var(struct fb_var_screeninfo *var,
837 struct fb_info *info)
838 {
839 struct tridentfb_par *par = info->par;
840 int bpp = var->bits_per_pixel;
841 int line_length;
842 int ramdac = 230000; /* 230MHz for most 3D chips */
843 debug("enter\n");
844
845 /* check color depth */
846 if (bpp == 24)
847 bpp = var->bits_per_pixel = 32;
848 if (bpp != 8 && bpp != 16 && bpp != 32)
849 return -EINVAL;
850 if (par->chip_id == TGUI9440 && bpp == 32)
851 return -EINVAL;
852 /* check whether resolution fits on panel and in memory */
853 if (par->flatpanel && nativex && var->xres > nativex)
854 return -EINVAL;
855 /* various resolution checks */
856 var->xres = (var->xres + 7) & ~0x7;
857 if (var->xres > var->xres_virtual)
858 var->xres_virtual = var->xres;
859 if (var->yres > var->yres_virtual)
860 var->yres_virtual = var->yres;
861 if (var->xres_virtual > 4095 || var->yres > 2048)
862 return -EINVAL;
863 /* prevent from position overflow for acceleration */
864 if (var->yres_virtual > 0xffff)
865 return -EINVAL;
866 line_length = var->xres_virtual * bpp / 8;
867
868 if (!is3Dchip(par->chip_id) &&
869 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
870 /* acceleration requires line length to be power of 2 */
871 if (line_length <= 512)
872 var->xres_virtual = 512 * 8 / bpp;
873 else if (line_length <= 1024)
874 var->xres_virtual = 1024 * 8 / bpp;
875 else if (line_length <= 2048)
876 var->xres_virtual = 2048 * 8 / bpp;
877 else if (line_length <= 4096)
878 var->xres_virtual = 4096 * 8 / bpp;
879 else if (line_length <= 8192)
880 var->xres_virtual = 8192 * 8 / bpp;
881 else
882 return -EINVAL;
883
884 line_length = var->xres_virtual * bpp / 8;
885 }
886
887 if (var->yres > var->yres_virtual)
888 var->yres_virtual = var->yres;
889 if (line_length * var->yres_virtual > info->fix.smem_len)
890 return -EINVAL;
891
892 switch (bpp) {
893 case 8:
894 var->red.offset = 0;
895 var->green.offset = 0;
896 var->blue.offset = 0;
897 var->red.length = 6;
898 var->green.length = 6;
899 var->blue.length = 6;
900 break;
901 case 16:
902 var->red.offset = 11;
903 var->green.offset = 5;
904 var->blue.offset = 0;
905 var->red.length = 5;
906 var->green.length = 6;
907 var->blue.length = 5;
908 break;
909 case 32:
910 var->red.offset = 16;
911 var->green.offset = 8;
912 var->blue.offset = 0;
913 var->red.length = 8;
914 var->green.length = 8;
915 var->blue.length = 8;
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 if (is_xp(par->chip_id))
922 ramdac = 350000;
923
924 switch (par->chip_id) {
925 case TGUI9440:
926 ramdac = (bpp >= 16) ? 45000 : 90000;
927 break;
928 case CYBER9320:
929 case TGUI9660:
930 ramdac = 135000;
931 break;
932 case PROVIDIA9685:
933 case CYBER9388:
934 case CYBER9382:
935 case CYBER9385:
936 ramdac = 170000;
937 break;
938 }
939
940 /* The clock is doubled for 32 bpp */
941 if (bpp == 32)
942 ramdac /= 2;
943
944 if (PICOS2KHZ(var->pixclock) > ramdac)
945 return -EINVAL;
946
947 debug("exit\n");
948
949 return 0;
950
951 }
952
953 /* Pan the display */
954 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
955 struct fb_info *info)
956 {
957 struct tridentfb_par *par = info->par;
958 unsigned int offset;
959
960 debug("enter\n");
961 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
962 * var->bits_per_pixel / 32;
963 info->var.xoffset = var->xoffset;
964 info->var.yoffset = var->yoffset;
965 set_screen_start(par, offset);
966 debug("exit\n");
967 return 0;
968 }
969
970 static void shadowmode_on(struct tridentfb_par *par)
971 {
972 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
973 }
974
975 static void shadowmode_off(struct tridentfb_par *par)
976 {
977 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
978 }
979
980 /* Set the hardware to the requested video mode */
981 static int tridentfb_set_par(struct fb_info *info)
982 {
983 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
984 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
985 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
986 struct fb_var_screeninfo *var = &info->var;
987 int bpp = var->bits_per_pixel;
988 unsigned char tmp;
989 unsigned long vclk;
990
991 debug("enter\n");
992 hdispend = var->xres / 8 - 1;
993 hsyncstart = (var->xres + var->right_margin) / 8;
994 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
995 htotal = (var->xres + var->left_margin + var->right_margin +
996 var->hsync_len) / 8 - 5;
997 hblankstart = hdispend + 1;
998 hblankend = htotal + 3;
999
1000 vdispend = var->yres - 1;
1001 vsyncstart = var->yres + var->lower_margin;
1002 vsyncend = vsyncstart + var->vsync_len;
1003 vtotal = var->upper_margin + vsyncend - 2;
1004 vblankstart = vdispend + 1;
1005 vblankend = vtotal;
1006
1007 if (info->var.vmode & FB_VMODE_INTERLACED) {
1008 vtotal /= 2;
1009 vdispend /= 2;
1010 vsyncstart /= 2;
1011 vsyncend /= 2;
1012 vblankstart /= 2;
1013 vblankend /= 2;
1014 }
1015
1016 crtc_unlock(par);
1017 write3CE(par, CyberControl, 8);
1018 tmp = 0xEB;
1019 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1020 tmp &= ~0x40;
1021 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1022 tmp &= ~0x80;
1023
1024 if (par->flatpanel && var->xres < nativex) {
1025 /*
1026 * on flat panels with native size larger
1027 * than requested resolution decide whether
1028 * we stretch or center
1029 */
1030 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1031
1032 shadowmode_on(par);
1033
1034 if (center)
1035 screen_center(par);
1036 else if (stretch)
1037 screen_stretch(par);
1038
1039 } else {
1040 t_outb(par, tmp, VGA_MIS_W);
1041 write3CE(par, CyberControl, 8);
1042 }
1043
1044 /* vertical timing values */
1045 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1046 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1047 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1048 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1049 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1050 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1051
1052 /* horizontal timing values */
1053 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1054 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1055 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1056 write3X4(par, VGA_CRTC_H_SYNC_END,
1057 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1058 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1059 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1060
1061 /* higher bits of vertical timing values */
1062 tmp = 0x10;
1063 if (vtotal & 0x100) tmp |= 0x01;
1064 if (vdispend & 0x100) tmp |= 0x02;
1065 if (vsyncstart & 0x100) tmp |= 0x04;
1066 if (vblankstart & 0x100) tmp |= 0x08;
1067
1068 if (vtotal & 0x200) tmp |= 0x20;
1069 if (vdispend & 0x200) tmp |= 0x40;
1070 if (vsyncstart & 0x200) tmp |= 0x80;
1071 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1072
1073 tmp = read3X4(par, CRTHiOrd) & 0x07;
1074 tmp |= 0x08; /* line compare bit 10 */
1075 if (vtotal & 0x400) tmp |= 0x80;
1076 if (vblankstart & 0x400) tmp |= 0x40;
1077 if (vsyncstart & 0x400) tmp |= 0x20;
1078 if (vdispend & 0x400) tmp |= 0x10;
1079 write3X4(par, CRTHiOrd, tmp);
1080
1081 tmp = (htotal >> 8) & 0x01;
1082 tmp |= (hdispend >> 7) & 0x02;
1083 tmp |= (hsyncstart >> 5) & 0x08;
1084 tmp |= (hblankstart >> 4) & 0x10;
1085 write3X4(par, HorizOverflow, tmp);
1086
1087 tmp = 0x40;
1088 if (vblankstart & 0x200) tmp |= 0x20;
1089 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1090 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1091
1092 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1093 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1094 write3X4(par, VGA_CRTC_MODE, 0xC3);
1095
1096 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1097
1098 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1099 /* enable access extended memory */
1100 write3X4(par, CRTCModuleTest, tmp);
1101 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1102 if (info->var.vmode & FB_VMODE_INTERLACED)
1103 tmp |= 0x4;
1104 write3CE(par, MiscIntContReg, tmp);
1105
1106 /* enable GE for text acceleration */
1107 write3X4(par, GraphEngReg, 0x80);
1108
1109 switch (bpp) {
1110 case 8:
1111 tmp = 0x00;
1112 break;
1113 case 16:
1114 tmp = 0x05;
1115 break;
1116 case 24:
1117 tmp = 0x29;
1118 break;
1119 case 32:
1120 tmp = 0x09;
1121 break;
1122 }
1123
1124 write3X4(par, PixelBusReg, tmp);
1125
1126 tmp = read3X4(par, DRAMControl);
1127 if (!is_oldprotect(par->chip_id))
1128 tmp |= 0x10;
1129 if (iscyber(par->chip_id))
1130 tmp |= 0x20;
1131 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1132
1133 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1134 if (!is_xp(par->chip_id))
1135 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1136 /* MMIO & PCI read and write burst enable */
1137 if (par->chip_id != TGUI9440)
1138 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1139
1140 vga_mm_wseq(par->io_virt, 0, 3);
1141 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1142 /* enable 4 maps because needed in chain4 mode */
1143 vga_mm_wseq(par->io_virt, 2, 0x0F);
1144 vga_mm_wseq(par->io_virt, 3, 0);
1145 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1146
1147 /* convert from picoseconds to kHz */
1148 vclk = PICOS2KHZ(info->var.pixclock);
1149
1150 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1151 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1152 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1153 tmp |= 8;
1154 vclk *= 2;
1155 }
1156 set_vclk(par, vclk);
1157 write3CE(par, MiscExtFunc, tmp | 0x12);
1158 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1159 write3CE(par, 0x6, 0x05); /* graphics mode */
1160 write3CE(par, 0x7, 0x0F); /* planes? */
1161
1162 if (par->chip_id == CYBERBLADEXPAi1) {
1163 /* This fixes snow-effect in 32 bpp */
1164 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1165 }
1166
1167 /* graphics mode and support 256 color modes */
1168 writeAttr(par, 0x10, 0x41);
1169 writeAttr(par, 0x12, 0x0F); /* planes */
1170 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1171
1172 /* colors */
1173 for (tmp = 0; tmp < 0x10; tmp++)
1174 writeAttr(par, tmp, tmp);
1175 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1176 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1177
1178 switch (bpp) {
1179 case 8:
1180 tmp = 0;
1181 break;
1182 case 16:
1183 tmp = 0x30;
1184 break;
1185 case 24:
1186 case 32:
1187 tmp = 0xD0;
1188 break;
1189 }
1190
1191 t_inb(par, VGA_PEL_IW);
1192 t_inb(par, VGA_PEL_MSK);
1193 t_inb(par, VGA_PEL_MSK);
1194 t_inb(par, VGA_PEL_MSK);
1195 t_inb(par, VGA_PEL_MSK);
1196 t_outb(par, tmp, VGA_PEL_MSK);
1197 t_inb(par, VGA_PEL_IW);
1198
1199 if (par->flatpanel)
1200 set_number_of_lines(par, info->var.yres);
1201 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1202 set_lwidth(par, info->fix.line_length / 8);
1203
1204 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1205 par->init_accel(par, info->var.xres_virtual, bpp);
1206
1207 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1208 info->cmap.len = (bpp == 8) ? 256 : 16;
1209 debug("exit\n");
1210 return 0;
1211 }
1212
1213 /* Set one color register */
1214 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1215 unsigned blue, unsigned transp,
1216 struct fb_info *info)
1217 {
1218 int bpp = info->var.bits_per_pixel;
1219 struct tridentfb_par *par = info->par;
1220
1221 if (regno >= info->cmap.len)
1222 return 1;
1223
1224 if (bpp == 8) {
1225 t_outb(par, 0xFF, VGA_PEL_MSK);
1226 t_outb(par, regno, VGA_PEL_IW);
1227
1228 t_outb(par, red >> 10, VGA_PEL_D);
1229 t_outb(par, green >> 10, VGA_PEL_D);
1230 t_outb(par, blue >> 10, VGA_PEL_D);
1231
1232 } else if (regno < 16) {
1233 if (bpp == 16) { /* RGB 565 */
1234 u32 col;
1235
1236 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1237 ((blue & 0xF800) >> 11);
1238 col |= col << 16;
1239 ((u32 *)(info->pseudo_palette))[regno] = col;
1240 } else if (bpp == 32) /* ARGB 8888 */
1241 ((u32*)info->pseudo_palette)[regno] =
1242 ((transp & 0xFF00) << 16) |
1243 ((red & 0xFF00) << 8) |
1244 ((green & 0xFF00)) |
1245 ((blue & 0xFF00) >> 8);
1246 }
1247
1248 /* debug("exit\n"); */
1249 return 0;
1250 }
1251
1252 /* Try blanking the screen.For flat panels it does nothing */
1253 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1254 {
1255 unsigned char PMCont, DPMSCont;
1256 struct tridentfb_par *par = info->par;
1257
1258 debug("enter\n");
1259 if (par->flatpanel)
1260 return 0;
1261 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1262 PMCont = t_inb(par, 0x83C6) & 0xFC;
1263 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1264 switch (blank_mode) {
1265 case FB_BLANK_UNBLANK:
1266 /* Screen: On, HSync: On, VSync: On */
1267 case FB_BLANK_NORMAL:
1268 /* Screen: Off, HSync: On, VSync: On */
1269 PMCont |= 0x03;
1270 DPMSCont |= 0x00;
1271 break;
1272 case FB_BLANK_HSYNC_SUSPEND:
1273 /* Screen: Off, HSync: Off, VSync: On */
1274 PMCont |= 0x02;
1275 DPMSCont |= 0x01;
1276 break;
1277 case FB_BLANK_VSYNC_SUSPEND:
1278 /* Screen: Off, HSync: On, VSync: Off */
1279 PMCont |= 0x02;
1280 DPMSCont |= 0x02;
1281 break;
1282 case FB_BLANK_POWERDOWN:
1283 /* Screen: Off, HSync: Off, VSync: Off */
1284 PMCont |= 0x00;
1285 DPMSCont |= 0x03;
1286 break;
1287 }
1288
1289 write3CE(par, PowerStatus, DPMSCont);
1290 t_outb(par, 4, 0x83C8);
1291 t_outb(par, PMCont, 0x83C6);
1292
1293 debug("exit\n");
1294
1295 /* let fbcon do a softblank for us */
1296 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1297 }
1298
1299 static struct fb_ops tridentfb_ops = {
1300 .owner = THIS_MODULE,
1301 .fb_setcolreg = tridentfb_setcolreg,
1302 .fb_pan_display = tridentfb_pan_display,
1303 .fb_blank = tridentfb_blank,
1304 .fb_check_var = tridentfb_check_var,
1305 .fb_set_par = tridentfb_set_par,
1306 .fb_fillrect = tridentfb_fillrect,
1307 .fb_copyarea = tridentfb_copyarea,
1308 .fb_imageblit = cfb_imageblit,
1309 #ifdef CONFIG_FB_TRIDENT_ACCEL
1310 .fb_sync = tridentfb_sync,
1311 #endif
1312 };
1313
1314 static int __devinit trident_pci_probe(struct pci_dev *dev,
1315 const struct pci_device_id *id)
1316 {
1317 int err;
1318 unsigned char revision;
1319 struct fb_info *info;
1320 struct tridentfb_par *default_par;
1321 int chip3D;
1322 int chip_id;
1323
1324 err = pci_enable_device(dev);
1325 if (err)
1326 return err;
1327
1328 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1329 if (!info)
1330 return -ENOMEM;
1331 default_par = info->par;
1332
1333 chip_id = id->device;
1334
1335 if (chip_id == CYBERBLADEi1)
1336 output("*** Please do use cyblafb, Cyberblade/i1 support "
1337 "will soon be removed from tridentfb!\n");
1338
1339 #ifndef CONFIG_FB_TRIDENT_ACCEL
1340 noaccel = 1;
1341 #endif
1342
1343 /* If PCI id is 0x9660 then further detect chip type */
1344
1345 if (chip_id == TGUI9660) {
1346 revision = vga_io_rseq(RevisionID);
1347
1348 switch (revision) {
1349 case 0x21:
1350 chip_id = PROVIDIA9685;
1351 break;
1352 case 0x22:
1353 case 0x23:
1354 chip_id = CYBER9397;
1355 break;
1356 case 0x2A:
1357 chip_id = CYBER9397DVD;
1358 break;
1359 case 0x30:
1360 case 0x33:
1361 case 0x34:
1362 case 0x35:
1363 case 0x38:
1364 case 0x3A:
1365 case 0xB3:
1366 chip_id = CYBER9385;
1367 break;
1368 case 0x40 ... 0x43:
1369 chip_id = CYBER9382;
1370 break;
1371 case 0x4A:
1372 chip_id = CYBER9388;
1373 break;
1374 default:
1375 break;
1376 }
1377 }
1378
1379 chip3D = is3Dchip(chip_id);
1380
1381 if (is_xp(chip_id)) {
1382 default_par->init_accel = xp_init_accel;
1383 default_par->wait_engine = xp_wait_engine;
1384 default_par->fill_rect = xp_fill_rect;
1385 default_par->copy_rect = xp_copy_rect;
1386 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1387 } else if (is_blade(chip_id)) {
1388 default_par->init_accel = blade_init_accel;
1389 default_par->wait_engine = blade_wait_engine;
1390 default_par->fill_rect = blade_fill_rect;
1391 default_par->copy_rect = blade_copy_rect;
1392 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1393 } else if (chip3D) { /* 3DImage family left */
1394 default_par->init_accel = image_init_accel;
1395 default_par->wait_engine = image_wait_engine;
1396 default_par->fill_rect = image_fill_rect;
1397 default_par->copy_rect = image_copy_rect;
1398 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1399 } else { /* TGUI 9440/96XX family */
1400 default_par->init_accel = tgui_init_accel;
1401 default_par->wait_engine = xp_wait_engine;
1402 default_par->fill_rect = tgui_fill_rect;
1403 default_par->copy_rect = tgui_copy_rect;
1404 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1405 }
1406
1407 default_par->chip_id = chip_id;
1408
1409 /* setup MMIO region */
1410 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1411 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1412
1413 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1414 debug("request_region failed!\n");
1415 framebuffer_release(info);
1416 return -1;
1417 }
1418
1419 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1420 tridentfb_fix.mmio_len);
1421
1422 if (!default_par->io_virt) {
1423 debug("ioremap failed\n");
1424 err = -1;
1425 goto out_unmap1;
1426 }
1427
1428 enable_mmio();
1429
1430 /* setup framebuffer memory */
1431 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1432 tridentfb_fix.smem_len = get_memsize(default_par);
1433
1434 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1435 debug("request_mem_region failed!\n");
1436 disable_mmio(info->par);
1437 err = -1;
1438 goto out_unmap1;
1439 }
1440
1441 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1442 tridentfb_fix.smem_len);
1443
1444 if (!info->screen_base) {
1445 debug("ioremap failed\n");
1446 err = -1;
1447 goto out_unmap2;
1448 }
1449
1450 output("%s board found\n", pci_name(dev));
1451 default_par->flatpanel = is_flatpanel(default_par);
1452
1453 if (default_par->flatpanel)
1454 nativex = get_nativex(default_par);
1455
1456 info->fix = tridentfb_fix;
1457 info->fbops = &tridentfb_ops;
1458 info->pseudo_palette = default_par->pseudo_pal;
1459
1460 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1461 if (!noaccel && default_par->init_accel) {
1462 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1463 info->flags |= FBINFO_HWACCEL_COPYAREA;
1464 info->flags |= FBINFO_HWACCEL_FILLRECT;
1465 } else
1466 info->flags |= FBINFO_HWACCEL_DISABLED;
1467
1468 if (!fb_find_mode(&info->var, info,
1469 mode_option, NULL, 0, NULL, bpp)) {
1470 err = -EINVAL;
1471 goto out_unmap2;
1472 }
1473 err = fb_alloc_cmap(&info->cmap, 256, 0);
1474 if (err < 0)
1475 goto out_unmap2;
1476
1477 info->var.activate |= FB_ACTIVATE_NOW;
1478 info->device = &dev->dev;
1479 if (register_framebuffer(info) < 0) {
1480 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1481 fb_dealloc_cmap(&info->cmap);
1482 err = -EINVAL;
1483 goto out_unmap2;
1484 }
1485 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1486 info->node, info->fix.id, info->var.xres,
1487 info->var.yres, info->var.bits_per_pixel);
1488
1489 pci_set_drvdata(dev, info);
1490 return 0;
1491
1492 out_unmap2:
1493 if (info->screen_base)
1494 iounmap(info->screen_base);
1495 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1496 disable_mmio(info->par);
1497 out_unmap1:
1498 if (default_par->io_virt)
1499 iounmap(default_par->io_virt);
1500 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1501 framebuffer_release(info);
1502 return err;
1503 }
1504
1505 static void __devexit trident_pci_remove(struct pci_dev *dev)
1506 {
1507 struct fb_info *info = pci_get_drvdata(dev);
1508 struct tridentfb_par *par = info->par;
1509
1510 unregister_framebuffer(info);
1511 iounmap(par->io_virt);
1512 iounmap(info->screen_base);
1513 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1514 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1515 pci_set_drvdata(dev, NULL);
1516 framebuffer_release(info);
1517 }
1518
1519 /* List of boards that we are trying to support */
1520 static struct pci_device_id trident_devices[] = {
1521 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1522 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1523 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1524 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1525 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1526 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1527 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1528 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1529 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1530 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1531 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1532 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1533 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1534 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1535 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1536 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1537 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1538 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1540 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1542 {0,}
1543 };
1544
1545 MODULE_DEVICE_TABLE(pci, trident_devices);
1546
1547 static struct pci_driver tridentfb_pci_driver = {
1548 .name = "tridentfb",
1549 .id_table = trident_devices,
1550 .probe = trident_pci_probe,
1551 .remove = __devexit_p(trident_pci_remove)
1552 };
1553
1554 /*
1555 * Parse user specified options (`video=trident:')
1556 * example:
1557 * video=trident:800x600,bpp=16,noaccel
1558 */
1559 #ifndef MODULE
1560 static int __init tridentfb_setup(char *options)
1561 {
1562 char *opt;
1563 if (!options || !*options)
1564 return 0;
1565 while ((opt = strsep(&options, ",")) != NULL) {
1566 if (!*opt)
1567 continue;
1568 if (!strncmp(opt, "noaccel", 7))
1569 noaccel = 1;
1570 else if (!strncmp(opt, "fp", 2))
1571 fp = 1;
1572 else if (!strncmp(opt, "crt", 3))
1573 fp = 0;
1574 else if (!strncmp(opt, "bpp=", 4))
1575 bpp = simple_strtoul(opt + 4, NULL, 0);
1576 else if (!strncmp(opt, "center", 6))
1577 center = 1;
1578 else if (!strncmp(opt, "stretch", 7))
1579 stretch = 1;
1580 else if (!strncmp(opt, "memsize=", 8))
1581 memsize = simple_strtoul(opt + 8, NULL, 0);
1582 else if (!strncmp(opt, "memdiff=", 8))
1583 memdiff = simple_strtoul(opt + 8, NULL, 0);
1584 else if (!strncmp(opt, "nativex=", 8))
1585 nativex = simple_strtoul(opt + 8, NULL, 0);
1586 else
1587 mode_option = opt;
1588 }
1589 return 0;
1590 }
1591 #endif
1592
1593 static int __init tridentfb_init(void)
1594 {
1595 #ifndef MODULE
1596 char *option = NULL;
1597
1598 if (fb_get_options("tridentfb", &option))
1599 return -ENODEV;
1600 tridentfb_setup(option);
1601 #endif
1602 output("Trident framebuffer %s initializing\n", VERSION);
1603 return pci_register_driver(&tridentfb_pci_driver);
1604 }
1605
1606 static void __exit tridentfb_exit(void)
1607 {
1608 pci_unregister_driver(&tridentfb_pci_driver);
1609 }
1610
1611 module_init(tridentfb_init);
1612 module_exit(tridentfb_exit);
1613
1614 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1615 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1616 MODULE_LICENSE("GPL");
1617
kernel source for telekom puls (alcatel/mediatek)