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[PATCH] fbdev driver for S3 Trio/Virge
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / svgalib.c
1 /*
2 * Common utility functions for VGA-based graphics cards.
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/string.h>
16 #include <linux/fb.h>
17 #include <linux/svga.h>
18 #include <linux/slab.h>
19 #include <asm/types.h>
20 #include <asm/io.h>
21
22
23 /* Write a CRT register value spread across multiple registers */
24 void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
25
26 u8 regval, bitval, bitnum;
27
28 while (regset->regnum != VGA_REGSET_END_VAL) {
29 regval = vga_rcrt(NULL, regset->regnum);
30 bitnum = regset->lowbit;
31 while (bitnum <= regset->highbit) {
32 bitval = 1 << bitnum;
33 regval = regval & ~bitval;
34 if (value & 1) regval = regval | bitval;
35 bitnum ++;
36 value = value >> 1;
37 }
38 vga_wcrt(NULL, regset->regnum, regval);
39 regset ++;
40 }
41 }
42
43 /* Write a sequencer register value spread across multiple registers */
44 void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
45
46 u8 regval, bitval, bitnum;
47
48 while (regset->regnum != VGA_REGSET_END_VAL) {
49 regval = vga_rseq(NULL, regset->regnum);
50 bitnum = regset->lowbit;
51 while (bitnum <= regset->highbit) {
52 bitval = 1 << bitnum;
53 regval = regval & ~bitval;
54 if (value & 1) regval = regval | bitval;
55 bitnum ++;
56 value = value >> 1;
57 }
58 vga_wseq(NULL, regset->regnum, regval);
59 regset ++;
60 }
61 }
62
63 static unsigned int svga_regset_size(const struct vga_regset *regset)
64 {
65 u8 count = 0;
66
67 while (regset->regnum != VGA_REGSET_END_VAL) {
68 count += regset->highbit - regset->lowbit + 1;
69 regset ++;
70 }
71 return 1 << count;
72 }
73
74
75 /* ------------------------------------------------------------------------- */
76
77
78 /* Set graphics controller registers to sane values */
79 void svga_set_default_gfx_regs(void)
80 {
81 /* All standard GFX registers (GR00 - GR08) */
82 vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00);
83 vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00);
84 vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00);
85 vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00);
86 vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00);
87 vga_wgfx(NULL, VGA_GFX_MODE, 0x00);
88 /* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */
89 /* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */
90 vga_wgfx(NULL, VGA_GFX_MISC, 0x05);
91 /* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */
92 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F);
93 vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF);
94 }
95
96 /* Set attribute controller registers to sane values */
97 void svga_set_default_atc_regs(void)
98 {
99 u8 count;
100
101 vga_r(NULL, 0x3DA);
102 vga_w(NULL, VGA_ATT_W, 0x00);
103
104 /* All standard ATC registers (AR00 - AR14) */
105 for (count = 0; count <= 0xF; count ++)
106 svga_wattr(count, count);
107
108 svga_wattr(VGA_ATC_MODE, 0x01);
109 /* svga_wattr(VGA_ATC_MODE, 0x41); */
110 svga_wattr(VGA_ATC_OVERSCAN, 0x00);
111 svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F);
112 svga_wattr(VGA_ATC_PEL, 0x00);
113 svga_wattr(VGA_ATC_COLOR_PAGE, 0x00);
114
115 vga_r(NULL, 0x3DA);
116 vga_w(NULL, VGA_ATT_W, 0x20);
117 }
118
119 /* Set sequencer registers to sane values */
120 void svga_set_default_seq_regs(void)
121 {
122 /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
123 vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
124 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
125 vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00);
126 /* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
127 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
128 }
129
130 /* Set CRTC registers to sane values */
131 void svga_set_default_crt_regs(void)
132 {
133 /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
134 svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
135 vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0);
136 svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F);
137 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0);
138 vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3);
139 }
140
141 void svga_set_textmode_vga_regs(void)
142 {
143 /* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
144 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
145 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03);
146
147 vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
148 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f);
149 svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f);
150
151 vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d);
152 vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e);
153 vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00);
154 vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00);
155
156 vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
157 vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
158 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00);
159
160 vga_r(NULL, 0x3DA);
161 vga_w(NULL, VGA_ATT_W, 0x00);
162
163 svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
164 svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */
165
166 vga_r(NULL, 0x3DA);
167 vga_w(NULL, VGA_ATT_W, 0x20);
168 }
169
170 #if 0
171 void svga_dump_var(struct fb_var_screeninfo *var, int node)
172 {
173 pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
174 pr_debug("fb%d: var.xres : %d\n", node, var->xres);
175 pr_debug("fb%d: var.yres : %d\n", node, var->yres);
176 pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
177 pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
178 pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
179 pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
180 pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
181 pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
182 pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
183 pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
184 pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
185 pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
186 pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
187 }
188 #endif /* 0 */
189
190
191 /* ------------------------------------------------------------------------- */
192
193
194 void svga_settile(struct fb_info *info, struct fb_tilemap *map)
195 {
196 const u8 *font = map->data;
197 u8* fb = (u8 *) info->screen_base;
198 int i, c;
199
200 if ((map->width != 8) || (map->height != 16) ||
201 (map->depth != 1) || (map->length != 256)) {
202 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
203 info->node, map->width, map->height, map->depth, map->length);
204 return;
205 }
206
207 fb += 2;
208 for (c = 0; c < map->length; c++) {
209 for (i = 0; i < map->height; i++) {
210 fb[i * 4] = font[i];
211 }
212 fb += 128;
213 font += map->height;
214 }
215 }
216
217 /* Copy area in text (tileblit) mode */
218 void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
219 {
220 int dx, dy;
221 /* colstride is halved in this function because u16 are used */
222 int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
223 int rowstride = colstride * (info->var.xres_virtual / 8);
224 u16 *fb = (u16 *) info->screen_base;
225 u16 *src, *dst;
226
227 if ((area->sy > area->dy) ||
228 ((area->sy == area->dy) && (area->sx > area->dx))) {
229 src = fb + area->sx * colstride + area->sy * rowstride;
230 dst = fb + area->dx * colstride + area->dy * rowstride;
231 } else {
232 src = fb + (area->sx + area->width - 1) * colstride
233 + (area->sy + area->height - 1) * rowstride;
234 dst = fb + (area->dx + area->width - 1) * colstride
235 + (area->dy + area->height - 1) * rowstride;
236
237 colstride = -colstride;
238 rowstride = -rowstride;
239 }
240
241 for (dy = 0; dy < area->height; dy++) {
242 u16* src2 = src;
243 u16* dst2 = dst;
244 for (dx = 0; dx < area->width; dx++) {
245 *dst2 = *src2;
246 src2 += colstride;
247 dst2 += colstride;
248 }
249 src += rowstride;
250 dst += rowstride;
251 }
252 }
253
254 /* Fill area in text (tileblit) mode */
255 void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
256 {
257 int dx, dy;
258 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
259 int rowstride = colstride * (info->var.xres_virtual / 8);
260 int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
261 u8 *fb = (u8 *) info->screen_base;
262 fb += rect->sx * colstride + rect->sy * rowstride;
263
264 for (dy = 0; dy < rect->height; dy++) {
265 u8* fb2 = fb;
266 for (dx = 0; dx < rect->width; dx++) {
267 fb2[0] = rect->index;
268 fb2[1] = attr;
269 fb2 += colstride;
270 }
271 fb += rowstride;
272 }
273 }
274
275 /* Write text in text (tileblit) mode */
276 void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
277 {
278 int dx, dy, i;
279 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
280 int rowstride = colstride * (info->var.xres_virtual / 8);
281 int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
282 u8* fb = (u8 *) info->screen_base;
283 fb += blit->sx * colstride + blit->sy * rowstride;
284
285 i=0;
286 for (dy=0; dy < blit->height; dy ++) {
287 u8* fb2 = fb;
288 for (dx = 0; dx < blit->width; dx ++) {
289 fb2[0] = blit->indices[i];
290 fb2[1] = attr;
291 fb2 += colstride;
292 i ++;
293 if (i == blit->length) return;
294 }
295 fb += rowstride;
296 }
297
298 }
299
300 /* Set cursor in text (tileblit) mode */
301 void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
302 {
303 u8 cs = 0x0d;
304 u8 ce = 0x0e;
305 u16 pos = cursor->sx + (info->var.xoffset / 8)
306 + (cursor->sy + (info->var.yoffset / 16))
307 * (info->var.xres_virtual / 8);
308
309 if (! cursor -> mode)
310 return;
311
312 svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */
313
314 if (cursor -> shape == FB_TILE_CURSOR_NONE)
315 return;
316
317 switch (cursor -> shape) {
318 case FB_TILE_CURSOR_UNDERLINE:
319 cs = 0x0d;
320 break;
321 case FB_TILE_CURSOR_LOWER_THIRD:
322 cs = 0x09;
323 break;
324 case FB_TILE_CURSOR_LOWER_HALF:
325 cs = 0x07;
326 break;
327 case FB_TILE_CURSOR_TWO_THIRDS:
328 cs = 0x05;
329 break;
330 case FB_TILE_CURSOR_BLOCK:
331 cs = 0x01;
332 break;
333 }
334
335 /* set cursor position */
336 vga_wcrt(NULL, 0x0E, pos >> 8);
337 vga_wcrt(NULL, 0x0F, pos & 0xFF);
338
339 vga_wcrt(NULL, 0x0B, ce); /* set cursor end */
340 vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */
341 }
342
343
344 /* ------------------------------------------------------------------------- */
345
346
347 /*
348 * Compute PLL settings (M, N, R)
349 * F_VCO = (F_BASE * M) / N
350 * F_OUT = F_VCO / (2^R)
351 */
352
353 static inline u32 abs_diff(u32 a, u32 b)
354 {
355 return (a > b) ? (a - b) : (b - a);
356 }
357
358 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
359 {
360 u16 am, an, ar;
361 u32 f_vco, f_current, delta_current, delta_best;
362
363 pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
364
365 ar = pll->r_max;
366 f_vco = f_wanted << ar;
367
368 /* overflow check */
369 if ((f_vco >> ar) != f_wanted)
370 return -EINVAL;
371
372 /* It is usually better to have greater VCO clock
373 because of better frequency stability.
374 So first try r_max, then r smaller. */
375 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
376 ar--;
377 f_vco = f_vco >> 1;
378 }
379
380 /* VCO bounds check */
381 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
382 return -EINVAL;
383
384 delta_best = 0xFFFFFFFF;
385 *m = 0;
386 *n = 0;
387 *r = ar;
388
389 am = pll->m_min;
390 an = pll->n_min;
391
392 while ((am <= pll->m_max) && (an <= pll->n_max)) {
393 f_current = (pll->f_base * am) / an;
394 delta_current = abs_diff (f_current, f_vco);
395
396 if (delta_current < delta_best) {
397 delta_best = delta_current;
398 *m = am;
399 *n = an;
400 }
401
402 if (f_current <= f_vco) {
403 am ++;
404 } else {
405 an ++;
406 }
407 }
408
409 f_current = (pll->f_base * *m) / *n;
410 pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
411 pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
412 return 0;
413 }
414
415
416 /* ------------------------------------------------------------------------- */
417
418
419 /* Check CRT timing values */
420 int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
421 {
422 u32 value;
423
424 var->xres = (var->xres+7)&~7;
425 var->left_margin = (var->left_margin+7)&~7;
426 var->right_margin = (var->right_margin+7)&~7;
427 var->hsync_len = (var->hsync_len+7)&~7;
428
429 /* Check horizontal total */
430 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
431 if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
432 return -EINVAL;
433
434 /* Check horizontal display and blank start */
435 value = var->xres;
436 if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
437 return -EINVAL;
438 if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
439 return -EINVAL;
440
441 /* Check horizontal sync start */
442 value = var->xres + var->right_margin;
443 if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
444 return -EINVAL;
445
446 /* Check horizontal blank end (or length) */
447 value = var->left_margin + var->right_margin + var->hsync_len;
448 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
449 return -EINVAL;
450
451 /* Check horizontal sync end (or length) */
452 value = var->hsync_len;
453 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
454 return -EINVAL;
455
456 /* Check vertical total */
457 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
458 if ((value - 1) >= svga_regset_size(tm->v_total_regs))
459 return -EINVAL;
460
461 /* Check vertical display and blank start */
462 value = var->yres;
463 if ((value - 1) >= svga_regset_size(tm->v_display_regs))
464 return -EINVAL;
465 if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
466 return -EINVAL;
467
468 /* Check vertical sync start */
469 value = var->yres + var->lower_margin;
470 if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
471 return -EINVAL;
472
473 /* Check vertical blank end (or length) */
474 value = var->upper_margin + var->lower_margin + var->vsync_len;
475 if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
476 return -EINVAL;
477
478 /* Check vertical sync end (or length) */
479 value = var->vsync_len;
480 if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
481 return -EINVAL;
482
483 return 0;
484 }
485
486 /* Set CRT timing registers */
487 void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var,
488 u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
489 {
490 u8 regval;
491 u32 value;
492
493 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
494 value = (value * hmul) / hdiv;
495 pr_debug("fb%d: horizontal total : %d\n", node, value);
496 svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5);
497
498 value = var->xres;
499 value = (value * hmul) / hdiv;
500 pr_debug("fb%d: horizontal display : %d\n", node, value);
501 svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1);
502
503 value = var->xres;
504 value = (value * hmul) / hdiv;
505 pr_debug("fb%d: horizontal blank start: %d\n", node, value);
506 svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder);
507
508 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
509 value = (value * hmul) / hdiv;
510 pr_debug("fb%d: horizontal blank end : %d\n", node, value);
511 svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder);
512
513 value = var->xres + var->right_margin;
514 value = (value * hmul) / hdiv;
515 pr_debug("fb%d: horizontal sync start : %d\n", node, value);
516 svga_wcrt_multi(tm->h_sync_start_regs, (value / 8));
517
518 value = var->xres + var->right_margin + var->hsync_len;
519 value = (value * hmul) / hdiv;
520 pr_debug("fb%d: horizontal sync end : %d\n", node, value);
521 svga_wcrt_multi(tm->h_sync_end_regs, (value / 8));
522
523 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
524 value = (value * vmul) / vdiv;
525 pr_debug("fb%d: vertical total : %d\n", node, value);
526 svga_wcrt_multi(tm->v_total_regs, value - 2);
527
528 value = var->yres;
529 value = (value * vmul) / vdiv;
530 pr_debug("fb%d: vertical display : %d\n", node, value);
531 svga_wcrt_multi(tm->v_display_regs, value - 1);
532
533 value = var->yres;
534 value = (value * vmul) / vdiv;
535 pr_debug("fb%d: vertical blank start : %d\n", node, value);
536 svga_wcrt_multi(tm->v_blank_start_regs, value);
537
538 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
539 value = (value * vmul) / vdiv;
540 pr_debug("fb%d: vertical blank end : %d\n", node, value);
541 svga_wcrt_multi(tm->v_blank_end_regs, value - 2);
542
543 value = var->yres + var->lower_margin;
544 value = (value * vmul) / vdiv;
545 pr_debug("fb%d: vertical sync start : %d\n", node, value);
546 svga_wcrt_multi(tm->v_sync_start_regs, value);
547
548 value = var->yres + var->lower_margin + var->vsync_len;
549 value = (value * vmul) / vdiv;
550 pr_debug("fb%d: vertical sync end : %d\n", node, value);
551 svga_wcrt_multi(tm->v_sync_end_regs, value);
552
553 /* Set horizontal and vertical sync pulse polarity in misc register */
554
555 regval = vga_r(NULL, VGA_MIS_R);
556 if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
557 pr_debug("fb%d: positive horizontal sync\n", node);
558 regval = regval & ~0x80;
559 } else {
560 pr_debug("fb%d: negative horizontal sync\n", node);
561 regval = regval | 0x80;
562 }
563 if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
564 pr_debug("fb%d: positive vertical sync\n", node);
565 regval = regval & ~0x40;
566 } else {
567 pr_debug("fb%d: negative vertical sync\n\n", node);
568 regval = regval | 0x40;
569 }
570 vga_w(NULL, VGA_MIS_W, regval);
571 }
572
573
574 /* ------------------------------------------------------------------------- */
575
576
577 int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix)
578 {
579 int i = 0;
580
581 while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
582 {
583 if ((var->bits_per_pixel == frm->bits_per_pixel) &&
584 (var->red.length <= frm->red.length) &&
585 (var->green.length <= frm->green.length) &&
586 (var->blue.length <= frm->blue.length) &&
587 (var->transp.length <= frm->transp.length) &&
588 (var->nonstd == frm->nonstd)) {
589 var->bits_per_pixel = frm->bits_per_pixel;
590 var->red = frm->red;
591 var->green = frm->green;
592 var->blue = frm->blue;
593 var->transp = frm->transp;
594 var->nonstd = frm->nonstd;
595 if (fix != NULL) {
596 fix->type = frm->type;
597 fix->type_aux = frm->type_aux;
598 fix->visual = frm->visual;
599 fix->xpanstep = frm->xpanstep;
600 }
601 return i;
602 }
603 i++;
604 frm++;
605 }
606 return -EINVAL;
607 }
608
609
610 EXPORT_SYMBOL(svga_wcrt_multi);
611 EXPORT_SYMBOL(svga_wseq_multi);
612
613 EXPORT_SYMBOL(svga_set_default_gfx_regs);
614 EXPORT_SYMBOL(svga_set_default_atc_regs);
615 EXPORT_SYMBOL(svga_set_default_seq_regs);
616 EXPORT_SYMBOL(svga_set_default_crt_regs);
617 EXPORT_SYMBOL(svga_set_textmode_vga_regs);
618
619 EXPORT_SYMBOL(svga_settile);
620 EXPORT_SYMBOL(svga_tilecopy);
621 EXPORT_SYMBOL(svga_tilefill);
622 EXPORT_SYMBOL(svga_tileblit);
623 EXPORT_SYMBOL(svga_tilecursor);
624
625 EXPORT_SYMBOL(svga_compute_pll);
626 EXPORT_SYMBOL(svga_check_timings);
627 EXPORT_SYMBOL(svga_set_timings);
628 EXPORT_SYMBOL(svga_match_format);
629
630 MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
631 MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
632 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)