drivers/video/sh_mobile_meram.c

   1 /*
   2  * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
   3  *
   4  * Copyright (c) 2011   Damian Hobson-Garcia <dhobsong@igel.co.jp>
   5  *                      Takanari Hayama <taki@igel.co.jp>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/err.h>
  14 #include <linux/genalloc.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/slab.h>
  21
  22 #include <video/sh_mobile_meram.h>
  23
  24 /* -----------------------------------------------------------------------------
  25  * MERAM registers
  26  */
  27
  28 #define MEVCR1                  0x4
  29 #define MEVCR1_RST              (1 << 31)
  30 #define MEVCR1_WD               (1 << 30)
  31 #define MEVCR1_AMD1             (1 << 29)
  32 #define MEVCR1_AMD0             (1 << 28)
  33 #define MEQSEL1                 0x40
  34 #define MEQSEL2                 0x44
  35
  36 #define MExxCTL                 0x400
  37 #define MExxCTL_BV              (1 << 31)
  38 #define MExxCTL_BSZ_SHIFT       28
  39 #define MExxCTL_MSAR_MASK       (0x7ff << MExxCTL_MSAR_SHIFT)
  40 #define MExxCTL_MSAR_SHIFT      16
  41 #define MExxCTL_NXT_MASK        (0x1f << MExxCTL_NXT_SHIFT)
  42 #define MExxCTL_NXT_SHIFT       11
  43 #define MExxCTL_WD1             (1 << 10)
  44 #define MExxCTL_WD0             (1 << 9)
  45 #define MExxCTL_WS              (1 << 8)
  46 #define MExxCTL_CB              (1 << 7)
  47 #define MExxCTL_WBF             (1 << 6)
  48 #define MExxCTL_WF              (1 << 5)
  49 #define MExxCTL_RF              (1 << 4)
  50 #define MExxCTL_CM              (1 << 3)
  51 #define MExxCTL_MD_READ         (1 << 0)
  52 #define MExxCTL_MD_WRITE        (2 << 0)
  53 #define MExxCTL_MD_ICB_WB       (3 << 0)
  54 #define MExxCTL_MD_ICB          (4 << 0)
  55 #define MExxCTL_MD_FB           (7 << 0)
  56 #define MExxCTL_MD_MASK         (7 << 0)
  57 #define MExxBSIZE               0x404
  58 #define MExxBSIZE_RCNT_SHIFT    28
  59 #define MExxBSIZE_YSZM1_SHIFT   16
  60 #define MExxBSIZE_XSZM1_SHIFT   0
  61 #define MExxMNCF                0x408
  62 #define MExxMNCF_KWBNM_SHIFT    28
  63 #define MExxMNCF_KRBNM_SHIFT    24
  64 #define MExxMNCF_BNM_SHIFT      16
  65 #define MExxMNCF_XBV            (1 << 15)
  66 #define MExxMNCF_CPL_YCBCR444   (1 << 12)
  67 #define MExxMNCF_CPL_YCBCR420   (2 << 12)
  68 #define MExxMNCF_CPL_YCBCR422   (3 << 12)
  69 #define MExxMNCF_CPL_MSK        (3 << 12)
  70 #define MExxMNCF_BL             (1 << 2)
  71 #define MExxMNCF_LNM_SHIFT      0
  72 #define MExxSARA                0x410
  73 #define MExxSARB                0x414
  74 #define MExxSBSIZE              0x418
  75 #define MExxSBSIZE_HDV          (1 << 31)
  76 #define MExxSBSIZE_HSZ16        (0 << 28)
  77 #define MExxSBSIZE_HSZ32        (1 << 28)
  78 #define MExxSBSIZE_HSZ64        (2 << 28)
  79 #define MExxSBSIZE_HSZ128       (3 << 28)
  80 #define MExxSBSIZE_SBSIZZ_SHIFT 0
  81
  82 #define MERAM_MExxCTL_VAL(next, addr)   \
  83         ((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \
  84          (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK))
  85 #define MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \
  86         (((rcnt) << MExxBSIZE_RCNT_SHIFT) | \
  87          ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \
  88          ((xszm1) << MExxBSIZE_XSZM1_SHIFT))
  89
  90 static const unsigned long common_regs[] = {
  91         MEVCR1,
  92         MEQSEL1,
  93         MEQSEL2,
  94 };
  95 #define MERAM_REGS_SIZE ARRAY_SIZE(common_regs)
  96
  97 static const unsigned long icb_regs[] = {
  98         MExxCTL,
  99         MExxBSIZE,
 100         MExxMNCF,
 101         MExxSARA,
 102         MExxSARB,
 103         MExxSBSIZE,
 104 };
 105 #define ICB_REGS_SIZE ARRAY_SIZE(icb_regs)
 106
 107 /*
 108  * sh_mobile_meram_icb - MERAM ICB information
 109  * @regs: Registers cache
 110  * @index: ICB index
 111  * @offset: MERAM block offset
 112  * @size: MERAM block size in KiB
 113  * @cache_unit: Bytes to cache per ICB
 114  * @pixelformat: Video pixel format of the data stored in the ICB
 115  * @current_reg: Which of Start Address Register A (0) or B (1) is in use
 116  */
 117 struct sh_mobile_meram_icb {
 118         unsigned long regs[ICB_REGS_SIZE];
 119         unsigned int index;
 120         unsigned long offset;
 121         unsigned int size;
 122
 123         unsigned int cache_unit;
 124         unsigned int pixelformat;
 125         unsigned int current_reg;
 126 };
 127
 128 #define MERAM_ICB_NUM                   32
 129
 130 struct sh_mobile_meram_fb_plane {
 131         struct sh_mobile_meram_icb *marker;
 132         struct sh_mobile_meram_icb *cache;
 133 };
 134
 135 struct sh_mobile_meram_fb_cache {
 136         unsigned int nplanes;
 137         struct sh_mobile_meram_fb_plane planes[2];
 138 };
 139
 140 /*
 141  * sh_mobile_meram_priv - MERAM device
 142  * @base: Registers base address
 143  * @meram: MERAM physical address
 144  * @regs: Registers cache
 145  * @lock: Protects used_icb and icbs
 146  * @used_icb: Bitmask of used ICBs
 147  * @icbs: ICBs
 148  * @pool: Allocation pool to manage the MERAM
 149  */
 150 struct sh_mobile_meram_priv {
 151         void __iomem *base;
 152         unsigned long meram;
 153         unsigned long regs[MERAM_REGS_SIZE];
 154
 155         struct mutex lock;
 156         unsigned long used_icb;
 157         struct sh_mobile_meram_icb icbs[MERAM_ICB_NUM];
 158
 159         struct gen_pool *pool;
 160 };
 161
 162 /* settings */
 163 #define MERAM_GRANULARITY               1024
 164 #define MERAM_SEC_LINE                  15
 165 #define MERAM_LINE_WIDTH                2048
 166
 167 /* -----------------------------------------------------------------------------
 168  * Registers access
 169  */
 170
 171 #define MERAM_ICB_OFFSET(base, idx, off)        ((base) + (off) + (idx) * 0x20)
 172
 173 static inline void meram_write_icb(void __iomem *base, unsigned int idx,
 174                                    unsigned int off, unsigned long val)
 175 {
 176         iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
 177 }
 178
 179 static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx,
 180                                            unsigned int off)
 181 {
 182         return ioread32(MERAM_ICB_OFFSET(base, idx, off));
 183 }
 184
 185 static inline void meram_write_reg(void __iomem *base, unsigned int off,
 186                                    unsigned long val)
 187 {
 188         iowrite32(val, base + off);
 189 }
 190
 191 static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off)
 192 {
 193         return ioread32(base + off);
 194 }
 195
 196 /* -----------------------------------------------------------------------------
 197  * LCDC cache planes allocation, init, cleanup and free
 198  */
 199
 200 /* Allocate ICBs and MERAM for a plane. */
 201 static int meram_plane_alloc(struct sh_mobile_meram_priv *priv,
 202                              struct sh_mobile_meram_fb_plane *plane,
 203                              size_t size)
 204 {
 205         unsigned long mem;
 206         unsigned long idx;
 207
 208         idx = find_first_zero_bit(&priv->used_icb, 28);
 209         if (idx == 28)
 210                 return -ENOMEM;
 211         plane->cache = &priv->icbs[idx];
 212
 213         idx = find_next_zero_bit(&priv->used_icb, 32, 28);
 214         if (idx == 32)
 215                 return -ENOMEM;
 216         plane->marker = &priv->icbs[idx];
 217
 218         mem = gen_pool_alloc(priv->pool, size * 1024);
 219         if (mem == 0)
 220                 return -ENOMEM;
 221
 222         __set_bit(plane->marker->index, &priv->used_icb);
 223         __set_bit(plane->cache->index, &priv->used_icb);
 224
 225         plane->marker->offset = mem - priv->meram;
 226         plane->marker->size = size;
 227
 228         return 0;
 229 }
 230
 231 /* Free ICBs and MERAM for a plane. */
 232 static void meram_plane_free(struct sh_mobile_meram_priv *priv,
 233                              struct sh_mobile_meram_fb_plane *plane)
 234 {
 235         gen_pool_free(priv->pool, priv->meram + plane->marker->offset,
 236                       plane->marker->size * 1024);
 237
 238         __clear_bit(plane->marker->index, &priv->used_icb);
 239         __clear_bit(plane->cache->index, &priv->used_icb);
 240 }
 241
 242 /* Is this a YCbCr(NV12, NV16 or NV24) colorspace? */
 243 static int is_nvcolor(int cspace)
 244 {
 245         if (cspace == SH_MOBILE_MERAM_PF_NV ||
 246             cspace == SH_MOBILE_MERAM_PF_NV24)
 247                 return 1;
 248         return 0;
 249 }
 250
 251 /* Set the next address to fetch. */
 252 static void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
 253                                 struct sh_mobile_meram_fb_cache *cache,
 254                                 unsigned long base_addr_y,
 255                                 unsigned long base_addr_c)
 256 {
 257         struct sh_mobile_meram_icb *icb = cache->planes[0].marker;
 258         unsigned long target;
 259
 260         icb->current_reg ^= 1;
 261         target = icb->current_reg ? MExxSARB : MExxSARA;
 262
 263         /* set the next address to fetch */
 264         meram_write_icb(priv->base, cache->planes[0].cache->index, target,
 265                         base_addr_y);
 266         meram_write_icb(priv->base, cache->planes[0].marker->index, target,
 267                         base_addr_y + cache->planes[0].marker->cache_unit);
 268
 269         if (cache->nplanes == 2) {
 270                 meram_write_icb(priv->base, cache->planes[1].cache->index,
 271                                 target, base_addr_c);
 272                 meram_write_icb(priv->base, cache->planes[1].marker->index,
 273                                 target, base_addr_c +
 274                                 cache->planes[1].marker->cache_unit);
 275         }
 276 }
 277
 278 /* Get the next ICB address. */
 279 static void
 280 meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
 281                         struct sh_mobile_meram_fb_cache *cache,
 282                         unsigned long *icb_addr_y, unsigned long *icb_addr_c)
 283 {
 284         struct sh_mobile_meram_icb *icb = cache->planes[0].marker;
 285         unsigned long icb_offset;
 286
 287         if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
 288                 icb_offset = 0x80000000 | (icb->current_reg << 29);
 289         else
 290                 icb_offset = 0xc0000000 | (icb->current_reg << 23);
 291
 292         *icb_addr_y = icb_offset | (cache->planes[0].marker->index << 24);
 293         if (cache->nplanes == 2)
 294                 *icb_addr_c = icb_offset
 295                             | (cache->planes[1].marker->index << 24);
 296 }
 297
 298 #define MERAM_CALC_BYTECOUNT(x, y) \
 299         (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
 300
 301 /* Initialize MERAM. */
 302 static int meram_plane_init(struct sh_mobile_meram_priv *priv,
 303                             struct sh_mobile_meram_fb_plane *plane,
 304                             unsigned int xres, unsigned int yres,
 305                             unsigned int *out_pitch)
 306 {
 307         struct sh_mobile_meram_icb *marker = plane->marker;
 308         unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
 309         unsigned long bnm;
 310         unsigned int lcdc_pitch;
 311         unsigned int xpitch;
 312         unsigned int line_cnt;
 313         unsigned int save_lines;
 314
 315         /* adjust pitch to 1024, 2048, 4096 or 8192 */
 316         lcdc_pitch = (xres - 1) | 1023;
 317         lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
 318         lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
 319         lcdc_pitch += 1;
 320
 321         /* derive settings */
 322         if (lcdc_pitch == 8192 && yres >= 1024) {
 323                 lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
 324                 line_cnt = total_byte_count >> 11;
 325                 *out_pitch = xres;
 326                 save_lines = plane->marker->size / 16 / MERAM_SEC_LINE;
 327                 save_lines *= MERAM_SEC_LINE;
 328         } else {
 329                 xpitch = xres;
 330                 line_cnt = yres;
 331                 *out_pitch = lcdc_pitch;
 332                 save_lines = plane->marker->size / (lcdc_pitch >> 10) / 2;
 333                 save_lines &= 0xff;
 334         }
 335         bnm = (save_lines - 1) << 16;
 336
 337         /* TODO: we better to check if we have enough MERAM buffer size */
 338
 339         /* set up ICB */
 340         meram_write_icb(priv->base, plane->cache->index,  MExxBSIZE,
 341                         MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
 342         meram_write_icb(priv->base, plane->marker->index, MExxBSIZE,
 343                         MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
 344
 345         meram_write_icb(priv->base, plane->cache->index,  MExxMNCF, bnm);
 346         meram_write_icb(priv->base, plane->marker->index, MExxMNCF, bnm);
 347
 348         meram_write_icb(priv->base, plane->cache->index,  MExxSBSIZE, xpitch);
 349         meram_write_icb(priv->base, plane->marker->index, MExxSBSIZE, xpitch);
 350
 351         /* save a cache unit size */
 352         plane->cache->cache_unit = xres * save_lines;
 353         plane->marker->cache_unit = xres * save_lines;
 354
 355         /*
 356          * Set MERAM for framebuffer
 357          *
 358          * we also chain the cache_icb and the marker_icb.
 359          * we also split the allocated MERAM buffer between two ICBs.
 360          */
 361         meram_write_icb(priv->base, plane->cache->index, MExxCTL,
 362                         MERAM_MExxCTL_VAL(plane->marker->index, marker->offset)
 363                         | MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
 364                         MExxCTL_MD_FB);
 365         meram_write_icb(priv->base, plane->marker->index, MExxCTL,
 366                         MERAM_MExxCTL_VAL(plane->cache->index, marker->offset +
 367                                           plane->marker->size / 2) |
 368                         MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
 369                         MExxCTL_MD_FB);
 370
 371         return 0;
 372 }
 373
 374 static void meram_plane_cleanup(struct sh_mobile_meram_priv *priv,
 375                                 struct sh_mobile_meram_fb_plane *plane)
 376 {
 377         /* disable ICB */
 378         meram_write_icb(priv->base, plane->cache->index,  MExxCTL,
 379                         MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
 380         meram_write_icb(priv->base, plane->marker->index, MExxCTL,
 381                         MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
 382
 383         plane->cache->cache_unit = 0;
 384         plane->marker->cache_unit = 0;
 385 }
 386
 387 /* -----------------------------------------------------------------------------
 388  * LCDC cache operations
 389  */
 390
 391 /* Allocate memory for the ICBs and mark them as used. */
 392 static struct sh_mobile_meram_fb_cache *
 393 meram_cache_alloc(struct sh_mobile_meram_priv *priv,
 394                   const struct sh_mobile_meram_cfg *cfg,
 395                   int pixelformat)
 396 {
 397         unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1;
 398         struct sh_mobile_meram_fb_cache *cache;
 399         int ret;
 400
 401         cache = kzalloc(sizeof(*cache), GFP_KERNEL);
 402         if (cache == NULL)
 403                 return ERR_PTR(-ENOMEM);
 404
 405         cache->nplanes = nplanes;
 406
 407         ret = meram_plane_alloc(priv, &cache->planes[0],
 408                                 cfg->icb[0].meram_size);
 409         if (ret < 0)
 410                 goto error;
 411
 412         cache->planes[0].marker->current_reg = 1;
 413         cache->planes[0].marker->pixelformat = pixelformat;
 414
 415         if (cache->nplanes == 1)
 416                 return cache;
 417
 418         ret = meram_plane_alloc(priv, &cache->planes[1],
 419                                 cfg->icb[1].meram_size);
 420         if (ret < 0) {
 421                 meram_plane_free(priv, &cache->planes[0]);
 422                 goto error;
 423         }
 424
 425         return cache;
 426
 427 error:
 428         kfree(cache);
 429         return ERR_PTR(-ENOMEM);
 430 }
 431
 432 static void *sh_mobile_cache_alloc(struct sh_mobile_meram_info *pdata,
 433                                    const struct sh_mobile_meram_cfg *cfg,
 434                                    unsigned int xres, unsigned int yres,
 435                                    unsigned int pixelformat,
 436                                    unsigned int *pitch)
 437 {
 438         struct sh_mobile_meram_fb_cache *cache;
 439         struct sh_mobile_meram_priv *priv = pdata->priv;
 440         struct platform_device *pdev = pdata->pdev;
 441         unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1;
 442         unsigned int out_pitch;
 443
 444         if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
 445             pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
 446             pixelformat != SH_MOBILE_MERAM_PF_RGB)
 447                 return ERR_PTR(-EINVAL);
 448
 449         dev_dbg(&pdev->dev, "registering %dx%d (%s)", xres, yres,
 450                 !pixelformat ? "yuv" : "rgb");
 451
 452         /* we can't handle wider than 8192px */
 453         if (xres > 8192) {
 454                 dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
 455                 return ERR_PTR(-EINVAL);
 456         }
 457
 458         if (cfg->icb[0].meram_size == 0)
 459                 return ERR_PTR(-EINVAL);
 460
 461         if (nplanes == 2 && cfg->icb[1].meram_size == 0)
 462                 return ERR_PTR(-EINVAL);
 463
 464         mutex_lock(&priv->lock);
 465
 466         /* We now register the ICBs and allocate the MERAM regions. */
 467         cache = meram_cache_alloc(priv, cfg, pixelformat);
 468         if (IS_ERR(cache)) {
 469                 dev_err(&pdev->dev, "MERAM allocation failed (%ld).",
 470                         PTR_ERR(cache));
 471                 goto err;
 472         }
 473
 474         /* initialize MERAM */
 475         meram_plane_init(priv, &cache->planes[0], xres, yres, &out_pitch);
 476         *pitch = out_pitch;
 477         if (pixelformat == SH_MOBILE_MERAM_PF_NV)
 478                 meram_plane_init(priv, &cache->planes[1],
 479                                  xres, (yres + 1) / 2, &out_pitch);
 480         else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
 481                 meram_plane_init(priv, &cache->planes[1],
 482                                  2 * xres, (yres + 1) / 2, &out_pitch);
 483
 484 err:
 485         mutex_unlock(&priv->lock);
 486         return cache;
 487 }
 488
 489 static void
 490 sh_mobile_cache_free(struct sh_mobile_meram_info *pdata, void *data)
 491 {
 492         struct sh_mobile_meram_fb_cache *cache = data;
 493         struct sh_mobile_meram_priv *priv = pdata->priv;
 494
 495         mutex_lock(&priv->lock);
 496
 497         /* Cleanup and free. */
 498         meram_plane_cleanup(priv, &cache->planes[0]);
 499         meram_plane_free(priv, &cache->planes[0]);
 500
 501         if (cache->nplanes == 2) {
 502                 meram_plane_cleanup(priv, &cache->planes[1]);
 503                 meram_plane_free(priv, &cache->planes[1]);
 504         }
 505
 506         kfree(cache);
 507
 508         mutex_unlock(&priv->lock);
 509 }
 510
 511 static void
 512 sh_mobile_cache_update(struct sh_mobile_meram_info *pdata, void *data,
 513                        unsigned long base_addr_y, unsigned long base_addr_c,
 514                        unsigned long *icb_addr_y, unsigned long *icb_addr_c)
 515 {
 516         struct sh_mobile_meram_fb_cache *cache = data;
 517         struct sh_mobile_meram_priv *priv = pdata->priv;
 518
 519         mutex_lock(&priv->lock);
 520
 521         meram_set_next_addr(priv, cache, base_addr_y, base_addr_c);
 522         meram_get_next_icb_addr(pdata, cache, icb_addr_y, icb_addr_c);
 523
 524         mutex_unlock(&priv->lock);
 525 }
 526
 527 static struct sh_mobile_meram_ops sh_mobile_meram_ops = {
 528         .module                 = THIS_MODULE,
 529         .cache_alloc            = sh_mobile_cache_alloc,
 530         .cache_free             = sh_mobile_cache_free,
 531         .cache_update           = sh_mobile_cache_update,
 532 };
 533
 534 /* -----------------------------------------------------------------------------
 535  * Power management
 536  */
 537
 538 static int sh_mobile_meram_suspend(struct device *dev)
 539 {
 540         struct platform_device *pdev = to_platform_device(dev);
 541         struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
 542         unsigned int i, j;
 543
 544         for (i = 0; i < MERAM_REGS_SIZE; i++)
 545                 priv->regs[i] = meram_read_reg(priv->base, common_regs[i]);
 546
 547         for (i = 0; i < 32; i++) {
 548                 if (!test_bit(i, &priv->used_icb))
 549                         continue;
 550                 for (j = 0; j < ICB_REGS_SIZE; j++) {
 551                         priv->icbs[i].regs[j] =
 552                                 meram_read_icb(priv->base, i, icb_regs[j]);
 553                         /* Reset ICB on resume */
 554                         if (icb_regs[j] == MExxCTL)
 555                                 priv->icbs[i].regs[j] |=
 556                                         MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF;
 557                 }
 558         }
 559         return 0;
 560 }
 561
 562 static int sh_mobile_meram_resume(struct device *dev)
 563 {
 564         struct platform_device *pdev = to_platform_device(dev);
 565         struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
 566         unsigned int i, j;
 567
 568         for (i = 0; i < 32; i++) {
 569                 if (!test_bit(i, &priv->used_icb))
 570                         continue;
 571                 for (j = 0; j < ICB_REGS_SIZE; j++)
 572                         meram_write_icb(priv->base, i, icb_regs[j],
 573                                         priv->icbs[i].regs[j]);
 574         }
 575
 576         for (i = 0; i < MERAM_REGS_SIZE; i++)
 577                 meram_write_reg(priv->base, common_regs[i], priv->regs[i]);
 578         return 0;
 579 }
 580
 581 static UNIVERSAL_DEV_PM_OPS(sh_mobile_meram_dev_pm_ops,
 582                             sh_mobile_meram_suspend,
 583                             sh_mobile_meram_resume, NULL);
 584
 585 /* -----------------------------------------------------------------------------
 586  * Probe/remove and driver init/exit
 587  */
 588
 589 static int __devinit sh_mobile_meram_probe(struct platform_device *pdev)
 590 {
 591         struct sh_mobile_meram_priv *priv;
 592         struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
 593         struct resource *regs;
 594         struct resource *meram;
 595         unsigned int i;
 596         int error;
 597
 598         if (!pdata) {
 599                 dev_err(&pdev->dev, "no platform data defined\n");
 600                 return -EINVAL;
 601         }
 602
 603         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 604         meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 605         if (regs == NULL || meram == NULL) {
 606                 dev_err(&pdev->dev, "cannot get platform resources\n");
 607                 return -ENOENT;
 608         }
 609
 610         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 611         if (!priv) {
 612                 dev_err(&pdev->dev, "cannot allocate device data\n");
 613                 return -ENOMEM;
 614         }
 615
 616         /* Initialize private data. */
 617         mutex_init(&priv->lock);
 618         priv->used_icb = pdata->reserved_icbs;
 619
 620         for (i = 0; i < MERAM_ICB_NUM; ++i)
 621                 priv->icbs[i].index = i;
 622
 623         pdata->ops = &sh_mobile_meram_ops;
 624         pdata->priv = priv;
 625         pdata->pdev = pdev;
 626
 627         /* Request memory regions and remap the registers. */
 628         if (!request_mem_region(regs->start, resource_size(regs), pdev->name)) {
 629                 dev_err(&pdev->dev, "MERAM registers region already claimed\n");
 630                 error = -EBUSY;
 631                 goto err_req_regs;
 632         }
 633
 634         if (!request_mem_region(meram->start, resource_size(meram),
 635                                 pdev->name)) {
 636                 dev_err(&pdev->dev, "MERAM memory region already claimed\n");
 637                 error = -EBUSY;
 638                 goto err_req_meram;
 639         }
 640
 641         priv->base = ioremap_nocache(regs->start, resource_size(regs));
 642         if (!priv->base) {
 643                 dev_err(&pdev->dev, "ioremap failed\n");
 644                 error = -EFAULT;
 645                 goto err_ioremap;
 646         }
 647
 648         priv->meram = meram->start;
 649
 650         /* Create and initialize the MERAM memory pool. */
 651         priv->pool = gen_pool_create(ilog2(MERAM_GRANULARITY), -1);
 652         if (priv->pool == NULL) {
 653                 error = -ENOMEM;
 654                 goto err_genpool;
 655         }
 656
 657         error = gen_pool_add(priv->pool, meram->start, resource_size(meram),
 658                              -1);
 659         if (error < 0)
 660                 goto err_genpool;
 661
 662         /* initialize ICB addressing mode */
 663         if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
 664                 meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
 665
 666         platform_set_drvdata(pdev, priv);
 667         pm_runtime_enable(&pdev->dev);
 668
 669         dev_info(&pdev->dev, "sh_mobile_meram initialized.");
 670
 671         return 0;
 672
 673 err_genpool:
 674         if (priv->pool)
 675                 gen_pool_destroy(priv->pool);
 676         iounmap(priv->base);
 677 err_ioremap:
 678         release_mem_region(meram->start, resource_size(meram));
 679 err_req_meram:
 680         release_mem_region(regs->start, resource_size(regs));
 681 err_req_regs:
 682         mutex_destroy(&priv->lock);
 683         kfree(priv);
 684
 685         return error;
 686 }
 687
 688
 689 static int sh_mobile_meram_remove(struct platform_device *pdev)
 690 {
 691         struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
 692         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 693         struct resource *meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 694
 695         pm_runtime_disable(&pdev->dev);
 696
 697         gen_pool_destroy(priv->pool);
 698
 699         iounmap(priv->base);
 700         release_mem_region(meram->start, resource_size(meram));
 701         release_mem_region(regs->start, resource_size(regs));
 702
 703         mutex_destroy(&priv->lock);
 704
 705         kfree(priv);
 706
 707         return 0;
 708 }
 709
 710 static struct platform_driver sh_mobile_meram_driver = {
 711         .driver = {
 712                 .name           = "sh_mobile_meram",
 713                 .owner          = THIS_MODULE,
 714                 .pm             = &sh_mobile_meram_dev_pm_ops,
 715         },
 716         .probe          = sh_mobile_meram_probe,
 717         .remove         = sh_mobile_meram_remove,
 718 };
 719
 720 module_platform_driver(sh_mobile_meram_driver);
 721
 722 MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
 723 MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
 724 MODULE_LICENSE("GPL v2");