projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:


30a3305ba3668d0a36aa6cadb8e358307b91c1e9
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mobile_meram.c
1 /*
2 * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
3 *
4 * Copyright (c) 2011 Damian Hobson-Garcia <dhobsong@igel.co.jp>
5 * Takanari Hayama <taki@igel.co.jp>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19
20 #include <video/sh_mobile_meram.h>
21
22 /* -----------------------------------------------------------------------------
23 * MERAM registers
24 */
25
26 #define MEVCR1 0x4
27 #define MEVCR1_RST (1 << 31)
28 #define MEVCR1_WD (1 << 30)
29 #define MEVCR1_AMD1 (1 << 29)
30 #define MEVCR1_AMD0 (1 << 28)
31 #define MEQSEL1 0x40
32 #define MEQSEL2 0x44
33
34 #define MExxCTL 0x400
35 #define MExxCTL_BV (1 << 31)
36 #define MExxCTL_BSZ_SHIFT 28
37 #define MExxCTL_MSAR_MASK (0x7ff << MExxCTL_MSAR_SHIFT)
38 #define MExxCTL_MSAR_SHIFT 16
39 #define MExxCTL_NXT_MASK (0x1f << MExxCTL_NXT_SHIFT)
40 #define MExxCTL_NXT_SHIFT 11
41 #define MExxCTL_WD1 (1 << 10)
42 #define MExxCTL_WD0 (1 << 9)
43 #define MExxCTL_WS (1 << 8)
44 #define MExxCTL_CB (1 << 7)
45 #define MExxCTL_WBF (1 << 6)
46 #define MExxCTL_WF (1 << 5)
47 #define MExxCTL_RF (1 << 4)
48 #define MExxCTL_CM (1 << 3)
49 #define MExxCTL_MD_READ (1 << 0)
50 #define MExxCTL_MD_WRITE (2 << 0)
51 #define MExxCTL_MD_ICB_WB (3 << 0)
52 #define MExxCTL_MD_ICB (4 << 0)
53 #define MExxCTL_MD_FB (7 << 0)
54 #define MExxCTL_MD_MASK (7 << 0)
55 #define MExxBSIZE 0x404
56 #define MExxBSIZE_RCNT_SHIFT 28
57 #define MExxBSIZE_YSZM1_SHIFT 16
58 #define MExxBSIZE_XSZM1_SHIFT 0
59 #define MExxMNCF 0x408
60 #define MExxMNCF_KWBNM_SHIFT 28
61 #define MExxMNCF_KRBNM_SHIFT 24
62 #define MExxMNCF_BNM_SHIFT 16
63 #define MExxMNCF_XBV (1 << 15)
64 #define MExxMNCF_CPL_YCBCR444 (1 << 12)
65 #define MExxMNCF_CPL_YCBCR420 (2 << 12)
66 #define MExxMNCF_CPL_YCBCR422 (3 << 12)
67 #define MExxMNCF_CPL_MSK (3 << 12)
68 #define MExxMNCF_BL (1 << 2)
69 #define MExxMNCF_LNM_SHIFT 0
70 #define MExxSARA 0x410
71 #define MExxSARB 0x414
72 #define MExxSBSIZE 0x418
73 #define MExxSBSIZE_HDV (1 << 31)
74 #define MExxSBSIZE_HSZ16 (0 << 28)
75 #define MExxSBSIZE_HSZ32 (1 << 28)
76 #define MExxSBSIZE_HSZ64 (2 << 28)
77 #define MExxSBSIZE_HSZ128 (3 << 28)
78 #define MExxSBSIZE_SBSIZZ_SHIFT 0
79
80 #define MERAM_MExxCTL_VAL(next, addr) \
81 ((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \
82 (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK))
83 #define MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \
84 (((rcnt) << MExxBSIZE_RCNT_SHIFT) | \
85 ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \
86 ((xszm1) << MExxBSIZE_XSZM1_SHIFT))
87
88 static const unsigned long common_regs[] = {
89 MEVCR1,
90 MEQSEL1,
91 MEQSEL2,
92 };
93 #define MERAM_REGS_SIZE ARRAY_SIZE(common_regs)
94
95 static const unsigned long icb_regs[] = {
96 MExxCTL,
97 MExxBSIZE,
98 MExxMNCF,
99 MExxSARA,
100 MExxSARB,
101 MExxSBSIZE,
102 };
103 #define ICB_REGS_SIZE ARRAY_SIZE(icb_regs)
104
105 /*
106 * sh_mobile_meram_icb - MERAM ICB information
107 * @regs: Registers cache
108 * @region: Start and end addresses of the MERAM region
109 * @cache_unit: Bytes to cache per ICB
110 * @pixelformat: Video pixel format of the data stored in the ICB
111 * @current_reg: Which of Start Address Register A (0) or B (1) is in use
112 */
113 struct sh_mobile_meram_icb {
114 unsigned long regs[ICB_REGS_SIZE];
115
116 unsigned long region;
117 unsigned int cache_unit;
118 unsigned int pixelformat;
119 unsigned int current_reg;
120 };
121
122 #define MERAM_ICB_NUM 32
123
124 /*
125 * sh_mobile_meram_priv - MERAM device
126 * @base: Registers base address
127 * @regs: Registers cache
128 * @lock: Protects used_icb and icbs
129 * @used_icb: Bitmask of used ICBs
130 * @icbs: ICBs
131 */
132 struct sh_mobile_meram_priv {
133 void __iomem *base;
134 unsigned long regs[MERAM_REGS_SIZE];
135
136 struct mutex lock;
137 unsigned long used_icb;
138 struct sh_mobile_meram_icb icbs[MERAM_ICB_NUM];
139 };
140
141 /* settings */
142 #define MERAM_SEC_LINE 15
143 #define MERAM_LINE_WIDTH 2048
144
145 /* -----------------------------------------------------------------------------
146 * Registers access
147 */
148
149 #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20)
150
151 static inline void meram_write_icb(void __iomem *base, unsigned int idx,
152 unsigned int off, unsigned long val)
153 {
154 iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
155 }
156
157 static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx,
158 unsigned int off)
159 {
160 return ioread32(MERAM_ICB_OFFSET(base, idx, off));
161 }
162
163 static inline void meram_write_reg(void __iomem *base, unsigned int off,
164 unsigned long val)
165 {
166 iowrite32(val, base + off);
167 }
168
169 static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off)
170 {
171 return ioread32(base + off);
172 }
173
174 /* -----------------------------------------------------------------------------
175 * Allocation
176 */
177
178 #define MERAM_CACHE_START(p) ((p) >> 16)
179 #define MERAM_CACHE_END(p) ((p) & 0xffff)
180 #define MERAM_CACHE_SET(o, s) ((((o) & 0xffff) << 16) | \
181 (((o) + (s) - 1) & 0xffff))
182
183 /* Check if there's no overlaps in MERAM allocation. */
184 static int meram_check_overlap(struct sh_mobile_meram_priv *priv,
185 const struct sh_mobile_meram_icb_cfg *new)
186 {
187 unsigned int used_start, used_end, meram_start, meram_end;
188 unsigned int i;
189
190 /* valid ICB? */
191 if (new->marker_icb & ~0x1f || new->cache_icb & ~0x1f)
192 return 1;
193
194 if (test_bit(new->marker_icb, &priv->used_icb) ||
195 test_bit(new->cache_icb, &priv->used_icb))
196 return 1;
197
198 for (i = 0; i < MERAM_ICB_NUM; i++) {
199 if (!test_bit(i, &priv->used_icb))
200 continue;
201
202 used_start = MERAM_CACHE_START(priv->icbs[i].region);
203 used_end = MERAM_CACHE_END(priv->icbs[i].region);
204 meram_start = new->meram_offset;
205 meram_end = new->meram_offset + new->meram_size;
206
207 if ((meram_start >= used_start && meram_start < used_end) ||
208 (meram_end > used_start && meram_end < used_end))
209 return 1;
210 }
211
212 return 0;
213 }
214
215 /* Mark the specified ICB as used. */
216 static void meram_mark(struct sh_mobile_meram_priv *priv,
217 const struct sh_mobile_meram_icb_cfg *new,
218 int pixelformat)
219 {
220 __set_bit(new->marker_icb, &priv->used_icb);
221 __set_bit(new->cache_icb, &priv->used_icb);
222
223 priv->icbs[new->marker_icb].region = MERAM_CACHE_SET(new->meram_offset,
224 new->meram_size);
225 priv->icbs[new->cache_icb].region = MERAM_CACHE_SET(new->meram_offset,
226 new->meram_size);
227 priv->icbs[new->marker_icb].current_reg = 1;
228 priv->icbs[new->marker_icb].pixelformat = pixelformat;
229 }
230
231 /* Unmark the specified ICB as used. */
232 static void meram_unmark(struct sh_mobile_meram_priv *priv,
233 const struct sh_mobile_meram_icb_cfg *icb)
234 {
235 __clear_bit(icb->marker_icb, &priv->used_icb);
236 __clear_bit(icb->cache_icb, &priv->used_icb);
237 }
238
239 /* Is this a YCbCr(NV12, NV16 or NV24) colorspace? */
240 static int is_nvcolor(int cspace)
241 {
242 if (cspace == SH_MOBILE_MERAM_PF_NV ||
243 cspace == SH_MOBILE_MERAM_PF_NV24)
244 return 1;
245 return 0;
246 }
247
248 /* Set the next address to fetch. */
249 static void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
250 const struct sh_mobile_meram_cfg *cfg,
251 unsigned long base_addr_y,
252 unsigned long base_addr_c)
253 {
254 struct sh_mobile_meram_icb *icb = &priv->icbs[cfg->icb[0].marker_icb];
255 unsigned long target;
256
257 icb->current_reg ^= 1;
258 target = icb->current_reg ? MExxSARB : MExxSARA;
259
260 /* set the next address to fetch */
261 meram_write_icb(priv->base, cfg->icb[0].cache_icb, target,
262 base_addr_y);
263 meram_write_icb(priv->base, cfg->icb[0].marker_icb, target,
264 base_addr_y +
265 priv->icbs[cfg->icb[0].marker_icb].cache_unit);
266
267 if (is_nvcolor(icb->pixelformat)) {
268 meram_write_icb(priv->base, cfg->icb[1].cache_icb, target,
269 base_addr_c);
270 meram_write_icb(priv->base, cfg->icb[1].marker_icb, target,
271 base_addr_c +
272 priv->icbs[cfg->icb[1].marker_icb].cache_unit);
273 }
274 }
275
276 /* Get the next ICB address. */
277 static void
278 meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
279 const struct sh_mobile_meram_cfg *cfg,
280 unsigned long *icb_addr_y, unsigned long *icb_addr_c)
281 {
282 struct sh_mobile_meram_priv *priv = pdata->priv;
283 struct sh_mobile_meram_icb *icb = &priv->icbs[cfg->icb[0].marker_icb];
284 unsigned long icb_offset;
285
286 if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
287 icb_offset = 0x80000000 | (icb->current_reg << 29);
288 else
289 icb_offset = 0xc0000000 | (icb->current_reg << 23);
290
291 *icb_addr_y = icb_offset | (cfg->icb[0].marker_icb << 24);
292 if (is_nvcolor(icb->pixelformat))
293 *icb_addr_c = icb_offset | (cfg->icb[1].marker_icb << 24);
294 }
295
296 #define MERAM_CALC_BYTECOUNT(x, y) \
297 (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
298
299 /* Initialize MERAM. */
300 static int meram_init(struct sh_mobile_meram_priv *priv,
301 const struct sh_mobile_meram_icb_cfg *icb,
302 unsigned int xres, unsigned int yres,
303 unsigned int *out_pitch)
304 {
305 unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
306 unsigned long bnm;
307 unsigned int lcdc_pitch;
308 unsigned int xpitch;
309 unsigned int line_cnt;
310 unsigned int save_lines;
311
312 /* adjust pitch to 1024, 2048, 4096 or 8192 */
313 lcdc_pitch = (xres - 1) | 1023;
314 lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
315 lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
316 lcdc_pitch += 1;
317
318 /* derive settings */
319 if (lcdc_pitch == 8192 && yres >= 1024) {
320 lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
321 line_cnt = total_byte_count >> 11;
322 *out_pitch = xres;
323 save_lines = (icb->meram_size / 16 / MERAM_SEC_LINE);
324 save_lines *= MERAM_SEC_LINE;
325 } else {
326 xpitch = xres;
327 line_cnt = yres;
328 *out_pitch = lcdc_pitch;
329 save_lines = icb->meram_size / (lcdc_pitch >> 10) / 2;
330 save_lines &= 0xff;
331 }
332 bnm = (save_lines - 1) << 16;
333
334 /* TODO: we better to check if we have enough MERAM buffer size */
335
336 /* set up ICB */
337 meram_write_icb(priv->base, icb->cache_icb, MExxBSIZE,
338 MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
339 meram_write_icb(priv->base, icb->marker_icb, MExxBSIZE,
340 MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
341
342 meram_write_icb(priv->base, icb->cache_icb, MExxMNCF, bnm);
343 meram_write_icb(priv->base, icb->marker_icb, MExxMNCF, bnm);
344
345 meram_write_icb(priv->base, icb->cache_icb, MExxSBSIZE, xpitch);
346 meram_write_icb(priv->base, icb->marker_icb, MExxSBSIZE, xpitch);
347
348 /* save a cache unit size */
349 priv->icbs[icb->cache_icb].cache_unit = xres * save_lines;
350 priv->icbs[icb->marker_icb].cache_unit = xres * save_lines;
351
352 /*
353 * Set MERAM for framebuffer
354 *
355 * we also chain the cache_icb and the marker_icb.
356 * we also split the allocated MERAM buffer between two ICBs.
357 */
358 meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
359 MERAM_MExxCTL_VAL(icb->marker_icb, icb->meram_offset) |
360 MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
361 MExxCTL_MD_FB);
362 meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
363 MERAM_MExxCTL_VAL(icb->cache_icb, icb->meram_offset +
364 icb->meram_size / 2) |
365 MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
366 MExxCTL_MD_FB);
367
368 return 0;
369 }
370
371 static void meram_deinit(struct sh_mobile_meram_priv *priv,
372 const struct sh_mobile_meram_icb_cfg *icb)
373 {
374 /* disable ICB */
375 meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
376 MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
377 meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
378 MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
379
380 priv->icbs[icb->cache_icb].cache_unit = 0;
381 priv->icbs[icb->marker_icb].cache_unit = 0;
382 }
383
384 /* -----------------------------------------------------------------------------
385 * Registration/unregistration
386 */
387
388 static int sh_mobile_meram_register(struct sh_mobile_meram_info *pdata,
389 const struct sh_mobile_meram_cfg *cfg,
390 unsigned int xres, unsigned int yres,
391 unsigned int pixelformat,
392 unsigned long base_addr_y,
393 unsigned long base_addr_c,
394 unsigned long *icb_addr_y,
395 unsigned long *icb_addr_c,
396 unsigned int *pitch)
397 {
398 struct platform_device *pdev;
399 struct sh_mobile_meram_priv *priv;
400 unsigned int out_pitch;
401 unsigned int n;
402 int error = 0;
403
404 if (!pdata || !pdata->priv || !pdata->pdev || !cfg)
405 return -EINVAL;
406
407 if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
408 pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
409 pixelformat != SH_MOBILE_MERAM_PF_RGB)
410 return -EINVAL;
411
412 priv = pdata->priv;
413 pdev = pdata->pdev;
414
415 dev_dbg(&pdev->dev, "registering %dx%d (%s) (y=%08lx, c=%08lx)",
416 xres, yres, (!pixelformat) ? "yuv" : "rgb",
417 base_addr_y, base_addr_c);
418
419 /* we can't handle wider than 8192px */
420 if (xres > 8192) {
421 dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
422 return -EINVAL;
423 }
424
425 /* do we have at least one ICB config? */
426 if (cfg->icb[0].marker_icb < 0 || cfg->icb[0].cache_icb < 0) {
427 dev_err(&pdev->dev, "at least one ICB is required.");
428 return -EINVAL;
429 }
430
431 mutex_lock(&priv->lock);
432
433 /* make sure that there's no overlaps */
434 if (meram_check_overlap(priv, &cfg->icb[0])) {
435 dev_err(&pdev->dev, "conflicting config detected.");
436 error = -EINVAL;
437 goto err;
438 }
439 n = 1;
440
441 /* do the same if we have the second ICB set */
442 if (cfg->icb[1].marker_icb >= 0 && cfg->icb[1].cache_icb >= 0) {
443 if (meram_check_overlap(priv, &cfg->icb[1])) {
444 dev_err(&pdev->dev, "conflicting config detected.");
445 error = -EINVAL;
446 goto err;
447 }
448 n = 2;
449 }
450
451 if (is_nvcolor(pixelformat) && n != 2) {
452 dev_err(&pdev->dev, "requires two ICB sets for planar Y/C.");
453 error = -EINVAL;
454 goto err;
455 }
456
457 /* we now register the ICB */
458 meram_mark(priv, &cfg->icb[0], pixelformat);
459 if (is_nvcolor(pixelformat))
460 meram_mark(priv, &cfg->icb[1], pixelformat);
461
462 /* initialize MERAM */
463 meram_init(priv, &cfg->icb[0], xres, yres, &out_pitch);
464 *pitch = out_pitch;
465 if (pixelformat == SH_MOBILE_MERAM_PF_NV)
466 meram_init(priv, &cfg->icb[1], xres, (yres + 1) / 2,
467 &out_pitch);
468 else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
469 meram_init(priv, &cfg->icb[1], 2 * xres, (yres + 1) / 2,
470 &out_pitch);
471
472 meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
473 meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
474
475 dev_dbg(&pdev->dev, "registered - can access via y=%08lx, c=%08lx",
476 *icb_addr_y, *icb_addr_c);
477
478 err:
479 mutex_unlock(&priv->lock);
480 return error;
481 }
482
483 static int sh_mobile_meram_unregister(struct sh_mobile_meram_info *pdata,
484 const struct sh_mobile_meram_cfg *cfg)
485 {
486 struct sh_mobile_meram_priv *priv;
487 struct sh_mobile_meram_icb *icb;
488
489 if (!pdata || !pdata->priv || !cfg)
490 return -EINVAL;
491
492 priv = pdata->priv;
493 icb = &priv->icbs[cfg->icb[0].marker_icb];
494
495 mutex_lock(&priv->lock);
496
497 /* deinit & unmark */
498 if (is_nvcolor(icb->pixelformat)) {
499 meram_deinit(priv, &cfg->icb[1]);
500 meram_unmark(priv, &cfg->icb[1]);
501 }
502 meram_deinit(priv, &cfg->icb[0]);
503 meram_unmark(priv, &cfg->icb[0]);
504
505 mutex_unlock(&priv->lock);
506
507 return 0;
508 }
509
510 static int sh_mobile_meram_update(struct sh_mobile_meram_info *pdata,
511 const struct sh_mobile_meram_cfg *cfg,
512 unsigned long base_addr_y,
513 unsigned long base_addr_c,
514 unsigned long *icb_addr_y,
515 unsigned long *icb_addr_c)
516 {
517 struct sh_mobile_meram_priv *priv;
518
519 if (!pdata || !pdata->priv || !cfg)
520 return -EINVAL;
521
522 priv = pdata->priv;
523
524 mutex_lock(&priv->lock);
525
526 meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
527 meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
528
529 mutex_unlock(&priv->lock);
530
531 return 0;
532 }
533
534 static struct sh_mobile_meram_ops sh_mobile_meram_ops = {
535 .module = THIS_MODULE,
536 .meram_register = sh_mobile_meram_register,
537 .meram_unregister = sh_mobile_meram_unregister,
538 .meram_update = sh_mobile_meram_update,
539 };
540
541 /* -----------------------------------------------------------------------------
542 * Power management
543 */
544
545 static int sh_mobile_meram_runtime_suspend(struct device *dev)
546 {
547 struct platform_device *pdev = to_platform_device(dev);
548 struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
549 unsigned int i, j;
550
551 for (i = 0; i < MERAM_REGS_SIZE; i++)
552 priv->regs[i] = meram_read_reg(priv->base, common_regs[i]);
553
554 for (i = 0; i < 32; i++) {
555 if (!test_bit(i, &priv->used_icb))
556 continue;
557 for (j = 0; j < ICB_REGS_SIZE; j++) {
558 priv->icbs[i].regs[j] =
559 meram_read_icb(priv->base, i, icb_regs[j]);
560 /* Reset ICB on resume */
561 if (icb_regs[j] == MExxCTL)
562 priv->icbs[i].regs[j] |=
563 MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF;
564 }
565 }
566 return 0;
567 }
568
569 static int sh_mobile_meram_runtime_resume(struct device *dev)
570 {
571 struct platform_device *pdev = to_platform_device(dev);
572 struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
573 unsigned int i, j;
574
575 for (i = 0; i < 32; i++) {
576 if (!test_bit(i, &priv->used_icb))
577 continue;
578 for (j = 0; j < ICB_REGS_SIZE; j++)
579 meram_write_icb(priv->base, i, icb_regs[j],
580 priv->icbs[i].regs[j]);
581 }
582
583 for (i = 0; i < MERAM_REGS_SIZE; i++)
584 meram_write_reg(priv->base, common_regs[i], priv->regs[i]);
585 return 0;
586 }
587
588 static const struct dev_pm_ops sh_mobile_meram_dev_pm_ops = {
589 .runtime_suspend = sh_mobile_meram_runtime_suspend,
590 .runtime_resume = sh_mobile_meram_runtime_resume,
591 };
592
593 /* -----------------------------------------------------------------------------
594 * Probe/remove and driver init/exit
595 */
596
597 static int __devinit sh_mobile_meram_probe(struct platform_device *pdev)
598 {
599 struct sh_mobile_meram_priv *priv;
600 struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
601 struct resource *regs;
602 struct resource *meram;
603 int error;
604
605 if (!pdata) {
606 dev_err(&pdev->dev, "no platform data defined\n");
607 return -EINVAL;
608 }
609
610 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611 meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
612 if (regs == NULL || meram == NULL) {
613 dev_err(&pdev->dev, "cannot get platform resources\n");
614 return -ENOENT;
615 }
616
617 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
618 if (!priv) {
619 dev_err(&pdev->dev, "cannot allocate device data\n");
620 return -ENOMEM;
621 }
622
623 /* initialize private data */
624 mutex_init(&priv->lock);
625 pdata->ops = &sh_mobile_meram_ops;
626 pdata->priv = priv;
627 pdata->pdev = pdev;
628
629 if (!request_mem_region(regs->start, resource_size(regs), pdev->name)) {
630 dev_err(&pdev->dev, "MERAM registers region already claimed\n");
631 error = -EBUSY;
632 goto err_req_regs;
633 }
634
635 if (!request_mem_region(meram->start, resource_size(meram),
636 pdev->name)) {
637 dev_err(&pdev->dev, "MERAM memory region already claimed\n");
638 error = -EBUSY;
639 goto err_req_meram;
640 }
641
642 priv->base = ioremap_nocache(regs->start, resource_size(regs));
643 if (!priv->base) {
644 dev_err(&pdev->dev, "ioremap failed\n");
645 error = -EFAULT;
646 goto err_ioremap;
647 }
648
649 /* initialize ICB addressing mode */
650 if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
651 meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
652
653 platform_set_drvdata(pdev, priv);
654 pm_runtime_enable(&pdev->dev);
655
656 dev_info(&pdev->dev, "sh_mobile_meram initialized.");
657
658 return 0;
659
660 err_ioremap:
661 release_mem_region(meram->start, resource_size(meram));
662 err_req_meram:
663 release_mem_region(regs->start, resource_size(regs));
664 err_req_regs:
665 mutex_destroy(&priv->lock);
666 kfree(priv);
667
668 return error;
669 }
670
671
672 static int sh_mobile_meram_remove(struct platform_device *pdev)
673 {
674 struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
675 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
676 struct resource *meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
677
678 pm_runtime_disable(&pdev->dev);
679
680 iounmap(priv->base);
681 release_mem_region(meram->start, resource_size(meram));
682 release_mem_region(regs->start, resource_size(regs));
683
684 mutex_destroy(&priv->lock);
685
686 kfree(priv);
687
688 return 0;
689 }
690
691 static struct platform_driver sh_mobile_meram_driver = {
692 .driver = {
693 .name = "sh_mobile_meram",
694 .owner = THIS_MODULE,
695 .pm = &sh_mobile_meram_dev_pm_ops,
696 },
697 .probe = sh_mobile_meram_probe,
698 .remove = sh_mobile_meram_remove,
699 };
700
701 module_platform_driver(sh_mobile_meram_driver);
702
703 MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
704 MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
705 MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)