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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / s3c2410fb.c
1 /*
2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 *
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
11 *
12 * ChangeLog
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
16 *
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
18 * - Removed the ioctl
19 * - use readl/writel instead of __raw_writel/__raw_readl
20 *
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
23 * debugging mesaages
24 * - Replaced 0 and 1 by on or off when reading the
25 * /sys files
26 *
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
32 *
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
36 *
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
38 * - minor cleanups
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
47 *
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
50 *
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
52 * - code cleanup
53 *
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
57 * - Backlight support
58 *
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
62 *
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
64 * - code cleanup
65 * - added a forgotten return in h1940fb_init
66 *
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
69 *
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
71 * - First version
72 */
73
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
78 #include <linux/mm.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
81 #include <linux/fb.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
89
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
93
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
98
99 #ifdef CONFIG_PM
100 #include <linux/pm.h>
101 #endif
102
103 #include "s3c2410fb.h"
104
105 static struct s3c2410fb_mach_info *mach_info;
106
107 /* Debugging stuff */
108 #ifdef CONFIG_FB_S3C2410_DEBUG
109 static int debug = 1;
110 #else
111 static int debug = 0;
112 #endif
113
114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
115
116 /* useful functions */
117
118 /* s3c2410fb_set_lcdaddr
119 *
120 * initialise lcd controller address pointers
121 */
122 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
123 {
124 unsigned long saddr1, saddr2, saddr3;
125 int line_length = info->var.xres * info->var.bits_per_pixel;
126
127 saddr1 = info->fix.smem_start >> 1;
128 saddr2 = info->fix.smem_start;
129 saddr2 += (line_length * info->var.yres) / 8;
130 saddr2 >>= 1;
131
132 saddr3 = S3C2410_OFFSIZE(0) |
133 S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
134
135 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
136 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
137 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
138
139 writel(saddr1, S3C2410_LCDSADDR1);
140 writel(saddr2, S3C2410_LCDSADDR2);
141 writel(saddr3, S3C2410_LCDSADDR3);
142 }
143
144 /* s3c2410fb_calc_pixclk()
145 *
146 * calculate divisor for clk->pixclk
147 */
148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
149 unsigned long pixclk)
150 {
151 unsigned long clk = clk_get_rate(fbi->clk);
152 unsigned long long div;
153
154 /* pixclk is in picoseoncds, our clock is in Hz
155 *
156 * Hz -> picoseconds is / 10^-12
157 */
158
159 div = (unsigned long long)clk * pixclk;
160 do_div(div, 1000000UL);
161 do_div(div, 1000000UL);
162
163 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
164 return div;
165 }
166
167 /*
168 * s3c2410fb_check_var():
169 * Get the video params out of 'var'. If a value doesn't fit, round it up,
170 * if it's too big, return -EINVAL.
171 *
172 */
173 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
174 struct fb_info *info)
175 {
176 struct s3c2410fb_info *fbi = info->par;
177 struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
178 struct s3c2410fb_display *display = NULL;
179 unsigned i;
180
181 dprintk("check_var(var=%p, info=%p)\n", var, info);
182
183 /* validate x/y resolution */
184
185 for (i = 0; i < mach_info->num_displays; i++)
186 if (var->yres == mach_info->displays[i].yres &&
187 var->xres == mach_info->displays[i].xres &&
188 var->bits_per_pixel == mach_info->displays[i].bpp) {
189 display = mach_info->displays + i;
190 fbi->current_display = i;
191 break;
192 }
193
194 if (!display) {
195 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
196 var->xres, var->yres, var->bits_per_pixel);
197 return -EINVAL;
198 }
199
200 /* it is always the size as the display */
201 var->xres_virtual = display->xres;
202 var->yres_virtual = display->yres;
203
204 /* copy lcd settings */
205 var->left_margin = display->left_margin;
206 var->right_margin = display->right_margin;
207
208 var->transp.offset = 0;
209 var->transp.length = 0;
210 /* set r/g/b positions */
211 switch (var->bits_per_pixel) {
212 case 1:
213 case 2:
214 case 4:
215 var->red.offset = 0;
216 var->red.length = var->bits_per_pixel;
217 var->green = var->red;
218 var->blue = var->red;
219 break;
220 case 8:
221 if (display->type != S3C2410_LCDCON1_TFT) {
222 /* 8 bpp 332 */
223 var->red.length = 3;
224 var->red.offset = 5;
225 var->green.length = 3;
226 var->green.offset = 2;
227 var->blue.length = 2;
228 var->blue.offset = 0;
229 } else {
230 var->red.offset = 0;
231 var->red.length = 8;
232 var->green = var->red;
233 var->blue = var->red;
234 }
235 break;
236 case 12:
237 /* 12 bpp 444 */
238 var->red.length = 4;
239 var->red.offset = 8;
240 var->green.length = 4;
241 var->green.offset = 4;
242 var->blue.length = 4;
243 var->blue.offset = 0;
244 break;
245
246 default:
247 case 16:
248 if (display->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) {
249 /* 16 bpp, 565 format */
250 var->red.offset = 11;
251 var->green.offset = 5;
252 var->blue.offset = 0;
253 var->red.length = 5;
254 var->green.length = 6;
255 var->blue.length = 5;
256 } else {
257 /* 16 bpp, 5551 format */
258 var->red.offset = 11;
259 var->green.offset = 6;
260 var->blue.offset = 1;
261 var->red.length = 5;
262 var->green.length = 5;
263 var->blue.length = 5;
264 }
265 break;
266 case 24:
267 /* 24 bpp 888 */
268 var->red.length = 8;
269 var->red.offset = 16;
270 var->green.length = 8;
271 var->green.offset = 8;
272 var->blue.length = 8;
273 var->blue.offset = 0;
274 break;
275
276
277 }
278 return 0;
279 }
280
281 /* s3c2410fb_calculate_stn_lcd_regs
282 *
283 * calculate register values from var settings
284 */
285 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
286 struct s3c2410fb_hw *regs)
287 {
288 const struct s3c2410fb_info *fbi = info->par;
289 const struct fb_var_screeninfo *var = &info->var;
290 int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
291 int hs = var->xres >> 2;
292 unsigned wdly = (var->left_margin >> 4) - 1;
293
294 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
295 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
296 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
297
298 if (type != S3C2410_LCDCON1_STN4)
299 hs >>= 1;
300
301 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
302
303 switch (var->bits_per_pixel) {
304 case 1:
305 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
306 break;
307 case 2:
308 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
309 break;
310 case 4:
311 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
312 break;
313 case 8:
314 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
315 hs *= 3;
316 break;
317 case 12:
318 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
319 hs *= 3;
320 break;
321
322 default:
323 /* invalid pixel depth */
324 dev_err(fbi->dev, "invalid bpp %d\n",
325 var->bits_per_pixel);
326 }
327 /* update X/Y info */
328 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
329 var->upper_margin, var->lower_margin, var->vsync_len);
330
331 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
332 var->left_margin, var->right_margin, var->hsync_len);
333
334 regs->lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
335 regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
336
337 if (wdly > 3)
338 wdly = 3;
339
340 regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
341 S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
342 S3C2410_LCDCON3_HOZVAL(hs - 1);
343 }
344
345 /* s3c2410fb_calculate_tft_lcd_regs
346 *
347 * calculate register values from var settings
348 */
349 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
350 struct s3c2410fb_hw *regs)
351 {
352 const struct s3c2410fb_info *fbi = info->par;
353 const struct fb_var_screeninfo *var = &info->var;
354
355 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
356 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
357 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
358
359 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
360
361 switch (var->bits_per_pixel) {
362 case 1:
363 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
364 break;
365 case 2:
366 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
367 break;
368 case 4:
369 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
370 break;
371 case 8:
372 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
373 break;
374 case 16:
375 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
376 break;
377
378 default:
379 /* invalid pixel depth */
380 dev_err(fbi->dev, "invalid bpp %d\n",
381 var->bits_per_pixel);
382 }
383 /* update X/Y info */
384 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
385 var->upper_margin, var->lower_margin, var->vsync_len);
386
387 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
388 var->left_margin, var->right_margin, var->hsync_len);
389
390 regs->lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
391 regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
392
393 regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
394 S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
395 S3C2410_LCDCON3_HOZVAL(var->xres - 1);
396 }
397
398 /* s3c2410fb_activate_var
399 *
400 * activate (set) the controller from the given framebuffer
401 * information
402 */
403 static void s3c2410fb_activate_var(struct fb_info *info)
404 {
405 struct s3c2410fb_info *fbi = info->par;
406 struct fb_var_screeninfo *var = &info->var;
407 struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
408 struct s3c2410fb_display *display = mach_info->displays +
409 fbi->current_display;
410
411 /* set display type */
412 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
413 fbi->regs.lcdcon1 |= display->type;
414
415 /* check to see if we need to update sync/borders */
416
417 if (!mach_info->fixed_syncs) {
418 fbi->regs.lcdcon2 =
419 S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
420 S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
421 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
422
423 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
424 fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
425 }
426
427 if (var->pixclock > 0) {
428 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
429
430 if (display->type == S3C2410_LCDCON1_TFT) {
431 clkdiv = (clkdiv / 2) - 1;
432 if (clkdiv < 0)
433 clkdiv = 0;
434 } else {
435 clkdiv = (clkdiv / 2);
436 if (clkdiv < 2)
437 clkdiv = 2;
438 }
439
440 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
441 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
442 }
443
444 if (display->type == S3C2410_LCDCON1_TFT)
445 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
446 else
447 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
448
449 /* write new registers */
450
451 dprintk("new register set:\n");
452 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
453 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
454 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
455 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
456 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
457
458 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
459 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
460 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
461 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
462 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
463
464 /* set lcd address pointers */
465 s3c2410fb_set_lcdaddr(info);
466
467 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
468 }
469
470 /*
471 * s3c2410fb_set_par - Alters the hardware state.
472 * @info: frame buffer structure that represents a single frame buffer
473 *
474 */
475 static int s3c2410fb_set_par(struct fb_info *info)
476 {
477 struct fb_var_screeninfo *var = &info->var;
478
479 switch (var->bits_per_pixel) {
480 case 16:
481 info->fix.visual = FB_VISUAL_TRUECOLOR;
482 break;
483 case 1:
484 info->fix.visual = FB_VISUAL_MONO01;
485 break;
486 default:
487 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
488 break;
489 }
490
491 info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
492
493 /* activate this new configuration */
494
495 s3c2410fb_activate_var(info);
496 return 0;
497 }
498
499 static void schedule_palette_update(struct s3c2410fb_info *fbi,
500 unsigned int regno, unsigned int val)
501 {
502 unsigned long flags;
503 unsigned long irqen;
504 void __iomem *regs = fbi->io;
505
506 local_irq_save(flags);
507
508 fbi->palette_buffer[regno] = val;
509
510 if (!fbi->palette_ready) {
511 fbi->palette_ready = 1;
512
513 /* enable IRQ */
514 irqen = readl(regs + S3C2410_LCDINTMSK);
515 irqen &= ~S3C2410_LCDINT_FRSYNC;
516 writel(irqen, regs + S3C2410_LCDINTMSK);
517 }
518
519 local_irq_restore(flags);
520 }
521
522 /* from pxafb.c */
523 static inline unsigned int chan_to_field(unsigned int chan,
524 struct fb_bitfield *bf)
525 {
526 chan &= 0xffff;
527 chan >>= 16 - bf->length;
528 return chan << bf->offset;
529 }
530
531 static int s3c2410fb_setcolreg(unsigned regno,
532 unsigned red, unsigned green, unsigned blue,
533 unsigned transp, struct fb_info *info)
534 {
535 struct s3c2410fb_info *fbi = info->par;
536 unsigned int val;
537
538 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
539 regno, red, green, blue); */
540
541 switch (info->fix.visual) {
542 case FB_VISUAL_TRUECOLOR:
543 /* true-colour, use pseudo-palette */
544
545 if (regno < 16) {
546 u32 *pal = info->pseudo_palette;
547
548 val = chan_to_field(red, &info->var.red);
549 val |= chan_to_field(green, &info->var.green);
550 val |= chan_to_field(blue, &info->var.blue);
551
552 pal[regno] = val;
553 }
554 break;
555
556 case FB_VISUAL_PSEUDOCOLOR:
557 if (regno < 256) {
558 /* currently assume RGB 5-6-5 mode */
559
560 val = ((red >> 0) & 0xf800);
561 val |= ((green >> 5) & 0x07e0);
562 val |= ((blue >> 11) & 0x001f);
563
564 writel(val, S3C2410_TFTPAL(regno));
565 schedule_palette_update(fbi, regno, val);
566 }
567
568 break;
569
570 default:
571 return 1; /* unknown type */
572 }
573
574 return 0;
575 }
576
577 /*
578 * s3c2410fb_blank
579 * @blank_mode: the blank mode we want.
580 * @info: frame buffer structure that represents a single frame buffer
581 *
582 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
583 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
584 * video mode which doesn't support it. Implements VESA suspend
585 * and powerdown modes on hardware that supports disabling hsync/vsync:
586 * blank_mode == 2: suspend vsync
587 * blank_mode == 3: suspend hsync
588 * blank_mode == 4: powerdown
589 *
590 * Returns negative errno on error, or zero on success.
591 *
592 */
593 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
594 {
595 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
596
597 if (mach_info == NULL)
598 return -EINVAL;
599
600 if (blank_mode == FB_BLANK_UNBLANK)
601 writel(0x0, S3C2410_TPAL);
602 else {
603 dprintk("setting TPAL to output 0x000000\n");
604 writel(S3C2410_TPAL_EN, S3C2410_TPAL);
605 }
606
607 return 0;
608 }
609
610 static int s3c2410fb_debug_show(struct device *dev,
611 struct device_attribute *attr, char *buf)
612 {
613 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
614 }
615 static int s3c2410fb_debug_store(struct device *dev,
616 struct device_attribute *attr,
617 const char *buf, size_t len)
618 {
619 if (mach_info == NULL)
620 return -EINVAL;
621
622 if (len < 1)
623 return -EINVAL;
624
625 if (strnicmp(buf, "on", 2) == 0 ||
626 strnicmp(buf, "1", 1) == 0) {
627 debug = 1;
628 printk(KERN_DEBUG "s3c2410fb: Debug On");
629 } else if (strnicmp(buf, "off", 3) == 0 ||
630 strnicmp(buf, "0", 1) == 0) {
631 debug = 0;
632 printk(KERN_DEBUG "s3c2410fb: Debug Off");
633 } else {
634 return -EINVAL;
635 }
636
637 return len;
638 }
639
640 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
641
642 static struct fb_ops s3c2410fb_ops = {
643 .owner = THIS_MODULE,
644 .fb_check_var = s3c2410fb_check_var,
645 .fb_set_par = s3c2410fb_set_par,
646 .fb_blank = s3c2410fb_blank,
647 .fb_setcolreg = s3c2410fb_setcolreg,
648 .fb_fillrect = cfb_fillrect,
649 .fb_copyarea = cfb_copyarea,
650 .fb_imageblit = cfb_imageblit,
651 };
652
653 /*
654 * s3c2410fb_map_video_memory():
655 * Allocates the DRAM memory for the frame buffer. This buffer is
656 * remapped into a non-cached, non-buffered, memory region to
657 * allow palette and pixel writes to occur without flushing the
658 * cache. Once this area is remapped, all virtual memory
659 * access to the video memory should occur at the new region.
660 */
661 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
662 {
663 struct s3c2410fb_info *fbi = info->par;
664
665 dprintk("map_video_memory(fbi=%p)\n", fbi);
666
667 fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
668 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
669 &fbi->map_dma, GFP_KERNEL);
670
671 fbi->map_size = info->fix.smem_len;
672
673 if (fbi->map_cpu) {
674 /* prevent initial garbage on screen */
675 dprintk("map_video_memory: clear %p:%08x\n",
676 fbi->map_cpu, fbi->map_size);
677 memset(fbi->map_cpu, 0xf0, fbi->map_size);
678
679 fbi->screen_dma = fbi->map_dma;
680 info->screen_base = fbi->map_cpu;
681 info->fix.smem_start = fbi->screen_dma;
682
683 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
684 fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
685 }
686
687 return fbi->map_cpu ? 0 : -ENOMEM;
688 }
689
690 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
691 {
692 dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
693 fbi->map_dma);
694 }
695
696 static inline void modify_gpio(void __iomem *reg,
697 unsigned long set, unsigned long mask)
698 {
699 unsigned long tmp;
700
701 tmp = readl(reg) & ~mask;
702 writel(tmp | set, reg);
703 }
704
705 /*
706 * s3c2410fb_init_registers - Initialise all LCD-related registers
707 */
708 static int s3c2410fb_init_registers(struct fb_info *info)
709 {
710 struct s3c2410fb_info *fbi = info->par;
711 unsigned long flags;
712 void __iomem *regs = fbi->io;
713
714 /* Initialise LCD with values from haret */
715
716 local_irq_save(flags);
717
718 /* modify the gpio(s) with interrupts set (bjd) */
719
720 modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
721 modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
722 modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
723 modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
724
725 local_irq_restore(flags);
726
727 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
728 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
729 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
730 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
731 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
732
733 s3c2410fb_set_lcdaddr(info);
734
735 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
736 writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
737
738 dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
739
740 /* ensure temporary palette disabled */
741 writel(0x00, regs + S3C2410_TPAL);
742
743 /* Enable video by setting the ENVID bit to 1 */
744 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
745 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
746 return 0;
747 }
748
749 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
750 {
751 unsigned int i;
752 void __iomem *regs = fbi->io;
753
754 fbi->palette_ready = 0;
755
756 for (i = 0; i < 256; i++) {
757 unsigned long ent = fbi->palette_buffer[i];
758 if (ent == PALETTE_BUFF_CLEAR)
759 continue;
760
761 writel(ent, regs + S3C2410_TFTPAL(i));
762
763 /* it seems the only way to know exactly
764 * if the palette wrote ok, is to check
765 * to see if the value verifies ok
766 */
767
768 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
769 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
770 else
771 fbi->palette_ready = 1; /* retry */
772 }
773 }
774
775 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
776 {
777 struct s3c2410fb_info *fbi = dev_id;
778 void __iomem *regs = fbi->io;
779 unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
780
781 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
782 if (fbi->palette_ready)
783 s3c2410fb_write_palette(fbi);
784
785 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
786 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
787 }
788
789 return IRQ_HANDLED;
790 }
791
792 static char driver_name[] = "s3c2410fb";
793
794 static int __init s3c2410fb_probe(struct platform_device *pdev)
795 {
796 struct s3c2410fb_info *info;
797 struct s3c2410fb_display *display;
798 struct fb_info *fbinfo;
799 struct s3c2410fb_hw *mregs;
800 struct resource *res;
801 int ret;
802 int irq;
803 int i;
804 int size;
805 u32 lcdcon1;
806
807 mach_info = pdev->dev.platform_data;
808 if (mach_info == NULL) {
809 dev_err(&pdev->dev,
810 "no platform data for lcd, cannot attach\n");
811 return -EINVAL;
812 }
813
814 display = mach_info->displays + mach_info->default_display;
815 mregs = &display->regs;
816
817 irq = platform_get_irq(pdev, 0);
818 if (irq < 0) {
819 dev_err(&pdev->dev, "no irq for device\n");
820 return -ENOENT;
821 }
822
823 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
824 if (!fbinfo)
825 return -ENOMEM;
826
827 info = fbinfo->par;
828 info->dev = &pdev->dev;
829
830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
831 if (res == NULL) {
832 dev_err(&pdev->dev, "failed to get memory registers\n");
833 ret = -ENXIO;
834 goto dealloc_fb;
835 }
836
837 size = (res->end - res->start) + 1;
838 info->mem = request_mem_region(res->start, size, pdev->name);
839 if (info->mem == NULL) {
840 dev_err(&pdev->dev, "failed to get memory region\n");
841 ret = -ENOENT;
842 goto dealloc_fb;
843 }
844
845 info->io = ioremap(res->start, size);
846 if (info->io == NULL) {
847 dev_err(&pdev->dev, "ioremap() of registers failed\n");
848 ret = -ENXIO;
849 goto release_mem;
850 }
851
852 platform_set_drvdata(pdev, fbinfo);
853
854 dprintk("devinit\n");
855
856 strcpy(fbinfo->fix.id, driver_name);
857
858 memcpy(&info->regs, &display->regs, sizeof(info->regs));
859
860 /* Stop the video and unset ENVID if set */
861 info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
862 lcdcon1 = readl(info->io + S3C2410_LCDCON1);
863 writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
864
865 info->mach_info = pdev->dev.platform_data;
866 info->current_display = mach_info->default_display;
867
868 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
869 fbinfo->fix.type_aux = 0;
870 fbinfo->fix.xpanstep = 0;
871 fbinfo->fix.ypanstep = 0;
872 fbinfo->fix.ywrapstep = 0;
873 fbinfo->fix.accel = FB_ACCEL_NONE;
874
875 fbinfo->var.nonstd = 0;
876 fbinfo->var.activate = FB_ACTIVATE_NOW;
877 fbinfo->var.height = display->height;
878 fbinfo->var.width = display->width;
879 fbinfo->var.accel_flags = 0;
880 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
881
882 fbinfo->fbops = &s3c2410fb_ops;
883 fbinfo->flags = FBINFO_FLAG_DEFAULT;
884 fbinfo->pseudo_palette = &info->pseudo_pal;
885
886 fbinfo->var.xres = display->xres;
887 fbinfo->var.xres_virtual = display->xres;
888 fbinfo->var.yres = display->yres;
889 fbinfo->var.yres_virtual = display->yres;
890 fbinfo->var.bits_per_pixel = display->bpp;
891 fbinfo->var.left_margin = display->left_margin;
892 fbinfo->var.right_margin = display->right_margin;
893
894 fbinfo->var.upper_margin =
895 S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
896 fbinfo->var.lower_margin =
897 S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
898 fbinfo->var.vsync_len =
899 S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
900
901 fbinfo->var.hsync_len =
902 S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
903
904 fbinfo->var.red.offset = 11;
905 fbinfo->var.green.offset = 5;
906 fbinfo->var.blue.offset = 0;
907 fbinfo->var.transp.offset = 0;
908 fbinfo->var.red.length = 5;
909 fbinfo->var.green.length = 6;
910 fbinfo->var.blue.length = 5;
911 fbinfo->var.transp.length = 0;
912
913 /* find maximum required memory size for display */
914 for (i = 0; i < mach_info->num_displays; i++) {
915 unsigned long smem_len = mach_info->displays[i].xres;
916
917 smem_len *= mach_info->displays[i].yres;
918 smem_len *= mach_info->displays[i].bpp;
919 smem_len >>= 3;
920 if (fbinfo->fix.smem_len < smem_len)
921 fbinfo->fix.smem_len = smem_len;
922 }
923
924 for (i = 0; i < 256; i++)
925 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
926
927 ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
928 if (ret) {
929 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
930 ret = -EBUSY;
931 goto release_regs;
932 }
933
934 info->clk = clk_get(NULL, "lcd");
935 if (!info->clk || IS_ERR(info->clk)) {
936 printk(KERN_ERR "failed to get lcd clock source\n");
937 ret = -ENOENT;
938 goto release_irq;
939 }
940
941 clk_enable(info->clk);
942 dprintk("got and enabled clock\n");
943
944 msleep(1);
945
946 /* Initialize video memory */
947 ret = s3c2410fb_map_video_memory(fbinfo);
948 if (ret) {
949 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
950 ret = -ENOMEM;
951 goto release_clock;
952 }
953
954 dprintk("got video memory\n");
955
956 s3c2410fb_init_registers(fbinfo);
957
958 s3c2410fb_check_var(&fbinfo->var, fbinfo);
959
960 ret = register_framebuffer(fbinfo);
961 if (ret < 0) {
962 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
963 ret);
964 goto free_video_memory;
965 }
966
967 /* create device files */
968 device_create_file(&pdev->dev, &dev_attr_debug);
969
970 printk(KERN_INFO "fb%d: %s frame buffer device\n",
971 fbinfo->node, fbinfo->fix.id);
972
973 return 0;
974
975 free_video_memory:
976 s3c2410fb_unmap_video_memory(info);
977 release_clock:
978 clk_disable(info->clk);
979 clk_put(info->clk);
980 release_irq:
981 free_irq(irq, info);
982 release_regs:
983 iounmap(info->io);
984 release_mem:
985 release_resource(info->mem);
986 kfree(info->mem);
987 dealloc_fb:
988 framebuffer_release(fbinfo);
989 return ret;
990 }
991
992 /* s3c2410fb_stop_lcd
993 *
994 * shutdown the lcd controller
995 */
996 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
997 {
998 unsigned long flags;
999
1000 local_irq_save(flags);
1001
1002 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
1003 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
1004
1005 local_irq_restore(flags);
1006 }
1007
1008 /*
1009 * Cleanup
1010 */
1011 static int s3c2410fb_remove(struct platform_device *pdev)
1012 {
1013 struct fb_info *fbinfo = platform_get_drvdata(pdev);
1014 struct s3c2410fb_info *info = fbinfo->par;
1015 int irq;
1016
1017 s3c2410fb_stop_lcd(info);
1018 msleep(1);
1019
1020 s3c2410fb_unmap_video_memory(info);
1021
1022 if (info->clk) {
1023 clk_disable(info->clk);
1024 clk_put(info->clk);
1025 info->clk = NULL;
1026 }
1027
1028 irq = platform_get_irq(pdev, 0);
1029 free_irq(irq, info);
1030
1031 release_resource(info->mem);
1032 kfree(info->mem);
1033 iounmap(info->io);
1034 unregister_framebuffer(fbinfo);
1035
1036 return 0;
1037 }
1038
1039 #ifdef CONFIG_PM
1040
1041 /* suspend and resume support for the lcd controller */
1042 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1043 {
1044 struct fb_info *fbinfo = platform_get_drvdata(dev);
1045 struct s3c2410fb_info *info = fbinfo->par;
1046
1047 s3c2410fb_stop_lcd(info);
1048
1049 /* sleep before disabling the clock, we need to ensure
1050 * the LCD DMA engine is not going to get back on the bus
1051 * before the clock goes off again (bjd) */
1052
1053 msleep(1);
1054 clk_disable(info->clk);
1055
1056 return 0;
1057 }
1058
1059 static int s3c2410fb_resume(struct platform_device *dev)
1060 {
1061 struct fb_info *fbinfo = platform_get_drvdata(dev);
1062 struct s3c2410fb_info *info = fbinfo->par;
1063
1064 clk_enable(info->clk);
1065 msleep(1);
1066
1067 s3c2410fb_init_registers(info);
1068
1069 return 0;
1070 }
1071
1072 #else
1073 #define s3c2410fb_suspend NULL
1074 #define s3c2410fb_resume NULL
1075 #endif
1076
1077 static struct platform_driver s3c2410fb_driver = {
1078 .probe = s3c2410fb_probe,
1079 .remove = s3c2410fb_remove,
1080 .suspend = s3c2410fb_suspend,
1081 .resume = s3c2410fb_resume,
1082 .driver = {
1083 .name = "s3c2410-lcd",
1084 .owner = THIS_MODULE,
1085 },
1086 };
1087
1088 int __devinit s3c2410fb_init(void)
1089 {
1090 return platform_driver_register(&s3c2410fb_driver);
1091 }
1092
1093 static void __exit s3c2410fb_cleanup(void)
1094 {
1095 platform_driver_unregister(&s3c2410fb_driver);
1096 }
1097
1098 module_init(s3c2410fb_init);
1099 module_exit(s3c2410fb_cleanup);
1100
1101 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1102 "Ben Dooks <ben-linux@fluff.org>");
1103 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1104 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)