[ARM] pxafb: allow video memory size to be configurable
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pxafb.h
1 #ifndef __PXAFB_H__
2 #define __PXAFB_H__
3
4 /*
5 * linux/drivers/video/pxafb.h
6 * -- Intel PXA250/210 LCD Controller Frame Buffer Device
7 *
8 * Copyright (C) 1999 Eric A. Thomas.
9 * Copyright (C) 2004 Jean-Frederic Clere.
10 * Copyright (C) 2004 Ian Campbell.
11 * Copyright (C) 2004 Jeff Lackey.
12 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
13 * which in turn is
14 * Based on acornfb.c Copyright (C) Russell King.
15 *
16 * 2001-08-03: Cliff Brake <cbrake@acclent.com>
17 * - ported SA1100 code to PXA
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive
21 * for more details.
22 */
23
24 /* PXA LCD DMA descriptor */
25 struct pxafb_dma_descriptor {
26 unsigned int fdadr;
27 unsigned int fsadr;
28 unsigned int fidr;
29 unsigned int ldcmd;
30 };
31
32 enum {
33 PAL_NONE = -1,
34 PAL_BASE = 0,
35 PAL_OV1 = 1,
36 PAL_OV2 = 2,
37 PAL_MAX,
38 };
39
40 enum {
41 DMA_BASE = 0,
42 DMA_UPPER = 0,
43 DMA_LOWER = 1,
44 DMA_OV1 = 1,
45 DMA_OV2_Y = 2,
46 DMA_OV2_Cb = 3,
47 DMA_OV2_Cr = 4,
48 DMA_CURSOR = 5,
49 DMA_CMD = 6,
50 DMA_MAX,
51 };
52
53 /* maximum palette size - 256 entries, each 4 bytes long */
54 #define PALETTE_SIZE (256 * 4)
55 #define CMD_BUFF_SIZE (1024 * 50)
56
57 struct pxafb_dma_buff {
58 unsigned char palette[PAL_MAX * PALETTE_SIZE];
59 uint16_t cmd_buff[CMD_BUFF_SIZE];
60 struct pxafb_dma_descriptor pal_desc[PAL_MAX];
61 struct pxafb_dma_descriptor dma_desc[DMA_MAX];
62 };
63
64 struct pxafb_info {
65 struct fb_info fb;
66 struct device *dev;
67 struct clk *clk;
68
69 void __iomem *mmio_base;
70
71 struct pxafb_dma_buff *dma_buff;
72 size_t dma_buff_size;
73 dma_addr_t dma_buff_phys;
74 dma_addr_t fdadr[DMA_MAX];
75
76 void __iomem *video_mem; /* virtual address of frame buffer */
77 unsigned long video_mem_phys; /* physical address of frame buffer */
78 size_t video_mem_size; /* size of the frame buffer */
79 u16 * palette_cpu; /* virtual address of palette memory */
80 u_int palette_size;
81
82 u_int lccr0;
83 u_int lccr3;
84 u_int lccr4;
85 u_int cmap_inverse:1,
86 cmap_static:1,
87 unused:30;
88
89 u_int reg_lccr0;
90 u_int reg_lccr1;
91 u_int reg_lccr2;
92 u_int reg_lccr3;
93 u_int reg_lccr4;
94 u_int reg_cmdcr;
95
96 unsigned long hsync_time;
97
98 volatile u_char state;
99 volatile u_char task_state;
100 struct mutex ctrlr_lock;
101 wait_queue_head_t ctrlr_wait;
102 struct work_struct task;
103
104 struct completion disable_done;
105
106 #ifdef CONFIG_FB_PXA_SMARTPANEL
107 uint16_t *smart_cmds;
108 size_t n_smart_cmds;
109 struct completion command_done;
110 struct completion refresh_done;
111 struct task_struct *smart_thread;
112 #endif
113
114 #ifdef CONFIG_CPU_FREQ
115 struct notifier_block freq_transition;
116 struct notifier_block freq_policy;
117 #endif
118
119 void (*lcd_power)(int, struct fb_var_screeninfo *);
120 void (*backlight_power)(int);
121 };
122
123 #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
124
125 /*
126 * These are the actions for set_ctrlr_state
127 */
128 #define C_DISABLE (0)
129 #define C_ENABLE (1)
130 #define C_DISABLE_CLKCHANGE (2)
131 #define C_ENABLE_CLKCHANGE (3)
132 #define C_REENABLE (4)
133 #define C_DISABLE_PM (5)
134 #define C_ENABLE_PM (6)
135 #define C_STARTUP (7)
136
137 #define PXA_NAME "PXA"
138
139 /*
140 * Minimum X and Y resolutions
141 */
142 #define MIN_XRES 64
143 #define MIN_YRES 64
144
145 #endif /* __PXAFB_H__ */