[ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pxafb.h
1 #ifndef __PXAFB_H__
2 #define __PXAFB_H__
3
4 /*
5 * linux/drivers/video/pxafb.h
6 * -- Intel PXA250/210 LCD Controller Frame Buffer Device
7 *
8 * Copyright (C) 1999 Eric A. Thomas.
9 * Copyright (C) 2004 Jean-Frederic Clere.
10 * Copyright (C) 2004 Ian Campbell.
11 * Copyright (C) 2004 Jeff Lackey.
12 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
13 * which in turn is
14 * Based on acornfb.c Copyright (C) Russell King.
15 *
16 * 2001-08-03: Cliff Brake <cbrake@acclent.com>
17 * - ported SA1100 code to PXA
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive
21 * for more details.
22 */
23
24 /* PXA LCD DMA descriptor */
25 struct pxafb_dma_descriptor {
26 unsigned int fdadr;
27 unsigned int fsadr;
28 unsigned int fidr;
29 unsigned int ldcmd;
30 };
31
32 enum {
33 PAL_NONE = -1,
34 PAL_BASE = 0,
35 PAL_OV1 = 1,
36 PAL_OV2 = 2,
37 PAL_MAX,
38 };
39
40 enum {
41 DMA_BASE = 0,
42 DMA_UPPER = 0,
43 DMA_LOWER = 1,
44 DMA_OV1 = 1,
45 DMA_OV2_Y = 2,
46 DMA_OV2_Cb = 3,
47 DMA_OV2_Cr = 4,
48 DMA_CURSOR = 5,
49 DMA_CMD = 6,
50 DMA_MAX,
51 };
52
53 /* maximum palette size - 256 entries, each 4 bytes long */
54 #define PALETTE_SIZE (256 * 4)
55 #define CMD_BUFF_SIZE (1024 * 50)
56
57 /* NOTE: the palette and frame dma descriptors are doubled to allow
58 * the 2nd set for branch settings (FBRx)
59 */
60 struct pxafb_dma_buff {
61 unsigned char palette[PAL_MAX * PALETTE_SIZE];
62 uint16_t cmd_buff[CMD_BUFF_SIZE];
63 struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
64 struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
65 };
66
67 struct pxafb_info {
68 struct fb_info fb;
69 struct device *dev;
70 struct clk *clk;
71
72 void __iomem *mmio_base;
73
74 struct pxafb_dma_buff *dma_buff;
75 size_t dma_buff_size;
76 dma_addr_t dma_buff_phys;
77 dma_addr_t fdadr[DMA_MAX * 2];
78
79 void __iomem *video_mem; /* virtual address of frame buffer */
80 unsigned long video_mem_phys; /* physical address of frame buffer */
81 size_t video_mem_size; /* size of the frame buffer */
82 u16 * palette_cpu; /* virtual address of palette memory */
83 u_int palette_size;
84
85 u_int lccr0;
86 u_int lccr3;
87 u_int lccr4;
88 u_int cmap_inverse:1,
89 cmap_static:1,
90 unused:30;
91
92 u_int reg_lccr0;
93 u_int reg_lccr1;
94 u_int reg_lccr2;
95 u_int reg_lccr3;
96 u_int reg_lccr4;
97 u_int reg_cmdcr;
98
99 unsigned long hsync_time;
100
101 volatile u_char state;
102 volatile u_char task_state;
103 struct mutex ctrlr_lock;
104 wait_queue_head_t ctrlr_wait;
105 struct work_struct task;
106
107 struct completion disable_done;
108
109 #ifdef CONFIG_FB_PXA_SMARTPANEL
110 uint16_t *smart_cmds;
111 size_t n_smart_cmds;
112 struct completion command_done;
113 struct completion refresh_done;
114 struct task_struct *smart_thread;
115 #endif
116
117 #ifdef CONFIG_CPU_FREQ
118 struct notifier_block freq_transition;
119 struct notifier_block freq_policy;
120 #endif
121
122 void (*lcd_power)(int, struct fb_var_screeninfo *);
123 void (*backlight_power)(int);
124 };
125
126 #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
127
128 /*
129 * These are the actions for set_ctrlr_state
130 */
131 #define C_DISABLE (0)
132 #define C_ENABLE (1)
133 #define C_DISABLE_CLKCHANGE (2)
134 #define C_ENABLE_CLKCHANGE (3)
135 #define C_REENABLE (4)
136 #define C_DISABLE_PM (5)
137 #define C_ENABLE_PM (6)
138 #define C_STARTUP (7)
139
140 #define PXA_NAME "PXA"
141
142 /*
143 * Minimum X and Y resolutions
144 */
145 #define MIN_XRES 64
146 #define MIN_YRES 64
147
148 #endif /* __PXAFB_H__ */