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OMAPDSS: move omap_dispc_wait_for_irq_interruptible_timeout to dispc-compat.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/sizes.h>
40
41 #include <video/omapdss.h>
42
43 #include "dss.h"
44 #include "dss_features.h"
45 #include "dispc.h"
46
47 /* DISPC */
48 #define DISPC_SZ_REGS SZ_4K
49
50 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57 #define DISPC_MAX_NR_ISRS 8
58
59 struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63 };
64
65 enum omap_burst_size {
66 BURST_SIZE_X2 = 0,
67 BURST_SIZE_X4 = 1,
68 BURST_SIZE_X8 = 2,
69 };
70
71 #define REG_GET(idx, start, end) \
72 FLD_GET(dispc_read_reg(idx), start, end)
73
74 #define REG_FLD_MOD(idx, val, start, end) \
75 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
77 struct dispc_irq_stats {
78 unsigned long last_reset;
79 unsigned irq_count;
80 unsigned irqs[32];
81 };
82
83 struct dispc_features {
84 u8 sw_start;
85 u8 fp_start;
86 u8 bp_start;
87 u16 sw_max;
88 u16 vp_max;
89 u16 hp_max;
90 u8 mgr_width_start;
91 u8 mgr_height_start;
92 u16 mgr_width_max;
93 u16 mgr_height_max;
94 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
95 const struct omap_video_timings *mgr_timings,
96 u16 width, u16 height, u16 out_width, u16 out_height,
97 enum omap_color_mode color_mode, bool *five_taps,
98 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
99 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
100 unsigned long (*calc_core_clk) (unsigned long pclk,
101 u16 width, u16 height, u16 out_width, u16 out_height,
102 bool mem_to_mem);
103 u8 num_fifos;
104
105 /* swap GFX & WB fifos */
106 bool gfx_fifo_workaround:1;
107
108 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
109 bool no_framedone_tv:1;
110 };
111
112 #define DISPC_MAX_NR_FIFOS 5
113
114 static struct {
115 struct platform_device *pdev;
116 void __iomem *base;
117
118 int ctx_loss_cnt;
119
120 int irq;
121 struct clk *dss_clk;
122
123 u32 fifo_size[DISPC_MAX_NR_FIFOS];
124 /* maps which plane is using a fifo. fifo-id -> plane-id */
125 int fifo_assignment[DISPC_MAX_NR_FIFOS];
126
127 spinlock_t irq_lock;
128 u32 irq_error_mask;
129 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
130 u32 error_irqs;
131 struct work_struct error_work;
132
133 bool ctx_valid;
134 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
135
136 const struct dispc_features *feat;
137
138 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
139 spinlock_t irq_stats_lock;
140 struct dispc_irq_stats irq_stats;
141 #endif
142 } dispc;
143
144 enum omap_color_component {
145 /* used for all color formats for OMAP3 and earlier
146 * and for RGB and Y color component on OMAP4
147 */
148 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
149 /* used for UV component for
150 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
151 * color formats on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_UV = 1 << 1,
154 };
155
156 enum mgr_reg_fields {
157 DISPC_MGR_FLD_ENABLE,
158 DISPC_MGR_FLD_STNTFT,
159 DISPC_MGR_FLD_GO,
160 DISPC_MGR_FLD_TFTDATALINES,
161 DISPC_MGR_FLD_STALLMODE,
162 DISPC_MGR_FLD_TCKENABLE,
163 DISPC_MGR_FLD_TCKSELECTION,
164 DISPC_MGR_FLD_CPR,
165 DISPC_MGR_FLD_FIFOHANDCHECK,
166 /* used to maintain a count of the above fields */
167 DISPC_MGR_FLD_NUM,
168 };
169
170 static const struct {
171 const char *name;
172 u32 vsync_irq;
173 u32 framedone_irq;
174 u32 sync_lost_irq;
175 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
176 } mgr_desc[] = {
177 [OMAP_DSS_CHANNEL_LCD] = {
178 .name = "LCD",
179 .vsync_irq = DISPC_IRQ_VSYNC,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_DIGIT] = {
195 .name = "DIGIT",
196 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
197 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
201 [DISPC_MGR_FLD_STNTFT] = { },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { },
204 [DISPC_MGR_FLD_STALLMODE] = { },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
207 [DISPC_MGR_FLD_CPR] = { },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
209 },
210 },
211 [OMAP_DSS_CHANNEL_LCD2] = {
212 .name = "LCD2",
213 .vsync_irq = DISPC_IRQ_VSYNC2,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
226 },
227 },
228 [OMAP_DSS_CHANNEL_LCD3] = {
229 .name = "LCD3",
230 .vsync_irq = DISPC_IRQ_VSYNC3,
231 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
232 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
233 .reg_desc = {
234 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
235 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
236 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
237 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
238 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
239 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
240 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
241 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
242 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
243 },
244 },
245 };
246
247 struct color_conv_coef {
248 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249 int full_range;
250 };
251
252 static void _omap_dispc_set_irqs(void);
253 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
254 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
255
256 static inline void dispc_write_reg(const u16 idx, u32 val)
257 {
258 __raw_writel(val, dispc.base + idx);
259 }
260
261 static inline u32 dispc_read_reg(const u16 idx)
262 {
263 return __raw_readl(dispc.base + idx);
264 }
265
266 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
267 {
268 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269 return REG_GET(rfld.reg, rfld.high, rfld.low);
270 }
271
272 static void mgr_fld_write(enum omap_channel channel,
273 enum mgr_reg_fields regfld, int val) {
274 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
276 }
277
278 #define SR(reg) \
279 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
280 #define RR(reg) \
281 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
282
283 static void dispc_save_context(void)
284 {
285 int i, j;
286
287 DSSDBG("dispc_save_context\n");
288
289 SR(IRQENABLE);
290 SR(CONTROL);
291 SR(CONFIG);
292 SR(LINE_NUMBER);
293 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
294 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
295 SR(GLOBAL_ALPHA);
296 if (dss_has_feature(FEAT_MGR_LCD2)) {
297 SR(CONTROL2);
298 SR(CONFIG2);
299 }
300 if (dss_has_feature(FEAT_MGR_LCD3)) {
301 SR(CONTROL3);
302 SR(CONFIG3);
303 }
304
305 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
306 SR(DEFAULT_COLOR(i));
307 SR(TRANS_COLOR(i));
308 SR(SIZE_MGR(i));
309 if (i == OMAP_DSS_CHANNEL_DIGIT)
310 continue;
311 SR(TIMING_H(i));
312 SR(TIMING_V(i));
313 SR(POL_FREQ(i));
314 SR(DIVISORo(i));
315
316 SR(DATA_CYCLE1(i));
317 SR(DATA_CYCLE2(i));
318 SR(DATA_CYCLE3(i));
319
320 if (dss_has_feature(FEAT_CPR)) {
321 SR(CPR_COEF_R(i));
322 SR(CPR_COEF_G(i));
323 SR(CPR_COEF_B(i));
324 }
325 }
326
327 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
328 SR(OVL_BA0(i));
329 SR(OVL_BA1(i));
330 SR(OVL_POSITION(i));
331 SR(OVL_SIZE(i));
332 SR(OVL_ATTRIBUTES(i));
333 SR(OVL_FIFO_THRESHOLD(i));
334 SR(OVL_ROW_INC(i));
335 SR(OVL_PIXEL_INC(i));
336 if (dss_has_feature(FEAT_PRELOAD))
337 SR(OVL_PRELOAD(i));
338 if (i == OMAP_DSS_GFX) {
339 SR(OVL_WINDOW_SKIP(i));
340 SR(OVL_TABLE_BA(i));
341 continue;
342 }
343 SR(OVL_FIR(i));
344 SR(OVL_PICTURE_SIZE(i));
345 SR(OVL_ACCU0(i));
346 SR(OVL_ACCU1(i));
347
348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_H(i, j));
350
351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_HV(i, j));
353
354 for (j = 0; j < 5; j++)
355 SR(OVL_CONV_COEF(i, j));
356
357 if (dss_has_feature(FEAT_FIR_COEF_V)) {
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_V(i, j));
360 }
361
362 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363 SR(OVL_BA0_UV(i));
364 SR(OVL_BA1_UV(i));
365 SR(OVL_FIR2(i));
366 SR(OVL_ACCU2_0(i));
367 SR(OVL_ACCU2_1(i));
368
369 for (j = 0; j < 8; j++)
370 SR(OVL_FIR_COEF_H2(i, j));
371
372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_HV2(i, j));
374
375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_V2(i, j));
377 }
378 if (dss_has_feature(FEAT_ATTR2))
379 SR(OVL_ATTRIBUTES2(i));
380 }
381
382 if (dss_has_feature(FEAT_CORE_CLK_DIV))
383 SR(DIVISOR);
384
385 dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
386 dispc.ctx_valid = true;
387
388 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
389 }
390
391 static void dispc_restore_context(void)
392 {
393 int i, j, ctx;
394
395 DSSDBG("dispc_restore_context\n");
396
397 if (!dispc.ctx_valid)
398 return;
399
400 ctx = dss_get_ctx_loss_count();
401
402 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
403 return;
404
405 DSSDBG("ctx_loss_count: saved %d, current %d\n",
406 dispc.ctx_loss_cnt, ctx);
407
408 /*RR(IRQENABLE);*/
409 /*RR(CONTROL);*/
410 RR(CONFIG);
411 RR(LINE_NUMBER);
412 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
413 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
414 RR(GLOBAL_ALPHA);
415 if (dss_has_feature(FEAT_MGR_LCD2))
416 RR(CONFIG2);
417 if (dss_has_feature(FEAT_MGR_LCD3))
418 RR(CONFIG3);
419
420 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
421 RR(DEFAULT_COLOR(i));
422 RR(TRANS_COLOR(i));
423 RR(SIZE_MGR(i));
424 if (i == OMAP_DSS_CHANNEL_DIGIT)
425 continue;
426 RR(TIMING_H(i));
427 RR(TIMING_V(i));
428 RR(POL_FREQ(i));
429 RR(DIVISORo(i));
430
431 RR(DATA_CYCLE1(i));
432 RR(DATA_CYCLE2(i));
433 RR(DATA_CYCLE3(i));
434
435 if (dss_has_feature(FEAT_CPR)) {
436 RR(CPR_COEF_R(i));
437 RR(CPR_COEF_G(i));
438 RR(CPR_COEF_B(i));
439 }
440 }
441
442 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
443 RR(OVL_BA0(i));
444 RR(OVL_BA1(i));
445 RR(OVL_POSITION(i));
446 RR(OVL_SIZE(i));
447 RR(OVL_ATTRIBUTES(i));
448 RR(OVL_FIFO_THRESHOLD(i));
449 RR(OVL_ROW_INC(i));
450 RR(OVL_PIXEL_INC(i));
451 if (dss_has_feature(FEAT_PRELOAD))
452 RR(OVL_PRELOAD(i));
453 if (i == OMAP_DSS_GFX) {
454 RR(OVL_WINDOW_SKIP(i));
455 RR(OVL_TABLE_BA(i));
456 continue;
457 }
458 RR(OVL_FIR(i));
459 RR(OVL_PICTURE_SIZE(i));
460 RR(OVL_ACCU0(i));
461 RR(OVL_ACCU1(i));
462
463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_H(i, j));
465
466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_HV(i, j));
468
469 for (j = 0; j < 5; j++)
470 RR(OVL_CONV_COEF(i, j));
471
472 if (dss_has_feature(FEAT_FIR_COEF_V)) {
473 for (j = 0; j < 8; j++)
474 RR(OVL_FIR_COEF_V(i, j));
475 }
476
477 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478 RR(OVL_BA0_UV(i));
479 RR(OVL_BA1_UV(i));
480 RR(OVL_FIR2(i));
481 RR(OVL_ACCU2_0(i));
482 RR(OVL_ACCU2_1(i));
483
484 for (j = 0; j < 8; j++)
485 RR(OVL_FIR_COEF_H2(i, j));
486
487 for (j = 0; j < 8; j++)
488 RR(OVL_FIR_COEF_HV2(i, j));
489
490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_V2(i, j));
492 }
493 if (dss_has_feature(FEAT_ATTR2))
494 RR(OVL_ATTRIBUTES2(i));
495 }
496
497 if (dss_has_feature(FEAT_CORE_CLK_DIV))
498 RR(DIVISOR);
499
500 /* enable last, because LCD & DIGIT enable are here */
501 RR(CONTROL);
502 if (dss_has_feature(FEAT_MGR_LCD2))
503 RR(CONTROL2);
504 if (dss_has_feature(FEAT_MGR_LCD3))
505 RR(CONTROL3);
506 /* clear spurious SYNC_LOST_DIGIT interrupts */
507 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
508
509 /*
510 * enable last so IRQs won't trigger before
511 * the context is fully restored
512 */
513 RR(IRQENABLE);
514
515 DSSDBG("context restored\n");
516 }
517
518 #undef SR
519 #undef RR
520
521 int dispc_runtime_get(void)
522 {
523 int r;
524
525 DSSDBG("dispc_runtime_get\n");
526
527 r = pm_runtime_get_sync(&dispc.pdev->dev);
528 WARN_ON(r < 0);
529 return r < 0 ? r : 0;
530 }
531
532 void dispc_runtime_put(void)
533 {
534 int r;
535
536 DSSDBG("dispc_runtime_put\n");
537
538 r = pm_runtime_put_sync(&dispc.pdev->dev);
539 WARN_ON(r < 0 && r != -ENOSYS);
540 }
541
542 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543 {
544 return mgr_desc[channel].vsync_irq;
545 }
546
547 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
548 {
549 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
550 return 0;
551
552 return mgr_desc[channel].framedone_irq;
553 }
554
555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556 {
557 return mgr_desc[channel].sync_lost_irq;
558 }
559
560 u32 dispc_wb_get_framedone_irq(void)
561 {
562 return DISPC_IRQ_FRAMEDONEWB;
563 }
564
565 bool dispc_mgr_go_busy(enum omap_channel channel)
566 {
567 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
568 }
569
570 void dispc_mgr_go(enum omap_channel channel)
571 {
572 WARN_ON(dispc_mgr_is_enabled(channel) == false);
573 WARN_ON(dispc_mgr_go_busy(channel));
574
575 DSSDBG("GO %s\n", mgr_desc[channel].name);
576
577 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
578 }
579
580 bool dispc_wb_go_busy(void)
581 {
582 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583 }
584
585 void dispc_wb_go(void)
586 {
587 enum omap_plane plane = OMAP_DSS_WB;
588 bool enable, go;
589
590 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
591
592 if (!enable)
593 return;
594
595 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596 if (go) {
597 DSSERR("GO bit not down for WB\n");
598 return;
599 }
600
601 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
602 }
603
604 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
605 {
606 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
607 }
608
609 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
610 {
611 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
612 }
613
614 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
615 {
616 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
617 }
618
619 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
620 {
621 BUG_ON(plane == OMAP_DSS_GFX);
622
623 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
624 }
625
626 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
627 u32 value)
628 {
629 BUG_ON(plane == OMAP_DSS_GFX);
630
631 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
632 }
633
634 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
635 {
636 BUG_ON(plane == OMAP_DSS_GFX);
637
638 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
639 }
640
641 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
642 int fir_vinc, int five_taps,
643 enum omap_color_component color_comp)
644 {
645 const struct dispc_coef *h_coef, *v_coef;
646 int i;
647
648 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
649 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
650
651 for (i = 0; i < 8; i++) {
652 u32 h, hv;
653
654 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
655 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
656 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
657 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
658 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
659 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
660 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
661 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
662
663 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
664 dispc_ovl_write_firh_reg(plane, i, h);
665 dispc_ovl_write_firhv_reg(plane, i, hv);
666 } else {
667 dispc_ovl_write_firh2_reg(plane, i, h);
668 dispc_ovl_write_firhv2_reg(plane, i, hv);
669 }
670
671 }
672
673 if (five_taps) {
674 for (i = 0; i < 8; i++) {
675 u32 v;
676 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
677 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
678 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
679 dispc_ovl_write_firv_reg(plane, i, v);
680 else
681 dispc_ovl_write_firv2_reg(plane, i, v);
682 }
683 }
684 }
685
686
687 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
688 const struct color_conv_coef *ct)
689 {
690 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
691
692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
696 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
697
698 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
699
700 #undef CVAL
701 }
702
703 static void dispc_setup_color_conv_coef(void)
704 {
705 int i;
706 int num_ovl = dss_feat_get_num_ovls();
707 int num_wb = dss_feat_get_num_wbs();
708 const struct color_conv_coef ctbl_bt601_5_ovl = {
709 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
710 };
711 const struct color_conv_coef ctbl_bt601_5_wb = {
712 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
713 };
714
715 for (i = 1; i < num_ovl; i++)
716 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
717
718 for (; i < num_wb; i++)
719 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
720 }
721
722 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
723 {
724 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
725 }
726
727 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
728 {
729 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
730 }
731
732 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
733 {
734 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
735 }
736
737 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
738 {
739 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
740 }
741
742 static void dispc_ovl_set_pos(enum omap_plane plane,
743 enum omap_overlay_caps caps, int x, int y)
744 {
745 u32 val;
746
747 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
748 return;
749
750 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
751
752 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
753 }
754
755 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
756 int height)
757 {
758 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
759
760 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
761 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
762 else
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
764 }
765
766 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
767 int height)
768 {
769 u32 val;
770
771 BUG_ON(plane == OMAP_DSS_GFX);
772
773 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
774
775 if (plane == OMAP_DSS_WB)
776 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
777 else
778 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
779 }
780
781 static void dispc_ovl_set_zorder(enum omap_plane plane,
782 enum omap_overlay_caps caps, u8 zorder)
783 {
784 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
785 return;
786
787 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
788 }
789
790 static void dispc_ovl_enable_zorder_planes(void)
791 {
792 int i;
793
794 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
795 return;
796
797 for (i = 0; i < dss_feat_get_num_ovls(); i++)
798 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
799 }
800
801 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
802 enum omap_overlay_caps caps, bool enable)
803 {
804 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
805 return;
806
807 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
808 }
809
810 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
811 enum omap_overlay_caps caps, u8 global_alpha)
812 {
813 static const unsigned shifts[] = { 0, 8, 16, 24, };
814 int shift;
815
816 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
817 return;
818
819 shift = shifts[plane];
820 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
821 }
822
823 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
824 {
825 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
826 }
827
828 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
829 {
830 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
831 }
832
833 static void dispc_ovl_set_color_mode(enum omap_plane plane,
834 enum omap_color_mode color_mode)
835 {
836 u32 m = 0;
837 if (plane != OMAP_DSS_GFX) {
838 switch (color_mode) {
839 case OMAP_DSS_COLOR_NV12:
840 m = 0x0; break;
841 case OMAP_DSS_COLOR_RGBX16:
842 m = 0x1; break;
843 case OMAP_DSS_COLOR_RGBA16:
844 m = 0x2; break;
845 case OMAP_DSS_COLOR_RGB12U:
846 m = 0x4; break;
847 case OMAP_DSS_COLOR_ARGB16:
848 m = 0x5; break;
849 case OMAP_DSS_COLOR_RGB16:
850 m = 0x6; break;
851 case OMAP_DSS_COLOR_ARGB16_1555:
852 m = 0x7; break;
853 case OMAP_DSS_COLOR_RGB24U:
854 m = 0x8; break;
855 case OMAP_DSS_COLOR_RGB24P:
856 m = 0x9; break;
857 case OMAP_DSS_COLOR_YUV2:
858 m = 0xa; break;
859 case OMAP_DSS_COLOR_UYVY:
860 m = 0xb; break;
861 case OMAP_DSS_COLOR_ARGB32:
862 m = 0xc; break;
863 case OMAP_DSS_COLOR_RGBA32:
864 m = 0xd; break;
865 case OMAP_DSS_COLOR_RGBX32:
866 m = 0xe; break;
867 case OMAP_DSS_COLOR_XRGB16_1555:
868 m = 0xf; break;
869 default:
870 BUG(); return;
871 }
872 } else {
873 switch (color_mode) {
874 case OMAP_DSS_COLOR_CLUT1:
875 m = 0x0; break;
876 case OMAP_DSS_COLOR_CLUT2:
877 m = 0x1; break;
878 case OMAP_DSS_COLOR_CLUT4:
879 m = 0x2; break;
880 case OMAP_DSS_COLOR_CLUT8:
881 m = 0x3; break;
882 case OMAP_DSS_COLOR_RGB12U:
883 m = 0x4; break;
884 case OMAP_DSS_COLOR_ARGB16:
885 m = 0x5; break;
886 case OMAP_DSS_COLOR_RGB16:
887 m = 0x6; break;
888 case OMAP_DSS_COLOR_ARGB16_1555:
889 m = 0x7; break;
890 case OMAP_DSS_COLOR_RGB24U:
891 m = 0x8; break;
892 case OMAP_DSS_COLOR_RGB24P:
893 m = 0x9; break;
894 case OMAP_DSS_COLOR_RGBX16:
895 m = 0xa; break;
896 case OMAP_DSS_COLOR_RGBA16:
897 m = 0xb; break;
898 case OMAP_DSS_COLOR_ARGB32:
899 m = 0xc; break;
900 case OMAP_DSS_COLOR_RGBA32:
901 m = 0xd; break;
902 case OMAP_DSS_COLOR_RGBX32:
903 m = 0xe; break;
904 case OMAP_DSS_COLOR_XRGB16_1555:
905 m = 0xf; break;
906 default:
907 BUG(); return;
908 }
909 }
910
911 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
912 }
913
914 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
915 enum omap_dss_rotation_type rotation_type)
916 {
917 if (dss_has_feature(FEAT_BURST_2D) == 0)
918 return;
919
920 if (rotation_type == OMAP_DSS_ROT_TILER)
921 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
922 else
923 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
924 }
925
926 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
927 {
928 int shift;
929 u32 val;
930 int chan = 0, chan2 = 0;
931
932 switch (plane) {
933 case OMAP_DSS_GFX:
934 shift = 8;
935 break;
936 case OMAP_DSS_VIDEO1:
937 case OMAP_DSS_VIDEO2:
938 case OMAP_DSS_VIDEO3:
939 shift = 16;
940 break;
941 default:
942 BUG();
943 return;
944 }
945
946 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
947 if (dss_has_feature(FEAT_MGR_LCD2)) {
948 switch (channel) {
949 case OMAP_DSS_CHANNEL_LCD:
950 chan = 0;
951 chan2 = 0;
952 break;
953 case OMAP_DSS_CHANNEL_DIGIT:
954 chan = 1;
955 chan2 = 0;
956 break;
957 case OMAP_DSS_CHANNEL_LCD2:
958 chan = 0;
959 chan2 = 1;
960 break;
961 case OMAP_DSS_CHANNEL_LCD3:
962 if (dss_has_feature(FEAT_MGR_LCD3)) {
963 chan = 0;
964 chan2 = 2;
965 } else {
966 BUG();
967 return;
968 }
969 break;
970 default:
971 BUG();
972 return;
973 }
974
975 val = FLD_MOD(val, chan, shift, shift);
976 val = FLD_MOD(val, chan2, 31, 30);
977 } else {
978 val = FLD_MOD(val, channel, shift, shift);
979 }
980 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
981 }
982
983 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984 {
985 int shift;
986 u32 val;
987 enum omap_channel channel;
988
989 switch (plane) {
990 case OMAP_DSS_GFX:
991 shift = 8;
992 break;
993 case OMAP_DSS_VIDEO1:
994 case OMAP_DSS_VIDEO2:
995 case OMAP_DSS_VIDEO3:
996 shift = 16;
997 break;
998 default:
999 BUG();
1000 return 0;
1001 }
1002
1003 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
1005 if (dss_has_feature(FEAT_MGR_LCD3)) {
1006 if (FLD_GET(val, 31, 30) == 0)
1007 channel = FLD_GET(val, shift, shift);
1008 else if (FLD_GET(val, 31, 30) == 1)
1009 channel = OMAP_DSS_CHANNEL_LCD2;
1010 else
1011 channel = OMAP_DSS_CHANNEL_LCD3;
1012 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 } else {
1018 channel = FLD_GET(val, shift, shift);
1019 }
1020
1021 return channel;
1022 }
1023
1024 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025 {
1026 enum omap_plane plane = OMAP_DSS_WB;
1027
1028 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029 }
1030
1031 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1032 enum omap_burst_size burst_size)
1033 {
1034 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1035 int shift;
1036
1037 shift = shifts[plane];
1038 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1039 }
1040
1041 static void dispc_configure_burst_sizes(void)
1042 {
1043 int i;
1044 const int burst_size = BURST_SIZE_X8;
1045
1046 /* Configure burst size always to maximum size */
1047 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1048 dispc_ovl_set_burst_size(i, burst_size);
1049 }
1050
1051 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1052 {
1053 unsigned unit = dss_feat_get_burst_size_unit();
1054 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055 return unit * 8;
1056 }
1057
1058 void dispc_enable_gamma_table(bool enable)
1059 {
1060 /*
1061 * This is partially implemented to support only disabling of
1062 * the gamma table.
1063 */
1064 if (enable) {
1065 DSSWARN("Gamma table enabling for TV not yet supported");
1066 return;
1067 }
1068
1069 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070 }
1071
1072 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1073 {
1074 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1075 return;
1076
1077 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1078 }
1079
1080 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1081 const struct omap_dss_cpr_coefs *coefs)
1082 {
1083 u32 coef_r, coef_g, coef_b;
1084
1085 if (!dss_mgr_is_lcd(channel))
1086 return;
1087
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089 FLD_VAL(coefs->rb, 9, 0);
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091 FLD_VAL(coefs->gb, 9, 0);
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093 FLD_VAL(coefs->bb, 9, 0);
1094
1095 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098 }
1099
1100 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1101 {
1102 u32 val;
1103
1104 BUG_ON(plane == OMAP_DSS_GFX);
1105
1106 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1107 val = FLD_MOD(val, enable, 9, 9);
1108 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1109 }
1110
1111 static void dispc_ovl_enable_replication(enum omap_plane plane,
1112 enum omap_overlay_caps caps, bool enable)
1113 {
1114 static const unsigned shifts[] = { 5, 10, 10, 10 };
1115 int shift;
1116
1117 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 return;
1119
1120 shift = shifts[plane];
1121 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1122 }
1123
1124 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1125 u16 height)
1126 {
1127 u32 val;
1128
1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1133 }
1134
1135 static void dispc_init_fifos(void)
1136 {
1137 u32 size;
1138 int fifo;
1139 u8 start, end;
1140 u32 unit;
1141
1142 unit = dss_feat_get_buffer_size_unit();
1143
1144 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1145
1146 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1147 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1148 size *= unit;
1149 dispc.fifo_size[fifo] = size;
1150
1151 /*
1152 * By default fifos are mapped directly to overlays, fifo 0 to
1153 * ovl 0, fifo 1 to ovl 1, etc.
1154 */
1155 dispc.fifo_assignment[fifo] = fifo;
1156 }
1157
1158 /*
1159 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1160 * causes problems with certain use cases, like using the tiler in 2D
1161 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1162 * giving GFX plane a larger fifo. WB but should work fine with a
1163 * smaller fifo.
1164 */
1165 if (dispc.feat->gfx_fifo_workaround) {
1166 u32 v;
1167
1168 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1169
1170 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1171 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1172 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1173 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1174
1175 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1176
1177 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1178 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1179 }
1180 }
1181
1182 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1183 {
1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
1193 }
1194
1195 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1196 {
1197 u8 hi_start, hi_end, lo_start, lo_end;
1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
1207
1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1212 plane,
1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1214 lo_start, lo_end) * unit,
1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
1218
1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
1222 }
1223
1224 void dispc_enable_fifomerge(bool enable)
1225 {
1226 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227 WARN_ON(enable);
1228 return;
1229 }
1230
1231 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1232 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1233 }
1234
1235 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1236 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1237 bool manual_update)
1238 {
1239 /*
1240 * All sizes are in bytes. Both the buffer and burst are made of
1241 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242 */
1243
1244 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1245 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1246 int i;
1247
1248 burst_size = dispc_ovl_get_burst_size(plane);
1249 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1250
1251 if (use_fifomerge) {
1252 total_fifo_size = 0;
1253 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1254 total_fifo_size += dispc_ovl_get_fifo_size(i);
1255 } else {
1256 total_fifo_size = ovl_fifo_size;
1257 }
1258
1259 /*
1260 * We use the same low threshold for both fifomerge and non-fifomerge
1261 * cases, but for fifomerge we calculate the high threshold using the
1262 * combined fifo size
1263 */
1264
1265 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1266 *fifo_low = ovl_fifo_size - burst_size * 2;
1267 *fifo_high = total_fifo_size - burst_size;
1268 } else if (plane == OMAP_DSS_WB) {
1269 /*
1270 * Most optimal configuration for writeback is to push out data
1271 * to the interconnect the moment writeback pushes enough pixels
1272 * in the FIFO to form a burst
1273 */
1274 *fifo_low = 0;
1275 *fifo_high = burst_size;
1276 } else {
1277 *fifo_low = ovl_fifo_size - burst_size;
1278 *fifo_high = total_fifo_size - buf_unit;
1279 }
1280 }
1281
1282 static void dispc_ovl_set_fir(enum omap_plane plane,
1283 int hinc, int vinc,
1284 enum omap_color_component color_comp)
1285 {
1286 u32 val;
1287
1288 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1289 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1290
1291 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1292 &hinc_start, &hinc_end);
1293 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1294 &vinc_start, &vinc_end);
1295 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1296 FLD_VAL(hinc, hinc_start, hinc_end);
1297
1298 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1299 } else {
1300 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1301 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1302 }
1303 }
1304
1305 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1306 {
1307 u32 val;
1308 u8 hor_start, hor_end, vert_start, vert_end;
1309
1310 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1311 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1312
1313 val = FLD_VAL(vaccu, vert_start, vert_end) |
1314 FLD_VAL(haccu, hor_start, hor_end);
1315
1316 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1317 }
1318
1319 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1320 {
1321 u32 val;
1322 u8 hor_start, hor_end, vert_start, vert_end;
1323
1324 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1325 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1326
1327 val = FLD_VAL(vaccu, vert_start, vert_end) |
1328 FLD_VAL(haccu, hor_start, hor_end);
1329
1330 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1331 }
1332
1333 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334 int vaccu)
1335 {
1336 u32 val;
1337
1338 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1339 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1340 }
1341
1342 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343 int vaccu)
1344 {
1345 u32 val;
1346
1347 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1348 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1349 }
1350
1351 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1352 u16 orig_width, u16 orig_height,
1353 u16 out_width, u16 out_height,
1354 bool five_taps, u8 rotation,
1355 enum omap_color_component color_comp)
1356 {
1357 int fir_hinc, fir_vinc;
1358
1359 fir_hinc = 1024 * orig_width / out_width;
1360 fir_vinc = 1024 * orig_height / out_height;
1361
1362 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1363 color_comp);
1364 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1365 }
1366
1367 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1368 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1369 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1370 {
1371 int h_accu2_0, h_accu2_1;
1372 int v_accu2_0, v_accu2_1;
1373 int chroma_hinc, chroma_vinc;
1374 int idx;
1375
1376 struct accu {
1377 s8 h0_m, h0_n;
1378 s8 h1_m, h1_n;
1379 s8 v0_m, v0_n;
1380 s8 v1_m, v1_n;
1381 };
1382
1383 const struct accu *accu_table;
1384 const struct accu *accu_val;
1385
1386 static const struct accu accu_nv12[4] = {
1387 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1388 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1389 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1390 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1391 };
1392
1393 static const struct accu accu_nv12_ilace[4] = {
1394 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1395 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1396 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1397 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1398 };
1399
1400 static const struct accu accu_yuv[4] = {
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { 0, 1, 0, 1, 0, 1, 0, 1 },
1403 { -1, 1, 0, 1, 0, 1, 0, 1 },
1404 { 0, 1, 0, 1, -1, 1, 0, 1 },
1405 };
1406
1407 switch (rotation) {
1408 case OMAP_DSS_ROT_0:
1409 idx = 0;
1410 break;
1411 case OMAP_DSS_ROT_90:
1412 idx = 1;
1413 break;
1414 case OMAP_DSS_ROT_180:
1415 idx = 2;
1416 break;
1417 case OMAP_DSS_ROT_270:
1418 idx = 3;
1419 break;
1420 default:
1421 BUG();
1422 return;
1423 }
1424
1425 switch (color_mode) {
1426 case OMAP_DSS_COLOR_NV12:
1427 if (ilace)
1428 accu_table = accu_nv12_ilace;
1429 else
1430 accu_table = accu_nv12;
1431 break;
1432 case OMAP_DSS_COLOR_YUV2:
1433 case OMAP_DSS_COLOR_UYVY:
1434 accu_table = accu_yuv;
1435 break;
1436 default:
1437 BUG();
1438 return;
1439 }
1440
1441 accu_val = &accu_table[idx];
1442
1443 chroma_hinc = 1024 * orig_width / out_width;
1444 chroma_vinc = 1024 * orig_height / out_height;
1445
1446 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1447 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1448 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1449 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1450
1451 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1452 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1453 }
1454
1455 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1456 u16 orig_width, u16 orig_height,
1457 u16 out_width, u16 out_height,
1458 bool ilace, bool five_taps,
1459 bool fieldmode, enum omap_color_mode color_mode,
1460 u8 rotation)
1461 {
1462 int accu0 = 0;
1463 int accu1 = 0;
1464 u32 l;
1465
1466 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1467 out_width, out_height, five_taps,
1468 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1469 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1470
1471 /* RESIZEENABLE and VERTICALTAPS */
1472 l &= ~((0x3 << 5) | (0x1 << 21));
1473 l |= (orig_width != out_width) ? (1 << 5) : 0;
1474 l |= (orig_height != out_height) ? (1 << 6) : 0;
1475 l |= five_taps ? (1 << 21) : 0;
1476
1477 /* VRESIZECONF and HRESIZECONF */
1478 if (dss_has_feature(FEAT_RESIZECONF)) {
1479 l &= ~(0x3 << 7);
1480 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1481 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1482 }
1483
1484 /* LINEBUFFERSPLIT */
1485 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1486 l &= ~(0x1 << 22);
1487 l |= five_taps ? (1 << 22) : 0;
1488 }
1489
1490 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1491
1492 /*
1493 * field 0 = even field = bottom field
1494 * field 1 = odd field = top field
1495 */
1496 if (ilace && !fieldmode) {
1497 accu1 = 0;
1498 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1499 if (accu0 >= 1024/2) {
1500 accu1 = 1024/2;
1501 accu0 -= accu1;
1502 }
1503 }
1504
1505 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1506 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1507 }
1508
1509 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1510 u16 orig_width, u16 orig_height,
1511 u16 out_width, u16 out_height,
1512 bool ilace, bool five_taps,
1513 bool fieldmode, enum omap_color_mode color_mode,
1514 u8 rotation)
1515 {
1516 int scale_x = out_width != orig_width;
1517 int scale_y = out_height != orig_height;
1518 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1519
1520 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1521 return;
1522 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1523 color_mode != OMAP_DSS_COLOR_UYVY &&
1524 color_mode != OMAP_DSS_COLOR_NV12)) {
1525 /* reset chroma resampling for RGB formats */
1526 if (plane != OMAP_DSS_WB)
1527 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1528 return;
1529 }
1530
1531 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1532 out_height, ilace, color_mode, rotation);
1533
1534 switch (color_mode) {
1535 case OMAP_DSS_COLOR_NV12:
1536 if (chroma_upscale) {
1537 /* UV is subsampled by 2 horizontally and vertically */
1538 orig_height >>= 1;
1539 orig_width >>= 1;
1540 } else {
1541 /* UV is downsampled by 2 horizontally and vertically */
1542 orig_height <<= 1;
1543 orig_width <<= 1;
1544 }
1545
1546 break;
1547 case OMAP_DSS_COLOR_YUV2:
1548 case OMAP_DSS_COLOR_UYVY:
1549 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1550 if (rotation == OMAP_DSS_ROT_0 ||
1551 rotation == OMAP_DSS_ROT_180) {
1552 if (chroma_upscale)
1553 /* UV is subsampled by 2 horizontally */
1554 orig_width >>= 1;
1555 else
1556 /* UV is downsampled by 2 horizontally */
1557 orig_width <<= 1;
1558 }
1559
1560 /* must use FIR for YUV422 if rotated */
1561 if (rotation != OMAP_DSS_ROT_0)
1562 scale_x = scale_y = true;
1563
1564 break;
1565 default:
1566 BUG();
1567 return;
1568 }
1569
1570 if (out_width != orig_width)
1571 scale_x = true;
1572 if (out_height != orig_height)
1573 scale_y = true;
1574
1575 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1576 out_width, out_height, five_taps,
1577 rotation, DISPC_COLOR_COMPONENT_UV);
1578
1579 if (plane != OMAP_DSS_WB)
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1581 (scale_x || scale_y) ? 1 : 0, 8, 8);
1582
1583 /* set H scaling */
1584 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1585 /* set V scaling */
1586 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1587 }
1588
1589 static void dispc_ovl_set_scaling(enum omap_plane plane,
1590 u16 orig_width, u16 orig_height,
1591 u16 out_width, u16 out_height,
1592 bool ilace, bool five_taps,
1593 bool fieldmode, enum omap_color_mode color_mode,
1594 u8 rotation)
1595 {
1596 BUG_ON(plane == OMAP_DSS_GFX);
1597
1598 dispc_ovl_set_scaling_common(plane,
1599 orig_width, orig_height,
1600 out_width, out_height,
1601 ilace, five_taps,
1602 fieldmode, color_mode,
1603 rotation);
1604
1605 dispc_ovl_set_scaling_uv(plane,
1606 orig_width, orig_height,
1607 out_width, out_height,
1608 ilace, five_taps,
1609 fieldmode, color_mode,
1610 rotation);
1611 }
1612
1613 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1614 bool mirroring, enum omap_color_mode color_mode)
1615 {
1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1655 row_repeat = true;
1656 else
1657 row_repeat = false;
1658 }
1659
1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
1664 }
1665
1666 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1667 {
1668 switch (color_mode) {
1669 case OMAP_DSS_COLOR_CLUT1:
1670 return 1;
1671 case OMAP_DSS_COLOR_CLUT2:
1672 return 2;
1673 case OMAP_DSS_COLOR_CLUT4:
1674 return 4;
1675 case OMAP_DSS_COLOR_CLUT8:
1676 case OMAP_DSS_COLOR_NV12:
1677 return 8;
1678 case OMAP_DSS_COLOR_RGB12U:
1679 case OMAP_DSS_COLOR_RGB16:
1680 case OMAP_DSS_COLOR_ARGB16:
1681 case OMAP_DSS_COLOR_YUV2:
1682 case OMAP_DSS_COLOR_UYVY:
1683 case OMAP_DSS_COLOR_RGBA16:
1684 case OMAP_DSS_COLOR_RGBX16:
1685 case OMAP_DSS_COLOR_ARGB16_1555:
1686 case OMAP_DSS_COLOR_XRGB16_1555:
1687 return 16;
1688 case OMAP_DSS_COLOR_RGB24P:
1689 return 24;
1690 case OMAP_DSS_COLOR_RGB24U:
1691 case OMAP_DSS_COLOR_ARGB32:
1692 case OMAP_DSS_COLOR_RGBA32:
1693 case OMAP_DSS_COLOR_RGBX32:
1694 return 32;
1695 default:
1696 BUG();
1697 return 0;
1698 }
1699 }
1700
1701 static s32 pixinc(int pixels, u8 ps)
1702 {
1703 if (pixels == 1)
1704 return 1;
1705 else if (pixels > 1)
1706 return 1 + (pixels - 1) * ps;
1707 else if (pixels < 0)
1708 return 1 - (-pixels + 1) * ps;
1709 else
1710 BUG();
1711 return 0;
1712 }
1713
1714 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1715 u16 screen_width,
1716 u16 width, u16 height,
1717 enum omap_color_mode color_mode, bool fieldmode,
1718 unsigned int field_offset,
1719 unsigned *offset0, unsigned *offset1,
1720 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1721 {
1722 u8 ps;
1723
1724 /* FIXME CLUT formats */
1725 switch (color_mode) {
1726 case OMAP_DSS_COLOR_CLUT1:
1727 case OMAP_DSS_COLOR_CLUT2:
1728 case OMAP_DSS_COLOR_CLUT4:
1729 case OMAP_DSS_COLOR_CLUT8:
1730 BUG();
1731 return;
1732 case OMAP_DSS_COLOR_YUV2:
1733 case OMAP_DSS_COLOR_UYVY:
1734 ps = 4;
1735 break;
1736 default:
1737 ps = color_mode_to_bpp(color_mode) / 8;
1738 break;
1739 }
1740
1741 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1742 width, height);
1743
1744 /*
1745 * field 0 = even field = bottom field
1746 * field 1 = odd field = top field
1747 */
1748 switch (rotation + mirror * 4) {
1749 case OMAP_DSS_ROT_0:
1750 case OMAP_DSS_ROT_180:
1751 /*
1752 * If the pixel format is YUV or UYVY divide the width
1753 * of the image by 2 for 0 and 180 degree rotation.
1754 */
1755 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1756 color_mode == OMAP_DSS_COLOR_UYVY)
1757 width = width >> 1;
1758 case OMAP_DSS_ROT_90:
1759 case OMAP_DSS_ROT_270:
1760 *offset1 = 0;
1761 if (field_offset)
1762 *offset0 = field_offset * screen_width * ps;
1763 else
1764 *offset0 = 0;
1765
1766 *row_inc = pixinc(1 +
1767 (y_predecim * screen_width - x_predecim * width) +
1768 (fieldmode ? screen_width : 0), ps);
1769 *pix_inc = pixinc(x_predecim, ps);
1770 break;
1771
1772 case OMAP_DSS_ROT_0 + 4:
1773 case OMAP_DSS_ROT_180 + 4:
1774 /* If the pixel format is YUV or UYVY divide the width
1775 * of the image by 2 for 0 degree and 180 degree
1776 */
1777 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1778 color_mode == OMAP_DSS_COLOR_UYVY)
1779 width = width >> 1;
1780 case OMAP_DSS_ROT_90 + 4:
1781 case OMAP_DSS_ROT_270 + 4:
1782 *offset1 = 0;
1783 if (field_offset)
1784 *offset0 = field_offset * screen_width * ps;
1785 else
1786 *offset0 = 0;
1787 *row_inc = pixinc(1 -
1788 (y_predecim * screen_width + x_predecim * width) -
1789 (fieldmode ? screen_width : 0), ps);
1790 *pix_inc = pixinc(x_predecim, ps);
1791 break;
1792
1793 default:
1794 BUG();
1795 return;
1796 }
1797 }
1798
1799 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1800 u16 screen_width,
1801 u16 width, u16 height,
1802 enum omap_color_mode color_mode, bool fieldmode,
1803 unsigned int field_offset,
1804 unsigned *offset0, unsigned *offset1,
1805 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1806 {
1807 u8 ps;
1808 u16 fbw, fbh;
1809
1810 /* FIXME CLUT formats */
1811 switch (color_mode) {
1812 case OMAP_DSS_COLOR_CLUT1:
1813 case OMAP_DSS_COLOR_CLUT2:
1814 case OMAP_DSS_COLOR_CLUT4:
1815 case OMAP_DSS_COLOR_CLUT8:
1816 BUG();
1817 return;
1818 default:
1819 ps = color_mode_to_bpp(color_mode) / 8;
1820 break;
1821 }
1822
1823 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1824 width, height);
1825
1826 /* width & height are overlay sizes, convert to fb sizes */
1827
1828 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1829 fbw = width;
1830 fbh = height;
1831 } else {
1832 fbw = height;
1833 fbh = width;
1834 }
1835
1836 /*
1837 * field 0 = even field = bottom field
1838 * field 1 = odd field = top field
1839 */
1840 switch (rotation + mirror * 4) {
1841 case OMAP_DSS_ROT_0:
1842 *offset1 = 0;
1843 if (field_offset)
1844 *offset0 = *offset1 + field_offset * screen_width * ps;
1845 else
1846 *offset0 = *offset1;
1847 *row_inc = pixinc(1 +
1848 (y_predecim * screen_width - fbw * x_predecim) +
1849 (fieldmode ? screen_width : 0), ps);
1850 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1851 color_mode == OMAP_DSS_COLOR_UYVY)
1852 *pix_inc = pixinc(x_predecim, 2 * ps);
1853 else
1854 *pix_inc = pixinc(x_predecim, ps);
1855 break;
1856 case OMAP_DSS_ROT_90:
1857 *offset1 = screen_width * (fbh - 1) * ps;
1858 if (field_offset)
1859 *offset0 = *offset1 + field_offset * ps;
1860 else
1861 *offset0 = *offset1;
1862 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1863 y_predecim + (fieldmode ? 1 : 0), ps);
1864 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1865 break;
1866 case OMAP_DSS_ROT_180:
1867 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1868 if (field_offset)
1869 *offset0 = *offset1 - field_offset * screen_width * ps;
1870 else
1871 *offset0 = *offset1;
1872 *row_inc = pixinc(-1 -
1873 (y_predecim * screen_width - fbw * x_predecim) -
1874 (fieldmode ? screen_width : 0), ps);
1875 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876 color_mode == OMAP_DSS_COLOR_UYVY)
1877 *pix_inc = pixinc(-x_predecim, 2 * ps);
1878 else
1879 *pix_inc = pixinc(-x_predecim, ps);
1880 break;
1881 case OMAP_DSS_ROT_270:
1882 *offset1 = (fbw - 1) * ps;
1883 if (field_offset)
1884 *offset0 = *offset1 - field_offset * ps;
1885 else
1886 *offset0 = *offset1;
1887 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1888 y_predecim - (fieldmode ? 1 : 0), ps);
1889 *pix_inc = pixinc(x_predecim * screen_width, ps);
1890 break;
1891
1892 /* mirroring */
1893 case OMAP_DSS_ROT_0 + 4:
1894 *offset1 = (fbw - 1) * ps;
1895 if (field_offset)
1896 *offset0 = *offset1 + field_offset * screen_width * ps;
1897 else
1898 *offset0 = *offset1;
1899 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1900 (fieldmode ? screen_width : 0),
1901 ps);
1902 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1903 color_mode == OMAP_DSS_COLOR_UYVY)
1904 *pix_inc = pixinc(-x_predecim, 2 * ps);
1905 else
1906 *pix_inc = pixinc(-x_predecim, ps);
1907 break;
1908
1909 case OMAP_DSS_ROT_90 + 4:
1910 *offset1 = 0;
1911 if (field_offset)
1912 *offset0 = *offset1 + field_offset * ps;
1913 else
1914 *offset0 = *offset1;
1915 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1916 y_predecim + (fieldmode ? 1 : 0),
1917 ps);
1918 *pix_inc = pixinc(x_predecim * screen_width, ps);
1919 break;
1920
1921 case OMAP_DSS_ROT_180 + 4:
1922 *offset1 = screen_width * (fbh - 1) * ps;
1923 if (field_offset)
1924 *offset0 = *offset1 - field_offset * screen_width * ps;
1925 else
1926 *offset0 = *offset1;
1927 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1928 (fieldmode ? screen_width : 0),
1929 ps);
1930 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931 color_mode == OMAP_DSS_COLOR_UYVY)
1932 *pix_inc = pixinc(x_predecim, 2 * ps);
1933 else
1934 *pix_inc = pixinc(x_predecim, ps);
1935 break;
1936
1937 case OMAP_DSS_ROT_270 + 4:
1938 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1939 if (field_offset)
1940 *offset0 = *offset1 - field_offset * ps;
1941 else
1942 *offset0 = *offset1;
1943 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1944 y_predecim - (fieldmode ? 1 : 0),
1945 ps);
1946 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1947 break;
1948
1949 default:
1950 BUG();
1951 return;
1952 }
1953 }
1954
1955 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1956 enum omap_color_mode color_mode, bool fieldmode,
1957 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1958 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959 {
1960 u8 ps;
1961
1962 switch (color_mode) {
1963 case OMAP_DSS_COLOR_CLUT1:
1964 case OMAP_DSS_COLOR_CLUT2:
1965 case OMAP_DSS_COLOR_CLUT4:
1966 case OMAP_DSS_COLOR_CLUT8:
1967 BUG();
1968 return;
1969 default:
1970 ps = color_mode_to_bpp(color_mode) / 8;
1971 break;
1972 }
1973
1974 DSSDBG("scrw %d, width %d\n", screen_width, width);
1975
1976 /*
1977 * field 0 = even field = bottom field
1978 * field 1 = odd field = top field
1979 */
1980 *offset1 = 0;
1981 if (field_offset)
1982 *offset0 = *offset1 + field_offset * screen_width * ps;
1983 else
1984 *offset0 = *offset1;
1985 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1986 (fieldmode ? screen_width : 0), ps);
1987 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1988 color_mode == OMAP_DSS_COLOR_UYVY)
1989 *pix_inc = pixinc(x_predecim, 2 * ps);
1990 else
1991 *pix_inc = pixinc(x_predecim, ps);
1992 }
1993
1994 /*
1995 * This function is used to avoid synclosts in OMAP3, because of some
1996 * undocumented horizontal position and timing related limitations.
1997 */
1998 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
1999 const struct omap_video_timings *t, u16 pos_x,
2000 u16 width, u16 height, u16 out_width, u16 out_height)
2001 {
2002 const int ds = DIV_ROUND_UP(height, out_height);
2003 unsigned long nonactive;
2004 static const u8 limits[3] = { 8, 10, 20 };
2005 u64 val, blank;
2006 int i;
2007
2008 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2009
2010 i = 0;
2011 if (out_height < height)
2012 i++;
2013 if (out_width < width)
2014 i++;
2015 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2016 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2017 if (blank <= limits[i])
2018 return -EINVAL;
2019
2020 /*
2021 * Pixel data should be prepared before visible display point starts.
2022 * So, atleast DS-2 lines must have already been fetched by DISPC
2023 * during nonactive - pos_x period.
2024 */
2025 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2026 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2027 val, max(0, ds - 2) * width);
2028 if (val < max(0, ds - 2) * width)
2029 return -EINVAL;
2030
2031 /*
2032 * All lines need to be refilled during the nonactive period of which
2033 * only one line can be loaded during the active period. So, atleast
2034 * DS - 1 lines should be loaded during nonactive period.
2035 */
2036 val = div_u64((u64)nonactive * lclk, pclk);
2037 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2038 val, max(0, ds - 1) * width);
2039 if (val < max(0, ds - 1) * width)
2040 return -EINVAL;
2041
2042 return 0;
2043 }
2044
2045 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2046 const struct omap_video_timings *mgr_timings, u16 width,
2047 u16 height, u16 out_width, u16 out_height,
2048 enum omap_color_mode color_mode)
2049 {
2050 u32 core_clk = 0;
2051 u64 tmp;
2052
2053 if (height <= out_height && width <= out_width)
2054 return (unsigned long) pclk;
2055
2056 if (height > out_height) {
2057 unsigned int ppl = mgr_timings->x_res;
2058
2059 tmp = pclk * height * out_width;
2060 do_div(tmp, 2 * out_height * ppl);
2061 core_clk = tmp;
2062
2063 if (height > 2 * out_height) {
2064 if (ppl == out_width)
2065 return 0;
2066
2067 tmp = pclk * (height - 2 * out_height) * out_width;
2068 do_div(tmp, 2 * out_height * (ppl - out_width));
2069 core_clk = max_t(u32, core_clk, tmp);
2070 }
2071 }
2072
2073 if (width > out_width) {
2074 tmp = pclk * width;
2075 do_div(tmp, out_width);
2076 core_clk = max_t(u32, core_clk, tmp);
2077
2078 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2079 core_clk <<= 1;
2080 }
2081
2082 return core_clk;
2083 }
2084
2085 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2086 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2087 {
2088 if (height > out_height && width > out_width)
2089 return pclk * 4;
2090 else
2091 return pclk * 2;
2092 }
2093
2094 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2095 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2096 {
2097 unsigned int hf, vf;
2098
2099 /*
2100 * FIXME how to determine the 'A' factor
2101 * for the no downscaling case ?
2102 */
2103
2104 if (width > 3 * out_width)
2105 hf = 4;
2106 else if (width > 2 * out_width)
2107 hf = 3;
2108 else if (width > out_width)
2109 hf = 2;
2110 else
2111 hf = 1;
2112 if (height > out_height)
2113 vf = 2;
2114 else
2115 vf = 1;
2116
2117 return pclk * vf * hf;
2118 }
2119
2120 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2121 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2122 {
2123 /*
2124 * If the overlay/writeback is in mem to mem mode, there are no
2125 * downscaling limitations with respect to pixel clock, return 1 as
2126 * required core clock to represent that we have sufficient enough
2127 * core clock to do maximum downscaling
2128 */
2129 if (mem_to_mem)
2130 return 1;
2131
2132 if (width > out_width)
2133 return DIV_ROUND_UP(pclk, out_width) * width;
2134 else
2135 return pclk;
2136 }
2137
2138 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2139 const struct omap_video_timings *mgr_timings,
2140 u16 width, u16 height, u16 out_width, u16 out_height,
2141 enum omap_color_mode color_mode, bool *five_taps,
2142 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2143 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2144 {
2145 int error;
2146 u16 in_width, in_height;
2147 int min_factor = min(*decim_x, *decim_y);
2148 const int maxsinglelinewidth =
2149 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2150
2151 *five_taps = false;
2152
2153 do {
2154 in_height = DIV_ROUND_UP(height, *decim_y);
2155 in_width = DIV_ROUND_UP(width, *decim_x);
2156 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2157 in_height, out_width, out_height, mem_to_mem);
2158 error = (in_width > maxsinglelinewidth || !*core_clk ||
2159 *core_clk > dispc_core_clk_rate());
2160 if (error) {
2161 if (*decim_x == *decim_y) {
2162 *decim_x = min_factor;
2163 ++*decim_y;
2164 } else {
2165 swap(*decim_x, *decim_y);
2166 if (*decim_x < *decim_y)
2167 ++*decim_x;
2168 }
2169 }
2170 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2171
2172 if (in_width > maxsinglelinewidth) {
2173 DSSERR("Cannot scale max input width exceeded");
2174 return -EINVAL;
2175 }
2176 return 0;
2177 }
2178
2179 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2180 const struct omap_video_timings *mgr_timings,
2181 u16 width, u16 height, u16 out_width, u16 out_height,
2182 enum omap_color_mode color_mode, bool *five_taps,
2183 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2184 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2185 {
2186 int error;
2187 u16 in_width, in_height;
2188 int min_factor = min(*decim_x, *decim_y);
2189 const int maxsinglelinewidth =
2190 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2191
2192 do {
2193 in_height = DIV_ROUND_UP(height, *decim_y);
2194 in_width = DIV_ROUND_UP(width, *decim_x);
2195 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2196 in_width, in_height, out_width, out_height, color_mode);
2197
2198 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2199 pos_x, in_width, in_height, out_width,
2200 out_height);
2201
2202 if (in_width > maxsinglelinewidth)
2203 if (in_height > out_height &&
2204 in_height < out_height * 2)
2205 *five_taps = false;
2206 if (!*five_taps)
2207 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2208 in_height, out_width, out_height,
2209 mem_to_mem);
2210
2211 error = (error || in_width > maxsinglelinewidth * 2 ||
2212 (in_width > maxsinglelinewidth && *five_taps) ||
2213 !*core_clk || *core_clk > dispc_core_clk_rate());
2214 if (error) {
2215 if (*decim_x == *decim_y) {
2216 *decim_x = min_factor;
2217 ++*decim_y;
2218 } else {
2219 swap(*decim_x, *decim_y);
2220 if (*decim_x < *decim_y)
2221 ++*decim_x;
2222 }
2223 }
2224 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2225
2226 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2227 height, out_width, out_height)){
2228 DSSERR("horizontal timing too tight\n");
2229 return -EINVAL;
2230 }
2231
2232 if (in_width > (maxsinglelinewidth * 2)) {
2233 DSSERR("Cannot setup scaling");
2234 DSSERR("width exceeds maximum width possible");
2235 return -EINVAL;
2236 }
2237
2238 if (in_width > maxsinglelinewidth && *five_taps) {
2239 DSSERR("cannot setup scaling with five taps");
2240 return -EINVAL;
2241 }
2242 return 0;
2243 }
2244
2245 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2246 const struct omap_video_timings *mgr_timings,
2247 u16 width, u16 height, u16 out_width, u16 out_height,
2248 enum omap_color_mode color_mode, bool *five_taps,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2251 {
2252 u16 in_width, in_width_max;
2253 int decim_x_min = *decim_x;
2254 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2255 const int maxsinglelinewidth =
2256 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2257 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2258
2259 if (mem_to_mem) {
2260 in_width_max = out_width * maxdownscale;
2261 } else {
2262 in_width_max = dispc_core_clk_rate() /
2263 DIV_ROUND_UP(pclk, out_width);
2264 }
2265
2266 *decim_x = DIV_ROUND_UP(width, in_width_max);
2267
2268 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2269 if (*decim_x > *x_predecim)
2270 return -EINVAL;
2271
2272 do {
2273 in_width = DIV_ROUND_UP(width, *decim_x);
2274 } while (*decim_x <= *x_predecim &&
2275 in_width > maxsinglelinewidth && ++*decim_x);
2276
2277 if (in_width > maxsinglelinewidth) {
2278 DSSERR("Cannot scale width exceeds max line width");
2279 return -EINVAL;
2280 }
2281
2282 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2283 out_width, out_height, mem_to_mem);
2284 return 0;
2285 }
2286
2287 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2288 enum omap_overlay_caps caps,
2289 const struct omap_video_timings *mgr_timings,
2290 u16 width, u16 height, u16 out_width, u16 out_height,
2291 enum omap_color_mode color_mode, bool *five_taps,
2292 int *x_predecim, int *y_predecim, u16 pos_x,
2293 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2294 {
2295 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2296 const int max_decim_limit = 16;
2297 unsigned long core_clk = 0;
2298 int decim_x, decim_y, ret;
2299
2300 if (width == out_width && height == out_height)
2301 return 0;
2302
2303 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2304 return -EINVAL;
2305
2306 if (mem_to_mem) {
2307 *x_predecim = *y_predecim = 1;
2308 } else {
2309 *x_predecim = max_decim_limit;
2310 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2311 dss_has_feature(FEAT_BURST_2D)) ?
2312 2 : max_decim_limit;
2313 }
2314
2315 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2316 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2317 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2318 color_mode == OMAP_DSS_COLOR_CLUT8) {
2319 *x_predecim = 1;
2320 *y_predecim = 1;
2321 *five_taps = false;
2322 return 0;
2323 }
2324
2325 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2326 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2327
2328 if (decim_x > *x_predecim || out_width > width * 8)
2329 return -EINVAL;
2330
2331 if (decim_y > *y_predecim || out_height > height * 8)
2332 return -EINVAL;
2333
2334 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2335 out_width, out_height, color_mode, five_taps,
2336 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2337 mem_to_mem);
2338 if (ret)
2339 return ret;
2340
2341 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2342 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2343
2344 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2345 DSSERR("failed to set up scaling, "
2346 "required core clk rate = %lu Hz, "
2347 "current core clk rate = %lu Hz\n",
2348 core_clk, dispc_core_clk_rate());
2349 return -EINVAL;
2350 }
2351
2352 *x_predecim = decim_x;
2353 *y_predecim = decim_y;
2354 return 0;
2355 }
2356
2357 static int dispc_ovl_setup_common(enum omap_plane plane,
2358 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2359 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2360 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2361 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2362 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2363 bool replication, const struct omap_video_timings *mgr_timings,
2364 bool mem_to_mem)
2365 {
2366 bool five_taps = true;
2367 bool fieldmode = 0;
2368 int r, cconv = 0;
2369 unsigned offset0, offset1;
2370 s32 row_inc;
2371 s32 pix_inc;
2372 u16 frame_width, frame_height;
2373 unsigned int field_offset = 0;
2374 u16 in_height = height;
2375 u16 in_width = width;
2376 int x_predecim = 1, y_predecim = 1;
2377 bool ilace = mgr_timings->interlace;
2378 unsigned long pclk = dispc_plane_pclk_rate(plane);
2379 unsigned long lclk = dispc_plane_lclk_rate(plane);
2380
2381 if (paddr == 0)
2382 return -EINVAL;
2383
2384 out_width = out_width == 0 ? width : out_width;
2385 out_height = out_height == 0 ? height : out_height;
2386
2387 if (ilace && height == out_height)
2388 fieldmode = 1;
2389
2390 if (ilace) {
2391 if (fieldmode)
2392 in_height /= 2;
2393 pos_y /= 2;
2394 out_height /= 2;
2395
2396 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2397 "out_height %d\n", in_height, pos_y,
2398 out_height);
2399 }
2400
2401 if (!dss_feat_color_mode_supported(plane, color_mode))
2402 return -EINVAL;
2403
2404 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2405 in_height, out_width, out_height, color_mode,
2406 &five_taps, &x_predecim, &y_predecim, pos_x,
2407 rotation_type, mem_to_mem);
2408 if (r)
2409 return r;
2410
2411 in_width = DIV_ROUND_UP(in_width, x_predecim);
2412 in_height = DIV_ROUND_UP(in_height, y_predecim);
2413
2414 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2415 color_mode == OMAP_DSS_COLOR_UYVY ||
2416 color_mode == OMAP_DSS_COLOR_NV12)
2417 cconv = 1;
2418
2419 if (ilace && !fieldmode) {
2420 /*
2421 * when downscaling the bottom field may have to start several
2422 * source lines below the top field. Unfortunately ACCUI
2423 * registers will only hold the fractional part of the offset
2424 * so the integer part must be added to the base address of the
2425 * bottom field.
2426 */
2427 if (!in_height || in_height == out_height)
2428 field_offset = 0;
2429 else
2430 field_offset = in_height / out_height / 2;
2431 }
2432
2433 /* Fields are independent but interleaved in memory. */
2434 if (fieldmode)
2435 field_offset = 1;
2436
2437 offset0 = 0;
2438 offset1 = 0;
2439 row_inc = 0;
2440 pix_inc = 0;
2441
2442 if (plane == OMAP_DSS_WB) {
2443 frame_width = out_width;
2444 frame_height = out_height;
2445 } else {
2446 frame_width = in_width;
2447 frame_height = height;
2448 }
2449
2450 if (rotation_type == OMAP_DSS_ROT_TILER)
2451 calc_tiler_rotation_offset(screen_width, frame_width,
2452 color_mode, fieldmode, field_offset,
2453 &offset0, &offset1, &row_inc, &pix_inc,
2454 x_predecim, y_predecim);
2455 else if (rotation_type == OMAP_DSS_ROT_DMA)
2456 calc_dma_rotation_offset(rotation, mirror, screen_width,
2457 frame_width, frame_height,
2458 color_mode, fieldmode, field_offset,
2459 &offset0, &offset1, &row_inc, &pix_inc,
2460 x_predecim, y_predecim);
2461 else
2462 calc_vrfb_rotation_offset(rotation, mirror,
2463 screen_width, frame_width, frame_height,
2464 color_mode, fieldmode, field_offset,
2465 &offset0, &offset1, &row_inc, &pix_inc,
2466 x_predecim, y_predecim);
2467
2468 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2469 offset0, offset1, row_inc, pix_inc);
2470
2471 dispc_ovl_set_color_mode(plane, color_mode);
2472
2473 dispc_ovl_configure_burst_type(plane, rotation_type);
2474
2475 dispc_ovl_set_ba0(plane, paddr + offset0);
2476 dispc_ovl_set_ba1(plane, paddr + offset1);
2477
2478 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2479 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2480 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2481 }
2482
2483 dispc_ovl_set_row_inc(plane, row_inc);
2484 dispc_ovl_set_pix_inc(plane, pix_inc);
2485
2486 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2487 in_height, out_width, out_height);
2488
2489 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2490
2491 dispc_ovl_set_input_size(plane, in_width, in_height);
2492
2493 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2494 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2495 out_height, ilace, five_taps, fieldmode,
2496 color_mode, rotation);
2497 dispc_ovl_set_output_size(plane, out_width, out_height);
2498 dispc_ovl_set_vid_color_conv(plane, cconv);
2499 }
2500
2501 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
2502
2503 dispc_ovl_set_zorder(plane, caps, zorder);
2504 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2505 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2506
2507 dispc_ovl_enable_replication(plane, caps, replication);
2508
2509 return 0;
2510 }
2511
2512 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2513 bool replication, const struct omap_video_timings *mgr_timings,
2514 bool mem_to_mem)
2515 {
2516 int r;
2517 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2518 enum omap_channel channel;
2519
2520 channel = dispc_ovl_get_channel_out(plane);
2521
2522 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2523 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2524 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2525 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2526 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2527
2528 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2529 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2530 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2531 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2532 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2533
2534 return r;
2535 }
2536
2537 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2538 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2539 {
2540 int r;
2541 u32 l;
2542 enum omap_plane plane = OMAP_DSS_WB;
2543 const int pos_x = 0, pos_y = 0;
2544 const u8 zorder = 0, global_alpha = 0;
2545 const bool replication = false;
2546 bool truncation;
2547 int in_width = mgr_timings->x_res;
2548 int in_height = mgr_timings->y_res;
2549 enum omap_overlay_caps caps =
2550 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2551
2552 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2553 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2554 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2555 wi->mirror);
2556
2557 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2558 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2559 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2560 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2561 replication, mgr_timings, mem_to_mem);
2562
2563 switch (wi->color_mode) {
2564 case OMAP_DSS_COLOR_RGB16:
2565 case OMAP_DSS_COLOR_RGB24P:
2566 case OMAP_DSS_COLOR_ARGB16:
2567 case OMAP_DSS_COLOR_RGBA16:
2568 case OMAP_DSS_COLOR_RGB12U:
2569 case OMAP_DSS_COLOR_ARGB16_1555:
2570 case OMAP_DSS_COLOR_XRGB16_1555:
2571 case OMAP_DSS_COLOR_RGBX16:
2572 truncation = true;
2573 break;
2574 default:
2575 truncation = false;
2576 break;
2577 }
2578
2579 /* setup extra DISPC_WB_ATTRIBUTES */
2580 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2581 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2582 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2583 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2584
2585 return r;
2586 }
2587
2588 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2589 {
2590 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2591
2592 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2593
2594 return 0;
2595 }
2596
2597 bool dispc_ovl_enabled(enum omap_plane plane)
2598 {
2599 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2600 }
2601
2602 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2603 {
2604 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2605 /* flush posted write */
2606 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2607 }
2608
2609 bool dispc_mgr_is_enabled(enum omap_channel channel)
2610 {
2611 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2612 }
2613
2614 void dispc_wb_enable(bool enable)
2615 {
2616 dispc_ovl_enable(OMAP_DSS_WB, enable);
2617 }
2618
2619 bool dispc_wb_is_enabled(void)
2620 {
2621 return dispc_ovl_enabled(OMAP_DSS_WB);
2622 }
2623
2624 static void dispc_lcd_enable_signal_polarity(bool act_high)
2625 {
2626 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2627 return;
2628
2629 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2630 }
2631
2632 void dispc_lcd_enable_signal(bool enable)
2633 {
2634 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2635 return;
2636
2637 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2638 }
2639
2640 void dispc_pck_free_enable(bool enable)
2641 {
2642 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2643 return;
2644
2645 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2646 }
2647
2648 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2649 {
2650 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2651 }
2652
2653
2654 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2655 {
2656 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2657 }
2658
2659 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2660 {
2661 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2662 }
2663
2664
2665 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2666 {
2667 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2668 }
2669
2670 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2671 enum omap_dss_trans_key_type type,
2672 u32 trans_key)
2673 {
2674 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2675
2676 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2677 }
2678
2679 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2680 {
2681 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2682 }
2683
2684 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2685 bool enable)
2686 {
2687 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2688 return;
2689
2690 if (ch == OMAP_DSS_CHANNEL_LCD)
2691 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2692 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2693 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2694 }
2695
2696 void dispc_mgr_setup(enum omap_channel channel,
2697 const struct omap_overlay_manager_info *info)
2698 {
2699 dispc_mgr_set_default_color(channel, info->default_color);
2700 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2701 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2702 dispc_mgr_enable_alpha_fixed_zorder(channel,
2703 info->partial_alpha_enabled);
2704 if (dss_has_feature(FEAT_CPR)) {
2705 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2706 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2707 }
2708 }
2709
2710 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2711 {
2712 int code;
2713
2714 switch (data_lines) {
2715 case 12:
2716 code = 0;
2717 break;
2718 case 16:
2719 code = 1;
2720 break;
2721 case 18:
2722 code = 2;
2723 break;
2724 case 24:
2725 code = 3;
2726 break;
2727 default:
2728 BUG();
2729 return;
2730 }
2731
2732 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2733 }
2734
2735 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2736 {
2737 u32 l;
2738 int gpout0, gpout1;
2739
2740 switch (mode) {
2741 case DSS_IO_PAD_MODE_RESET:
2742 gpout0 = 0;
2743 gpout1 = 0;
2744 break;
2745 case DSS_IO_PAD_MODE_RFBI:
2746 gpout0 = 1;
2747 gpout1 = 0;
2748 break;
2749 case DSS_IO_PAD_MODE_BYPASS:
2750 gpout0 = 1;
2751 gpout1 = 1;
2752 break;
2753 default:
2754 BUG();
2755 return;
2756 }
2757
2758 l = dispc_read_reg(DISPC_CONTROL);
2759 l = FLD_MOD(l, gpout0, 15, 15);
2760 l = FLD_MOD(l, gpout1, 16, 16);
2761 dispc_write_reg(DISPC_CONTROL, l);
2762 }
2763
2764 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2765 {
2766 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2767 }
2768
2769 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2770 const struct dss_lcd_mgr_config *config)
2771 {
2772 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2773
2774 dispc_mgr_enable_stallmode(channel, config->stallmode);
2775 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2776
2777 dispc_mgr_set_clock_div(channel, &config->clock_info);
2778
2779 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2780
2781 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2782
2783 dispc_mgr_set_lcd_type_tft(channel);
2784 }
2785
2786 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2787 {
2788 return width <= dispc.feat->mgr_width_max &&
2789 height <= dispc.feat->mgr_height_max;
2790 }
2791
2792 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2793 int vsw, int vfp, int vbp)
2794 {
2795 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2796 hfp < 1 || hfp > dispc.feat->hp_max ||
2797 hbp < 1 || hbp > dispc.feat->hp_max ||
2798 vsw < 1 || vsw > dispc.feat->sw_max ||
2799 vfp < 0 || vfp > dispc.feat->vp_max ||
2800 vbp < 0 || vbp > dispc.feat->vp_max)
2801 return false;
2802 return true;
2803 }
2804
2805 bool dispc_mgr_timings_ok(enum omap_channel channel,
2806 const struct omap_video_timings *timings)
2807 {
2808 bool timings_ok;
2809
2810 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2811
2812 if (dss_mgr_is_lcd(channel))
2813 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2814 timings->hfp, timings->hbp,
2815 timings->vsw, timings->vfp,
2816 timings->vbp);
2817
2818 return timings_ok;
2819 }
2820
2821 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2822 int hfp, int hbp, int vsw, int vfp, int vbp,
2823 enum omap_dss_signal_level vsync_level,
2824 enum omap_dss_signal_level hsync_level,
2825 enum omap_dss_signal_edge data_pclk_edge,
2826 enum omap_dss_signal_level de_level,
2827 enum omap_dss_signal_edge sync_pclk_edge)
2828
2829 {
2830 u32 timing_h, timing_v, l;
2831 bool onoff, rf, ipc;
2832
2833 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2834 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2835 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2836 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2837 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2838 FLD_VAL(vbp, dispc.feat->bp_start, 20);
2839
2840 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2841 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2842
2843 switch (data_pclk_edge) {
2844 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2845 ipc = false;
2846 break;
2847 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2848 ipc = true;
2849 break;
2850 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2851 default:
2852 BUG();
2853 }
2854
2855 switch (sync_pclk_edge) {
2856 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2857 onoff = false;
2858 rf = false;
2859 break;
2860 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2861 onoff = true;
2862 rf = false;
2863 break;
2864 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2865 onoff = true;
2866 rf = true;
2867 break;
2868 default:
2869 BUG();
2870 };
2871
2872 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2873 l |= FLD_VAL(onoff, 17, 17);
2874 l |= FLD_VAL(rf, 16, 16);
2875 l |= FLD_VAL(de_level, 15, 15);
2876 l |= FLD_VAL(ipc, 14, 14);
2877 l |= FLD_VAL(hsync_level, 13, 13);
2878 l |= FLD_VAL(vsync_level, 12, 12);
2879 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2880 }
2881
2882 /* change name to mode? */
2883 void dispc_mgr_set_timings(enum omap_channel channel,
2884 const struct omap_video_timings *timings)
2885 {
2886 unsigned xtot, ytot;
2887 unsigned long ht, vt;
2888 struct omap_video_timings t = *timings;
2889
2890 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2891
2892 if (!dispc_mgr_timings_ok(channel, &t)) {
2893 BUG();
2894 return;
2895 }
2896
2897 if (dss_mgr_is_lcd(channel)) {
2898 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2899 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2900 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2901
2902 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2903 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2904
2905 ht = (timings->pixel_clock * 1000) / xtot;
2906 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2907
2908 DSSDBG("pck %u\n", timings->pixel_clock);
2909 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2910 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2911 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2912 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2913 t.de_level, t.sync_pclk_edge);
2914
2915 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2916 } else {
2917 if (t.interlace == true)
2918 t.y_res /= 2;
2919 }
2920
2921 dispc_mgr_set_size(channel, t.x_res, t.y_res);
2922 }
2923
2924 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2925 u16 pck_div)
2926 {
2927 BUG_ON(lck_div < 1);
2928 BUG_ON(pck_div < 1);
2929
2930 dispc_write_reg(DISPC_DIVISORo(channel),
2931 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2932 }
2933
2934 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2935 int *pck_div)
2936 {
2937 u32 l;
2938 l = dispc_read_reg(DISPC_DIVISORo(channel));
2939 *lck_div = FLD_GET(l, 23, 16);
2940 *pck_div = FLD_GET(l, 7, 0);
2941 }
2942
2943 unsigned long dispc_fclk_rate(void)
2944 {
2945 struct platform_device *dsidev;
2946 unsigned long r = 0;
2947
2948 switch (dss_get_dispc_clk_source()) {
2949 case OMAP_DSS_CLK_SRC_FCK:
2950 r = clk_get_rate(dispc.dss_clk);
2951 break;
2952 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2953 dsidev = dsi_get_dsidev_from_id(0);
2954 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2955 break;
2956 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2957 dsidev = dsi_get_dsidev_from_id(1);
2958 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2959 break;
2960 default:
2961 BUG();
2962 return 0;
2963 }
2964
2965 return r;
2966 }
2967
2968 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2969 {
2970 struct platform_device *dsidev;
2971 int lcd;
2972 unsigned long r;
2973 u32 l;
2974
2975 if (dss_mgr_is_lcd(channel)) {
2976 l = dispc_read_reg(DISPC_DIVISORo(channel));
2977
2978 lcd = FLD_GET(l, 23, 16);
2979
2980 switch (dss_get_lcd_clk_source(channel)) {
2981 case OMAP_DSS_CLK_SRC_FCK:
2982 r = clk_get_rate(dispc.dss_clk);
2983 break;
2984 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2985 dsidev = dsi_get_dsidev_from_id(0);
2986 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2987 break;
2988 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2989 dsidev = dsi_get_dsidev_from_id(1);
2990 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2991 break;
2992 default:
2993 BUG();
2994 return 0;
2995 }
2996
2997 return r / lcd;
2998 } else {
2999 return dispc_fclk_rate();
3000 }
3001 }
3002
3003 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3004 {
3005 unsigned long r;
3006
3007 if (dss_mgr_is_lcd(channel)) {
3008 int pcd;
3009 u32 l;
3010
3011 l = dispc_read_reg(DISPC_DIVISORo(channel));
3012
3013 pcd = FLD_GET(l, 7, 0);
3014
3015 r = dispc_mgr_lclk_rate(channel);
3016
3017 return r / pcd;
3018 } else {
3019 enum dss_hdmi_venc_clk_source_select source;
3020
3021 source = dss_get_hdmi_venc_clk_source();
3022
3023 switch (source) {
3024 case DSS_VENC_TV_CLK:
3025 return venc_get_pixel_clock();
3026 case DSS_HDMI_M_PCLK:
3027 return hdmi_get_pixel_clock();
3028 default:
3029 BUG();
3030 return 0;
3031 }
3032 }
3033 }
3034
3035 unsigned long dispc_core_clk_rate(void)
3036 {
3037 int lcd;
3038 unsigned long fclk = dispc_fclk_rate();
3039
3040 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3041 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3042 else
3043 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3044
3045 return fclk / lcd;
3046 }
3047
3048 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3049 {
3050 enum omap_channel channel;
3051
3052 if (plane == OMAP_DSS_WB)
3053 return 0;
3054
3055 channel = dispc_ovl_get_channel_out(plane);
3056
3057 return dispc_mgr_pclk_rate(channel);
3058 }
3059
3060 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3061 {
3062 enum omap_channel channel;
3063
3064 if (plane == OMAP_DSS_WB)
3065 return 0;
3066
3067 channel = dispc_ovl_get_channel_out(plane);
3068
3069 return dispc_mgr_lclk_rate(channel);
3070 }
3071
3072 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3073 {
3074 int lcd, pcd;
3075 enum omap_dss_clk_source lcd_clk_src;
3076
3077 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3078
3079 lcd_clk_src = dss_get_lcd_clk_source(channel);
3080
3081 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3082 dss_get_generic_clk_source_name(lcd_clk_src),
3083 dss_feat_get_clk_source_name(lcd_clk_src));
3084
3085 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3086
3087 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3088 dispc_mgr_lclk_rate(channel), lcd);
3089 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3090 dispc_mgr_pclk_rate(channel), pcd);
3091 }
3092
3093 void dispc_dump_clocks(struct seq_file *s)
3094 {
3095 int lcd;
3096 u32 l;
3097 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3098
3099 if (dispc_runtime_get())
3100 return;
3101
3102 seq_printf(s, "- DISPC -\n");
3103
3104 seq_printf(s, "dispc fclk source = %s (%s)\n",
3105 dss_get_generic_clk_source_name(dispc_clk_src),
3106 dss_feat_get_clk_source_name(dispc_clk_src));
3107
3108 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3109
3110 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3111 seq_printf(s, "- DISPC-CORE-CLK -\n");
3112 l = dispc_read_reg(DISPC_DIVISOR);
3113 lcd = FLD_GET(l, 23, 16);
3114
3115 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3116 (dispc_fclk_rate()/lcd), lcd);
3117 }
3118
3119 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3120
3121 if (dss_has_feature(FEAT_MGR_LCD2))
3122 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3123 if (dss_has_feature(FEAT_MGR_LCD3))
3124 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3125
3126 dispc_runtime_put();
3127 }
3128
3129 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3130 static void dispc_dump_irqs(struct seq_file *s)
3131 {
3132 unsigned long flags;
3133 struct dispc_irq_stats stats;
3134
3135 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3136
3137 stats = dispc.irq_stats;
3138 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3139 dispc.irq_stats.last_reset = jiffies;
3140
3141 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3142
3143 seq_printf(s, "period %u ms\n",
3144 jiffies_to_msecs(jiffies - stats.last_reset));
3145
3146 seq_printf(s, "irqs %d\n", stats.irq_count);
3147 #define PIS(x) \
3148 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3149
3150 PIS(FRAMEDONE);
3151 PIS(VSYNC);
3152 PIS(EVSYNC_EVEN);
3153 PIS(EVSYNC_ODD);
3154 PIS(ACBIAS_COUNT_STAT);
3155 PIS(PROG_LINE_NUM);
3156 PIS(GFX_FIFO_UNDERFLOW);
3157 PIS(GFX_END_WIN);
3158 PIS(PAL_GAMMA_MASK);
3159 PIS(OCP_ERR);
3160 PIS(VID1_FIFO_UNDERFLOW);
3161 PIS(VID1_END_WIN);
3162 PIS(VID2_FIFO_UNDERFLOW);
3163 PIS(VID2_END_WIN);
3164 if (dss_feat_get_num_ovls() > 3) {
3165 PIS(VID3_FIFO_UNDERFLOW);
3166 PIS(VID3_END_WIN);
3167 }
3168 PIS(SYNC_LOST);
3169 PIS(SYNC_LOST_DIGIT);
3170 PIS(WAKEUP);
3171 if (dss_has_feature(FEAT_MGR_LCD2)) {
3172 PIS(FRAMEDONE2);
3173 PIS(VSYNC2);
3174 PIS(ACBIAS_COUNT_STAT2);
3175 PIS(SYNC_LOST2);
3176 }
3177 if (dss_has_feature(FEAT_MGR_LCD3)) {
3178 PIS(FRAMEDONE3);
3179 PIS(VSYNC3);
3180 PIS(ACBIAS_COUNT_STAT3);
3181 PIS(SYNC_LOST3);
3182 }
3183 #undef PIS
3184 }
3185 #endif
3186
3187 static void dispc_dump_regs(struct seq_file *s)
3188 {
3189 int i, j;
3190 const char *mgr_names[] = {
3191 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3192 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3193 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3194 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3195 };
3196 const char *ovl_names[] = {
3197 [OMAP_DSS_GFX] = "GFX",
3198 [OMAP_DSS_VIDEO1] = "VID1",
3199 [OMAP_DSS_VIDEO2] = "VID2",
3200 [OMAP_DSS_VIDEO3] = "VID3",
3201 };
3202 const char **p_names;
3203
3204 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3205
3206 if (dispc_runtime_get())
3207 return;
3208
3209 /* DISPC common registers */
3210 DUMPREG(DISPC_REVISION);
3211 DUMPREG(DISPC_SYSCONFIG);
3212 DUMPREG(DISPC_SYSSTATUS);
3213 DUMPREG(DISPC_IRQSTATUS);
3214 DUMPREG(DISPC_IRQENABLE);
3215 DUMPREG(DISPC_CONTROL);
3216 DUMPREG(DISPC_CONFIG);
3217 DUMPREG(DISPC_CAPABLE);
3218 DUMPREG(DISPC_LINE_STATUS);
3219 DUMPREG(DISPC_LINE_NUMBER);
3220 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3221 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3222 DUMPREG(DISPC_GLOBAL_ALPHA);
3223 if (dss_has_feature(FEAT_MGR_LCD2)) {
3224 DUMPREG(DISPC_CONTROL2);
3225 DUMPREG(DISPC_CONFIG2);
3226 }
3227 if (dss_has_feature(FEAT_MGR_LCD3)) {
3228 DUMPREG(DISPC_CONTROL3);
3229 DUMPREG(DISPC_CONFIG3);
3230 }
3231
3232 #undef DUMPREG
3233
3234 #define DISPC_REG(i, name) name(i)
3235 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3236 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3237 dispc_read_reg(DISPC_REG(i, r)))
3238
3239 p_names = mgr_names;
3240
3241 /* DISPC channel specific registers */
3242 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3243 DUMPREG(i, DISPC_DEFAULT_COLOR);
3244 DUMPREG(i, DISPC_TRANS_COLOR);
3245 DUMPREG(i, DISPC_SIZE_MGR);
3246
3247 if (i == OMAP_DSS_CHANNEL_DIGIT)
3248 continue;
3249
3250 DUMPREG(i, DISPC_DEFAULT_COLOR);
3251 DUMPREG(i, DISPC_TRANS_COLOR);
3252 DUMPREG(i, DISPC_TIMING_H);
3253 DUMPREG(i, DISPC_TIMING_V);
3254 DUMPREG(i, DISPC_POL_FREQ);
3255 DUMPREG(i, DISPC_DIVISORo);
3256 DUMPREG(i, DISPC_SIZE_MGR);
3257
3258 DUMPREG(i, DISPC_DATA_CYCLE1);
3259 DUMPREG(i, DISPC_DATA_CYCLE2);
3260 DUMPREG(i, DISPC_DATA_CYCLE3);
3261
3262 if (dss_has_feature(FEAT_CPR)) {
3263 DUMPREG(i, DISPC_CPR_COEF_R);
3264 DUMPREG(i, DISPC_CPR_COEF_G);
3265 DUMPREG(i, DISPC_CPR_COEF_B);
3266 }
3267 }
3268
3269 p_names = ovl_names;
3270
3271 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3272 DUMPREG(i, DISPC_OVL_BA0);
3273 DUMPREG(i, DISPC_OVL_BA1);
3274 DUMPREG(i, DISPC_OVL_POSITION);
3275 DUMPREG(i, DISPC_OVL_SIZE);
3276 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3277 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3278 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3279 DUMPREG(i, DISPC_OVL_ROW_INC);
3280 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3281 if (dss_has_feature(FEAT_PRELOAD))
3282 DUMPREG(i, DISPC_OVL_PRELOAD);
3283
3284 if (i == OMAP_DSS_GFX) {
3285 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3286 DUMPREG(i, DISPC_OVL_TABLE_BA);
3287 continue;
3288 }
3289
3290 DUMPREG(i, DISPC_OVL_FIR);
3291 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3292 DUMPREG(i, DISPC_OVL_ACCU0);
3293 DUMPREG(i, DISPC_OVL_ACCU1);
3294 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3295 DUMPREG(i, DISPC_OVL_BA0_UV);
3296 DUMPREG(i, DISPC_OVL_BA1_UV);
3297 DUMPREG(i, DISPC_OVL_FIR2);
3298 DUMPREG(i, DISPC_OVL_ACCU2_0);
3299 DUMPREG(i, DISPC_OVL_ACCU2_1);
3300 }
3301 if (dss_has_feature(FEAT_ATTR2))
3302 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3303 if (dss_has_feature(FEAT_PRELOAD))
3304 DUMPREG(i, DISPC_OVL_PRELOAD);
3305 }
3306
3307 #undef DISPC_REG
3308 #undef DUMPREG
3309
3310 #define DISPC_REG(plane, name, i) name(plane, i)
3311 #define DUMPREG(plane, name, i) \
3312 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3313 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3314 dispc_read_reg(DISPC_REG(plane, name, i)))
3315
3316 /* Video pipeline coefficient registers */
3317
3318 /* start from OMAP_DSS_VIDEO1 */
3319 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3320 for (j = 0; j < 8; j++)
3321 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3322
3323 for (j = 0; j < 8; j++)
3324 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3325
3326 for (j = 0; j < 5; j++)
3327 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3328
3329 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3330 for (j = 0; j < 8; j++)
3331 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3332 }
3333
3334 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3335 for (j = 0; j < 8; j++)
3336 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3337
3338 for (j = 0; j < 8; j++)
3339 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3340
3341 for (j = 0; j < 8; j++)
3342 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3343 }
3344 }
3345
3346 dispc_runtime_put();
3347
3348 #undef DISPC_REG
3349 #undef DUMPREG
3350 }
3351
3352 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3353 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3354 struct dispc_clock_info *cinfo)
3355 {
3356 u16 pcd_min, pcd_max;
3357 unsigned long best_pck;
3358 u16 best_ld, cur_ld;
3359 u16 best_pd, cur_pd;
3360
3361 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3362 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3363
3364 best_pck = 0;
3365 best_ld = 0;
3366 best_pd = 0;
3367
3368 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3369 unsigned long lck = fck / cur_ld;
3370
3371 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3372 unsigned long pck = lck / cur_pd;
3373 long old_delta = abs(best_pck - req_pck);
3374 long new_delta = abs(pck - req_pck);
3375
3376 if (best_pck == 0 || new_delta < old_delta) {
3377 best_pck = pck;
3378 best_ld = cur_ld;
3379 best_pd = cur_pd;
3380
3381 if (pck == req_pck)
3382 goto found;
3383 }
3384
3385 if (pck < req_pck)
3386 break;
3387 }
3388
3389 if (lck / pcd_min < req_pck)
3390 break;
3391 }
3392
3393 found:
3394 cinfo->lck_div = best_ld;
3395 cinfo->pck_div = best_pd;
3396 cinfo->lck = fck / cinfo->lck_div;
3397 cinfo->pck = cinfo->lck / cinfo->pck_div;
3398 }
3399
3400 /* calculate clock rates using dividers in cinfo */
3401 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3402 struct dispc_clock_info *cinfo)
3403 {
3404 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3405 return -EINVAL;
3406 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3407 return -EINVAL;
3408
3409 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3410 cinfo->pck = cinfo->lck / cinfo->pck_div;
3411
3412 return 0;
3413 }
3414
3415 void dispc_mgr_set_clock_div(enum omap_channel channel,
3416 const struct dispc_clock_info *cinfo)
3417 {
3418 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3419 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3420
3421 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3422 }
3423
3424 int dispc_mgr_get_clock_div(enum omap_channel channel,
3425 struct dispc_clock_info *cinfo)
3426 {
3427 unsigned long fck;
3428
3429 fck = dispc_fclk_rate();
3430
3431 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3432 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3433
3434 cinfo->lck = fck / cinfo->lck_div;
3435 cinfo->pck = cinfo->lck / cinfo->pck_div;
3436
3437 return 0;
3438 }
3439
3440 u32 dispc_read_irqstatus(void)
3441 {
3442 return dispc_read_reg(DISPC_IRQSTATUS);
3443 }
3444
3445 void dispc_clear_irqstatus(u32 mask)
3446 {
3447 dispc_write_reg(DISPC_IRQSTATUS, mask);
3448 }
3449
3450 u32 dispc_read_irqenable(void)
3451 {
3452 return dispc_read_reg(DISPC_IRQENABLE);
3453 }
3454
3455 void dispc_write_irqenable(u32 mask)
3456 {
3457 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3458
3459 /* clear the irqstatus for newly enabled irqs */
3460 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3461
3462 dispc_write_reg(DISPC_IRQENABLE, mask);
3463 }
3464
3465 /* dispc.irq_lock has to be locked by the caller */
3466 static void _omap_dispc_set_irqs(void)
3467 {
3468 u32 mask;
3469 int i;
3470 struct omap_dispc_isr_data *isr_data;
3471
3472 mask = dispc.irq_error_mask;
3473
3474 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3475 isr_data = &dispc.registered_isr[i];
3476
3477 if (isr_data->isr == NULL)
3478 continue;
3479
3480 mask |= isr_data->mask;
3481 }
3482
3483 dispc_write_irqenable(mask);
3484 }
3485
3486 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3487 {
3488 int i;
3489 int ret;
3490 unsigned long flags;
3491 struct omap_dispc_isr_data *isr_data;
3492
3493 if (isr == NULL)
3494 return -EINVAL;
3495
3496 spin_lock_irqsave(&dispc.irq_lock, flags);
3497
3498 /* check for duplicate entry */
3499 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3500 isr_data = &dispc.registered_isr[i];
3501 if (isr_data->isr == isr && isr_data->arg == arg &&
3502 isr_data->mask == mask) {
3503 ret = -EINVAL;
3504 goto err;
3505 }
3506 }
3507
3508 isr_data = NULL;
3509 ret = -EBUSY;
3510
3511 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3512 isr_data = &dispc.registered_isr[i];
3513
3514 if (isr_data->isr != NULL)
3515 continue;
3516
3517 isr_data->isr = isr;
3518 isr_data->arg = arg;
3519 isr_data->mask = mask;
3520 ret = 0;
3521
3522 break;
3523 }
3524
3525 if (ret)
3526 goto err;
3527
3528 _omap_dispc_set_irqs();
3529
3530 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3531
3532 return 0;
3533 err:
3534 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3535
3536 return ret;
3537 }
3538 EXPORT_SYMBOL(omap_dispc_register_isr);
3539
3540 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3541 {
3542 int i;
3543 unsigned long flags;
3544 int ret = -EINVAL;
3545 struct omap_dispc_isr_data *isr_data;
3546
3547 spin_lock_irqsave(&dispc.irq_lock, flags);
3548
3549 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3550 isr_data = &dispc.registered_isr[i];
3551 if (isr_data->isr != isr || isr_data->arg != arg ||
3552 isr_data->mask != mask)
3553 continue;
3554
3555 /* found the correct isr */
3556
3557 isr_data->isr = NULL;
3558 isr_data->arg = NULL;
3559 isr_data->mask = 0;
3560
3561 ret = 0;
3562 break;
3563 }
3564
3565 if (ret == 0)
3566 _omap_dispc_set_irqs();
3567
3568 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3569
3570 return ret;
3571 }
3572 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3573
3574 static void print_irq_status(u32 status)
3575 {
3576 if ((status & dispc.irq_error_mask) == 0)
3577 return;
3578
3579 #define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
3580
3581 pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
3582 status,
3583 PIS(OCP_ERR),
3584 PIS(GFX_FIFO_UNDERFLOW),
3585 PIS(VID1_FIFO_UNDERFLOW),
3586 PIS(VID2_FIFO_UNDERFLOW),
3587 dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
3588 PIS(SYNC_LOST),
3589 PIS(SYNC_LOST_DIGIT),
3590 dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
3591 dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
3592 #undef PIS
3593 }
3594
3595 /* Called from dss.c. Note that we don't touch clocks here,
3596 * but we presume they are on because we got an IRQ. However,
3597 * an irq handler may turn the clocks off, so we may not have
3598 * clock later in the function. */
3599 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3600 {
3601 int i;
3602 u32 irqstatus, irqenable;
3603 u32 handledirqs = 0;
3604 u32 unhandled_errors;
3605 struct omap_dispc_isr_data *isr_data;
3606 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3607
3608 spin_lock(&dispc.irq_lock);
3609
3610 irqstatus = dispc_read_irqstatus();
3611 irqenable = dispc_read_irqenable();
3612
3613 /* IRQ is not for us */
3614 if (!(irqstatus & irqenable)) {
3615 spin_unlock(&dispc.irq_lock);
3616 return IRQ_NONE;
3617 }
3618
3619 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3620 spin_lock(&dispc.irq_stats_lock);
3621 dispc.irq_stats.irq_count++;
3622 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3623 spin_unlock(&dispc.irq_stats_lock);
3624 #endif
3625
3626 print_irq_status(irqstatus);
3627
3628 /* Ack the interrupt. Do it here before clocks are possibly turned
3629 * off */
3630 dispc_clear_irqstatus(irqstatus);
3631 /* flush posted write */
3632 dispc_read_irqstatus();
3633
3634 /* make a copy and unlock, so that isrs can unregister
3635 * themselves */
3636 memcpy(registered_isr, dispc.registered_isr,
3637 sizeof(registered_isr));
3638
3639 spin_unlock(&dispc.irq_lock);
3640
3641 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3642 isr_data = &registered_isr[i];
3643
3644 if (!isr_data->isr)
3645 continue;
3646
3647 if (isr_data->mask & irqstatus) {
3648 isr_data->isr(isr_data->arg, irqstatus);
3649 handledirqs |= isr_data->mask;
3650 }
3651 }
3652
3653 spin_lock(&dispc.irq_lock);
3654
3655 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3656
3657 if (unhandled_errors) {
3658 dispc.error_irqs |= unhandled_errors;
3659
3660 dispc.irq_error_mask &= ~unhandled_errors;
3661 _omap_dispc_set_irqs();
3662
3663 schedule_work(&dispc.error_work);
3664 }
3665
3666 spin_unlock(&dispc.irq_lock);
3667
3668 return IRQ_HANDLED;
3669 }
3670
3671 static void dispc_error_worker(struct work_struct *work)
3672 {
3673 int i;
3674 u32 errors;
3675 unsigned long flags;
3676 static const unsigned fifo_underflow_bits[] = {
3677 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3678 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3679 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3680 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3681 };
3682
3683 spin_lock_irqsave(&dispc.irq_lock, flags);
3684 errors = dispc.error_irqs;
3685 dispc.error_irqs = 0;
3686 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3687
3688 dispc_runtime_get();
3689
3690 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3691 struct omap_overlay *ovl;
3692 unsigned bit;
3693
3694 ovl = omap_dss_get_overlay(i);
3695 bit = fifo_underflow_bits[i];
3696
3697 if (bit & errors) {
3698 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3699 ovl->name);
3700 dispc_ovl_enable(ovl->id, false);
3701 dispc_mgr_go(ovl->manager->id);
3702 msleep(50);
3703 }
3704 }
3705
3706 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3707 struct omap_overlay_manager *mgr;
3708 unsigned bit;
3709
3710 mgr = omap_dss_get_overlay_manager(i);
3711 bit = mgr_desc[i].sync_lost_irq;
3712
3713 if (bit & errors) {
3714 int j;
3715
3716 DSSERR("SYNC_LOST on channel %s, restarting the output "
3717 "with video overlays disabled\n",
3718 mgr->name);
3719
3720 dss_mgr_disable(mgr);
3721
3722 for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
3723 struct omap_overlay *ovl;
3724 ovl = omap_dss_get_overlay(j);
3725
3726 if (ovl->id != OMAP_DSS_GFX &&
3727 ovl->manager == mgr)
3728 ovl->disable(ovl);
3729 }
3730
3731 dss_mgr_enable(mgr);
3732 }
3733 }
3734
3735 if (errors & DISPC_IRQ_OCP_ERR) {
3736 DSSERR("OCP_ERR\n");
3737 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3738 struct omap_overlay_manager *mgr;
3739
3740 mgr = omap_dss_get_overlay_manager(i);
3741 dss_mgr_disable(mgr);
3742 }
3743 }
3744
3745 spin_lock_irqsave(&dispc.irq_lock, flags);
3746 dispc.irq_error_mask |= errors;
3747 _omap_dispc_set_irqs();
3748 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3749
3750 dispc_runtime_put();
3751 }
3752
3753 static void _omap_dispc_initialize_irq(void)
3754 {
3755 unsigned long flags;
3756
3757 spin_lock_irqsave(&dispc.irq_lock, flags);
3758
3759 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3760
3761 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3762 if (dss_has_feature(FEAT_MGR_LCD2))
3763 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3764 if (dss_has_feature(FEAT_MGR_LCD3))
3765 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
3766 if (dss_feat_get_num_ovls() > 3)
3767 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3768
3769 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3770 * so clear it */
3771 dispc_clear_irqstatus(dispc_read_irqstatus());
3772
3773 _omap_dispc_set_irqs();
3774
3775 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3776 }
3777
3778 void dispc_enable_sidle(void)
3779 {
3780 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3781 }
3782
3783 void dispc_disable_sidle(void)
3784 {
3785 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3786 }
3787
3788 static void _omap_dispc_initial_config(void)
3789 {
3790 u32 l;
3791
3792 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3793 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3794 l = dispc_read_reg(DISPC_DIVISOR);
3795 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3796 l = FLD_MOD(l, 1, 0, 0);
3797 l = FLD_MOD(l, 1, 23, 16);
3798 dispc_write_reg(DISPC_DIVISOR, l);
3799 }
3800
3801 /* FUNCGATED */
3802 if (dss_has_feature(FEAT_FUNCGATED))
3803 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3804
3805 dispc_setup_color_conv_coef();
3806
3807 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3808
3809 dispc_init_fifos();
3810
3811 dispc_configure_burst_sizes();
3812
3813 dispc_ovl_enable_zorder_planes();
3814 }
3815
3816 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3817 .sw_start = 5,
3818 .fp_start = 15,
3819 .bp_start = 27,
3820 .sw_max = 64,
3821 .vp_max = 255,
3822 .hp_max = 256,
3823 .mgr_width_start = 10,
3824 .mgr_height_start = 26,
3825 .mgr_width_max = 2048,
3826 .mgr_height_max = 2048,
3827 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3828 .calc_core_clk = calc_core_clk_24xx,
3829 .num_fifos = 3,
3830 .no_framedone_tv = true,
3831 };
3832
3833 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3834 .sw_start = 5,
3835 .fp_start = 15,
3836 .bp_start = 27,
3837 .sw_max = 64,
3838 .vp_max = 255,
3839 .hp_max = 256,
3840 .mgr_width_start = 10,
3841 .mgr_height_start = 26,
3842 .mgr_width_max = 2048,
3843 .mgr_height_max = 2048,
3844 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3845 .calc_core_clk = calc_core_clk_34xx,
3846 .num_fifos = 3,
3847 .no_framedone_tv = true,
3848 };
3849
3850 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3851 .sw_start = 7,
3852 .fp_start = 19,
3853 .bp_start = 31,
3854 .sw_max = 256,
3855 .vp_max = 4095,
3856 .hp_max = 4096,
3857 .mgr_width_start = 10,
3858 .mgr_height_start = 26,
3859 .mgr_width_max = 2048,
3860 .mgr_height_max = 2048,
3861 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3862 .calc_core_clk = calc_core_clk_34xx,
3863 .num_fifos = 3,
3864 .no_framedone_tv = true,
3865 };
3866
3867 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3868 .sw_start = 7,
3869 .fp_start = 19,
3870 .bp_start = 31,
3871 .sw_max = 256,
3872 .vp_max = 4095,
3873 .hp_max = 4096,
3874 .mgr_width_start = 10,
3875 .mgr_height_start = 26,
3876 .mgr_width_max = 2048,
3877 .mgr_height_max = 2048,
3878 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3879 .calc_core_clk = calc_core_clk_44xx,
3880 .num_fifos = 5,
3881 .gfx_fifo_workaround = true,
3882 };
3883
3884 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3885 .sw_start = 7,
3886 .fp_start = 19,
3887 .bp_start = 31,
3888 .sw_max = 256,
3889 .vp_max = 4095,
3890 .hp_max = 4096,
3891 .mgr_width_start = 11,
3892 .mgr_height_start = 27,
3893 .mgr_width_max = 4096,
3894 .mgr_height_max = 4096,
3895 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3896 .calc_core_clk = calc_core_clk_44xx,
3897 .num_fifos = 5,
3898 .gfx_fifo_workaround = true,
3899 };
3900
3901 static int __init dispc_init_features(struct platform_device *pdev)
3902 {
3903 const struct dispc_features *src;
3904 struct dispc_features *dst;
3905
3906 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3907 if (!dst) {
3908 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3909 return -ENOMEM;
3910 }
3911
3912 switch (omapdss_get_version()) {
3913 case OMAPDSS_VER_OMAP24xx:
3914 src = &omap24xx_dispc_feats;
3915 break;
3916
3917 case OMAPDSS_VER_OMAP34xx_ES1:
3918 src = &omap34xx_rev1_0_dispc_feats;
3919 break;
3920
3921 case OMAPDSS_VER_OMAP34xx_ES3:
3922 case OMAPDSS_VER_OMAP3630:
3923 case OMAPDSS_VER_AM35xx:
3924 src = &omap34xx_rev3_0_dispc_feats;
3925 break;
3926
3927 case OMAPDSS_VER_OMAP4430_ES1:
3928 case OMAPDSS_VER_OMAP4430_ES2:
3929 case OMAPDSS_VER_OMAP4:
3930 src = &omap44xx_dispc_feats;
3931 break;
3932
3933 case OMAPDSS_VER_OMAP5:
3934 src = &omap54xx_dispc_feats;
3935 break;
3936
3937 default:
3938 return -ENODEV;
3939 }
3940
3941 memcpy(dst, src, sizeof(*dst));
3942 dispc.feat = dst;
3943
3944 return 0;
3945 }
3946
3947 /* DISPC HW IP initialisation */
3948 static int __init omap_dispchw_probe(struct platform_device *pdev)
3949 {
3950 u32 rev;
3951 int r = 0;
3952 struct resource *dispc_mem;
3953 struct clk *clk;
3954
3955 dispc.pdev = pdev;
3956
3957 r = dispc_init_features(dispc.pdev);
3958 if (r)
3959 return r;
3960
3961 spin_lock_init(&dispc.irq_lock);
3962
3963 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3964 spin_lock_init(&dispc.irq_stats_lock);
3965 dispc.irq_stats.last_reset = jiffies;
3966 #endif
3967
3968 INIT_WORK(&dispc.error_work, dispc_error_worker);
3969
3970 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3971 if (!dispc_mem) {
3972 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3973 return -EINVAL;
3974 }
3975
3976 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3977 resource_size(dispc_mem));
3978 if (!dispc.base) {
3979 DSSERR("can't ioremap DISPC\n");
3980 return -ENOMEM;
3981 }
3982
3983 dispc.irq = platform_get_irq(dispc.pdev, 0);
3984 if (dispc.irq < 0) {
3985 DSSERR("platform_get_irq failed\n");
3986 return -ENODEV;
3987 }
3988
3989 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3990 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
3991 if (r < 0) {
3992 DSSERR("request_irq failed\n");
3993 return r;
3994 }
3995
3996 clk = clk_get(&pdev->dev, "fck");
3997 if (IS_ERR(clk)) {
3998 DSSERR("can't get fck\n");
3999 r = PTR_ERR(clk);
4000 return r;
4001 }
4002
4003 dispc.dss_clk = clk;
4004
4005 pm_runtime_enable(&pdev->dev);
4006
4007 r = dispc_runtime_get();
4008 if (r)
4009 goto err_runtime_get;
4010
4011 _omap_dispc_initial_config();
4012
4013 _omap_dispc_initialize_irq();
4014
4015 rev = dispc_read_reg(DISPC_REVISION);
4016 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4017 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4018
4019 dispc_runtime_put();
4020
4021 dss_debugfs_create_file("dispc", dispc_dump_regs);
4022
4023 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4024 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4025 #endif
4026 return 0;
4027
4028 err_runtime_get:
4029 pm_runtime_disable(&pdev->dev);
4030 clk_put(dispc.dss_clk);
4031 return r;
4032 }
4033
4034 static int __exit omap_dispchw_remove(struct platform_device *pdev)
4035 {
4036 pm_runtime_disable(&pdev->dev);
4037
4038 clk_put(dispc.dss_clk);
4039
4040 return 0;
4041 }
4042
4043 static int dispc_runtime_suspend(struct device *dev)
4044 {
4045 dispc_save_context();
4046
4047 return 0;
4048 }
4049
4050 static int dispc_runtime_resume(struct device *dev)
4051 {
4052 dispc_restore_context();
4053
4054 return 0;
4055 }
4056
4057 static const struct dev_pm_ops dispc_pm_ops = {
4058 .runtime_suspend = dispc_runtime_suspend,
4059 .runtime_resume = dispc_runtime_resume,
4060 };
4061
4062 static struct platform_driver omap_dispchw_driver = {
4063 .remove = __exit_p(omap_dispchw_remove),
4064 .driver = {
4065 .name = "omapdss_dispc",
4066 .owner = THIS_MODULE,
4067 .pm = &dispc_pm_ops,
4068 },
4069 };
4070
4071 int __init dispc_init_platform_driver(void)
4072 {
4073 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
4074 }
4075
4076 void __exit dispc_uninit_platform_driver(void)
4077 {
4078 platform_driver_unregister(&omap_dispchw_driver);
4079 }
kernel source for telekom puls (alcatel/mediatek)