drivers/video/omap2/dss/dispc-compat.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #define DSS_SUBSYS_NAME "APPLY"
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/delay.h>
  26
  27 #include <video/omapdss.h>
  28
  29 #include "dss.h"
  30 #include "dss_features.h"
  31 #include "dispc-compat.h"
  32
  33 static void dispc_mgr_disable_isr(void *data, u32 mask)
  34 {
  35         struct completion *compl = data;
  36         complete(compl);
  37 }
  38
  39 static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
  40 {
  41         dispc_mgr_enable(channel, true);
  42 }
  43
  44 static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
  45 {
  46         DECLARE_COMPLETION_ONSTACK(framedone_compl);
  47         int r;
  48         u32 irq;
  49
  50         if (dispc_mgr_is_enabled(channel) == false)
  51                 return;
  52
  53         /*
  54          * When we disable LCD output, we need to wait for FRAMEDONE to know
  55          * that DISPC has finished with the LCD output.
  56          */
  57
  58         irq = dispc_mgr_get_framedone_irq(channel);
  59
  60         r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
  61                         irq);
  62         if (r)
  63                 DSSERR("failed to register FRAMEDONE isr\n");
  64
  65         dispc_mgr_enable(channel, false);
  66
  67         /* if we couldn't register for framedone, just sleep and exit */
  68         if (r) {
  69                 msleep(100);
  70                 return;
  71         }
  72
  73         if (!wait_for_completion_timeout(&framedone_compl,
  74                                 msecs_to_jiffies(100)))
  75                 DSSERR("timeout waiting for FRAME DONE\n");
  76
  77         r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
  78                         irq);
  79         if (r)
  80                 DSSERR("failed to unregister FRAMEDONE isr\n");
  81 }
  82
  83 static void dispc_digit_out_enable_isr(void *data, u32 mask)
  84 {
  85         struct completion *compl = data;
  86
  87         /* ignore any sync lost interrupts */
  88         if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
  89                 complete(compl);
  90 }
  91
  92 static void dispc_mgr_enable_digit_out(void)
  93 {
  94         DECLARE_COMPLETION_ONSTACK(vsync_compl);
  95         int r;
  96         u32 irq_mask;
  97
  98         if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
  99                 return;
 100
 101         /*
 102          * Digit output produces some sync lost interrupts during the first
 103          * frame when enabling. Those need to be ignored, so we register for the
 104          * sync lost irq to prevent the error handler from triggering.
 105          */
 106
 107         irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
 108                 dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
 109
 110         r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
 111                         irq_mask);
 112         if (r) {
 113                 DSSERR("failed to register %x isr\n", irq_mask);
 114                 return;
 115         }
 116
 117         dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
 118
 119         /* wait for the first evsync */
 120         if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
 121                 DSSERR("timeout waiting for digit out to start\n");
 122
 123         r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
 124                         irq_mask);
 125         if (r)
 126                 DSSERR("failed to unregister %x isr\n", irq_mask);
 127 }
 128
 129 static void dispc_mgr_disable_digit_out(void)
 130 {
 131         DECLARE_COMPLETION_ONSTACK(framedone_compl);
 132         int r, i;
 133         u32 irq_mask;
 134         int num_irqs;
 135
 136         if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
 137                 return;
 138
 139         /*
 140          * When we disable the digit output, we need to wait for FRAMEDONE to
 141          * know that DISPC has finished with the output.
 142          */
 143
 144         irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
 145         num_irqs = 1;
 146
 147         if (!irq_mask) {
 148                 /*
 149                  * omap 2/3 don't have framedone irq for TV, so we need to use
 150                  * vsyncs for this.
 151                  */
 152
 153                 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
 154                 /*
 155                  * We need to wait for both even and odd vsyncs. Note that this
 156                  * is not totally reliable, as we could get a vsync interrupt
 157                  * before we disable the output, which leads to timeout in the
 158                  * wait_for_completion.
 159                  */
 160                 num_irqs = 2;
 161         }
 162
 163         r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
 164                         irq_mask);
 165         if (r)
 166                 DSSERR("failed to register %x isr\n", irq_mask);
 167
 168         dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
 169
 170         /* if we couldn't register the irq, just sleep and exit */
 171         if (r) {
 172                 msleep(100);
 173                 return;
 174         }
 175
 176         for (i = 0; i < num_irqs; ++i) {
 177                 if (!wait_for_completion_timeout(&framedone_compl,
 178                                         msecs_to_jiffies(100)))
 179                         DSSERR("timeout waiting for digit out to stop\n");
 180         }
 181
 182         r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
 183                         irq_mask);
 184         if (r)
 185                 DSSERR("failed to unregister %x isr\n", irq_mask);
 186 }
 187
 188 void dispc_mgr_enable_sync(enum omap_channel channel)
 189 {
 190         if (dss_mgr_is_lcd(channel))
 191                 dispc_mgr_enable_lcd_out(channel);
 192         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
 193                 dispc_mgr_enable_digit_out();
 194         else
 195                 WARN_ON(1);
 196 }
 197
 198 void dispc_mgr_disable_sync(enum omap_channel channel)
 199 {
 200         if (dss_mgr_is_lcd(channel))
 201                 dispc_mgr_disable_lcd_out(channel);
 202         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
 203                 dispc_mgr_disable_digit_out();
 204         else
 205                 WARN_ON(1);
 206 }
 207
 208 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 209                 unsigned long timeout)
 210 {
 211         void dispc_irq_wait_handler(void *data, u32 mask)
 212         {
 213                 complete((struct completion *)data);
 214         }
 215
 216         int r;
 217         DECLARE_COMPLETION_ONSTACK(completion);
 218
 219         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
 220                         irqmask);
 221
 222         if (r)
 223                 return r;
 224
 225         timeout = wait_for_completion_interruptible_timeout(&completion,
 226                         timeout);
 227
 228         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
 229
 230         if (timeout == 0)
 231                 return -ETIMEDOUT;
 232
 233         if (timeout == -ERESTARTSYS)
 234                 return -ERESTARTSYS;
 235
 236         return 0;
 237 }