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[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap / dispc.c
1 /*
2 * OMAP2 display controller support
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/kernel.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mm.h>
24 #include <linux/vmalloc.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27
28 #include <mach/sram.h>
29 #include <mach/omapfb.h>
30 #include <mach/board.h>
31
32 #include "dispc.h"
33
34 #define MODULE_NAME "dispc"
35
36 #define DSS_BASE 0x48050000
37 #define DSS_SYSCONFIG 0x0010
38
39 #define DISPC_BASE 0x48050400
40
41 /* DISPC common */
42 #define DISPC_REVISION 0x0000
43 #define DISPC_SYSCONFIG 0x0010
44 #define DISPC_SYSSTATUS 0x0014
45 #define DISPC_IRQSTATUS 0x0018
46 #define DISPC_IRQENABLE 0x001C
47 #define DISPC_CONTROL 0x0040
48 #define DISPC_CONFIG 0x0044
49 #define DISPC_CAPABLE 0x0048
50 #define DISPC_DEFAULT_COLOR0 0x004C
51 #define DISPC_DEFAULT_COLOR1 0x0050
52 #define DISPC_TRANS_COLOR0 0x0054
53 #define DISPC_TRANS_COLOR1 0x0058
54 #define DISPC_LINE_STATUS 0x005C
55 #define DISPC_LINE_NUMBER 0x0060
56 #define DISPC_TIMING_H 0x0064
57 #define DISPC_TIMING_V 0x0068
58 #define DISPC_POL_FREQ 0x006C
59 #define DISPC_DIVISOR 0x0070
60 #define DISPC_SIZE_DIG 0x0078
61 #define DISPC_SIZE_LCD 0x007C
62
63 #define DISPC_DATA_CYCLE1 0x01D4
64 #define DISPC_DATA_CYCLE2 0x01D8
65 #define DISPC_DATA_CYCLE3 0x01DC
66
67 /* DISPC GFX plane */
68 #define DISPC_GFX_BA0 0x0080
69 #define DISPC_GFX_BA1 0x0084
70 #define DISPC_GFX_POSITION 0x0088
71 #define DISPC_GFX_SIZE 0x008C
72 #define DISPC_GFX_ATTRIBUTES 0x00A0
73 #define DISPC_GFX_FIFO_THRESHOLD 0x00A4
74 #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8
75 #define DISPC_GFX_ROW_INC 0x00AC
76 #define DISPC_GFX_PIXEL_INC 0x00B0
77 #define DISPC_GFX_WINDOW_SKIP 0x00B4
78 #define DISPC_GFX_TABLE_BA 0x00B8
79
80 /* DISPC Video plane 1/2 */
81 #define DISPC_VID1_BASE 0x00BC
82 #define DISPC_VID2_BASE 0x014C
83
84 /* Offsets into DISPC_VID1/2_BASE */
85 #define DISPC_VID_BA0 0x0000
86 #define DISPC_VID_BA1 0x0004
87 #define DISPC_VID_POSITION 0x0008
88 #define DISPC_VID_SIZE 0x000C
89 #define DISPC_VID_ATTRIBUTES 0x0010
90 #define DISPC_VID_FIFO_THRESHOLD 0x0014
91 #define DISPC_VID_FIFO_SIZE_STATUS 0x0018
92 #define DISPC_VID_ROW_INC 0x001C
93 #define DISPC_VID_PIXEL_INC 0x0020
94 #define DISPC_VID_FIR 0x0024
95 #define DISPC_VID_PICTURE_SIZE 0x0028
96 #define DISPC_VID_ACCU0 0x002C
97 #define DISPC_VID_ACCU1 0x0030
98
99 /* 8 elements in 8 byte increments */
100 #define DISPC_VID_FIR_COEF_H0 0x0034
101 /* 8 elements in 8 byte increments */
102 #define DISPC_VID_FIR_COEF_HV0 0x0038
103 /* 5 elements in 4 byte increments */
104 #define DISPC_VID_CONV_COEF0 0x0074
105
106 #define DISPC_IRQ_FRAMEMASK 0x0001
107 #define DISPC_IRQ_VSYNC 0x0002
108 #define DISPC_IRQ_EVSYNC_EVEN 0x0004
109 #define DISPC_IRQ_EVSYNC_ODD 0x0008
110 #define DISPC_IRQ_ACBIAS_COUNT_STAT 0x0010
111 #define DISPC_IRQ_PROG_LINE_NUM 0x0020
112 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW 0x0040
113 #define DISPC_IRQ_GFX_END_WIN 0x0080
114 #define DISPC_IRQ_PAL_GAMMA_MASK 0x0100
115 #define DISPC_IRQ_OCP_ERR 0x0200
116 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW 0x0400
117 #define DISPC_IRQ_VID1_END_WIN 0x0800
118 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW 0x1000
119 #define DISPC_IRQ_VID2_END_WIN 0x2000
120 #define DISPC_IRQ_SYNC_LOST 0x4000
121
122 #define DISPC_IRQ_MASK_ALL 0x7fff
123
124 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
125 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
126 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
127 DISPC_IRQ_SYNC_LOST)
128
129 #define RFBI_CONTROL 0x48050040
130
131 #define MAX_PALETTE_SIZE (256 * 16)
132
133 #define FLD_MASK(pos, len) (((1 << len) - 1) << pos)
134
135 #define MOD_REG_FLD(reg, mask, val) \
136 dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
137
138 #define OMAP2_SRAM_START 0x40200000
139 /* Maximum size, in reality this is smaller if SRAM is partially locked. */
140 #define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
141
142 /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */
143 #define DISPC_MEMTYPE_NUM 2
144
145 #define RESMAP_SIZE(_page_cnt) \
146 ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
147 #define RESMAP_PTR(_res_map, _page_nr) \
148 (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
149 #define RESMAP_MASK(_page_nr) \
150 (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
151
152 struct resmap {
153 unsigned long start;
154 unsigned page_cnt;
155 unsigned long *map;
156 };
157
158 static struct {
159 u32 base;
160
161 struct omapfb_mem_desc mem_desc;
162 struct resmap *res_map[DISPC_MEMTYPE_NUM];
163 atomic_t map_count[OMAPFB_PLANE_NUM];
164
165 dma_addr_t palette_paddr;
166 void *palette_vaddr;
167
168 int ext_mode;
169
170 unsigned long enabled_irqs;
171 void (*irq_callback)(void *);
172 void *irq_callback_data;
173 struct completion frame_done;
174
175 int fir_hinc[OMAPFB_PLANE_NUM];
176 int fir_vinc[OMAPFB_PLANE_NUM];
177
178 struct clk *dss_ick, *dss1_fck;
179 struct clk *dss_54m_fck;
180
181 enum omapfb_update_mode update_mode;
182 struct omapfb_device *fbdev;
183
184 struct omapfb_color_key color_key;
185 } dispc;
186
187 static void enable_lcd_clocks(int enable);
188
189 static void inline dispc_write_reg(int idx, u32 val)
190 {
191 __raw_writel(val, dispc.base + idx);
192 }
193
194 static u32 inline dispc_read_reg(int idx)
195 {
196 u32 l = __raw_readl(dispc.base + idx);
197 return l;
198 }
199
200 /* Select RFBI or bypass mode */
201 static void enable_rfbi_mode(int enable)
202 {
203 u32 l;
204
205 l = dispc_read_reg(DISPC_CONTROL);
206 /* Enable RFBI, GPIO0/1 */
207 l &= ~((1 << 11) | (1 << 15) | (1 << 16));
208 l |= enable ? (1 << 11) : 0;
209 /* RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11 */
210 l |= 1 << 15;
211 l |= enable ? 0 : (1 << 16);
212 dispc_write_reg(DISPC_CONTROL, l);
213
214 /* Set bypass mode in RFBI module */
215 l = __raw_readl(io_p2v(RFBI_CONTROL));
216 l |= enable ? 0 : (1 << 1);
217 __raw_writel(l, io_p2v(RFBI_CONTROL));
218 }
219
220 static void set_lcd_data_lines(int data_lines)
221 {
222 u32 l;
223 int code = 0;
224
225 switch (data_lines) {
226 case 12:
227 code = 0;
228 break;
229 case 16:
230 code = 1;
231 break;
232 case 18:
233 code = 2;
234 break;
235 case 24:
236 code = 3;
237 break;
238 default:
239 BUG();
240 }
241
242 l = dispc_read_reg(DISPC_CONTROL);
243 l &= ~(0x03 << 8);
244 l |= code << 8;
245 dispc_write_reg(DISPC_CONTROL, l);
246 }
247
248 static void set_load_mode(int mode)
249 {
250 BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
251 DISPC_LOAD_CLUT_ONCE_FRAME));
252 MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
253 }
254
255 void omap_dispc_set_lcd_size(int x, int y)
256 {
257 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
258 enable_lcd_clocks(1);
259 MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
260 ((y - 1) << 16) | (x - 1));
261 enable_lcd_clocks(0);
262 }
263 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
264
265 void omap_dispc_set_digit_size(int x, int y)
266 {
267 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
268 enable_lcd_clocks(1);
269 MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
270 ((y - 1) << 16) | (x - 1));
271 enable_lcd_clocks(0);
272 }
273 EXPORT_SYMBOL(omap_dispc_set_digit_size);
274
275 static void setup_plane_fifo(int plane, int ext_mode)
276 {
277 const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
278 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
279 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
280 const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
281 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
282 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
283 int low, high;
284 u32 l;
285
286 BUG_ON(plane > 2);
287
288 l = dispc_read_reg(fsz_reg[plane]);
289 l &= FLD_MASK(0, 9);
290 if (ext_mode) {
291 low = l * 3 / 4;
292 high = l;
293 } else {
294 low = l / 4;
295 high = l * 3 / 4;
296 }
297 MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
298 (high << 16) | low);
299 }
300
301 void omap_dispc_enable_lcd_out(int enable)
302 {
303 enable_lcd_clocks(1);
304 MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
305 enable_lcd_clocks(0);
306 }
307 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
308
309 void omap_dispc_enable_digit_out(int enable)
310 {
311 enable_lcd_clocks(1);
312 MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
313 enable_lcd_clocks(0);
314 }
315 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
316
317 static inline int _setup_plane(int plane, int channel_out,
318 u32 paddr, int screen_width,
319 int pos_x, int pos_y, int width, int height,
320 int color_mode)
321 {
322 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
323 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
324 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
325 const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
326 DISPC_VID2_BASE + DISPC_VID_BA0 };
327 const u32 ps_reg[] = { DISPC_GFX_POSITION,
328 DISPC_VID1_BASE + DISPC_VID_POSITION,
329 DISPC_VID2_BASE + DISPC_VID_POSITION };
330 const u32 sz_reg[] = { DISPC_GFX_SIZE,
331 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
332 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
333 const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
334 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
335 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
336 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
337 DISPC_VID2_BASE + DISPC_VID_SIZE };
338
339 int chout_shift, burst_shift;
340 int chout_val;
341 int color_code;
342 int bpp;
343 int cconv_en;
344 int set_vsize;
345 u32 l;
346
347 #ifdef VERBOSE
348 dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d"
349 " pos_x %d pos_y %d width %d height %d color_mode %d\n",
350 plane, channel_out, paddr, screen_width, pos_x, pos_y,
351 width, height, color_mode);
352 #endif
353
354 set_vsize = 0;
355 switch (plane) {
356 case OMAPFB_PLANE_GFX:
357 burst_shift = 6;
358 chout_shift = 8;
359 break;
360 case OMAPFB_PLANE_VID1:
361 case OMAPFB_PLANE_VID2:
362 burst_shift = 14;
363 chout_shift = 16;
364 set_vsize = 1;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 switch (channel_out) {
371 case OMAPFB_CHANNEL_OUT_LCD:
372 chout_val = 0;
373 break;
374 case OMAPFB_CHANNEL_OUT_DIGIT:
375 chout_val = 1;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 cconv_en = 0;
382 switch (color_mode) {
383 case OMAPFB_COLOR_RGB565:
384 color_code = DISPC_RGB_16_BPP;
385 bpp = 16;
386 break;
387 case OMAPFB_COLOR_YUV422:
388 if (plane == 0)
389 return -EINVAL;
390 color_code = DISPC_UYVY_422;
391 cconv_en = 1;
392 bpp = 16;
393 break;
394 case OMAPFB_COLOR_YUY422:
395 if (plane == 0)
396 return -EINVAL;
397 color_code = DISPC_YUV2_422;
398 cconv_en = 1;
399 bpp = 16;
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 l = dispc_read_reg(at_reg[plane]);
406
407 l &= ~(0x0f << 1);
408 l |= color_code << 1;
409 l &= ~(1 << 9);
410 l |= cconv_en << 9;
411
412 l &= ~(0x03 << burst_shift);
413 l |= DISPC_BURST_8x32 << burst_shift;
414
415 l &= ~(1 << chout_shift);
416 l |= chout_val << chout_shift;
417
418 dispc_write_reg(at_reg[plane], l);
419
420 dispc_write_reg(ba_reg[plane], paddr);
421 MOD_REG_FLD(ps_reg[plane],
422 FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
423
424 MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
425 ((height - 1) << 16) | (width - 1));
426
427 if (set_vsize) {
428 /* Set video size if set_scale hasn't set it */
429 if (!dispc.fir_vinc[plane])
430 MOD_REG_FLD(vs_reg[plane],
431 FLD_MASK(16, 11), (height - 1) << 16);
432 if (!dispc.fir_hinc[plane])
433 MOD_REG_FLD(vs_reg[plane],
434 FLD_MASK(0, 11), width - 1);
435 }
436
437 dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
438
439 return height * screen_width * bpp / 8;
440 }
441
442 static int omap_dispc_setup_plane(int plane, int channel_out,
443 unsigned long offset,
444 int screen_width,
445 int pos_x, int pos_y, int width, int height,
446 int color_mode)
447 {
448 u32 paddr;
449 int r;
450
451 if ((unsigned)plane > dispc.mem_desc.region_cnt)
452 return -EINVAL;
453 paddr = dispc.mem_desc.region[plane].paddr + offset;
454 enable_lcd_clocks(1);
455 r = _setup_plane(plane, channel_out, paddr,
456 screen_width,
457 pos_x, pos_y, width, height, color_mode);
458 enable_lcd_clocks(0);
459 return r;
460 }
461
462 static void write_firh_reg(int plane, int reg, u32 value)
463 {
464 u32 base;
465
466 if (plane == 1)
467 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
468 else
469 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
470 dispc_write_reg(base + reg * 8, value);
471 }
472
473 static void write_firhv_reg(int plane, int reg, u32 value)
474 {
475 u32 base;
476
477 if (plane == 1)
478 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
479 else
480 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
481 dispc_write_reg(base + reg * 8, value);
482 }
483
484 static void set_upsampling_coef_table(int plane)
485 {
486 const u32 coef[][2] = {
487 { 0x00800000, 0x00800000 },
488 { 0x0D7CF800, 0x037B02FF },
489 { 0x1E70F5FF, 0x0C6F05FE },
490 { 0x335FF5FE, 0x205907FB },
491 { 0xF74949F7, 0x00404000 },
492 { 0xF55F33FB, 0x075920FE },
493 { 0xF5701EFE, 0x056F0CFF },
494 { 0xF87C0DFF, 0x027B0300 },
495 };
496 int i;
497
498 for (i = 0; i < 8; i++) {
499 write_firh_reg(plane, i, coef[i][0]);
500 write_firhv_reg(plane, i, coef[i][1]);
501 }
502 }
503
504 static int omap_dispc_set_scale(int plane,
505 int orig_width, int orig_height,
506 int out_width, int out_height)
507 {
508 const u32 at_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
509 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
510 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
511 DISPC_VID2_BASE + DISPC_VID_SIZE };
512 const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
513 DISPC_VID2_BASE + DISPC_VID_FIR };
514
515 u32 l;
516 int fir_hinc;
517 int fir_vinc;
518
519 if ((unsigned)plane > OMAPFB_PLANE_NUM)
520 return -ENODEV;
521
522 if (plane == OMAPFB_PLANE_GFX &&
523 (out_width != orig_width || out_height != orig_height))
524 return -EINVAL;
525
526 enable_lcd_clocks(1);
527 if (orig_width < out_width) {
528 /*
529 * Upsampling.
530 * Currently you can only scale both dimensions in one way.
531 */
532 if (orig_height > out_height ||
533 orig_width * 8 < out_width ||
534 orig_height * 8 < out_height) {
535 enable_lcd_clocks(0);
536 return -EINVAL;
537 }
538 set_upsampling_coef_table(plane);
539 } else if (orig_width > out_width) {
540 /* Downsampling not yet supported
541 */
542
543 enable_lcd_clocks(0);
544 return -EINVAL;
545 }
546 if (!orig_width || orig_width == out_width)
547 fir_hinc = 0;
548 else
549 fir_hinc = 1024 * orig_width / out_width;
550 if (!orig_height || orig_height == out_height)
551 fir_vinc = 0;
552 else
553 fir_vinc = 1024 * orig_height / out_height;
554 dispc.fir_hinc[plane] = fir_hinc;
555 dispc.fir_vinc[plane] = fir_vinc;
556
557 MOD_REG_FLD(fir_reg[plane],
558 FLD_MASK(16, 12) | FLD_MASK(0, 12),
559 ((fir_vinc & 4095) << 16) |
560 (fir_hinc & 4095));
561
562 dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
563 "orig_height %d fir_hinc %d fir_vinc %d\n",
564 out_width, out_height, orig_width, orig_height,
565 fir_hinc, fir_vinc);
566
567 MOD_REG_FLD(vs_reg[plane],
568 FLD_MASK(16, 11) | FLD_MASK(0, 11),
569 ((out_height - 1) << 16) | (out_width - 1));
570
571 l = dispc_read_reg(at_reg[plane]);
572 l &= ~(0x03 << 5);
573 l |= fir_hinc ? (1 << 5) : 0;
574 l |= fir_vinc ? (1 << 6) : 0;
575 dispc_write_reg(at_reg[plane], l);
576
577 enable_lcd_clocks(0);
578 return 0;
579 }
580
581 static int omap_dispc_enable_plane(int plane, int enable)
582 {
583 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
584 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
585 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
586 if ((unsigned int)plane > dispc.mem_desc.region_cnt)
587 return -EINVAL;
588
589 enable_lcd_clocks(1);
590 MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
591 enable_lcd_clocks(0);
592
593 return 0;
594 }
595
596 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
597 {
598 u32 df_reg, tr_reg;
599 int shift, val;
600
601 switch (ck->channel_out) {
602 case OMAPFB_CHANNEL_OUT_LCD:
603 df_reg = DISPC_DEFAULT_COLOR0;
604 tr_reg = DISPC_TRANS_COLOR0;
605 shift = 10;
606 break;
607 case OMAPFB_CHANNEL_OUT_DIGIT:
608 df_reg = DISPC_DEFAULT_COLOR1;
609 tr_reg = DISPC_TRANS_COLOR1;
610 shift = 12;
611 break;
612 default:
613 return -EINVAL;
614 }
615 switch (ck->key_type) {
616 case OMAPFB_COLOR_KEY_DISABLED:
617 val = 0;
618 break;
619 case OMAPFB_COLOR_KEY_GFX_DST:
620 val = 1;
621 break;
622 case OMAPFB_COLOR_KEY_VID_SRC:
623 val = 3;
624 break;
625 default:
626 return -EINVAL;
627 }
628 enable_lcd_clocks(1);
629 MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
630
631 if (val != 0)
632 dispc_write_reg(tr_reg, ck->trans_key);
633 dispc_write_reg(df_reg, ck->background);
634 enable_lcd_clocks(0);
635
636 dispc.color_key = *ck;
637
638 return 0;
639 }
640
641 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
642 {
643 *ck = dispc.color_key;
644 return 0;
645 }
646
647 static void load_palette(void)
648 {
649 }
650
651 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
652 {
653 int r = 0;
654
655 if (mode != dispc.update_mode) {
656 switch (mode) {
657 case OMAPFB_AUTO_UPDATE:
658 case OMAPFB_MANUAL_UPDATE:
659 enable_lcd_clocks(1);
660 omap_dispc_enable_lcd_out(1);
661 dispc.update_mode = mode;
662 break;
663 case OMAPFB_UPDATE_DISABLED:
664 init_completion(&dispc.frame_done);
665 omap_dispc_enable_lcd_out(0);
666 if (!wait_for_completion_timeout(&dispc.frame_done,
667 msecs_to_jiffies(500))) {
668 dev_err(dispc.fbdev->dev,
669 "timeout waiting for FRAME DONE\n");
670 }
671 dispc.update_mode = mode;
672 enable_lcd_clocks(0);
673 break;
674 default:
675 r = -EINVAL;
676 }
677 }
678
679 return r;
680 }
681
682 static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps)
683 {
684 caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM;
685 if (plane > 0)
686 caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE;
687 caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) |
688 (1 << OMAPFB_COLOR_YUV422) |
689 (1 << OMAPFB_COLOR_YUY422);
690 if (plane == 0)
691 caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) |
692 (1 << OMAPFB_COLOR_CLUT_4BPP) |
693 (1 << OMAPFB_COLOR_CLUT_2BPP) |
694 (1 << OMAPFB_COLOR_CLUT_1BPP) |
695 (1 << OMAPFB_COLOR_RGB444);
696 }
697
698 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
699 {
700 return dispc.update_mode;
701 }
702
703 static void setup_color_conv_coef(void)
704 {
705 u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
706 int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
707 int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
708 int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
709 int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
710 const struct color_conv_coef {
711 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
712 int full_range;
713 } ctbl_bt601_5 = {
714 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
715 };
716 const struct color_conv_coef *ct;
717 #define CVAL(x, y) (((x & 2047) << 16) | (y & 2047))
718
719 ct = &ctbl_bt601_5;
720
721 MOD_REG_FLD(cf1_reg, mask, CVAL(ct->rcr, ct->ry));
722 MOD_REG_FLD(cf1_reg + 4, mask, CVAL(ct->gy, ct->rcb));
723 MOD_REG_FLD(cf1_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
724 MOD_REG_FLD(cf1_reg + 12, mask, CVAL(ct->bcr, ct->by));
725 MOD_REG_FLD(cf1_reg + 16, mask, CVAL(0, ct->bcb));
726
727 MOD_REG_FLD(cf2_reg, mask, CVAL(ct->rcr, ct->ry));
728 MOD_REG_FLD(cf2_reg + 4, mask, CVAL(ct->gy, ct->rcb));
729 MOD_REG_FLD(cf2_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
730 MOD_REG_FLD(cf2_reg + 12, mask, CVAL(ct->bcr, ct->by));
731 MOD_REG_FLD(cf2_reg + 16, mask, CVAL(0, ct->bcb));
732 #undef CVAL
733
734 MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
735 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
736 }
737
738 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
739 {
740 unsigned long fck, lck;
741
742 *lck_div = 1;
743 pck = max(1, pck);
744 fck = clk_get_rate(dispc.dss1_fck);
745 lck = fck;
746 *pck_div = (lck + pck - 1) / pck;
747 if (is_tft)
748 *pck_div = max(2, *pck_div);
749 else
750 *pck_div = max(3, *pck_div);
751 if (*pck_div > 255) {
752 *pck_div = 255;
753 lck = pck * *pck_div;
754 *lck_div = fck / lck;
755 BUG_ON(*lck_div < 1);
756 if (*lck_div > 255) {
757 *lck_div = 255;
758 dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
759 pck / 1000);
760 }
761 }
762 }
763
764 static void set_lcd_tft_mode(int enable)
765 {
766 u32 mask;
767
768 mask = 1 << 3;
769 MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
770 }
771
772 static void set_lcd_timings(void)
773 {
774 u32 l;
775 int lck_div, pck_div;
776 struct lcd_panel *panel = dispc.fbdev->panel;
777 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
778 unsigned long fck;
779
780 l = dispc_read_reg(DISPC_TIMING_H);
781 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
782 l |= ( max(1, (min(64, panel->hsw))) - 1 ) << 0;
783 l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
784 l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
785 dispc_write_reg(DISPC_TIMING_H, l);
786
787 l = dispc_read_reg(DISPC_TIMING_V);
788 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
789 l |= ( max(1, (min(64, panel->vsw))) - 1 ) << 0;
790 l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
791 l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
792 dispc_write_reg(DISPC_TIMING_V, l);
793
794 l = dispc_read_reg(DISPC_POL_FREQ);
795 l &= ~FLD_MASK(12, 6);
796 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
797 l |= panel->acb & 0xff;
798 dispc_write_reg(DISPC_POL_FREQ, l);
799
800 calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
801
802 l = dispc_read_reg(DISPC_DIVISOR);
803 l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
804 l |= (lck_div << 16) | (pck_div << 0);
805 dispc_write_reg(DISPC_DIVISOR, l);
806
807 /* update panel info with the exact clock */
808 fck = clk_get_rate(dispc.dss1_fck);
809 panel->pixel_clock = fck / lck_div / pck_div / 1000;
810 }
811
812 int omap_dispc_request_irq(void (*callback)(void *data), void *data)
813 {
814 int r = 0;
815
816 BUG_ON(callback == NULL);
817
818 if (dispc.irq_callback)
819 r = -EBUSY;
820 else {
821 dispc.irq_callback = callback;
822 dispc.irq_callback_data = data;
823 }
824
825 return r;
826 }
827 EXPORT_SYMBOL(omap_dispc_request_irq);
828
829 void omap_dispc_enable_irqs(int irq_mask)
830 {
831 enable_lcd_clocks(1);
832 dispc.enabled_irqs = irq_mask;
833 irq_mask |= DISPC_IRQ_MASK_ERROR;
834 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
835 enable_lcd_clocks(0);
836 }
837 EXPORT_SYMBOL(omap_dispc_enable_irqs);
838
839 void omap_dispc_disable_irqs(int irq_mask)
840 {
841 enable_lcd_clocks(1);
842 dispc.enabled_irqs &= ~irq_mask;
843 irq_mask &= ~DISPC_IRQ_MASK_ERROR;
844 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
845 enable_lcd_clocks(0);
846 }
847 EXPORT_SYMBOL(omap_dispc_disable_irqs);
848
849 void omap_dispc_free_irq(void)
850 {
851 enable_lcd_clocks(1);
852 omap_dispc_disable_irqs(DISPC_IRQ_MASK_ALL);
853 dispc.irq_callback = NULL;
854 dispc.irq_callback_data = NULL;
855 enable_lcd_clocks(0);
856 }
857 EXPORT_SYMBOL(omap_dispc_free_irq);
858
859 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
860 {
861 u32 stat = dispc_read_reg(DISPC_IRQSTATUS);
862
863 if (stat & DISPC_IRQ_FRAMEMASK)
864 complete(&dispc.frame_done);
865
866 if (stat & DISPC_IRQ_MASK_ERROR) {
867 if (printk_ratelimit()) {
868 dev_err(dispc.fbdev->dev, "irq error status %04x\n",
869 stat & 0x7fff);
870 }
871 }
872
873 if ((stat & dispc.enabled_irqs) && dispc.irq_callback)
874 dispc.irq_callback(dispc.irq_callback_data);
875
876 dispc_write_reg(DISPC_IRQSTATUS, stat);
877
878 return IRQ_HANDLED;
879 }
880
881 static int get_dss_clocks(void)
882 {
883 if (IS_ERR((dispc.dss_ick = clk_get(dispc.fbdev->dev, "dss_ick")))) {
884 dev_err(dispc.fbdev->dev, "can't get dss_ick\n");
885 return PTR_ERR(dispc.dss_ick);
886 }
887
888 if (IS_ERR((dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck")))) {
889 dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
890 clk_put(dispc.dss_ick);
891 return PTR_ERR(dispc.dss1_fck);
892 }
893
894 if (IS_ERR((dispc.dss_54m_fck =
895 clk_get(dispc.fbdev->dev, "dss_54m_fck")))) {
896 dev_err(dispc.fbdev->dev, "can't get dss_54m_fck\n");
897 clk_put(dispc.dss_ick);
898 clk_put(dispc.dss1_fck);
899 return PTR_ERR(dispc.dss_54m_fck);
900 }
901
902 return 0;
903 }
904
905 static void put_dss_clocks(void)
906 {
907 clk_put(dispc.dss_54m_fck);
908 clk_put(dispc.dss1_fck);
909 clk_put(dispc.dss_ick);
910 }
911
912 static void enable_lcd_clocks(int enable)
913 {
914 if (enable)
915 clk_enable(dispc.dss1_fck);
916 else
917 clk_disable(dispc.dss1_fck);
918 }
919
920 static void enable_interface_clocks(int enable)
921 {
922 if (enable)
923 clk_enable(dispc.dss_ick);
924 else
925 clk_disable(dispc.dss_ick);
926 }
927
928 static void enable_digit_clocks(int enable)
929 {
930 if (enable)
931 clk_enable(dispc.dss_54m_fck);
932 else
933 clk_disable(dispc.dss_54m_fck);
934 }
935
936 static void omap_dispc_suspend(void)
937 {
938 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
939 init_completion(&dispc.frame_done);
940 omap_dispc_enable_lcd_out(0);
941 if (!wait_for_completion_timeout(&dispc.frame_done,
942 msecs_to_jiffies(500))) {
943 dev_err(dispc.fbdev->dev,
944 "timeout waiting for FRAME DONE\n");
945 }
946 enable_lcd_clocks(0);
947 }
948 }
949
950 static void omap_dispc_resume(void)
951 {
952 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
953 enable_lcd_clocks(1);
954 if (!dispc.ext_mode) {
955 set_lcd_timings();
956 load_palette();
957 }
958 omap_dispc_enable_lcd_out(1);
959 }
960 }
961
962
963 static int omap_dispc_update_window(struct fb_info *fbi,
964 struct omapfb_update_window *win,
965 void (*complete_callback)(void *arg),
966 void *complete_callback_data)
967 {
968 return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
969 }
970
971 static int mmap_kern(struct omapfb_mem_region *region)
972 {
973 struct vm_struct *kvma;
974 struct vm_area_struct vma;
975 pgprot_t pgprot;
976 unsigned long vaddr;
977
978 kvma = get_vm_area(region->size, VM_IOREMAP);
979 if (kvma == NULL) {
980 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
981 return -ENOMEM;
982 }
983 vma.vm_mm = &init_mm;
984
985 vaddr = (unsigned long)kvma->addr;
986
987 pgprot = pgprot_writecombine(pgprot_kernel);
988 vma.vm_start = vaddr;
989 vma.vm_end = vaddr + region->size;
990 if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
991 region->size, pgprot) < 0) {
992 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
993 return -EAGAIN;
994 }
995 region->vaddr = (void *)vaddr;
996
997 return 0;
998 }
999
1000 static void mmap_user_open(struct vm_area_struct *vma)
1001 {
1002 int plane = (int)vma->vm_private_data;
1003
1004 atomic_inc(&dispc.map_count[plane]);
1005 }
1006
1007 static void mmap_user_close(struct vm_area_struct *vma)
1008 {
1009 int plane = (int)vma->vm_private_data;
1010
1011 atomic_dec(&dispc.map_count[plane]);
1012 }
1013
1014 static struct vm_operations_struct mmap_user_ops = {
1015 .open = mmap_user_open,
1016 .close = mmap_user_close,
1017 };
1018
1019 static int omap_dispc_mmap_user(struct fb_info *info,
1020 struct vm_area_struct *vma)
1021 {
1022 struct omapfb_plane_struct *plane = info->par;
1023 unsigned long off;
1024 unsigned long start;
1025 u32 len;
1026
1027 if (vma->vm_end - vma->vm_start == 0)
1028 return 0;
1029 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1030 return -EINVAL;
1031 off = vma->vm_pgoff << PAGE_SHIFT;
1032
1033 start = info->fix.smem_start;
1034 len = info->fix.smem_len;
1035 if (off >= len)
1036 return -EINVAL;
1037 if ((vma->vm_end - vma->vm_start + off) > len)
1038 return -EINVAL;
1039 off += start;
1040 vma->vm_pgoff = off >> PAGE_SHIFT;
1041 vma->vm_flags |= VM_IO | VM_RESERVED;
1042 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1043 vma->vm_ops = &mmap_user_ops;
1044 vma->vm_private_data = (void *)plane->idx;
1045 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1046 vma->vm_end - vma->vm_start, vma->vm_page_prot))
1047 return -EAGAIN;
1048 /* vm_ops.open won't be called for mmap itself. */
1049 atomic_inc(&dispc.map_count[plane->idx]);
1050 return 0;
1051 }
1052
1053 static void unmap_kern(struct omapfb_mem_region *region)
1054 {
1055 vunmap(region->vaddr);
1056 }
1057
1058 static int alloc_palette_ram(void)
1059 {
1060 dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1061 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
1062 if (dispc.palette_vaddr == NULL) {
1063 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
1064 return -ENOMEM;
1065 }
1066
1067 return 0;
1068 }
1069
1070 static void free_palette_ram(void)
1071 {
1072 dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1073 dispc.palette_vaddr, dispc.palette_paddr);
1074 }
1075
1076 static int alloc_fbmem(struct omapfb_mem_region *region)
1077 {
1078 region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1079 region->size, &region->paddr, GFP_KERNEL);
1080
1081 if (region->vaddr == NULL) {
1082 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1083 return -ENOMEM;
1084 }
1085
1086 return 0;
1087 }
1088
1089 static void free_fbmem(struct omapfb_mem_region *region)
1090 {
1091 dma_free_writecombine(dispc.fbdev->dev, region->size,
1092 region->vaddr, region->paddr);
1093 }
1094
1095 static struct resmap *init_resmap(unsigned long start, size_t size)
1096 {
1097 unsigned page_cnt;
1098 struct resmap *res_map;
1099
1100 page_cnt = PAGE_ALIGN(size) / PAGE_SIZE;
1101 res_map =
1102 kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL);
1103 if (res_map == NULL)
1104 return NULL;
1105 res_map->start = start;
1106 res_map->page_cnt = page_cnt;
1107 res_map->map = (unsigned long *)(res_map + 1);
1108 return res_map;
1109 }
1110
1111 static void cleanup_resmap(struct resmap *res_map)
1112 {
1113 kfree(res_map);
1114 }
1115
1116 static inline int resmap_mem_type(unsigned long start)
1117 {
1118 if (start >= OMAP2_SRAM_START &&
1119 start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1120 return OMAPFB_MEMTYPE_SRAM;
1121 else
1122 return OMAPFB_MEMTYPE_SDRAM;
1123 }
1124
1125 static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr)
1126 {
1127 return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0;
1128 }
1129
1130 static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr)
1131 {
1132 BUG_ON(resmap_page_reserved(res_map, page_nr));
1133 *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr);
1134 }
1135
1136 static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr)
1137 {
1138 BUG_ON(!resmap_page_reserved(res_map, page_nr));
1139 *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr);
1140 }
1141
1142 static void resmap_reserve_region(unsigned long start, size_t size)
1143 {
1144
1145 struct resmap *res_map;
1146 unsigned start_page;
1147 unsigned end_page;
1148 int mtype;
1149 unsigned i;
1150
1151 mtype = resmap_mem_type(start);
1152 res_map = dispc.res_map[mtype];
1153 dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n",
1154 mtype, start, size);
1155 start_page = (start - res_map->start) / PAGE_SIZE;
1156 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1157 for (i = start_page; i < end_page; i++)
1158 resmap_reserve_page(res_map, i);
1159 }
1160
1161 static void resmap_free_region(unsigned long start, size_t size)
1162 {
1163 struct resmap *res_map;
1164 unsigned start_page;
1165 unsigned end_page;
1166 unsigned i;
1167 int mtype;
1168
1169 mtype = resmap_mem_type(start);
1170 res_map = dispc.res_map[mtype];
1171 dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n",
1172 mtype, start, size);
1173 start_page = (start - res_map->start) / PAGE_SIZE;
1174 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1175 for (i = start_page; i < end_page; i++)
1176 resmap_free_page(res_map, i);
1177 }
1178
1179 static unsigned long resmap_alloc_region(int mtype, size_t size)
1180 {
1181 unsigned i;
1182 unsigned total;
1183 unsigned start_page;
1184 unsigned long start;
1185 struct resmap *res_map = dispc.res_map[mtype];
1186
1187 BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size);
1188
1189 size = PAGE_ALIGN(size) / PAGE_SIZE;
1190 start_page = 0;
1191 total = 0;
1192 for (i = 0; i < res_map->page_cnt; i++) {
1193 if (resmap_page_reserved(res_map, i)) {
1194 start_page = i + 1;
1195 total = 0;
1196 } else if (++total == size)
1197 break;
1198 }
1199 if (total < size)
1200 return 0;
1201
1202 start = res_map->start + start_page * PAGE_SIZE;
1203 resmap_reserve_region(start, size * PAGE_SIZE);
1204
1205 return start;
1206 }
1207
1208 /* Note that this will only work for user mappings, we don't deal with
1209 * kernel mappings here, so fbcon will keep using the old region.
1210 */
1211 static int omap_dispc_setup_mem(int plane, size_t size, int mem_type,
1212 unsigned long *paddr)
1213 {
1214 struct omapfb_mem_region *rg;
1215 unsigned long new_addr = 0;
1216
1217 if ((unsigned)plane > dispc.mem_desc.region_cnt)
1218 return -EINVAL;
1219 if (mem_type >= DISPC_MEMTYPE_NUM)
1220 return -EINVAL;
1221 if (dispc.res_map[mem_type] == NULL)
1222 return -ENOMEM;
1223 rg = &dispc.mem_desc.region[plane];
1224 if (size == rg->size && mem_type == rg->type)
1225 return 0;
1226 if (atomic_read(&dispc.map_count[plane]))
1227 return -EBUSY;
1228 if (rg->size != 0)
1229 resmap_free_region(rg->paddr, rg->size);
1230 if (size != 0) {
1231 new_addr = resmap_alloc_region(mem_type, size);
1232 if (!new_addr) {
1233 /* Reallocate old region. */
1234 resmap_reserve_region(rg->paddr, rg->size);
1235 return -ENOMEM;
1236 }
1237 }
1238 rg->paddr = new_addr;
1239 rg->size = size;
1240 rg->type = mem_type;
1241
1242 *paddr = new_addr;
1243
1244 return 0;
1245 }
1246
1247 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1248 {
1249 struct omapfb_mem_region *rg;
1250 int i;
1251 int r;
1252 unsigned long mem_start[DISPC_MEMTYPE_NUM];
1253 unsigned long mem_end[DISPC_MEMTYPE_NUM];
1254
1255 if (!req_md->region_cnt) {
1256 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1257 return -ENOENT;
1258 }
1259
1260 rg = &req_md->region[0];
1261 memset(mem_start, 0xff, sizeof(mem_start));
1262 memset(mem_end, 0, sizeof(mem_end));
1263
1264 for (i = 0; i < req_md->region_cnt; i++, rg++) {
1265 int mtype;
1266 if (rg->paddr) {
1267 rg->alloc = 0;
1268 if (rg->vaddr == NULL) {
1269 rg->map = 1;
1270 if ((r = mmap_kern(rg)) < 0)
1271 return r;
1272 }
1273 } else {
1274 if (rg->type != OMAPFB_MEMTYPE_SDRAM) {
1275 dev_err(dispc.fbdev->dev,
1276 "unsupported memory type\n");
1277 return -EINVAL;
1278 }
1279 rg->alloc = rg->map = 1;
1280 if ((r = alloc_fbmem(rg)) < 0)
1281 return r;
1282 }
1283 mtype = rg->type;
1284
1285 if (rg->paddr < mem_start[mtype])
1286 mem_start[mtype] = rg->paddr;
1287 if (rg->paddr + rg->size > mem_end[mtype])
1288 mem_end[mtype] = rg->paddr + rg->size;
1289 }
1290
1291 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1292 unsigned long start;
1293 size_t size;
1294 if (mem_end[i] == 0)
1295 continue;
1296 start = mem_start[i];
1297 size = mem_end[i] - start;
1298 dispc.res_map[i] = init_resmap(start, size);
1299 r = -ENOMEM;
1300 if (dispc.res_map[i] == NULL)
1301 goto fail;
1302 /* Initial state is that everything is reserved. This
1303 * includes possible holes as well, which will never be
1304 * freed.
1305 */
1306 resmap_reserve_region(start, size);
1307 }
1308
1309 dispc.mem_desc = *req_md;
1310
1311 return 0;
1312 fail:
1313 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1314 if (dispc.res_map[i] != NULL)
1315 cleanup_resmap(dispc.res_map[i]);
1316 }
1317 return r;
1318 }
1319
1320 static void cleanup_fbmem(void)
1321 {
1322 struct omapfb_mem_region *rg;
1323 int i;
1324
1325 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1326 if (dispc.res_map[i] != NULL)
1327 cleanup_resmap(dispc.res_map[i]);
1328 }
1329 rg = &dispc.mem_desc.region[0];
1330 for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) {
1331 if (rg->alloc)
1332 free_fbmem(rg);
1333 else {
1334 if (rg->map)
1335 unmap_kern(rg);
1336 }
1337 }
1338 }
1339
1340 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1341 struct omapfb_mem_desc *req_vram)
1342 {
1343 int r;
1344 u32 l;
1345 struct lcd_panel *panel = fbdev->panel;
1346 int tmo = 10000;
1347 int skip_init = 0;
1348 int i;
1349
1350 memset(&dispc, 0, sizeof(dispc));
1351
1352 dispc.base = io_p2v(DISPC_BASE);
1353 dispc.fbdev = fbdev;
1354 dispc.ext_mode = ext_mode;
1355
1356 init_completion(&dispc.frame_done);
1357
1358 if ((r = get_dss_clocks()) < 0)
1359 return r;
1360
1361 enable_interface_clocks(1);
1362 enable_lcd_clocks(1);
1363
1364 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1365 l = dispc_read_reg(DISPC_CONTROL);
1366 /* LCD enabled ? */
1367 if (l & 1) {
1368 pr_info("omapfb: skipping hardware initialization\n");
1369 skip_init = 1;
1370 }
1371 #endif
1372
1373 if (!skip_init) {
1374 /* Reset monitoring works only w/ the 54M clk */
1375 enable_digit_clocks(1);
1376
1377 /* Soft reset */
1378 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1379
1380 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1381 if (!--tmo) {
1382 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1383 r = -ENODEV;
1384 enable_digit_clocks(0);
1385 goto fail1;
1386 }
1387 }
1388
1389 enable_digit_clocks(0);
1390 }
1391
1392 /* Enable smart idle and autoidle */
1393 l = dispc_read_reg(DISPC_CONTROL);
1394 l &= ~((3 << 12) | (3 << 3));
1395 l |= (2 << 12) | (2 << 3) | (1 << 0);
1396 dispc_write_reg(DISPC_SYSCONFIG, l);
1397 omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1398
1399 /* Set functional clock autogating */
1400 l = dispc_read_reg(DISPC_CONFIG);
1401 l |= 1 << 9;
1402 dispc_write_reg(DISPC_CONFIG, l);
1403
1404 l = dispc_read_reg(DISPC_IRQSTATUS);
1405 dispc_write_reg(l, DISPC_IRQSTATUS);
1406
1407 /* Enable those that we handle always */
1408 omap_dispc_enable_irqs(DISPC_IRQ_FRAMEMASK);
1409
1410 if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1411 0, MODULE_NAME, fbdev)) < 0) {
1412 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1413 goto fail1;
1414 }
1415
1416 /* L3 firewall setting: enable access to OCM RAM */
1417 __raw_writel(0x402000b0, io_p2v(0x680050a0));
1418
1419 if ((r = alloc_palette_ram()) < 0)
1420 goto fail2;
1421
1422 if ((r = setup_fbmem(req_vram)) < 0)
1423 goto fail3;
1424
1425 if (!skip_init) {
1426 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1427 memset(dispc.mem_desc.region[i].vaddr, 0,
1428 dispc.mem_desc.region[i].size);
1429 }
1430
1431 /* Set logic clock to fck, pixel clock to fck/2 for now */
1432 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1433 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1434
1435 setup_plane_fifo(0, ext_mode);
1436 setup_plane_fifo(1, ext_mode);
1437 setup_plane_fifo(2, ext_mode);
1438
1439 setup_color_conv_coef();
1440
1441 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1442 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1443
1444 if (!ext_mode) {
1445 set_lcd_data_lines(panel->data_lines);
1446 omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1447 set_lcd_timings();
1448 } else
1449 set_lcd_data_lines(panel->bpp);
1450 enable_rfbi_mode(ext_mode);
1451 }
1452
1453 l = dispc_read_reg(DISPC_REVISION);
1454 pr_info("omapfb: DISPC version %d.%d initialized\n",
1455 l >> 4 & 0x0f, l & 0x0f);
1456 enable_lcd_clocks(0);
1457
1458 return 0;
1459 fail3:
1460 free_palette_ram();
1461 fail2:
1462 free_irq(INT_24XX_DSS_IRQ, fbdev);
1463 fail1:
1464 enable_lcd_clocks(0);
1465 enable_interface_clocks(0);
1466 put_dss_clocks();
1467
1468 return r;
1469 }
1470
1471 static void omap_dispc_cleanup(void)
1472 {
1473 int i;
1474
1475 omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1476 /* This will also disable clocks that are on */
1477 for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1478 omap_dispc_enable_plane(i, 0);
1479 cleanup_fbmem();
1480 free_palette_ram();
1481 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1482 enable_interface_clocks(0);
1483 put_dss_clocks();
1484 }
1485
1486 const struct lcd_ctrl omap2_int_ctrl = {
1487 .name = "internal",
1488 .init = omap_dispc_init,
1489 .cleanup = omap_dispc_cleanup,
1490 .get_caps = omap_dispc_get_caps,
1491 .set_update_mode = omap_dispc_set_update_mode,
1492 .get_update_mode = omap_dispc_get_update_mode,
1493 .update_window = omap_dispc_update_window,
1494 .suspend = omap_dispc_suspend,
1495 .resume = omap_dispc_resume,
1496 .setup_plane = omap_dispc_setup_plane,
1497 .setup_mem = omap_dispc_setup_mem,
1498 .set_scale = omap_dispc_set_scale,
1499 .enable_plane = omap_dispc_enable_plane,
1500 .set_color_key = omap_dispc_set_color_key,
1501 .get_color_key = omap_dispc_get_color_key,
1502 .mmap = omap_dispc_mmap_user,
1503 };
kernel source for telekom puls (alcatel/mediatek)