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Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / nvidia / nv_hw.c
1 /***************************************************************************\
2 |* *|
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
9 |* *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
12 |* as follows: *|
13 |* *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15 |* *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27 |* *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
37 |* *|
38 \***************************************************************************/
39
40 /*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
51
52 #include <linux/pci.h>
53 #include "nv_type.h"
54 #include "nv_local.h"
55 #include "nv_proto.h"
56
57 void NVLockUnlock(struct nvidia_par *par, int Lock)
58 {
59 u8 cr11;
60
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F);
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
63
64 VGA_WR08(par->PCIO, 0x3D4, 0x11);
65 cr11 = VGA_RD08(par->PCIO, 0x3D5);
66 if (Lock)
67 cr11 |= 0x80;
68 else
69 cr11 &= ~0x80;
70 VGA_WR08(par->PCIO, 0x3D5, cr11);
71 }
72
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
74 {
75 int cur = par->CurrentState->cursor1;
76
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
78 (ShowHide & 0x01);
79 VGA_WR08(par->PCIO, 0x3D4, 0x31);
80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
81
82 if (par->Architecture == NV_ARCH_40)
83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
84
85 return (cur & 0x01);
86 }
87
88 /****************************************************************************\
89 * *
90 * The video arbitration routines calculate some "magic" numbers. Fixes *
91 * the snow seen when accessing the framebuffer without it. *
92 * It just works (I hope). *
93 * *
94 \****************************************************************************/
95
96 typedef struct {
97 int graphics_lwm;
98 int video_lwm;
99 int graphics_burst_size;
100 int video_burst_size;
101 int valid;
102 } nv4_fifo_info;
103
104 typedef struct {
105 int pclk_khz;
106 int mclk_khz;
107 int nvclk_khz;
108 char mem_page_miss;
109 char mem_latency;
110 int memory_width;
111 char enable_video;
112 char gr_during_vid;
113 char pix_bpp;
114 char mem_aligned;
115 char enable_mp;
116 } nv4_sim_state;
117
118 typedef struct {
119 int graphics_lwm;
120 int video_lwm;
121 int graphics_burst_size;
122 int video_burst_size;
123 int valid;
124 } nv10_fifo_info;
125
126 typedef struct {
127 int pclk_khz;
128 int mclk_khz;
129 int nvclk_khz;
130 char mem_page_miss;
131 char mem_latency;
132 int memory_type;
133 int memory_width;
134 char enable_video;
135 char gr_during_vid;
136 char pix_bpp;
137 char mem_aligned;
138 char enable_mp;
139 } nv10_sim_state;
140
141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
142 unsigned int *NVClk)
143 {
144 unsigned int pll, N, M, MB, NB, P;
145
146 if (par->Architecture >= NV_ARCH_40) {
147 pll = NV_RD32(par->PMC, 0x4020);
148 P = (pll >> 16) & 0x07;
149 pll = NV_RD32(par->PMC, 0x4024);
150 M = pll & 0xFF;
151 N = (pll >> 8) & 0xFF;
152 if (((par->Chipset & 0xfff0) == 0x0290) || ((par->Chipset & 0xfff0) == 0x0390) || ((par->Chipset & 0xfff0) == 0x02E0)) {
153 MB = 1;
154 NB = 1;
155 } else {
156 MB = (pll >> 16) & 0xFF;
157 NB = (pll >> 24) & 0xFF;
158 }
159 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
160
161 pll = NV_RD32(par->PMC, 0x4000);
162 P = (pll >> 16) & 0x03;
163 pll = NV_RD32(par->PMC, 0x4004);
164 M = pll & 0xFF;
165 N = (pll >> 8) & 0xFF;
166 MB = (pll >> 16) & 0xFF;
167 NB = (pll >> 24) & 0xFF;
168
169 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
170 } else if (par->twoStagePLL) {
171 pll = NV_RD32(par->PRAMDAC0, 0x0504);
172 M = pll & 0xFF;
173 N = (pll >> 8) & 0xFF;
174 P = (pll >> 16) & 0x0F;
175 pll = NV_RD32(par->PRAMDAC0, 0x0574);
176 if (pll & 0x80000000) {
177 MB = pll & 0xFF;
178 NB = (pll >> 8) & 0xFF;
179 } else {
180 MB = 1;
181 NB = 1;
182 }
183 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
184
185 pll = NV_RD32(par->PRAMDAC0, 0x0500);
186 M = pll & 0xFF;
187 N = (pll >> 8) & 0xFF;
188 P = (pll >> 16) & 0x0F;
189 pll = NV_RD32(par->PRAMDAC0, 0x0570);
190 if (pll & 0x80000000) {
191 MB = pll & 0xFF;
192 NB = (pll >> 8) & 0xFF;
193 } else {
194 MB = 1;
195 NB = 1;
196 }
197 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
198 } else
199 if (((par->Chipset & 0x0ff0) == 0x0300) ||
200 ((par->Chipset & 0x0ff0) == 0x0330)) {
201 pll = NV_RD32(par->PRAMDAC0, 0x0504);
202 M = pll & 0x0F;
203 N = (pll >> 8) & 0xFF;
204 P = (pll >> 16) & 0x07;
205 if (pll & 0x00000080) {
206 MB = (pll >> 4) & 0x07;
207 NB = (pll >> 19) & 0x1f;
208 } else {
209 MB = 1;
210 NB = 1;
211 }
212 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
213
214 pll = NV_RD32(par->PRAMDAC0, 0x0500);
215 M = pll & 0x0F;
216 N = (pll >> 8) & 0xFF;
217 P = (pll >> 16) & 0x07;
218 if (pll & 0x00000080) {
219 MB = (pll >> 4) & 0x07;
220 NB = (pll >> 19) & 0x1f;
221 } else {
222 MB = 1;
223 NB = 1;
224 }
225 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
226 } else {
227 pll = NV_RD32(par->PRAMDAC0, 0x0504);
228 M = pll & 0xFF;
229 N = (pll >> 8) & 0xFF;
230 P = (pll >> 16) & 0x0F;
231 *MClk = (N * par->CrystalFreqKHz / M) >> P;
232
233 pll = NV_RD32(par->PRAMDAC0, 0x0500);
234 M = pll & 0xFF;
235 N = (pll >> 8) & 0xFF;
236 P = (pll >> 16) & 0x0F;
237 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
238 }
239 }
240
241 static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
242 {
243 int data, pagemiss, cas, width, video_enable, bpp;
244 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
245 int found, mclk_extra, mclk_loop, cbs, m1, p1;
246 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
247 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
248 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
249
250 fifo->valid = 1;
251 pclk_freq = arb->pclk_khz;
252 mclk_freq = arb->mclk_khz;
253 nvclk_freq = arb->nvclk_khz;
254 pagemiss = arb->mem_page_miss;
255 cas = arb->mem_latency;
256 width = arb->memory_width >> 6;
257 video_enable = arb->enable_video;
258 bpp = arb->pix_bpp;
259 mp_enable = arb->enable_mp;
260 clwm = 0;
261 vlwm = 0;
262 cbs = 128;
263 pclks = 2;
264 nvclks = 2;
265 nvclks += 2;
266 nvclks += 1;
267 mclks = 5;
268 mclks += 3;
269 mclks += 1;
270 mclks += cas;
271 mclks += 1;
272 mclks += 1;
273 mclks += 1;
274 mclks += 1;
275 mclk_extra = 3;
276 nvclks += 2;
277 nvclks += 1;
278 nvclks += 1;
279 nvclks += 1;
280 if (mp_enable)
281 mclks += 4;
282 nvclks += 0;
283 pclks += 0;
284 found = 0;
285 vbs = 0;
286 while (found != 1) {
287 fifo->valid = 1;
288 found = 1;
289 mclk_loop = mclks + mclk_extra;
290 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
291 us_n = nvclks * 1000 * 1000 / nvclk_freq;
292 us_p = nvclks * 1000 * 1000 / pclk_freq;
293 if (video_enable) {
294 video_drain_rate = pclk_freq * 2;
295 crtc_drain_rate = pclk_freq * bpp / 8;
296 vpagemiss = 2;
297 vpagemiss += 1;
298 crtpagemiss = 2;
299 vpm_us =
300 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
301 if (nvclk_freq * 2 > mclk_freq * width)
302 video_fill_us =
303 cbs * 1000 * 1000 / 16 / nvclk_freq;
304 else
305 video_fill_us =
306 cbs * 1000 * 1000 / (8 * width) /
307 mclk_freq;
308 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
309 vlwm = us_video * video_drain_rate / (1000 * 1000);
310 vlwm++;
311 vbs = 128;
312 if (vlwm > 128)
313 vbs = 64;
314 if (vlwm > (256 - 64))
315 vbs = 32;
316 if (nvclk_freq * 2 > mclk_freq * width)
317 video_fill_us =
318 vbs * 1000 * 1000 / 16 / nvclk_freq;
319 else
320 video_fill_us =
321 vbs * 1000 * 1000 / (8 * width) /
322 mclk_freq;
323 cpm_us =
324 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
325 us_crt =
326 us_video + video_fill_us + cpm_us + us_m + us_n +
327 us_p;
328 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
329 clwm++;
330 } else {
331 crtc_drain_rate = pclk_freq * bpp / 8;
332 crtpagemiss = 2;
333 crtpagemiss += 1;
334 cpm_us =
335 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
336 us_crt = cpm_us + us_m + us_n + us_p;
337 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
338 clwm++;
339 }
340 m1 = clwm + cbs - 512;
341 p1 = m1 * pclk_freq / mclk_freq;
342 p1 = p1 * bpp / 8;
343 if ((p1 < m1) && (m1 > 0)) {
344 fifo->valid = 0;
345 found = 0;
346 if (mclk_extra == 0)
347 found = 1;
348 mclk_extra--;
349 } else if (video_enable) {
350 if ((clwm > 511) || (vlwm > 255)) {
351 fifo->valid = 0;
352 found = 0;
353 if (mclk_extra == 0)
354 found = 1;
355 mclk_extra--;
356 }
357 } else {
358 if (clwm > 519) {
359 fifo->valid = 0;
360 found = 0;
361 if (mclk_extra == 0)
362 found = 1;
363 mclk_extra--;
364 }
365 }
366 if (clwm < 384)
367 clwm = 384;
368 if (vlwm < 128)
369 vlwm = 128;
370 data = (int)(clwm);
371 fifo->graphics_lwm = data;
372 fifo->graphics_burst_size = 128;
373 data = (int)((vlwm + 15));
374 fifo->video_lwm = data;
375 fifo->video_burst_size = vbs;
376 }
377 }
378
379 static void nv4UpdateArbitrationSettings(unsigned VClk,
380 unsigned pixelDepth,
381 unsigned *burst,
382 unsigned *lwm, struct nvidia_par *par)
383 {
384 nv4_fifo_info fifo_data;
385 nv4_sim_state sim_data;
386 unsigned int MClk, NVClk, cfg1;
387
388 nvGetClocks(par, &MClk, &NVClk);
389
390 cfg1 = NV_RD32(par->PFB, 0x00000204);
391 sim_data.pix_bpp = (char)pixelDepth;
392 sim_data.enable_video = 0;
393 sim_data.enable_mp = 0;
394 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
395 128 : 64;
396 sim_data.mem_latency = (char)cfg1 & 0x0F;
397 sim_data.mem_aligned = 1;
398 sim_data.mem_page_miss =
399 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
400 sim_data.gr_during_vid = 0;
401 sim_data.pclk_khz = VClk;
402 sim_data.mclk_khz = MClk;
403 sim_data.nvclk_khz = NVClk;
404 nv4CalcArbitration(&fifo_data, &sim_data);
405 if (fifo_data.valid) {
406 int b = fifo_data.graphics_burst_size >> 4;
407 *burst = 0;
408 while (b >>= 1)
409 (*burst)++;
410 *lwm = fifo_data.graphics_lwm >> 3;
411 }
412 }
413
414 static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
415 {
416 int data, pagemiss, width, video_enable, bpp;
417 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
418 int nvclk_fill;
419 int found, mclk_extra, mclk_loop, cbs, m1;
420 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
421 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
422 int vus_m;
423 int vpm_us, us_video, cpm_us, us_crt, clwm;
424 int clwm_rnd_down;
425 int m2us, us_pipe_min, p1clk, p2;
426 int min_mclk_extra;
427 int us_min_mclk_extra;
428
429 fifo->valid = 1;
430 pclk_freq = arb->pclk_khz; /* freq in KHz */
431 mclk_freq = arb->mclk_khz;
432 nvclk_freq = arb->nvclk_khz;
433 pagemiss = arb->mem_page_miss;
434 width = arb->memory_width / 64;
435 video_enable = arb->enable_video;
436 bpp = arb->pix_bpp;
437 mp_enable = arb->enable_mp;
438 clwm = 0;
439
440 cbs = 512;
441
442 pclks = 4; /* lwm detect. */
443
444 nvclks = 3; /* lwm -> sync. */
445 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
446 /* 2 edge sync. may be very close to edge so just put one. */
447 mclks = 1;
448 mclks += 1; /* arb_hp_req */
449 mclks += 5; /* ap_hp_req tiling pipeline */
450
451 mclks += 2; /* tc_req latency fifo */
452 mclks += 2; /* fb_cas_n_ memory request to fbio block */
453 mclks += 7; /* sm_d_rdv data returned from fbio block */
454
455 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
456 if (arb->memory_type == 0)
457 if (arb->memory_width == 64) /* 64 bit bus */
458 mclks += 4;
459 else
460 mclks += 2;
461 else if (arb->memory_width == 64) /* 64 bit bus */
462 mclks += 2;
463 else
464 mclks += 1;
465
466 if ((!video_enable) && (arb->memory_width == 128)) {
467 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
468 min_mclk_extra = 17;
469 } else {
470 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
471 /* mclk_extra = 4; *//* Margin of error */
472 min_mclk_extra = 18;
473 }
474
475 /* 2 edge sync. may be very close to edge so just put one. */
476 nvclks += 1;
477 nvclks += 1; /* fbi_d_rdv_n */
478 nvclks += 1; /* Fbi_d_rdata */
479 nvclks += 1; /* crtfifo load */
480
481 if (mp_enable)
482 mclks += 4; /* Mp can get in with a burst of 8. */
483 /* Extra clocks determined by heuristics */
484
485 nvclks += 0;
486 pclks += 0;
487 found = 0;
488 while (found != 1) {
489 fifo->valid = 1;
490 found = 1;
491 mclk_loop = mclks + mclk_extra;
492 /* Mclk latency in us */
493 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
494 /* Minimum Mclk latency in us */
495 us_m_min = mclks * 1000 * 1000 / mclk_freq;
496 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
497 /* nvclk latency in us */
498 us_n = nvclks * 1000 * 1000 / nvclk_freq;
499 /* nvclk latency in us */
500 us_p = pclks * 1000 * 1000 / pclk_freq;
501 us_pipe_min = us_m_min + us_n + us_p;
502
503 /* Mclk latency in us */
504 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
505
506 if (video_enable) {
507 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
508
509 vpagemiss = 1; /* self generating page miss */
510 vpagemiss += 1; /* One higher priority before */
511
512 crtpagemiss = 2; /* self generating page miss */
513 if (mp_enable)
514 crtpagemiss += 1; /* if MA0 conflict */
515
516 vpm_us =
517 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
518
519 /* Video has separate read return path */
520 us_video = vpm_us + vus_m;
521
522 cpm_us =
523 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
524 /* Wait for video */
525 us_crt = us_video
526 + cpm_us /* CRT Page miss */
527 + us_m + us_n + us_p /* other latency */
528 ;
529
530 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
531 /* fixed point <= float_point - 1. Fixes that */
532 clwm++;
533 } else {
534 /* bpp * pclk/8 */
535 crtc_drain_rate = pclk_freq * bpp / 8;
536
537 crtpagemiss = 1; /* self generating page miss */
538 crtpagemiss += 1; /* MA0 page miss */
539 if (mp_enable)
540 crtpagemiss += 1; /* if MA0 conflict */
541 cpm_us =
542 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
543 us_crt = cpm_us + us_m + us_n + us_p;
544 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
545 /* fixed point <= float_point - 1. Fixes that */
546 clwm++;
547
548 /* Finally, a heuristic check when width == 64 bits */
549 if (width == 1) {
550 nvclk_fill = nvclk_freq * 8;
551 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
552 /*Large number to fail */
553 clwm = 0xfff;
554
555 else if (crtc_drain_rate * 100 >=
556 nvclk_fill * 98) {
557 clwm = 1024;
558 cbs = 512;
559 }
560 }
561 }
562
563 /*
564 Overfill check:
565 */
566
567 clwm_rnd_down = ((int)clwm / 8) * 8;
568 if (clwm_rnd_down < clwm)
569 clwm += 8;
570
571 m1 = clwm + cbs - 1024; /* Amount of overfill */
572 m2us = us_pipe_min + us_min_mclk_extra;
573
574 /* pclk cycles to drain */
575 p1clk = m2us * pclk_freq / (1000 * 1000);
576 p2 = p1clk * bpp / 8; /* bytes drained. */
577
578 if ((p2 < m1) && (m1 > 0)) {
579 fifo->valid = 0;
580 found = 0;
581 if (min_mclk_extra == 0) {
582 if (cbs <= 32) {
583 /* Can't adjust anymore! */
584 found = 1;
585 } else {
586 /* reduce the burst size */
587 cbs = cbs / 2;
588 }
589 } else {
590 min_mclk_extra--;
591 }
592 } else {
593 if (clwm > 1023) { /* Have some margin */
594 fifo->valid = 0;
595 found = 0;
596 if (min_mclk_extra == 0)
597 /* Can't adjust anymore! */
598 found = 1;
599 else
600 min_mclk_extra--;
601 }
602 }
603
604 if (clwm < (1024 - cbs + 8))
605 clwm = 1024 - cbs + 8;
606 data = (int)(clwm);
607 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
608 clwm, data ); */
609 fifo->graphics_lwm = data;
610 fifo->graphics_burst_size = cbs;
611
612 fifo->video_lwm = 1024;
613 fifo->video_burst_size = 512;
614 }
615 }
616
617 static void nv10UpdateArbitrationSettings(unsigned VClk,
618 unsigned pixelDepth,
619 unsigned *burst,
620 unsigned *lwm,
621 struct nvidia_par *par)
622 {
623 nv10_fifo_info fifo_data;
624 nv10_sim_state sim_data;
625 unsigned int MClk, NVClk, cfg1;
626
627 nvGetClocks(par, &MClk, &NVClk);
628
629 cfg1 = NV_RD32(par->PFB, 0x0204);
630 sim_data.pix_bpp = (char)pixelDepth;
631 sim_data.enable_video = 1;
632 sim_data.enable_mp = 0;
633 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
634 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
635 128 : 64;
636 sim_data.mem_latency = (char)cfg1 & 0x0F;
637 sim_data.mem_aligned = 1;
638 sim_data.mem_page_miss =
639 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
640 sim_data.gr_during_vid = 0;
641 sim_data.pclk_khz = VClk;
642 sim_data.mclk_khz = MClk;
643 sim_data.nvclk_khz = NVClk;
644 nv10CalcArbitration(&fifo_data, &sim_data);
645 if (fifo_data.valid) {
646 int b = fifo_data.graphics_burst_size >> 4;
647 *burst = 0;
648 while (b >>= 1)
649 (*burst)++;
650 *lwm = fifo_data.graphics_lwm >> 3;
651 }
652 }
653
654 static void nv30UpdateArbitrationSettings (
655 struct nvidia_par *par,
656 unsigned int *burst,
657 unsigned int *lwm
658 )
659 {
660 unsigned int MClk, NVClk;
661 unsigned int fifo_size, burst_size, graphics_lwm;
662
663 fifo_size = 2048;
664 burst_size = 512;
665 graphics_lwm = fifo_size - burst_size;
666
667 nvGetClocks(par, &MClk, &NVClk);
668
669 *burst = 0;
670 burst_size >>= 5;
671 while(burst_size >>= 1) (*burst)++;
672 *lwm = graphics_lwm >> 3;
673 }
674
675 static void nForceUpdateArbitrationSettings(unsigned VClk,
676 unsigned pixelDepth,
677 unsigned *burst,
678 unsigned *lwm,
679 struct nvidia_par *par)
680 {
681 nv10_fifo_info fifo_data;
682 nv10_sim_state sim_data;
683 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
684 struct pci_dev *dev;
685
686 if ((par->Chipset & 0x0FF0) == 0x01A0) {
687 unsigned int uMClkPostDiv;
688 dev = pci_get_bus_and_slot(0, 3);
689 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
690 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
691
692 if (!uMClkPostDiv)
693 uMClkPostDiv = 4;
694 MClk = 400000 / uMClkPostDiv;
695 } else {
696 dev = pci_get_bus_and_slot(0, 5);
697 pci_read_config_dword(dev, 0x4c, &MClk);
698 MClk /= 1000;
699 }
700 pci_dev_put(dev);
701 pll = NV_RD32(par->PRAMDAC0, 0x0500);
702 M = (pll >> 0) & 0xFF;
703 N = (pll >> 8) & 0xFF;
704 P = (pll >> 16) & 0x0F;
705 NVClk = (N * par->CrystalFreqKHz / M) >> P;
706 sim_data.pix_bpp = (char)pixelDepth;
707 sim_data.enable_video = 0;
708 sim_data.enable_mp = 0;
709 dev = pci_get_bus_and_slot(0, 1);
710 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
711 pci_dev_put(dev);
712 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
713 sim_data.memory_width = 64;
714
715 dev = pci_get_bus_and_slot(0, 3);
716 pci_read_config_dword(dev, 0, &memctrl);
717 pci_dev_put(dev);
718 memctrl >>= 16;
719
720 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
721 int dimm[3];
722
723 dev = pci_get_bus_and_slot(0, 2);
724 pci_read_config_dword(dev, 0x40, &dimm[0]);
725 dimm[0] = (dimm[0] >> 8) & 0x4f;
726 pci_read_config_dword(dev, 0x44, &dimm[1]);
727 dimm[1] = (dimm[1] >> 8) & 0x4f;
728 pci_read_config_dword(dev, 0x48, &dimm[2]);
729 dimm[2] = (dimm[2] >> 8) & 0x4f;
730
731 if ((dimm[0] + dimm[1]) != dimm[2]) {
732 printk("nvidiafb: your nForce DIMMs are not arranged "
733 "in optimal banks!\n");
734 }
735 pci_dev_put(dev);
736 }
737
738 sim_data.mem_latency = 3;
739 sim_data.mem_aligned = 1;
740 sim_data.mem_page_miss = 10;
741 sim_data.gr_during_vid = 0;
742 sim_data.pclk_khz = VClk;
743 sim_data.mclk_khz = MClk;
744 sim_data.nvclk_khz = NVClk;
745 nv10CalcArbitration(&fifo_data, &sim_data);
746 if (fifo_data.valid) {
747 int b = fifo_data.graphics_burst_size >> 4;
748 *burst = 0;
749 while (b >>= 1)
750 (*burst)++;
751 *lwm = fifo_data.graphics_lwm >> 3;
752 }
753 }
754
755 /****************************************************************************\
756 * *
757 * RIVA Mode State Routines *
758 * *
759 \****************************************************************************/
760
761 /*
762 * Calculate the Video Clock parameters for the PLL.
763 */
764 static void CalcVClock(int clockIn,
765 int *clockOut, u32 * pllOut, struct nvidia_par *par)
766 {
767 unsigned lowM, highM;
768 unsigned DeltaNew, DeltaOld;
769 unsigned VClk, Freq;
770 unsigned M, N, P;
771
772 DeltaOld = 0xFFFFFFFF;
773
774 VClk = (unsigned)clockIn;
775
776 if (par->CrystalFreqKHz == 13500) {
777 lowM = 7;
778 highM = 13;
779 } else {
780 lowM = 8;
781 highM = 14;
782 }
783
784 for (P = 0; P <= 4; P++) {
785 Freq = VClk << P;
786 if ((Freq >= 128000) && (Freq <= 350000)) {
787 for (M = lowM; M <= highM; M++) {
788 N = ((VClk << P) * M) / par->CrystalFreqKHz;
789 if (N <= 255) {
790 Freq =
791 ((par->CrystalFreqKHz * N) /
792 M) >> P;
793 if (Freq > VClk)
794 DeltaNew = Freq - VClk;
795 else
796 DeltaNew = VClk - Freq;
797 if (DeltaNew < DeltaOld) {
798 *pllOut =
799 (P << 16) | (N << 8) | M;
800 *clockOut = Freq;
801 DeltaOld = DeltaNew;
802 }
803 }
804 }
805 }
806 }
807 }
808
809 static void CalcVClock2Stage(int clockIn,
810 int *clockOut,
811 u32 * pllOut,
812 u32 * pllBOut, struct nvidia_par *par)
813 {
814 unsigned DeltaNew, DeltaOld;
815 unsigned VClk, Freq;
816 unsigned M, N, P;
817
818 DeltaOld = 0xFFFFFFFF;
819
820 *pllBOut = 0x80000401; /* fixed at x4 for now */
821
822 VClk = (unsigned)clockIn;
823
824 for (P = 0; P <= 6; P++) {
825 Freq = VClk << P;
826 if ((Freq >= 400000) && (Freq <= 1000000)) {
827 for (M = 1; M <= 13; M++) {
828 N = ((VClk << P) * M) /
829 (par->CrystalFreqKHz << 2);
830 if ((N >= 5) && (N <= 255)) {
831 Freq =
832 (((par->CrystalFreqKHz << 2) * N) /
833 M) >> P;
834 if (Freq > VClk)
835 DeltaNew = Freq - VClk;
836 else
837 DeltaNew = VClk - Freq;
838 if (DeltaNew < DeltaOld) {
839 *pllOut =
840 (P << 16) | (N << 8) | M;
841 *clockOut = Freq;
842 DeltaOld = DeltaNew;
843 }
844 }
845 }
846 }
847 }
848 }
849
850 /*
851 * Calculate extended mode parameters (SVGA) and save in a
852 * mode state structure.
853 */
854 void NVCalcStateExt(struct nvidia_par *par,
855 RIVA_HW_STATE * state,
856 int bpp,
857 int width,
858 int hDisplaySize, int height, int dotClock, int flags)
859 {
860 int pixelDepth, VClk = 0;
861 /*
862 * Save mode parameters.
863 */
864 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
865 state->width = width;
866 state->height = height;
867 /*
868 * Extended RIVA registers.
869 */
870 pixelDepth = (bpp + 1) / 8;
871 if (par->twoStagePLL)
872 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
873 par);
874 else
875 CalcVClock(dotClock, &VClk, &state->pll, par);
876
877 switch (par->Architecture) {
878 case NV_ARCH_04:
879 nv4UpdateArbitrationSettings(VClk,
880 pixelDepth * 8,
881 &(state->arbitration0),
882 &(state->arbitration1), par);
883 state->cursor0 = 0x00;
884 state->cursor1 = 0xbC;
885 if (flags & FB_VMODE_DOUBLE)
886 state->cursor1 |= 2;
887 state->cursor2 = 0x00000000;
888 state->pllsel = 0x10000700;
889 state->config = 0x00001114;
890 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
891 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
892 break;
893 case NV_ARCH_10:
894 case NV_ARCH_20:
895 case NV_ARCH_30:
896 default:
897 if ((par->Chipset & 0xfff0) == 0x0240) {
898 state->arbitration0 = 256;
899 state->arbitration1 = 0x0480;
900 } else if (((par->Chipset & 0xffff) == 0x01A0) ||
901 ((par->Chipset & 0xffff) == 0x01f0)) {
902 nForceUpdateArbitrationSettings(VClk,
903 pixelDepth * 8,
904 &(state->arbitration0),
905 &(state->arbitration1),
906 par);
907 } else if (par->Architecture < NV_ARCH_30) {
908 nv10UpdateArbitrationSettings(VClk,
909 pixelDepth * 8,
910 &(state->arbitration0),
911 &(state->arbitration1),
912 par);
913 } else {
914 nv30UpdateArbitrationSettings(par,
915 &(state->arbitration0),
916 &(state->arbitration1));
917 }
918
919 state->cursor0 = 0x80 | (par->CursorStart >> 17);
920 state->cursor1 = (par->CursorStart >> 11) << 2;
921 state->cursor2 = par->CursorStart >> 24;
922 if (flags & FB_VMODE_DOUBLE)
923 state->cursor1 |= 2;
924 state->pllsel = 0x10000700;
925 state->config = NV_RD32(par->PFB, 0x00000200);
926 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
927 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
928 break;
929 }
930
931 if (bpp != 8) /* DirectColor */
932 state->general |= 0x00000030;
933
934 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
935 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
936 }
937
938 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
939 {
940 int i;
941
942 NV_WR32(par->PMC, 0x0140, 0x00000000);
943 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
944 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
945
946 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
947 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
948 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
949 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
950
951 if (par->Architecture == NV_ARCH_04) {
952 NV_WR32(par->PFB, 0x0200, state->config);
953 } else if ((par->Architecture < NV_ARCH_40) ||
954 (par->Chipset & 0xfff0) == 0x0040) {
955 for (i = 0; i < 8; i++) {
956 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
957 NV_WR32(par->PFB, 0x0244 + (i * 0x10),
958 par->FbMapSize - 1);
959 }
960 } else {
961 int regions = 12;
962
963 if (((par->Chipset & 0xfff0) == 0x0090) ||
964 ((par->Chipset & 0xfff0) == 0x01D0) ||
965 ((par->Chipset & 0xfff0) == 0x02E0) ||
966 ((par->Chipset & 0xfff0) == 0x0290))
967 regions = 15;
968 for(i = 0; i < regions; i++) {
969 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
970 NV_WR32(par->PFB, 0x0604 + (i * 0x10),
971 par->FbMapSize - 1);
972 }
973 }
974
975 if (par->Architecture >= NV_ARCH_40) {
976 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
977 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
978 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
979 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
980 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
981 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
982 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
983 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
984 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
985 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
986 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
987 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
988 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
989 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
990 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
991 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
992 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
993 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
994 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
995 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
996 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
997 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
998 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
999 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
1000 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
1001 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
1002 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1003 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1004 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1005 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1006 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1007 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1008 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1009 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1010 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1011 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1012 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1013 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1014 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1015 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1016 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1017 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1018 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1019 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1020 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1021 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1022 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1023 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1024 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1025 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1026 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1027 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1028 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1029 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1030 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1031 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1032 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1033 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1034 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1035 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1036 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1037 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1038 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1039 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1040 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1041 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1042 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1043 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1044 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1045 NV_WR32(par->PRAMIN, 0x084E * 4,
1046 par->FbUsableSize | 0x00000002);
1047
1048 #ifdef __BIG_ENDIAN
1049 NV_WR32(par->PRAMIN, 0x080A * 4,
1050 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1051 NV_WR32(par->PRAMIN, 0x0812 * 4,
1052 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1053 NV_WR32(par->PRAMIN, 0x081A * 4,
1054 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1055 NV_WR32(par->PRAMIN, 0x0822 * 4,
1056 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1057 NV_WR32(par->PRAMIN, 0x082A * 4,
1058 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1059 NV_WR32(par->PRAMIN, 0x0832 * 4,
1060 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1061 NV_WR32(par->PRAMIN, 0x083A * 4,
1062 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1063 NV_WR32(par->PRAMIN, 0x0842 * 4,
1064 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1065 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1066 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1067 #endif
1068 } else {
1069 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1070 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1071 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1072 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1073 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1074 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1075 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1076 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1077 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1078 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1079 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1080 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1081 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1082 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1083 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1084 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1085 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1086 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1087 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1088 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1089 if (par->Architecture >= NV_ARCH_10)
1090 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1091 else
1092 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1093 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1094 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1095 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1096 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1097 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1098 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1099 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1100 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1101 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1102 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1103 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1104 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1105 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1106 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1107 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1108 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1109 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1110 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1111 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1112 if (par->WaitVSyncPossible)
1113 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1114 else
1115 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1116 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1117 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1118 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1119 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1120 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1121 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1122 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1123 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1124 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1125 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1126 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1127 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1128 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1129 NV_WR32(par->PRAMIN, 0x0826 * 4,
1130 par->FbUsableSize | 0x00000002);
1131 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1132 #ifdef __BIG_ENDIAN
1133 NV_WR32(par->PRAMIN, 0x0804 * 4,
1134 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1135 NV_WR32(par->PRAMIN, 0x0808 * 4,
1136 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1137 NV_WR32(par->PRAMIN, 0x080C * 4,
1138 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1139 NV_WR32(par->PRAMIN, 0x0810 * 4,
1140 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1141 NV_WR32(par->PRAMIN, 0x0814 * 4,
1142 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1143 NV_WR32(par->PRAMIN, 0x0818 * 4,
1144 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1145 NV_WR32(par->PRAMIN, 0x081C * 4,
1146 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1147 NV_WR32(par->PRAMIN, 0x0820 * 4,
1148 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1149 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1150 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1151 #endif
1152 }
1153 if (par->Architecture < NV_ARCH_10) {
1154 if ((par->Chipset & 0x0fff) == 0x0020) {
1155 NV_WR32(par->PRAMIN, 0x0824 * 4,
1156 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1157 NV_WR32(par->PRAMIN, 0x0826 * 4,
1158 NV_RD32(par->PRAMIN,
1159 0x0826 * 4) + par->FbAddress);
1160 }
1161 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1162 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1163 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1164 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1165 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1166 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1167 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1168 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1169 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1170 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1171 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1172 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1173 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1174 } else {
1175 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1176 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1177
1178 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1179 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1180 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1181 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1182 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1183 NV_WR32(par->PGRAPH, 0x0710,
1184 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1185 NV_WR32(par->PGRAPH, 0x0710,
1186 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1187
1188 if (par->Architecture == NV_ARCH_10) {
1189 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1190 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1191 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1192
1193 for (i = 0; i < 32; i++)
1194 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1195 NV_RD32(&par->PFB[(0x0240 / 4) + i],
1196 0));
1197
1198 NV_WR32(par->PGRAPH, 0x640, 0);
1199 NV_WR32(par->PGRAPH, 0x644, 0);
1200 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1201 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1202
1203 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1204 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1205 } else {
1206 if (par->Architecture >= NV_ARCH_40) {
1207 u32 tmp;
1208
1209 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1210 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1211 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1212 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1213
1214 tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
1215 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
1216 NV_WR32(par->PGRAPH, 0x5000, i);
1217
1218 if ((par->Chipset & 0xfff0) == 0x0040) {
1219 NV_WR32(par->PGRAPH, 0x09b0,
1220 0x83280fff);
1221 NV_WR32(par->PGRAPH, 0x09b4,
1222 0x000000a0);
1223 } else {
1224 NV_WR32(par->PGRAPH, 0x0820,
1225 0x83280eff);
1226 NV_WR32(par->PGRAPH, 0x0824,
1227 0x000000a0);
1228 }
1229
1230 switch (par->Chipset & 0xfff0) {
1231 case 0x0040:
1232 case 0x0210:
1233 NV_WR32(par->PGRAPH, 0x09b8,
1234 0x0078e366);
1235 NV_WR32(par->PGRAPH, 0x09bc,
1236 0x0000014c);
1237 NV_WR32(par->PFB, 0x033C,
1238 NV_RD32(par->PFB, 0x33C) &
1239 0xffff7fff);
1240 break;
1241 case 0x00C0:
1242 case 0x0120:
1243 NV_WR32(par->PGRAPH, 0x0828,
1244 0x007596ff);
1245 NV_WR32(par->PGRAPH, 0x082C,
1246 0x00000108);
1247 break;
1248 case 0x0160:
1249 case 0x01D0:
1250 case 0x0240:
1251 NV_WR32(par->PMC, 0x1700,
1252 NV_RD32(par->PFB, 0x020C));
1253 NV_WR32(par->PMC, 0x1704, 0);
1254 NV_WR32(par->PMC, 0x1708, 0);
1255 NV_WR32(par->PMC, 0x170C,
1256 NV_RD32(par->PFB, 0x020C));
1257 NV_WR32(par->PGRAPH, 0x0860, 0);
1258 NV_WR32(par->PGRAPH, 0x0864, 0);
1259 NV_WR32(par->PRAMDAC, 0x0608,
1260 NV_RD32(par->PRAMDAC,
1261 0x0608) | 0x00100000);
1262 break;
1263 case 0x0140:
1264 NV_WR32(par->PGRAPH, 0x0828,
1265 0x0072cb77);
1266 NV_WR32(par->PGRAPH, 0x082C,
1267 0x00000108);
1268 break;
1269 case 0x0220:
1270 case 0x0230:
1271 NV_WR32(par->PGRAPH, 0x0860, 0);
1272 NV_WR32(par->PGRAPH, 0x0864, 0);
1273 NV_WR32(par->PRAMDAC, 0x0608,
1274 NV_RD32(par->PRAMDAC, 0x0608) |
1275 0x00100000);
1276 break;
1277 case 0x0090:
1278 case 0x02E0:
1279 case 0x0290:
1280 NV_WR32(par->PRAMDAC, 0x0608,
1281 NV_RD32(par->PRAMDAC, 0x0608) |
1282 0x00100000);
1283 NV_WR32(par->PGRAPH, 0x0828,
1284 0x07830610);
1285 NV_WR32(par->PGRAPH, 0x082C,
1286 0x0000016A);
1287 break;
1288 default:
1289 break;
1290 };
1291
1292 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1293 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1294 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1295 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1296 } else if (par->Architecture == NV_ARCH_30) {
1297 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1298 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1299 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1300 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1301 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1302 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1303 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1304 } else {
1305 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1306 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1307 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1308 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1309
1310 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1311 NV_WR32(par->PGRAPH, 0x0890,
1312 0x00080000);
1313 NV_WR32(par->PGRAPH, 0x0610,
1314 0x304B1FB6);
1315 NV_WR32(par->PGRAPH, 0x0B80,
1316 0x18B82880);
1317 NV_WR32(par->PGRAPH, 0x0B84,
1318 0x44000000);
1319 NV_WR32(par->PGRAPH, 0x0098,
1320 0x40000080);
1321 NV_WR32(par->PGRAPH, 0x0B88,
1322 0x000000ff);
1323 } else {
1324 NV_WR32(par->PGRAPH, 0x0880,
1325 0x00080000);
1326 NV_WR32(par->PGRAPH, 0x0094,
1327 0x00000005);
1328 NV_WR32(par->PGRAPH, 0x0B80,
1329 0x45CAA208);
1330 NV_WR32(par->PGRAPH, 0x0B84,
1331 0x24000000);
1332 NV_WR32(par->PGRAPH, 0x0098,
1333 0x00000040);
1334 NV_WR32(par->PGRAPH, 0x0750,
1335 0x00E00038);
1336 NV_WR32(par->PGRAPH, 0x0754,
1337 0x00000030);
1338 NV_WR32(par->PGRAPH, 0x0750,
1339 0x00E10038);
1340 NV_WR32(par->PGRAPH, 0x0754,
1341 0x00000030);
1342 }
1343 }
1344
1345 if ((par->Architecture < NV_ARCH_40) ||
1346 ((par->Chipset & 0xfff0) == 0x0040)) {
1347 for (i = 0; i < 32; i++) {
1348 NV_WR32(par->PGRAPH, 0x0900 + i*4,
1349 NV_RD32(par->PFB, 0x0240 +i*4));
1350 NV_WR32(par->PGRAPH, 0x6900 + i*4,
1351 NV_RD32(par->PFB, 0x0240 +i*4));
1352 }
1353 } else {
1354 if (((par->Chipset & 0xfff0) == 0x0090) ||
1355 ((par->Chipset & 0xfff0) == 0x01D0) ||
1356 ((par->Chipset & 0xfff0) == 0x02E0) ||
1357 ((par->Chipset & 0xfff0) == 0x0290)) {
1358 for (i = 0; i < 60; i++) {
1359 NV_WR32(par->PGRAPH,
1360 0x0D00 + i*4,
1361 NV_RD32(par->PFB,
1362 0x0600 + i*4));
1363 NV_WR32(par->PGRAPH,
1364 0x6900 + i*4,
1365 NV_RD32(par->PFB,
1366 0x0600 + i*4));
1367 }
1368 } else {
1369 for (i = 0; i < 48; i++) {
1370 NV_WR32(par->PGRAPH,
1371 0x0900 + i*4,
1372 NV_RD32(par->PFB,
1373 0x0600 + i*4));
1374 if(((par->Chipset & 0xfff0)
1375 != 0x0160) &&
1376 ((par->Chipset & 0xfff0)
1377 != 0x0220) &&
1378 ((par->Chipset & 0xfff0)
1379 != 0x240))
1380 NV_WR32(par->PGRAPH,
1381 0x6900 + i*4,
1382 NV_RD32(par->PFB,
1383 0x0600 + i*4));
1384 }
1385 }
1386 }
1387
1388 if (par->Architecture >= NV_ARCH_40) {
1389 if ((par->Chipset & 0xfff0) == 0x0040) {
1390 NV_WR32(par->PGRAPH, 0x09A4,
1391 NV_RD32(par->PFB, 0x0200));
1392 NV_WR32(par->PGRAPH, 0x09A8,
1393 NV_RD32(par->PFB, 0x0204));
1394 NV_WR32(par->PGRAPH, 0x69A4,
1395 NV_RD32(par->PFB, 0x0200));
1396 NV_WR32(par->PGRAPH, 0x69A8,
1397 NV_RD32(par->PFB, 0x0204));
1398
1399 NV_WR32(par->PGRAPH, 0x0820, 0);
1400 NV_WR32(par->PGRAPH, 0x0824, 0);
1401 NV_WR32(par->PGRAPH, 0x0864,
1402 par->FbMapSize - 1);
1403 NV_WR32(par->PGRAPH, 0x0868,
1404 par->FbMapSize - 1);
1405 } else {
1406 if ((par->Chipset & 0xfff0) == 0x0090 ||
1407 (par->Chipset & 0xfff0) == 0x01D0 ||
1408 (par->Chipset & 0xfff0) == 0x02E0 ||
1409 (par->Chipset & 0xfff0) == 0x0290) {
1410 NV_WR32(par->PGRAPH, 0x0DF0,
1411 NV_RD32(par->PFB, 0x0200));
1412 NV_WR32(par->PGRAPH, 0x0DF4,
1413 NV_RD32(par->PFB, 0x0204));
1414 } else {
1415 NV_WR32(par->PGRAPH, 0x09F0,
1416 NV_RD32(par->PFB, 0x0200));
1417 NV_WR32(par->PGRAPH, 0x09F4,
1418 NV_RD32(par->PFB, 0x0204));
1419 }
1420 NV_WR32(par->PGRAPH, 0x69F0,
1421 NV_RD32(par->PFB, 0x0200));
1422 NV_WR32(par->PGRAPH, 0x69F4,
1423 NV_RD32(par->PFB, 0x0204));
1424
1425 NV_WR32(par->PGRAPH, 0x0840, 0);
1426 NV_WR32(par->PGRAPH, 0x0844, 0);
1427 NV_WR32(par->PGRAPH, 0x08a0,
1428 par->FbMapSize - 1);
1429 NV_WR32(par->PGRAPH, 0x08a4,
1430 par->FbMapSize - 1);
1431 }
1432 } else {
1433 NV_WR32(par->PGRAPH, 0x09A4,
1434 NV_RD32(par->PFB, 0x0200));
1435 NV_WR32(par->PGRAPH, 0x09A8,
1436 NV_RD32(par->PFB, 0x0204));
1437 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1438 NV_WR32(par->PGRAPH, 0x0754,
1439 NV_RD32(par->PFB, 0x0200));
1440 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1441 NV_WR32(par->PGRAPH, 0x0754,
1442 NV_RD32(par->PFB, 0x0204));
1443
1444 NV_WR32(par->PGRAPH, 0x0820, 0);
1445 NV_WR32(par->PGRAPH, 0x0824, 0);
1446 NV_WR32(par->PGRAPH, 0x0864,
1447 par->FbMapSize - 1);
1448 NV_WR32(par->PGRAPH, 0x0868,
1449 par->FbMapSize - 1);
1450 }
1451 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1452 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1453 }
1454 }
1455 NV_WR32(par->PGRAPH, 0x053C, 0);
1456 NV_WR32(par->PGRAPH, 0x0540, 0);
1457 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1458 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1459
1460 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1461 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1462 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1463 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1464 if (par->Architecture >= NV_ARCH_40)
1465 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1466 else
1467 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1468 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1469 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1470 if (par->Architecture >= NV_ARCH_40)
1471 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1472 else
1473 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1474 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1475 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1476 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1477 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1478 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1479 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1480 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1481 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1482 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1483 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1484 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1485 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1486 #ifdef __BIG_ENDIAN
1487 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1488 #else
1489 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1490 #endif
1491 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1492 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1493 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1494 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1495 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1496 if (par->Architecture >= NV_ARCH_10) {
1497 if (par->twoHeads) {
1498 NV_WR32(par->PCRTC0, 0x0860, state->head);
1499 NV_WR32(par->PCRTC0, 0x2860, state->head2);
1500 }
1501 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1502 (1 << 25));
1503
1504 NV_WR32(par->PMC, 0x8704, 1);
1505 NV_WR32(par->PMC, 0x8140, 0);
1506 NV_WR32(par->PMC, 0x8920, 0);
1507 NV_WR32(par->PMC, 0x8924, 0);
1508 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1509 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1510 NV_WR32(par->PMC, 0x1588, 0);
1511
1512 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1513 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1514 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1515
1516 if (par->FlatPanel) {
1517 if ((par->Chipset & 0x0ff0) == 0x0110) {
1518 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1519 } else if (par->twoHeads) {
1520 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1521 }
1522
1523 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1524 VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1525 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1526 VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1527 VGA_WR08(par->PCIO, 0x03D4, 0x21);
1528 VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1529 }
1530
1531 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1532 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1533 }
1534
1535 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1536 VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1537 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1538 VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1539 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1540 VGA_WR08(par->PCIO, 0x03D5, state->screen);
1541 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1542 VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1543 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1544 VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1545 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1546 VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1547 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1548 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1549 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1550 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1551
1552 if(par->Architecture >= NV_ARCH_30) {
1553 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1554 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1555 }
1556
1557 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1558 VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1559 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1560 VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1561 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1562 VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1563 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1564 VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1565
1566 if (!par->FlatPanel) {
1567 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1568 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1569 if (par->twoHeads)
1570 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1571 if (par->twoStagePLL) {
1572 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1573 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1574 }
1575 } else {
1576 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1577 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1578 par->PanelTweak);
1579 }
1580
1581 NV_WR32(par->PRAMDAC, 0x0600, state->general);
1582
1583 NV_WR32(par->PCRTC, 0x0140, 0);
1584 NV_WR32(par->PCRTC, 0x0100, 1);
1585
1586 par->CurrentState = state;
1587 }
1588
1589 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1590 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1591 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1592 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1593 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1594 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1595 state->screen = VGA_RD08(par->PCIO, 0x03D5);
1596 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1597 state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1598 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1599 state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1600 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1601 state->fifo = VGA_RD08(par->PCIO, 0x03D5);
1602 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1603 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1604 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1605 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1606
1607 if(par->Architecture >= NV_ARCH_30) {
1608 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1609 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1610 }
1611
1612 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1613 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1614 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1615 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1616 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1617 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1618 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1619 state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1620 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1621 if (par->twoHeads)
1622 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1623 if (par->twoStagePLL) {
1624 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1625 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1626 }
1627 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1628 state->general = NV_RD32(par->PRAMDAC, 0x0600);
1629 state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1630 state->config = NV_RD32(par->PFB, 0x0200);
1631
1632 if (par->Architecture >= NV_ARCH_10) {
1633 if (par->twoHeads) {
1634 state->head = NV_RD32(par->PCRTC0, 0x0860);
1635 state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1636 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1637 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1638 }
1639 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1640 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1641 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1642
1643 if ((par->Chipset & 0x0ff0) == 0x0110) {
1644 state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1645 } else if (par->twoHeads) {
1646 state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1647 }
1648
1649 if (par->FlatPanel) {
1650 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1651 state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1652 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1653 state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1654 }
1655 }
1656 }
1657
1658 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1659 {
1660 NV_WR32(par->PCRTC, 0x800, start);
1661 }
kernel source for telekom puls (alcatel/mediatek)