3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
30 #include <mach/hardware.h>
32 #include <mach/mx3fb.h>
35 #include <asm/uaccess.h>
37 #define MX3FB_NAME "mx3_sdc_fb"
39 #define MX3FB_REG_OFFSET 0xB4
42 #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
43 #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
44 #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
45 #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
46 #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
47 #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
48 #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
49 #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
50 #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
51 #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
55 #define SDC_COM_TFT_COLOR 0x00000001UL
56 #define SDC_COM_FG_EN 0x00000010UL
57 #define SDC_COM_GWSEL 0x00000020UL
58 #define SDC_COM_GLB_A 0x00000040UL
59 #define SDC_COM_KEY_COLOR_G 0x00000080UL
60 #define SDC_COM_BG_EN 0x00000200UL
61 #define SDC_COM_SHARP 0x00001000UL
63 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
65 /* Display Interface registers */
66 #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
67 #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
68 #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
70 #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
71 #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
74 #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
77 #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
80 #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
81 #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
87 #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
90 #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
93 #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
99 #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
102 #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
103 #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
106 /* DI_DISP_SIG_POL bits */
107 #define DI_D3_VSYNC_POL_SHIFT 28
108 #define DI_D3_HSYNC_POL_SHIFT 27
109 #define DI_D3_DRDY_SHARP_POL_SHIFT 26
110 #define DI_D3_CLK_POL_SHIFT 25
111 #define DI_D3_DATA_POL_SHIFT 24
113 /* DI_DISP_IF_CONF bits */
114 #define DI_D3_CLK_IDLE_SHIFT 26
115 #define DI_D3_CLK_SEL_SHIFT 25
116 #define DI_D3_DATAMSK_SHIFT 24
123 struct ipu_di_signal_cfg
{
124 unsigned datamask_en
:1;
125 unsigned clksel_en
:1;
126 unsigned clkidle_en
:1;
127 unsigned data_pol
:1; /* true = inverted */
128 unsigned clk_pol
:1; /* true = rising edge */
129 unsigned enable_pol
:1;
130 unsigned Hsync_pol
:1; /* true = active high */
131 unsigned Vsync_pol
:1;
134 static const struct fb_videomode mx3fb_modedb
[] = {
136 /* 240x320 @ 60 Hz */
137 .name
= "Sharp-QVGA",
148 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_SHARP_MODE
|
149 FB_SYNC_CLK_INVERT
| FB_SYNC_DATA_INVERT
|
151 .vmode
= FB_VMODE_NONINTERLACED
,
163 .lower_margin
= 9 + 287,
166 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_SHARP_MODE
|
167 FB_SYNC_CLK_INVERT
| FB_SYNC_DATA_INVERT
|
169 .vmode
= FB_VMODE_NONINTERLACED
,
172 /* 640x480 @ 60 Hz */
184 .sync
= FB_SYNC_VERT_HIGH_ACT
| FB_SYNC_OE_ACT_HIGH
,
185 .vmode
= FB_VMODE_NONINTERLACED
,
195 .right_margin
= 858 - 640 - 38 - 3,
197 .lower_margin
= 518 - 480 - 36 - 1,
201 .vmode
= FB_VMODE_NONINTERLACED
,
211 .right_margin
= 960 - 640 - 38 - 32,
213 .lower_margin
= 555 - 480 - 32 - 3,
217 .vmode
= FB_VMODE_NONINTERLACED
,
220 /* TV output VGA mode, 640x480 @ 65 Hz */
233 .vmode
= FB_VMODE_NONINTERLACED
,
241 void __iomem
*reg_base
;
245 uint32_t h_start_width
;
246 uint32_t v_start_width
;
249 struct dma_chan_request
{
250 struct mx3fb_data
*mx3fb
;
254 /* MX3 specific framebuffer information. */
257 enum ipu_channel ipu_ch
;
258 uint32_t cur_ipu_buf
;
260 u32 pseudo_palette
[16];
262 struct completion flip_cmpl
;
263 struct mutex mutex
; /* Protects fb-ops */
264 struct mx3fb_data
*mx3fb
;
265 struct idmac_channel
*idmac_channel
;
266 struct dma_async_tx_descriptor
*txd
;
268 struct scatterlist sg
[2];
270 u32 sync
; /* preserve var->sync flags */
273 static void mx3fb_dma_done(void *);
275 /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
276 static const char *fb_mode
;
277 static unsigned long default_bpp
= 16;
279 static u32
mx3fb_read_reg(struct mx3fb_data
*mx3fb
, unsigned long reg
)
281 return __raw_readl(mx3fb
->reg_base
+ reg
);
284 static void mx3fb_write_reg(struct mx3fb_data
*mx3fb
, u32 value
, unsigned long reg
)
286 __raw_writel(value
, mx3fb
->reg_base
+ reg
);
289 static const uint32_t di_mappings
[] = {
290 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
291 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
292 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
293 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
296 static void sdc_fb_init(struct mx3fb_info
*fbi
)
298 struct mx3fb_data
*mx3fb
= fbi
->mx3fb
;
301 reg
= mx3fb_read_reg(mx3fb
, SDC_COM_CONF
);
303 mx3fb_write_reg(mx3fb
, reg
| SDC_COM_BG_EN
, SDC_COM_CONF
);
306 /* Returns enabled flag before uninit */
307 static uint32_t sdc_fb_uninit(struct mx3fb_info
*fbi
)
309 struct mx3fb_data
*mx3fb
= fbi
->mx3fb
;
312 reg
= mx3fb_read_reg(mx3fb
, SDC_COM_CONF
);
314 mx3fb_write_reg(mx3fb
, reg
& ~SDC_COM_BG_EN
, SDC_COM_CONF
);
316 return reg
& SDC_COM_BG_EN
;
319 static void sdc_enable_channel(struct mx3fb_info
*mx3_fbi
)
321 struct mx3fb_data
*mx3fb
= mx3_fbi
->mx3fb
;
322 struct idmac_channel
*ichan
= mx3_fbi
->idmac_channel
;
323 struct dma_chan
*dma_chan
= &ichan
->dma_chan
;
327 dev_dbg(mx3fb
->dev
, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi
,
328 to_tx_desc(mx3_fbi
->txd
), to_tx_desc(mx3_fbi
->txd
)->sg
);
330 /* This enables the channel */
331 if (mx3_fbi
->cookie
< 0) {
332 mx3_fbi
->txd
= dma_chan
->device
->device_prep_slave_sg(dma_chan
,
333 &mx3_fbi
->sg
[0], 1, DMA_TO_DEVICE
, DMA_PREP_INTERRUPT
);
335 dev_err(mx3fb
->dev
, "Cannot allocate descriptor on %d\n",
340 mx3_fbi
->txd
->callback_param
= mx3_fbi
->txd
;
341 mx3_fbi
->txd
->callback
= mx3fb_dma_done
;
343 cookie
= mx3_fbi
->txd
->tx_submit(mx3_fbi
->txd
);
344 dev_dbg(mx3fb
->dev
, "%d: Submit %p #%d [%c]\n", __LINE__
,
345 mx3_fbi
->txd
, cookie
, list_empty(&ichan
->queue
) ? '-' : '+');
347 if (!mx3_fbi
->txd
|| !mx3_fbi
->txd
->tx_submit
) {
348 dev_err(mx3fb
->dev
, "Cannot enable channel %d\n",
353 /* Just re-activate the same buffer */
354 dma_async_issue_pending(dma_chan
);
355 cookie
= mx3_fbi
->cookie
;
356 dev_dbg(mx3fb
->dev
, "%d: Re-submit %p #%d [%c]\n", __LINE__
,
357 mx3_fbi
->txd
, cookie
, list_empty(&ichan
->queue
) ? '-' : '+');
361 spin_lock_irqsave(&mx3fb
->lock
, flags
);
362 sdc_fb_init(mx3_fbi
);
363 mx3_fbi
->cookie
= cookie
;
364 spin_unlock_irqrestore(&mx3fb
->lock
, flags
);
368 * Attention! Without this msleep the channel keeps generating
369 * interrupts. Next sdc_set_brightness() is going to be called
370 * from mx3fb_blank().
375 static void sdc_disable_channel(struct mx3fb_info
*mx3_fbi
)
377 struct mx3fb_data
*mx3fb
= mx3_fbi
->mx3fb
;
381 spin_lock_irqsave(&mx3fb
->lock
, flags
);
383 enabled
= sdc_fb_uninit(mx3_fbi
);
385 spin_unlock_irqrestore(&mx3fb
->lock
, flags
);
387 mx3_fbi
->txd
->chan
->device
->device_terminate_all(mx3_fbi
->txd
->chan
);
389 mx3_fbi
->cookie
= -EINVAL
;
393 * sdc_set_window_pos() - set window position of the respective plane.
394 * @mx3fb: mx3fb context.
395 * @channel: IPU DMAC channel ID.
396 * @x_pos: X coordinate relative to the top left corner to place window at.
397 * @y_pos: Y coordinate relative to the top left corner to place window at.
398 * @return: 0 on success or negative error code on failure.
400 static int sdc_set_window_pos(struct mx3fb_data
*mx3fb
, enum ipu_channel channel
,
401 int16_t x_pos
, int16_t y_pos
)
403 x_pos
+= mx3fb
->h_start_width
;
404 y_pos
+= mx3fb
->v_start_width
;
406 if (channel
!= IDMAC_SDC_0
)
409 mx3fb_write_reg(mx3fb
, (x_pos
<< 16) | y_pos
, SDC_BG_POS
);
414 * sdc_init_panel() - initialize a synchronous LCD panel.
415 * @mx3fb: mx3fb context.
416 * @panel: panel type.
417 * @pixel_clk: desired pixel clock frequency in Hz.
418 * @width: width of panel in pixels.
419 * @height: height of panel in pixels.
420 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
421 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
422 * and the start of valid data.
423 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
424 * @h_end_width: number of pixel clocks between the end of valid data
425 * and the HSYNC signal for next line.
426 * @v_start_width: number of lines between the VSYNC signal pulse and the
427 * start of valid data.
428 * @v_sync_width: width of the VSYNC signal in units of lines
429 * @v_end_width: number of lines between the end of valid data and the
430 * VSYNC signal for next frame.
431 * @sig: bitfield of signal polarities for LCD interface.
432 * @return: 0 on success or negative error code on failure.
434 static int sdc_init_panel(struct mx3fb_data
*mx3fb
, enum ipu_panel panel
,
436 uint16_t width
, uint16_t height
,
437 enum pixel_fmt pixel_fmt
,
438 uint16_t h_start_width
, uint16_t h_sync_width
,
439 uint16_t h_end_width
, uint16_t v_start_width
,
440 uint16_t v_sync_width
, uint16_t v_end_width
,
441 struct ipu_di_signal_cfg sig
)
443 unsigned long lock_flags
;
449 dev_dbg(mx3fb
->dev
, "panel size = %d x %d", width
, height
);
451 if (v_sync_width
== 0 || h_sync_width
== 0)
454 /* Init panel size and blanking periods */
455 reg
= ((uint32_t) (h_sync_width
- 1) << 26) |
456 ((uint32_t) (width
+ h_start_width
+ h_end_width
- 1) << 16);
457 mx3fb_write_reg(mx3fb
, reg
, SDC_HOR_CONF
);
460 printk(KERN_CONT
" hor_conf %x,", reg
);
463 reg
= ((uint32_t) (v_sync_width
- 1) << 26) | SDC_V_SYNC_WIDTH_L
|
464 ((uint32_t) (height
+ v_start_width
+ v_end_width
- 1) << 16);
465 mx3fb_write_reg(mx3fb
, reg
, SDC_VER_CONF
);
468 printk(KERN_CONT
" ver_conf %x\n", reg
);
471 mx3fb
->h_start_width
= h_start_width
;
472 mx3fb
->v_start_width
= v_start_width
;
475 case IPU_PANEL_SHARP_TFT
:
476 mx3fb_write_reg(mx3fb
, 0x00FD0102L
, SDC_SHARP_CONF_1
);
477 mx3fb_write_reg(mx3fb
, 0x00F500F4L
, SDC_SHARP_CONF_2
);
478 mx3fb_write_reg(mx3fb
, SDC_COM_SHARP
| SDC_COM_TFT_COLOR
, SDC_COM_CONF
);
481 mx3fb_write_reg(mx3fb
, SDC_COM_TFT_COLOR
, SDC_COM_CONF
);
490 * Calculate divider: fractional part is 4 bits so simply multiple by
491 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
492 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
494 dev_dbg(mx3fb
->dev
, "pixel clk = %d\n", pixel_clk
);
496 ipu_clk
= clk_get(mx3fb
->dev
, "ipu_clk");
497 div
= clk_get_rate(ipu_clk
) * 16 / pixel_clk
;
500 if (div
< 0x40) { /* Divider less than 4 */
502 "InitPanel() - Pixel clock divider less than 4\n");
506 spin_lock_irqsave(&mx3fb
->lock
, lock_flags
);
509 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
510 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
511 * debug. DISP3_IF_CLK_UP_WR is 0
513 mx3fb_write_reg(mx3fb
, (((div
/ 8) - 1) << 22) | div
, DI_DISP3_TIME_CONF
);
516 old_conf
= mx3fb_read_reg(mx3fb
, DI_DISP_IF_CONF
) & 0x78FFFFFF;
517 old_conf
|= sig
.datamask_en
<< DI_D3_DATAMSK_SHIFT
|
518 sig
.clksel_en
<< DI_D3_CLK_SEL_SHIFT
|
519 sig
.clkidle_en
<< DI_D3_CLK_IDLE_SHIFT
;
520 mx3fb_write_reg(mx3fb
, old_conf
, DI_DISP_IF_CONF
);
522 old_conf
= mx3fb_read_reg(mx3fb
, DI_DISP_SIG_POL
) & 0xE0FFFFFF;
523 old_conf
|= sig
.data_pol
<< DI_D3_DATA_POL_SHIFT
|
524 sig
.clk_pol
<< DI_D3_CLK_POL_SHIFT
|
525 sig
.enable_pol
<< DI_D3_DRDY_SHARP_POL_SHIFT
|
526 sig
.Hsync_pol
<< DI_D3_HSYNC_POL_SHIFT
|
527 sig
.Vsync_pol
<< DI_D3_VSYNC_POL_SHIFT
;
528 mx3fb_write_reg(mx3fb
, old_conf
, DI_DISP_SIG_POL
);
531 case IPU_PIX_FMT_RGB24
:
532 mx3fb_write_reg(mx3fb
, di_mappings
[0], DI_DISP3_B0_MAP
);
533 mx3fb_write_reg(mx3fb
, di_mappings
[1], DI_DISP3_B1_MAP
);
534 mx3fb_write_reg(mx3fb
, di_mappings
[2], DI_DISP3_B2_MAP
);
535 mx3fb_write_reg(mx3fb
, mx3fb_read_reg(mx3fb
, DI_DISP_ACC_CC
) |
536 ((di_mappings
[3] - 1) << 12), DI_DISP_ACC_CC
);
538 case IPU_PIX_FMT_RGB666
:
539 mx3fb_write_reg(mx3fb
, di_mappings
[4], DI_DISP3_B0_MAP
);
540 mx3fb_write_reg(mx3fb
, di_mappings
[5], DI_DISP3_B1_MAP
);
541 mx3fb_write_reg(mx3fb
, di_mappings
[6], DI_DISP3_B2_MAP
);
542 mx3fb_write_reg(mx3fb
, mx3fb_read_reg(mx3fb
, DI_DISP_ACC_CC
) |
543 ((di_mappings
[7] - 1) << 12), DI_DISP_ACC_CC
);
545 case IPU_PIX_FMT_BGR666
:
546 mx3fb_write_reg(mx3fb
, di_mappings
[8], DI_DISP3_B0_MAP
);
547 mx3fb_write_reg(mx3fb
, di_mappings
[9], DI_DISP3_B1_MAP
);
548 mx3fb_write_reg(mx3fb
, di_mappings
[10], DI_DISP3_B2_MAP
);
549 mx3fb_write_reg(mx3fb
, mx3fb_read_reg(mx3fb
, DI_DISP_ACC_CC
) |
550 ((di_mappings
[11] - 1) << 12), DI_DISP_ACC_CC
);
553 mx3fb_write_reg(mx3fb
, di_mappings
[12], DI_DISP3_B0_MAP
);
554 mx3fb_write_reg(mx3fb
, di_mappings
[13], DI_DISP3_B1_MAP
);
555 mx3fb_write_reg(mx3fb
, di_mappings
[14], DI_DISP3_B2_MAP
);
556 mx3fb_write_reg(mx3fb
, mx3fb_read_reg(mx3fb
, DI_DISP_ACC_CC
) |
557 ((di_mappings
[15] - 1) << 12), DI_DISP_ACC_CC
);
561 spin_unlock_irqrestore(&mx3fb
->lock
, lock_flags
);
563 dev_dbg(mx3fb
->dev
, "DI_DISP_IF_CONF = 0x%08X\n",
564 mx3fb_read_reg(mx3fb
, DI_DISP_IF_CONF
));
565 dev_dbg(mx3fb
->dev
, "DI_DISP_SIG_POL = 0x%08X\n",
566 mx3fb_read_reg(mx3fb
, DI_DISP_SIG_POL
));
567 dev_dbg(mx3fb
->dev
, "DI_DISP3_TIME_CONF = 0x%08X\n",
568 mx3fb_read_reg(mx3fb
, DI_DISP3_TIME_CONF
));
574 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
575 * @mx3fb: mx3fb context.
576 * @channel: IPU DMAC channel ID.
577 * @enable: boolean to enable or disable color keyl.
578 * @color_key: 24-bit RGB color to use as transparent color key.
579 * @return: 0 on success or negative error code on failure.
581 static int sdc_set_color_key(struct mx3fb_data
*mx3fb
, enum ipu_channel channel
,
582 bool enable
, uint32_t color_key
)
584 uint32_t reg
, sdc_conf
;
585 unsigned long lock_flags
;
587 spin_lock_irqsave(&mx3fb
->lock
, lock_flags
);
589 sdc_conf
= mx3fb_read_reg(mx3fb
, SDC_COM_CONF
);
590 if (channel
== IDMAC_SDC_0
)
591 sdc_conf
&= ~SDC_COM_GWSEL
;
593 sdc_conf
|= SDC_COM_GWSEL
;
596 reg
= mx3fb_read_reg(mx3fb
, SDC_GW_CTRL
) & 0xFF000000L
;
597 mx3fb_write_reg(mx3fb
, reg
| (color_key
& 0x00FFFFFFL
),
600 sdc_conf
|= SDC_COM_KEY_COLOR_G
;
602 sdc_conf
&= ~SDC_COM_KEY_COLOR_G
;
604 mx3fb_write_reg(mx3fb
, sdc_conf
, SDC_COM_CONF
);
606 spin_unlock_irqrestore(&mx3fb
->lock
, lock_flags
);
612 * sdc_set_global_alpha() - set global alpha blending modes.
613 * @mx3fb: mx3fb context.
614 * @enable: boolean to enable or disable global alpha blending. If disabled,
615 * per pixel blending is used.
616 * @alpha: global alpha value.
617 * @return: 0 on success or negative error code on failure.
619 static int sdc_set_global_alpha(struct mx3fb_data
*mx3fb
, bool enable
, uint8_t alpha
)
622 unsigned long lock_flags
;
624 spin_lock_irqsave(&mx3fb
->lock
, lock_flags
);
627 reg
= mx3fb_read_reg(mx3fb
, SDC_GW_CTRL
) & 0x00FFFFFFL
;
628 mx3fb_write_reg(mx3fb
, reg
| ((uint32_t) alpha
<< 24), SDC_GW_CTRL
);
630 reg
= mx3fb_read_reg(mx3fb
, SDC_COM_CONF
);
631 mx3fb_write_reg(mx3fb
, reg
| SDC_COM_GLB_A
, SDC_COM_CONF
);
633 reg
= mx3fb_read_reg(mx3fb
, SDC_COM_CONF
);
634 mx3fb_write_reg(mx3fb
, reg
& ~SDC_COM_GLB_A
, SDC_COM_CONF
);
637 spin_unlock_irqrestore(&mx3fb
->lock
, lock_flags
);
642 static void sdc_set_brightness(struct mx3fb_data
*mx3fb
, uint8_t value
)
644 /* This might be board-specific */
645 mx3fb_write_reg(mx3fb
, 0x03000000UL
| value
<< 16, SDC_PWM_CTRL
);
649 static uint32_t bpp_to_pixfmt(int bpp
)
654 pixfmt
= IPU_PIX_FMT_BGR24
;
657 pixfmt
= IPU_PIX_FMT_BGR32
;
660 pixfmt
= IPU_PIX_FMT_RGB565
;
666 static int mx3fb_blank(int blank
, struct fb_info
*fbi
);
667 static int mx3fb_map_video_memory(struct fb_info
*fbi
);
668 static int mx3fb_unmap_video_memory(struct fb_info
*fbi
);
671 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
672 * @info: framebuffer information pointer
673 * @return: 0 on success or negative error code on failure.
675 static int mx3fb_set_fix(struct fb_info
*fbi
)
677 struct fb_fix_screeninfo
*fix
= &fbi
->fix
;
678 struct fb_var_screeninfo
*var
= &fbi
->var
;
680 strncpy(fix
->id
, "DISP3 BG", 8);
682 fix
->line_length
= var
->xres_virtual
* var
->bits_per_pixel
/ 8;
684 fix
->type
= FB_TYPE_PACKED_PIXELS
;
685 fix
->accel
= FB_ACCEL_NONE
;
686 fix
->visual
= FB_VISUAL_TRUECOLOR
;
693 static void mx3fb_dma_done(void *arg
)
695 struct idmac_tx_desc
*tx_desc
= to_tx_desc(arg
);
696 struct dma_chan
*chan
= tx_desc
->txd
.chan
;
697 struct idmac_channel
*ichannel
= to_idmac_chan(chan
);
698 struct mx3fb_data
*mx3fb
= ichannel
->client
;
699 struct mx3fb_info
*mx3_fbi
= mx3fb
->fbi
->par
;
701 dev_dbg(mx3fb
->dev
, "irq %d callback\n", ichannel
->eof_irq
);
703 /* We only need one interrupt, it will be re-enabled as needed */
704 disable_irq(ichannel
->eof_irq
);
706 complete(&mx3_fbi
->flip_cmpl
);
710 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
711 * @fbi: framebuffer information pointer.
712 * @return: 0 on success or negative error code on failure.
714 static int mx3fb_set_par(struct fb_info
*fbi
)
717 struct ipu_di_signal_cfg sig_cfg
;
718 enum ipu_panel mode
= IPU_PANEL_TFT
;
719 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
720 struct mx3fb_data
*mx3fb
= mx3_fbi
->mx3fb
;
721 struct idmac_channel
*ichan
= mx3_fbi
->idmac_channel
;
722 struct idmac_video_param
*video
= &ichan
->params
.video
;
723 struct scatterlist
*sg
= mx3_fbi
->sg
;
726 dev_dbg(mx3fb
->dev
, "%s [%c]\n", __func__
, list_empty(&ichan
->queue
) ? '-' : '+');
728 mutex_lock(&mx3_fbi
->mutex
);
732 sdc_disable_channel(mx3_fbi
);
736 mem_len
= fbi
->var
.yres_virtual
* fbi
->fix
.line_length
;
737 if (mem_len
> fbi
->fix
.smem_len
) {
738 if (fbi
->fix
.smem_start
)
739 mx3fb_unmap_video_memory(fbi
);
741 fbi
->fix
.smem_len
= mem_len
;
742 if (mx3fb_map_video_memory(fbi
) < 0) {
743 mutex_unlock(&mx3_fbi
->mutex
);
748 screen_size
= fbi
->fix
.line_length
* fbi
->var
.yres
;
750 sg_init_table(&sg
[0], 1);
751 sg_init_table(&sg
[1], 1);
753 sg_dma_address(&sg
[0]) = fbi
->fix
.smem_start
;
754 sg_set_page(&sg
[0], virt_to_page(fbi
->screen_base
),
756 offset_in_page(fbi
->screen_base
));
758 if (mx3_fbi
->ipu_ch
== IDMAC_SDC_0
) {
759 memset(&sig_cfg
, 0, sizeof(sig_cfg
));
760 if (fbi
->var
.sync
& FB_SYNC_HOR_HIGH_ACT
)
761 sig_cfg
.Hsync_pol
= true;
762 if (fbi
->var
.sync
& FB_SYNC_VERT_HIGH_ACT
)
763 sig_cfg
.Vsync_pol
= true;
764 if (fbi
->var
.sync
& FB_SYNC_CLK_INVERT
)
765 sig_cfg
.clk_pol
= true;
766 if (fbi
->var
.sync
& FB_SYNC_DATA_INVERT
)
767 sig_cfg
.data_pol
= true;
768 if (fbi
->var
.sync
& FB_SYNC_OE_ACT_HIGH
)
769 sig_cfg
.enable_pol
= true;
770 if (fbi
->var
.sync
& FB_SYNC_CLK_IDLE_EN
)
771 sig_cfg
.clkidle_en
= true;
772 if (fbi
->var
.sync
& FB_SYNC_CLK_SEL_EN
)
773 sig_cfg
.clksel_en
= true;
774 if (fbi
->var
.sync
& FB_SYNC_SHARP_MODE
)
775 mode
= IPU_PANEL_SHARP_TFT
;
777 dev_dbg(fbi
->device
, "pixclock = %ul Hz\n",
778 (u32
) (PICOS2KHZ(fbi
->var
.pixclock
) * 1000UL));
780 if (sdc_init_panel(mx3fb
, mode
,
781 (PICOS2KHZ(fbi
->var
.pixclock
)) * 1000UL,
782 fbi
->var
.xres
, fbi
->var
.yres
,
783 (fbi
->var
.sync
& FB_SYNC_SWAP_RGB
) ?
784 IPU_PIX_FMT_BGR666
: IPU_PIX_FMT_RGB666
,
785 fbi
->var
.left_margin
,
787 fbi
->var
.right_margin
+
789 fbi
->var
.upper_margin
,
791 fbi
->var
.lower_margin
+
792 fbi
->var
.vsync_len
, sig_cfg
) != 0) {
793 mutex_unlock(&mx3_fbi
->mutex
);
795 "mx3fb: Error initializing panel.\n");
800 sdc_set_window_pos(mx3fb
, mx3_fbi
->ipu_ch
, 0, 0);
802 mx3_fbi
->cur_ipu_buf
= 0;
804 video
->out_pixel_fmt
= bpp_to_pixfmt(fbi
->var
.bits_per_pixel
);
805 video
->out_width
= fbi
->var
.xres
;
806 video
->out_height
= fbi
->var
.yres
;
807 video
->out_stride
= fbi
->var
.xres_virtual
;
809 if (mx3_fbi
->blank
== FB_BLANK_UNBLANK
)
810 sdc_enable_channel(mx3_fbi
);
812 mutex_unlock(&mx3_fbi
->mutex
);
818 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
819 * @var: framebuffer variable parameters
820 * @fbi: framebuffer information pointer
822 static int mx3fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*fbi
)
824 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
828 dev_dbg(fbi
->device
, "%s\n", __func__
);
830 if (var
->xres_virtual
< var
->xres
)
831 var
->xres_virtual
= var
->xres
;
832 if (var
->yres_virtual
< var
->yres
)
833 var
->yres_virtual
= var
->yres
;
835 if ((var
->bits_per_pixel
!= 32) && (var
->bits_per_pixel
!= 24) &&
836 (var
->bits_per_pixel
!= 16))
837 var
->bits_per_pixel
= default_bpp
;
839 switch (var
->bits_per_pixel
) {
842 var
->red
.offset
= 11;
843 var
->red
.msb_right
= 0;
845 var
->green
.length
= 6;
846 var
->green
.offset
= 5;
847 var
->green
.msb_right
= 0;
849 var
->blue
.length
= 5;
850 var
->blue
.offset
= 0;
851 var
->blue
.msb_right
= 0;
853 var
->transp
.length
= 0;
854 var
->transp
.offset
= 0;
855 var
->transp
.msb_right
= 0;
859 var
->red
.offset
= 16;
860 var
->red
.msb_right
= 0;
862 var
->green
.length
= 8;
863 var
->green
.offset
= 8;
864 var
->green
.msb_right
= 0;
866 var
->blue
.length
= 8;
867 var
->blue
.offset
= 0;
868 var
->blue
.msb_right
= 0;
870 var
->transp
.length
= 0;
871 var
->transp
.offset
= 0;
872 var
->transp
.msb_right
= 0;
876 var
->red
.offset
= 16;
877 var
->red
.msb_right
= 0;
879 var
->green
.length
= 8;
880 var
->green
.offset
= 8;
881 var
->green
.msb_right
= 0;
883 var
->blue
.length
= 8;
884 var
->blue
.offset
= 0;
885 var
->blue
.msb_right
= 0;
887 var
->transp
.length
= 8;
888 var
->transp
.offset
= 24;
889 var
->transp
.msb_right
= 0;
893 if (var
->pixclock
< 1000) {
894 htotal
= var
->xres
+ var
->right_margin
+ var
->hsync_len
+
896 vtotal
= var
->yres
+ var
->lower_margin
+ var
->vsync_len
+
898 var
->pixclock
= (vtotal
* htotal
* 6UL) / 100UL;
899 var
->pixclock
= KHZ2PICOS(var
->pixclock
);
900 dev_dbg(fbi
->device
, "pixclock set for 60Hz refresh = %u ps\n",
908 /* Preserve sync flags */
909 var
->sync
|= mx3_fbi
->sync
;
910 mx3_fbi
->sync
|= var
->sync
;
915 static u32
chan_to_field(unsigned int chan
, struct fb_bitfield
*bf
)
918 chan
>>= 16 - bf
->length
;
919 return chan
<< bf
->offset
;
922 static int mx3fb_setcolreg(unsigned int regno
, unsigned int red
,
923 unsigned int green
, unsigned int blue
,
924 unsigned int trans
, struct fb_info
*fbi
)
926 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
930 dev_dbg(fbi
->device
, "%s\n", __func__
);
932 mutex_lock(&mx3_fbi
->mutex
);
934 * If greyscale is true, then we convert the RGB value
935 * to greyscale no matter what visual we are using.
937 if (fbi
->var
.grayscale
)
938 red
= green
= blue
= (19595 * red
+ 38470 * green
+
940 switch (fbi
->fix
.visual
) {
941 case FB_VISUAL_TRUECOLOR
:
943 * 16-bit True Colour. We encode the RGB value
944 * according to the RGB bitfield information.
947 u32
*pal
= fbi
->pseudo_palette
;
949 val
= chan_to_field(red
, &fbi
->var
.red
);
950 val
|= chan_to_field(green
, &fbi
->var
.green
);
951 val
|= chan_to_field(blue
, &fbi
->var
.blue
);
959 case FB_VISUAL_STATIC_PSEUDOCOLOR
:
960 case FB_VISUAL_PSEUDOCOLOR
:
963 mutex_unlock(&mx3_fbi
->mutex
);
969 * mx3fb_blank() - blank the display.
971 static int mx3fb_blank(int blank
, struct fb_info
*fbi
)
973 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
974 struct mx3fb_data
*mx3fb
= mx3_fbi
->mx3fb
;
976 dev_dbg(fbi
->device
, "%s\n", __func__
);
978 dev_dbg(fbi
->device
, "blank = %d\n", blank
);
980 if (mx3_fbi
->blank
== blank
)
983 mutex_lock(&mx3_fbi
->mutex
);
984 mx3_fbi
->blank
= blank
;
987 case FB_BLANK_POWERDOWN
:
988 case FB_BLANK_VSYNC_SUSPEND
:
989 case FB_BLANK_HSYNC_SUSPEND
:
990 case FB_BLANK_NORMAL
:
991 sdc_disable_channel(mx3_fbi
);
992 sdc_set_brightness(mx3fb
, 0);
994 case FB_BLANK_UNBLANK
:
995 sdc_enable_channel(mx3_fbi
);
996 sdc_set_brightness(mx3fb
, mx3fb
->backlight_level
);
999 mutex_unlock(&mx3_fbi
->mutex
);
1005 * mx3fb_pan_display() - pan or wrap the display
1006 * @var: variable screen buffer information.
1007 * @info: framebuffer information pointer.
1009 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1011 static int mx3fb_pan_display(struct fb_var_screeninfo
*var
,
1012 struct fb_info
*fbi
)
1014 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
1018 dma_cookie_t cookie
;
1019 struct scatterlist
*sg
= mx3_fbi
->sg
;
1020 struct dma_chan
*dma_chan
= &mx3_fbi
->idmac_channel
->dma_chan
;
1021 struct dma_async_tx_descriptor
*txd
;
1024 dev_dbg(fbi
->device
, "%s [%c]\n", __func__
,
1025 list_empty(&mx3_fbi
->idmac_channel
->queue
) ? '-' : '+');
1027 if (var
->xoffset
> 0) {
1028 dev_dbg(fbi
->device
, "x panning not supported\n");
1032 if (fbi
->var
.xoffset
== var
->xoffset
&&
1033 fbi
->var
.yoffset
== var
->yoffset
)
1034 return 0; /* No change, do nothing */
1036 y_bottom
= var
->yoffset
;
1038 if (!(var
->vmode
& FB_VMODE_YWRAP
))
1039 y_bottom
+= var
->yres
;
1041 if (y_bottom
> fbi
->var
.yres_virtual
)
1044 mutex_lock(&mx3_fbi
->mutex
);
1046 offset
= (var
->yoffset
* var
->xres_virtual
+ var
->xoffset
) *
1047 (var
->bits_per_pixel
/ 8);
1048 base
= fbi
->fix
.smem_start
+ offset
;
1050 dev_dbg(fbi
->device
, "Updating SDC BG buf %d address=0x%08lX\n",
1051 mx3_fbi
->cur_ipu_buf
, base
);
1054 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1055 * which we will need for the next device_prep_slave_sg(). The
1056 * IRQ-handler will disable the IRQ again.
1058 init_completion(&mx3_fbi
->flip_cmpl
);
1059 enable_irq(mx3_fbi
->idmac_channel
->eof_irq
);
1061 ret
= wait_for_completion_timeout(&mx3_fbi
->flip_cmpl
, HZ
/ 10);
1063 mutex_unlock(&mx3_fbi
->mutex
);
1064 dev_info(fbi
->device
, "Panning failed due to %s\n", ret
< 0 ?
1065 "user interrupt" : "timeout");
1066 return ret
? : -ETIMEDOUT
;
1069 mx3_fbi
->cur_ipu_buf
= !mx3_fbi
->cur_ipu_buf
;
1071 sg_dma_address(&sg
[mx3_fbi
->cur_ipu_buf
]) = base
;
1072 sg_set_page(&sg
[mx3_fbi
->cur_ipu_buf
],
1073 virt_to_page(fbi
->screen_base
+ offset
), fbi
->fix
.smem_len
,
1074 offset_in_page(fbi
->screen_base
+ offset
));
1076 txd
= dma_chan
->device
->device_prep_slave_sg(dma_chan
, sg
+
1077 mx3_fbi
->cur_ipu_buf
, 1, DMA_TO_DEVICE
, DMA_PREP_INTERRUPT
);
1079 dev_err(fbi
->device
,
1080 "Error preparing a DMA transaction descriptor.\n");
1081 mutex_unlock(&mx3_fbi
->mutex
);
1085 txd
->callback_param
= txd
;
1086 txd
->callback
= mx3fb_dma_done
;
1089 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1090 * should switch to another buffer
1092 cookie
= txd
->tx_submit(txd
);
1093 dev_dbg(fbi
->device
, "%d: Submit %p #%d\n", __LINE__
, txd
, cookie
);
1095 dev_err(fbi
->device
,
1096 "Error updating SDC buf %d to address=0x%08lX\n",
1097 mx3_fbi
->cur_ipu_buf
, base
);
1098 mutex_unlock(&mx3_fbi
->mutex
);
1103 async_tx_ack(mx3_fbi
->txd
);
1106 fbi
->var
.xoffset
= var
->xoffset
;
1107 fbi
->var
.yoffset
= var
->yoffset
;
1109 if (var
->vmode
& FB_VMODE_YWRAP
)
1110 fbi
->var
.vmode
|= FB_VMODE_YWRAP
;
1112 fbi
->var
.vmode
&= ~FB_VMODE_YWRAP
;
1114 mutex_unlock(&mx3_fbi
->mutex
);
1116 dev_dbg(fbi
->device
, "Update complete\n");
1122 * This structure contains the pointers to the control functions that are
1123 * invoked by the core framebuffer driver to perform operations like
1124 * blitting, rectangle filling, copy regions and cursor definition.
1126 static struct fb_ops mx3fb_ops
= {
1127 .owner
= THIS_MODULE
,
1128 .fb_set_par
= mx3fb_set_par
,
1129 .fb_check_var
= mx3fb_check_var
,
1130 .fb_setcolreg
= mx3fb_setcolreg
,
1131 .fb_pan_display
= mx3fb_pan_display
,
1132 .fb_fillrect
= cfb_fillrect
,
1133 .fb_copyarea
= cfb_copyarea
,
1134 .fb_imageblit
= cfb_imageblit
,
1135 .fb_blank
= mx3fb_blank
,
1140 * Power management hooks. Note that we won't be called from IRQ context,
1141 * unlike the blank functions above, so we may sleep.
1145 * Suspends the framebuffer and blanks the screen. Power management support
1147 static int mx3fb_suspend(struct platform_device
*pdev
, pm_message_t state
)
1149 struct mx3fb_data
*drv_data
= platform_get_drvdata(pdev
);
1150 struct mx3fb_info
*mx3_fbi
= drv_data
->fbi
->par
;
1152 acquire_console_sem();
1153 fb_set_suspend(drv_data
->fbi
, 1);
1154 release_console_sem();
1156 if (mx3_fbi
->blank
== FB_BLANK_UNBLANK
) {
1157 sdc_disable_channel(mx3_fbi
);
1158 sdc_set_brightness(mx3fb
, 0);
1165 * Resumes the framebuffer and unblanks the screen. Power management support
1167 static int mx3fb_resume(struct platform_device
*pdev
)
1169 struct mx3fb_data
*drv_data
= platform_get_drvdata(pdev
);
1170 struct mx3fb_info
*mx3_fbi
= drv_data
->fbi
->par
;
1172 if (mx3_fbi
->blank
== FB_BLANK_UNBLANK
) {
1173 sdc_enable_channel(mx3_fbi
);
1174 sdc_set_brightness(mx3fb
, drv_data
->backlight_level
);
1177 acquire_console_sem();
1178 fb_set_suspend(drv_data
->fbi
, 0);
1179 release_console_sem();
1184 #define mx3fb_suspend NULL
1185 #define mx3fb_resume NULL
1189 * Main framebuffer functions
1193 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1194 * @fbi: framebuffer information pointer
1195 * @return: Error code indicating success or failure
1197 * This buffer is remapped into a non-cached, non-buffered, memory region to
1198 * allow palette and pixel writes to occur without flushing the cache. Once this
1199 * area is remapped, all virtual memory access to the video memory should occur
1200 * at the new region.
1202 static int mx3fb_map_video_memory(struct fb_info
*fbi
)
1207 fbi
->screen_base
= dma_alloc_writecombine(fbi
->device
,
1211 if (!fbi
->screen_base
) {
1212 dev_err(fbi
->device
, "Cannot allocate %u bytes framebuffer memory\n",
1218 fbi
->fix
.smem_start
= addr
;
1220 dev_dbg(fbi
->device
, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1221 (uint32_t) fbi
->fix
.smem_start
, fbi
->screen_base
, fbi
->fix
.smem_len
);
1223 fbi
->screen_size
= fbi
->fix
.smem_len
;
1225 /* Clear the screen */
1226 memset((char *)fbi
->screen_base
, 0, fbi
->fix
.smem_len
);
1231 fbi
->fix
.smem_len
= 0;
1232 fbi
->fix
.smem_start
= 0;
1233 fbi
->screen_base
= NULL
;
1238 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1239 * @fbi: framebuffer information pointer
1240 * @return: error code indicating success or failure
1242 static int mx3fb_unmap_video_memory(struct fb_info
*fbi
)
1244 dma_free_writecombine(fbi
->device
, fbi
->fix
.smem_len
,
1245 fbi
->screen_base
, fbi
->fix
.smem_start
);
1247 fbi
->screen_base
= 0;
1248 fbi
->fix
.smem_start
= 0;
1249 fbi
->fix
.smem_len
= 0;
1254 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1255 * @return: initialized framebuffer structure.
1257 static struct fb_info
*mx3fb_init_fbinfo(struct device
*dev
, struct fb_ops
*ops
)
1259 struct fb_info
*fbi
;
1260 struct mx3fb_info
*mx3fbi
;
1263 /* Allocate sufficient memory for the fb structure */
1264 fbi
= framebuffer_alloc(sizeof(struct mx3fb_info
), dev
);
1269 mx3fbi
->cookie
= -EINVAL
;
1270 mx3fbi
->cur_ipu_buf
= 0;
1272 fbi
->var
.activate
= FB_ACTIVATE_NOW
;
1275 fbi
->flags
= FBINFO_FLAG_DEFAULT
;
1276 fbi
->pseudo_palette
= mx3fbi
->pseudo_palette
;
1278 mutex_init(&mx3fbi
->mutex
);
1280 /* Allocate colormap */
1281 ret
= fb_alloc_cmap(&fbi
->cmap
, 16, 0);
1283 framebuffer_release(fbi
);
1290 static int init_fb_chan(struct mx3fb_data
*mx3fb
, struct idmac_channel
*ichan
)
1292 struct device
*dev
= mx3fb
->dev
;
1293 struct mx3fb_platform_data
*mx3fb_pdata
= dev
->platform_data
;
1294 const char *name
= mx3fb_pdata
->name
;
1296 struct fb_info
*fbi
;
1297 struct mx3fb_info
*mx3fbi
;
1298 const struct fb_videomode
*mode
;
1301 ichan
->client
= mx3fb
;
1302 irq
= ichan
->eof_irq
;
1304 if (ichan
->dma_chan
.chan_id
!= IDMAC_SDC_0
)
1307 fbi
= mx3fb_init_fbinfo(dev
, &mx3fb_ops
);
1319 if (mx3fb_pdata
->mode
&& mx3fb_pdata
->num_modes
) {
1320 mode
= mx3fb_pdata
->mode
;
1321 num_modes
= mx3fb_pdata
->num_modes
;
1323 mode
= mx3fb_modedb
;
1324 num_modes
= ARRAY_SIZE(mx3fb_modedb
);
1327 if (!fb_find_mode(&fbi
->var
, fbi
, fb_mode
, mode
,
1328 num_modes
, NULL
, default_bpp
)) {
1333 fb_videomode_to_modelist(mode
, num_modes
, &fbi
->modelist
);
1335 /* Default Y virtual size is 2x panel size */
1336 fbi
->var
.yres_virtual
= fbi
->var
.yres
* 2;
1340 /* set Display Interface clock period */
1341 mx3fb_write_reg(mx3fb
, 0x00100010L
, DI_HSP_CLK_PER
);
1342 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1344 sdc_set_brightness(mx3fb
, 255);
1345 sdc_set_global_alpha(mx3fb
, true, 0xFF);
1346 sdc_set_color_key(mx3fb
, IDMAC_SDC_0
, false, 0);
1349 mx3fbi
->idmac_channel
= ichan
;
1350 mx3fbi
->ipu_ch
= ichan
->dma_chan
.chan_id
;
1351 mx3fbi
->mx3fb
= mx3fb
;
1352 mx3fbi
->blank
= FB_BLANK_NORMAL
;
1354 init_completion(&mx3fbi
->flip_cmpl
);
1355 disable_irq(ichan
->eof_irq
);
1356 dev_dbg(mx3fb
->dev
, "disabling irq %d\n", ichan
->eof_irq
);
1357 ret
= mx3fb_set_par(fbi
);
1361 mx3fb_blank(FB_BLANK_UNBLANK
, fbi
);
1363 dev_info(dev
, "mx3fb: fb registered, using mode %s\n", fb_mode
);
1365 ret
= register_framebuffer(fbi
);
1374 fb_dealloc_cmap(&fbi
->cmap
);
1375 framebuffer_release(fbi
);
1380 static bool chan_filter(struct dma_chan
*chan
, void *arg
)
1382 struct dma_chan_request
*rq
= arg
;
1384 struct mx3fb_platform_data
*mx3fb_pdata
;
1389 dev
= rq
->mx3fb
->dev
;
1390 mx3fb_pdata
= dev
->platform_data
;
1392 return rq
->id
== chan
->chan_id
&&
1393 mx3fb_pdata
->dma_dev
== chan
->device
->dev
;
1396 static void release_fbi(struct fb_info
*fbi
)
1398 mx3fb_unmap_video_memory(fbi
);
1400 fb_dealloc_cmap(&fbi
->cmap
);
1402 unregister_framebuffer(fbi
);
1403 framebuffer_release(fbi
);
1406 static int mx3fb_probe(struct platform_device
*pdev
)
1408 struct device
*dev
= &pdev
->dev
;
1410 struct resource
*sdc_reg
;
1411 struct mx3fb_data
*mx3fb
;
1412 dma_cap_mask_t mask
;
1413 struct dma_chan
*chan
;
1414 struct dma_chan_request rq
;
1417 * Display Interface (DI) and Synchronous Display Controller (SDC)
1420 sdc_reg
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1424 mx3fb
= kzalloc(sizeof(*mx3fb
), GFP_KERNEL
);
1428 spin_lock_init(&mx3fb
->lock
);
1430 mx3fb
->reg_base
= ioremap(sdc_reg
->start
, resource_size(sdc_reg
));
1431 if (!mx3fb
->reg_base
) {
1436 pr_debug("Remapped %x to %x at %p\n", sdc_reg
->start
, sdc_reg
->end
,
1439 /* IDMAC interface */
1443 platform_set_drvdata(pdev
, mx3fb
);
1448 dma_cap_set(DMA_SLAVE
, mask
);
1449 dma_cap_set(DMA_PRIVATE
, mask
);
1450 rq
.id
= IDMAC_SDC_0
;
1451 chan
= dma_request_channel(mask
, chan_filter
, &rq
);
1457 ret
= init_fb_chan(mx3fb
, to_idmac_chan(chan
));
1461 mx3fb
->backlight_level
= 255;
1466 dma_release_channel(chan
);
1469 iounmap(mx3fb
->reg_base
);
1472 dev_err(dev
, "mx3fb: failed to register fb\n");
1476 static int mx3fb_remove(struct platform_device
*dev
)
1478 struct mx3fb_data
*mx3fb
= platform_get_drvdata(dev
);
1479 struct fb_info
*fbi
= mx3fb
->fbi
;
1480 struct mx3fb_info
*mx3_fbi
= fbi
->par
;
1481 struct dma_chan
*chan
;
1483 chan
= &mx3_fbi
->idmac_channel
->dma_chan
;
1486 dma_release_channel(chan
);
1489 iounmap(mx3fb
->reg_base
);
1494 static struct platform_driver mx3fb_driver
= {
1498 .probe
= mx3fb_probe
,
1499 .remove
= mx3fb_remove
,
1500 .suspend
= mx3fb_suspend
,
1501 .resume
= mx3fb_resume
,
1505 * Parse user specified options (`video=mx3fb:')
1507 * video=mx3fb:bpp=16
1509 static int mx3fb_setup(void)
1512 char *opt
, *options
= NULL
;
1514 if (fb_get_options("mx3fb", &options
))
1517 if (!options
|| !*options
)
1520 while ((opt
= strsep(&options
, ",")) != NULL
) {
1523 if (!strncmp(opt
, "bpp=", 4))
1524 default_bpp
= simple_strtoul(opt
+ 4, NULL
, 0);
1533 static int __init
mx3fb_init(void)
1535 int ret
= mx3fb_setup();
1540 ret
= platform_driver_register(&mx3fb_driver
);
1544 static void __exit
mx3fb_exit(void)
1546 platform_driver_unregister(&mx3fb_driver
);
1549 module_init(mx3fb_init
);
1550 module_exit(mx3fb_exit
);
1552 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1553 MODULE_DESCRIPTION("MX3 framebuffer driver");
1554 MODULE_ALIAS("platform:" MX3FB_NAME
);
1555 MODULE_LICENSE("GPL v2");