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Merge tag 'v3.10.104' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / exynos / exynos_mipi_dsi_common.c
1 /* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
2 *
3 * Samsung SoC MIPI-DSI common driver.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
6 *
7 * InKi Dae, <inki.dae@samsung.com>
8 * Donghwa Lee, <dh09.lee@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/fs.h>
21 #include <linux/mm.h>
22 #include <linux/fb.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/memory.h>
27 #include <linux/delay.h>
28 #include <linux/irqreturn.h>
29 #include <linux/kthread.h>
30
31 #include <video/mipi_display.h>
32 #include <video/exynos_mipi_dsim.h>
33
34 #include "exynos_mipi_dsi_regs.h"
35 #include "exynos_mipi_dsi_lowlevel.h"
36 #include "exynos_mipi_dsi_common.h"
37
38 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
39 #define MIPI_RX_FIFO_READ_DONE 0x30800002
40 #define MIPI_MAX_RX_FIFO 20
41 #define MHZ (1000 * 1000)
42 #define FIN_HZ (24 * MHZ)
43
44 #define DFIN_PLL_MIN_HZ (6 * MHZ)
45 #define DFIN_PLL_MAX_HZ (12 * MHZ)
46
47 #define DFVCO_MIN_HZ (500 * MHZ)
48 #define DFVCO_MAX_HZ (1000 * MHZ)
49
50 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
51 #define TRY_FIFO_CLEAR (10)
52
53 /* MIPI-DSIM status types. */
54 enum {
55 DSIM_STATE_INIT, /* should be initialized. */
56 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
57 DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
58 DSIM_STATE_ULPS
59 };
60
61 /* define DSI lane types. */
62 enum {
63 DSIM_LANE_CLOCK = (1 << 0),
64 DSIM_LANE_DATA0 = (1 << 1),
65 DSIM_LANE_DATA1 = (1 << 2),
66 DSIM_LANE_DATA2 = (1 << 3),
67 DSIM_LANE_DATA3 = (1 << 4)
68 };
69
70 static unsigned int dpll_table[15] = {
71 100, 120, 170, 220, 270,
72 320, 390, 450, 510, 560,
73 640, 690, 770, 870, 950
74 };
75
76 irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
77 {
78 struct mipi_dsim_device *dsim = dev_id;
79 unsigned int intsrc, intmsk;
80
81 intsrc = exynos_mipi_dsi_read_interrupt(dsim);
82 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
83 intmsk = ~intmsk & intsrc;
84
85 if (intsrc & INTMSK_RX_DONE) {
86 complete(&dsim_rd_comp);
87 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
88 }
89 if (intsrc & INTMSK_FIFO_EMPTY) {
90 complete(&dsim_wr_comp);
91 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
92 }
93
94 exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
95
96 return IRQ_HANDLED;
97 }
98
99 /*
100 * write long packet to mipi dsi slave
101 * @dsim: mipi dsim device structure.
102 * @data0: packet data to send.
103 * @data1: size of packet data
104 */
105 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
106 const unsigned char *data0, unsigned int data_size)
107 {
108 unsigned int data_cnt = 0, payload = 0;
109
110 /* in case that data count is more then 4 */
111 for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
112 /*
113 * after sending 4bytes per one time,
114 * send remainder data less then 4.
115 */
116 if ((data_size - data_cnt) < 4) {
117 if ((data_size - data_cnt) == 3) {
118 payload = data0[data_cnt] |
119 data0[data_cnt + 1] << 8 |
120 data0[data_cnt + 2] << 16;
121 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
122 payload, data0[data_cnt],
123 data0[data_cnt + 1],
124 data0[data_cnt + 2]);
125 } else if ((data_size - data_cnt) == 2) {
126 payload = data0[data_cnt] |
127 data0[data_cnt + 1] << 8;
128 dev_dbg(dsim->dev,
129 "count = 2 payload = %x, %x %x\n", payload,
130 data0[data_cnt],
131 data0[data_cnt + 1]);
132 } else if ((data_size - data_cnt) == 1) {
133 payload = data0[data_cnt];
134 }
135
136 exynos_mipi_dsi_wr_tx_data(dsim, payload);
137 /* send 4bytes per one time. */
138 } else {
139 payload = data0[data_cnt] |
140 data0[data_cnt + 1] << 8 |
141 data0[data_cnt + 2] << 16 |
142 data0[data_cnt + 3] << 24;
143
144 dev_dbg(dsim->dev,
145 "count = 4 payload = %x, %x %x %x %x\n",
146 payload, *(u8 *)(data0 + data_cnt),
147 data0[data_cnt + 1],
148 data0[data_cnt + 2],
149 data0[data_cnt + 3]);
150
151 exynos_mipi_dsi_wr_tx_data(dsim, payload);
152 }
153 }
154 }
155
156 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
157 const unsigned char *data0, unsigned int data_size)
158 {
159 unsigned int check_rx_ack = 0;
160
161 if (dsim->state == DSIM_STATE_ULPS) {
162 dev_err(dsim->dev, "state is ULPS.\n");
163
164 return -EINVAL;
165 }
166
167 /* FIXME!!! why does it need this delay? */
168 msleep(20);
169
170 mutex_lock(&dsim->lock);
171
172 switch (data_id) {
173 /* short packet types of packet types for command. */
174 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
175 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
176 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
177 case MIPI_DSI_DCS_SHORT_WRITE:
178 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
179 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
180 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
181 if (check_rx_ack) {
182 /* process response func should be implemented */
183 mutex_unlock(&dsim->lock);
184 return 0;
185 } else {
186 mutex_unlock(&dsim->lock);
187 return -EINVAL;
188 }
189
190 /* general command */
191 case MIPI_DSI_COLOR_MODE_OFF:
192 case MIPI_DSI_COLOR_MODE_ON:
193 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
194 case MIPI_DSI_TURN_ON_PERIPHERAL:
195 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
196 if (check_rx_ack) {
197 /* process response func should be implemented. */
198 mutex_unlock(&dsim->lock);
199 return 0;
200 } else {
201 mutex_unlock(&dsim->lock);
202 return -EINVAL;
203 }
204
205 /* packet types for video data */
206 case MIPI_DSI_V_SYNC_START:
207 case MIPI_DSI_V_SYNC_END:
208 case MIPI_DSI_H_SYNC_START:
209 case MIPI_DSI_H_SYNC_END:
210 case MIPI_DSI_END_OF_TRANSMISSION:
211 mutex_unlock(&dsim->lock);
212 return 0;
213
214 /* long packet type and null packet */
215 case MIPI_DSI_NULL_PACKET:
216 case MIPI_DSI_BLANKING_PACKET:
217 mutex_unlock(&dsim->lock);
218 return 0;
219 case MIPI_DSI_GENERIC_LONG_WRITE:
220 case MIPI_DSI_DCS_LONG_WRITE:
221 {
222 unsigned int size, payload = 0;
223 INIT_COMPLETION(dsim_wr_comp);
224
225 size = data_size * 4;
226
227 /* if data count is less then 4, then send 3bytes data. */
228 if (data_size < 4) {
229 payload = data0[0] |
230 data0[1] << 8 |
231 data0[2] << 16;
232
233 exynos_mipi_dsi_wr_tx_data(dsim, payload);
234
235 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
236 data_size, payload, data0[0],
237 data0[1], data0[2]);
238
239 /* in case that data count is more then 4 */
240 } else
241 exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
242
243 /* put data into header fifo */
244 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
245 (data_size & 0xff00) >> 8);
246
247 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
248 MIPI_FIFO_TIMEOUT)) {
249 dev_warn(dsim->dev, "command write timeout.\n");
250 mutex_unlock(&dsim->lock);
251 return -EAGAIN;
252 }
253
254 if (check_rx_ack) {
255 /* process response func should be implemented. */
256 mutex_unlock(&dsim->lock);
257 return 0;
258 } else {
259 mutex_unlock(&dsim->lock);
260 return -EINVAL;
261 }
262 }
263
264 /* packet typo for video data */
265 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
266 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
267 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
268 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
269 if (check_rx_ack) {
270 /* process response func should be implemented. */
271 mutex_unlock(&dsim->lock);
272 return 0;
273 } else {
274 mutex_unlock(&dsim->lock);
275 return -EINVAL;
276 }
277 default:
278 dev_warn(dsim->dev,
279 "data id %x is not supported current DSI spec.\n",
280 data_id);
281
282 mutex_unlock(&dsim->lock);
283 return -EINVAL;
284 }
285 }
286
287 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
288 unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
289 {
290 unsigned int rcv_pkt, i, j;
291 u16 rxsize;
292
293 /* for long packet */
294 rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
295 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
296 if (rxsize != req_size) {
297 dev_dbg(dsim->dev,
298 "received size mismatch received: %d, requested: %d\n",
299 rxsize, req_size);
300 goto err;
301 }
302
303 for (i = 0; i < (rxsize >> 2); i++) {
304 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
305 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
306 for (j = 0; j < 4; j++) {
307 rx_buf[(i * 4) + j] =
308 (u8)(rcv_pkt >> (j * 8)) & 0xff;
309 dev_dbg(dsim->dev, "received value : %02x\n",
310 (rcv_pkt >> (j * 8)) & 0xff);
311 }
312 }
313 if (rxsize % 4) {
314 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
315 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
316 for (j = 0; j < (rxsize % 4); j++) {
317 rx_buf[(i * 4) + j] =
318 (u8)(rcv_pkt >> (j * 8)) & 0xff;
319 dev_dbg(dsim->dev, "received value : %02x\n",
320 (rcv_pkt >> (j * 8)) & 0xff);
321 }
322 }
323
324 return rxsize;
325
326 err:
327 return -EINVAL;
328 }
329
330 static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
331 {
332 switch (req_size) {
333 case 1:
334 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
335 case 2:
336 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
337 default:
338 return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
339 }
340 }
341
342 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
343 unsigned int data0, unsigned int req_size, u8 *rx_buf)
344 {
345 unsigned int rx_data, rcv_pkt, i;
346 u8 response = 0;
347 u16 rxsize;
348
349 if (dsim->state == DSIM_STATE_ULPS) {
350 dev_err(dsim->dev, "state is ULPS.\n");
351
352 return -EINVAL;
353 }
354
355 /* FIXME!!! */
356 msleep(20);
357
358 mutex_lock(&dsim->lock);
359 INIT_COMPLETION(dsim_rd_comp);
360 exynos_mipi_dsi_rd_tx_header(dsim,
361 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
362
363 response = exynos_mipi_dsi_response_size(req_size);
364
365 switch (data_id) {
366 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
367 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
368 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
369 case MIPI_DSI_DCS_READ:
370 exynos_mipi_dsi_rd_tx_header(dsim,
371 data_id, data0);
372 /* process response func should be implemented. */
373 break;
374 default:
375 dev_warn(dsim->dev,
376 "data id %x is not supported current DSI spec.\n",
377 data_id);
378
379 return -EINVAL;
380 }
381
382 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
383 MIPI_FIFO_TIMEOUT)) {
384 pr_err("RX done interrupt timeout\n");
385 mutex_unlock(&dsim->lock);
386 return 0;
387 }
388
389 msleep(20);
390
391 rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
392
393 if ((u8)(rx_data & 0xff) != response) {
394 printk(KERN_ERR
395 "mipi dsi wrong response rx_data : %x, response:%x\n",
396 rx_data, response);
397 goto clear_rx_fifo;
398 }
399
400 if (req_size <= 2) {
401 /* for short packet */
402 for (i = 0; i < req_size; i++)
403 rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
404 rxsize = req_size;
405 } else {
406 /* for long packet */
407 rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
408 rx_buf);
409 if (rxsize != req_size)
410 goto clear_rx_fifo;
411 }
412
413 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
414
415 msleep(20);
416
417 if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
418 dev_info(dsim->dev,
419 "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
420 goto clear_rx_fifo;
421 }
422
423 mutex_unlock(&dsim->lock);
424
425 return rxsize;
426
427 clear_rx_fifo:
428 i = 0;
429 while (1) {
430 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
431 if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
432 || (i > MIPI_MAX_RX_FIFO))
433 break;
434 dev_dbg(dsim->dev,
435 "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
436 i++;
437 }
438 dev_info(dsim->dev,
439 "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
440
441 mutex_unlock(&dsim->lock);
442
443 return 0;
444 }
445
446 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
447 unsigned int enable)
448 {
449 int sw_timeout;
450
451 if (enable) {
452 sw_timeout = 1000;
453
454 exynos_mipi_dsi_enable_pll(dsim, 1);
455 while (1) {
456 sw_timeout--;
457 if (exynos_mipi_dsi_is_pll_stable(dsim))
458 return 0;
459 if (sw_timeout == 0)
460 return -EINVAL;
461 }
462 } else
463 exynos_mipi_dsi_enable_pll(dsim, 0);
464
465 return 0;
466 }
467
468 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
469 unsigned int pre_divider, unsigned int main_divider,
470 unsigned int scaler)
471 {
472 unsigned long dfin_pll, dfvco, dpll_out;
473 unsigned int i, freq_band = 0xf;
474
475 dfin_pll = (FIN_HZ / pre_divider);
476
477 /******************************************************
478 * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
479 ******************************************************
480 * ~ 99.99 MHz 0000
481 * 100 ~ 119.99 MHz 0001
482 * 120 ~ 159.99 MHz 0010
483 * 160 ~ 199.99 MHz 0011
484 * 200 ~ 239.99 MHz 0100
485 * 140 ~ 319.99 MHz 0101
486 * 320 ~ 389.99 MHz 0110
487 * 390 ~ 449.99 MHz 0111
488 * 450 ~ 509.99 MHz 1000
489 * 510 ~ 559.99 MHz 1001
490 * 560 ~ 639.99 MHz 1010
491 * 640 ~ 689.99 MHz 1011
492 * 690 ~ 769.99 MHz 1100
493 * 770 ~ 869.99 MHz 1101
494 * 870 ~ 949.99 MHz 1110
495 * 950 ~ 1000 MHz 1111
496 ******************************************************/
497 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
498 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
499 exynos_mipi_dsi_enable_afc(dsim, 0, 0);
500 } else {
501 if (dfin_pll < 7 * MHZ)
502 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
503 else if (dfin_pll < 8 * MHZ)
504 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
505 else if (dfin_pll < 9 * MHZ)
506 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
507 else if (dfin_pll < 10 * MHZ)
508 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
509 else if (dfin_pll < 11 * MHZ)
510 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
511 else
512 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
513 }
514
515 dfvco = dfin_pll * main_divider;
516 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
517 dfvco, dfin_pll, main_divider);
518 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
519 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
520
521 dpll_out = dfvco / (1 << scaler);
522 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
523 dpll_out, dfvco, scaler);
524
525 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
526 if (dpll_out < dpll_table[i] * MHZ) {
527 freq_band = i;
528 break;
529 }
530 }
531
532 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
533
534 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
535
536 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
537 exynos_mipi_dsi_prep_ctrl(dsim, 0);
538
539 /* Freq Band */
540 exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
541
542 /* Stable time */
543 exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
544
545 /* Enable PLL */
546 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
547 (dpll_out / MHZ));
548
549 return dpll_out;
550 }
551
552 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
553 unsigned int byte_clk_sel, unsigned int enable)
554 {
555 unsigned int esc_div;
556 unsigned long esc_clk_error_rate;
557 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
558
559 if (enable) {
560 dsim->e_clk_src = byte_clk_sel;
561
562 /* Escape mode clock and byte clock source */
563 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
564
565 /* DPHY, DSIM Link : D-PHY clock out */
566 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
567 hs_clk = exynos_mipi_dsi_change_pll(dsim,
568 dsim->dsim_config->p, dsim->dsim_config->m,
569 dsim->dsim_config->s);
570 if (hs_clk == 0) {
571 dev_err(dsim->dev,
572 "failed to get hs clock.\n");
573 return -EINVAL;
574 }
575
576 byte_clk = hs_clk / 8;
577 exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
578 exynos_mipi_dsi_pll_on(dsim, 1);
579 /* DPHY : D-PHY clock out, DSIM link : external clock out */
580 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
581 dev_warn(dsim->dev, "this project is not support\n");
582 dev_warn(dsim->dev,
583 "external clock source for MIPI DSIM.\n");
584 } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
585 dev_warn(dsim->dev, "this project is not support\n");
586 dev_warn(dsim->dev,
587 "external clock source for MIPI DSIM\n");
588 }
589
590 /* escape clock divider */
591 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
592 dev_dbg(dsim->dev,
593 "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
594 esc_div, byte_clk, dsim->dsim_config->esc_clk);
595 if ((byte_clk / esc_div) >= (20 * MHZ) ||
596 (byte_clk / esc_div) >
597 dsim->dsim_config->esc_clk)
598 esc_div += 1;
599
600 escape_clk = byte_clk / esc_div;
601 dev_dbg(dsim->dev,
602 "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
603 escape_clk, byte_clk, esc_div);
604
605 /* enable escape clock. */
606 exynos_mipi_dsi_enable_byte_clock(dsim, 1);
607
608 /* enable byte clk and escape clock */
609 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
610 /* escape clock on lane */
611 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
612 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
613
614 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
615 (byte_clk / MHZ));
616 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
617 (dsim->dsim_config->esc_clk / MHZ));
618 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
619 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
620 ((byte_clk / esc_div) / MHZ));
621
622 if ((byte_clk / esc_div) > escape_clk) {
623 esc_clk_error_rate = escape_clk /
624 (byte_clk / esc_div);
625 dev_warn(dsim->dev, "error rate is %lu over.\n",
626 (esc_clk_error_rate / 100));
627 } else if ((byte_clk / esc_div) < (escape_clk)) {
628 esc_clk_error_rate = (byte_clk / esc_div) /
629 escape_clk;
630 dev_warn(dsim->dev, "error rate is %lu under.\n",
631 (esc_clk_error_rate / 100));
632 }
633 } else {
634 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
635 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
636 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
637
638 /* disable escape clock. */
639 exynos_mipi_dsi_enable_byte_clock(dsim, 0);
640
641 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
642 exynos_mipi_dsi_pll_on(dsim, 0);
643 }
644
645 return 0;
646 }
647
648 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
649 {
650 dsim->state = DSIM_STATE_INIT;
651
652 switch (dsim->dsim_config->e_no_data_lane) {
653 case DSIM_DATA_LANE_1:
654 dsim->data_lane = DSIM_LANE_DATA0;
655 break;
656 case DSIM_DATA_LANE_2:
657 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
658 break;
659 case DSIM_DATA_LANE_3:
660 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
661 DSIM_LANE_DATA2;
662 break;
663 case DSIM_DATA_LANE_4:
664 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
665 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
666 break;
667 default:
668 dev_info(dsim->dev, "data lane is invalid.\n");
669 return -EINVAL;
670 };
671
672 exynos_mipi_dsi_sw_reset(dsim);
673 exynos_mipi_dsi_func_reset(dsim);
674
675 exynos_mipi_dsi_dp_dn_swap(dsim, 0);
676
677 return 0;
678 }
679
680 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
681 {
682 unsigned int src = 0;
683
684 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
685 exynos_mipi_dsi_set_interrupt(dsim, src, 1);
686
687 src = 0;
688 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
689 exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
690 }
691
692 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
693 unsigned int enable)
694 {
695 /* enable only frame done interrupt */
696 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
697
698 return 0;
699 }
700
701 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
702 unsigned int enable)
703 {
704
705 /* consider Main display and Sub display. */
706
707 exynos_mipi_dsi_set_main_stand_by(dsim, enable);
708 }
709
710 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
711 struct mipi_dsim_config *dsim_config)
712 {
713 struct mipi_dsim_platform_data *dsim_pd;
714 struct fb_videomode *timing;
715
716 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
717 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
718
719 /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
720 if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
721 if (dsim_config->auto_vertical_cnt == 0) {
722 exynos_mipi_dsi_set_main_disp_vporch(dsim,
723 dsim_config->cmd_allow,
724 timing->lower_margin,
725 timing->upper_margin);
726 exynos_mipi_dsi_set_main_disp_hporch(dsim,
727 timing->right_margin,
728 timing->left_margin);
729 exynos_mipi_dsi_set_main_disp_sync_area(dsim,
730 timing->vsync_len,
731 timing->hsync_len);
732 }
733 }
734
735 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
736 timing->yres);
737
738 exynos_mipi_dsi_display_config(dsim, dsim_config);
739
740 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
741 timing->xres, timing->yres);
742
743 return 0;
744 }
745
746 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
747 {
748 unsigned int time_out = 100;
749
750 switch (dsim->state) {
751 case DSIM_STATE_INIT:
752 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
753
754 /* dsi configuration */
755 exynos_mipi_dsi_init_config(dsim);
756 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
757 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
758
759 /* set clock configuration */
760 exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
761
762 /* check clock and data lane state are stop state */
763 while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
764 time_out--;
765 if (time_out == 0) {
766 dev_err(dsim->dev,
767 "DSI Master is not stop state.\n");
768 dev_err(dsim->dev,
769 "Check initialization process\n");
770
771 return -EINVAL;
772 }
773 }
774 if (time_out != 0) {
775 dev_info(dsim->dev,
776 "DSI Master driver has been completed.\n");
777 dev_info(dsim->dev, "DSI Master state is stop state\n");
778 }
779
780 dsim->state = DSIM_STATE_STOP;
781
782 /* BTA sequence counters */
783 exynos_mipi_dsi_set_stop_state_counter(dsim,
784 dsim->dsim_config->stop_holding_cnt);
785 exynos_mipi_dsi_set_bta_timeout(dsim,
786 dsim->dsim_config->bta_timeout);
787 exynos_mipi_dsi_set_lpdr_timeout(dsim,
788 dsim->dsim_config->rx_timeout);
789
790 return 0;
791 default:
792 dev_info(dsim->dev, "DSI Master is already init.\n");
793 return 0;
794 }
795
796 return 0;
797 }
798
799 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
800 {
801 if (dsim->state != DSIM_STATE_STOP) {
802 dev_warn(dsim->dev, "DSIM is not in stop state.\n");
803 return 0;
804 }
805
806 if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
807 dev_warn(dsim->dev, "clock source is external bypass.\n");
808 return 0;
809 }
810
811 dsim->state = DSIM_STATE_HSCLKEN;
812
813 /* set LCDC and CPU transfer mode to HS. */
814 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
815 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
816 exynos_mipi_dsi_enable_hs_clock(dsim, 1);
817
818 return 0;
819 }
820
821 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
822 unsigned int mode)
823 {
824 if (mode) {
825 if (dsim->state != DSIM_STATE_HSCLKEN) {
826 dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
827 return -EINVAL;
828 }
829
830 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
831 } else {
832 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
833 DSIM_STATE_ULPS) {
834 dev_err(dsim->dev,
835 "DSI Master is not STOP or HSDT state.\n");
836 return -EINVAL;
837 }
838
839 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
840 }
841
842 return 0;
843 }
844
845 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
846 {
847 return _exynos_mipi_dsi_get_frame_done_status(dsim);
848 }
849
850 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
851 {
852 _exynos_mipi_dsi_clear_frame_done(dsim);
853
854 return 0;
855 }
856
857 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
858 unsigned int val)
859 {
860 int try = TRY_FIFO_CLEAR;
861
862 exynos_mipi_dsi_sw_reset_release(dsim);
863 exynos_mipi_dsi_func_reset(dsim);
864
865 do {
866 if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
867 exynos_mipi_dsi_init_interrupt(dsim);
868 dev_dbg(dsim->dev, "reset release done.\n");
869 return 0;
870 }
871 } while (--try);
872
873 dev_err(dsim->dev, "failed to clear dsim fifo.\n");
874 return -EAGAIN;
875 }
876
877 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
878 MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
879 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)