projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ARM: at91: fix board-rm9200-dt after sys_timer conversion
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / aty / aty128fb.c
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
54 #include <linux/mm.h>
55 #include <linux/vmalloc.h>
56 #include <linux/delay.h>
57 #include <linux/interrupt.h>
58 #include <linux/uaccess.h>
59 #include <linux/fb.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/ioport.h>
63 #include <linux/console.h>
64 #include <linux/backlight.h>
65 #include <asm/io.h>
66
67 #ifdef CONFIG_PPC_PMAC
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
70 #include <asm/prom.h>
71 #include <asm/pci-bridge.h>
72 #include "../macmodes.h"
73 #endif
74
75 #ifdef CONFIG_PMAC_BACKLIGHT
76 #include <asm/backlight.h>
77 #endif
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
82
83 #ifdef CONFIG_MTRR
84 #include <asm/mtrr.h>
85 #endif
86
87 #include <video/aty128.h>
88
89 /* Debug flag */
90 #undef DEBUG
91
92 #ifdef DEBUG
93 #define DBG(fmt, args...) \
94 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
95 #else
96 #define DBG(fmt, args...)
97 #endif
98
99 #ifndef CONFIG_PPC_PMAC
100 /* default mode */
101 static struct fb_var_screeninfo default_var __devinitdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107 };
108
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119 };
120 #endif /* CONFIG_PPC_PMAC */
121
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode __devinitdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137 };
138
139 /* Chip generations */
140 enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149 };
150
151 /* Must match above enum */
152 static char * const r128_family[] __devinitconst = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161 };
162
163 /*
164 * PCI driver prototypes
165 */
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
172
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270 };
271
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274 static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281 };
282
283 /* packed BIOS settings */
284 #ifndef CONFIG_PPC
285 typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
310
311 /* onboard memory information */
312 struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324 };
325
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336 static struct fb_fix_screeninfo aty128fb_fix __devinitdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344 };
345
346 static char *mode_option __devinitdata = NULL;
347
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode __devinitdata = VMODE_1024_768_60;
350 static int default_cmode __devinitdata = CMODE_8;
351 #endif
352
353 static int default_crt_on __devinitdata = 0;
354 static int default_lcd_on __devinitdata = 1;
355
356 #ifdef CONFIG_MTRR
357 static bool mtrr = true;
358 #endif
359
360 #ifdef CONFIG_PMAC_BACKLIGHT
361 static int backlight __devinitdata = 1;
362 #else
363 static int backlight __devinitdata = 0;
364 #endif
365
366 /* PLL constants */
367 struct aty128_constants {
368 u32 ref_clk;
369 u32 ppll_min;
370 u32 ppll_max;
371 u32 ref_divider;
372 u32 xclk;
373 u32 fifo_width;
374 u32 fifo_depth;
375 };
376
377 struct aty128_crtc {
378 u32 gen_cntl;
379 u32 h_total, h_sync_strt_wid;
380 u32 v_total, v_sync_strt_wid;
381 u32 pitch;
382 u32 offset, offset_cntl;
383 u32 xoffset, yoffset;
384 u32 vxres, vyres;
385 u32 depth, bpp;
386 };
387
388 struct aty128_pll {
389 u32 post_divider;
390 u32 feedback_divider;
391 u32 vclk;
392 };
393
394 struct aty128_ddafifo {
395 u32 dda_config;
396 u32 dda_on_off;
397 };
398
399 /* register values for a specific mode */
400 struct aty128fb_par {
401 struct aty128_crtc crtc;
402 struct aty128_pll pll;
403 struct aty128_ddafifo fifo_reg;
404 u32 accel_flags;
405 struct aty128_constants constants; /* PLL and others */
406 void __iomem *regbase; /* remapped mmio */
407 u32 vram_size; /* onboard video ram */
408 int chip_gen;
409 const struct aty128_meminfo *mem; /* onboard mem info */
410 #ifdef CONFIG_MTRR
411 struct { int vram; int vram_valid; } mtrr;
412 #endif
413 int blitter_may_be_busy;
414 int fifo_slots; /* free slots in FIFO (64 max) */
415
416 int pm_reg;
417 int crt_on, lcd_on;
418 struct pci_dev *pdev;
419 struct fb_info *next;
420 int asleep;
421 int lock_blank;
422
423 u8 red[32]; /* see aty128fb_setcolreg */
424 u8 green[64];
425 u8 blue[32];
426 u32 pseudo_palette[16]; /* used for TRUECOLOR */
427 };
428
429
430 #define round_div(n, d) ((n+(d/2))/d)
431
432 static int aty128fb_check_var(struct fb_var_screeninfo *var,
433 struct fb_info *info);
434 static int aty128fb_set_par(struct fb_info *info);
435 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
436 u_int transp, struct fb_info *info);
437 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
438 struct fb_info *fb);
439 static int aty128fb_blank(int blank, struct fb_info *fb);
440 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
441 static int aty128fb_sync(struct fb_info *info);
442
443 /*
444 * Internal routines
445 */
446
447 static int aty128_encode_var(struct fb_var_screeninfo *var,
448 const struct aty128fb_par *par);
449 static int aty128_decode_var(struct fb_var_screeninfo *var,
450 struct aty128fb_par *par);
451 #if 0
452 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
453 void __iomem *bios);
454 static void __devinit __iomem *aty128_map_ROM(struct pci_dev *pdev,
455 const struct aty128fb_par *par);
456 #endif
457 static void aty128_timings(struct aty128fb_par *par);
458 static void aty128_init_engine(struct aty128fb_par *par);
459 static void aty128_reset_engine(const struct aty128fb_par *par);
460 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
461 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
462 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
463 static void wait_for_idle(struct aty128fb_par *par);
464 static u32 depth_to_dst(u32 depth);
465
466 #ifdef CONFIG_FB_ATY128_BACKLIGHT
467 static void aty128_bl_set_power(struct fb_info *info, int power);
468 #endif
469
470 #define BIOS_IN8(v) (readb(bios + (v)))
471 #define BIOS_IN16(v) (readb(bios + (v)) | \
472 (readb(bios + (v) + 1) << 8))
473 #define BIOS_IN32(v) (readb(bios + (v)) | \
474 (readb(bios + (v) + 1) << 8) | \
475 (readb(bios + (v) + 2) << 16) | \
476 (readb(bios + (v) + 3) << 24))
477
478
479 static struct fb_ops aty128fb_ops = {
480 .owner = THIS_MODULE,
481 .fb_check_var = aty128fb_check_var,
482 .fb_set_par = aty128fb_set_par,
483 .fb_setcolreg = aty128fb_setcolreg,
484 .fb_pan_display = aty128fb_pan_display,
485 .fb_blank = aty128fb_blank,
486 .fb_ioctl = aty128fb_ioctl,
487 .fb_sync = aty128fb_sync,
488 .fb_fillrect = cfb_fillrect,
489 .fb_copyarea = cfb_copyarea,
490 .fb_imageblit = cfb_imageblit,
491 };
492
493 /*
494 * Functions to read from/write to the mmio registers
495 * - endian conversions may possibly be avoided by
496 * using the other register aperture. TODO.
497 */
498 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
499 const struct aty128fb_par *par)
500 {
501 return readl (par->regbase + regindex);
502 }
503
504 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
505 const struct aty128fb_par *par)
506 {
507 writel (val, par->regbase + regindex);
508 }
509
510 static inline u8 _aty_ld_8(unsigned int regindex,
511 const struct aty128fb_par *par)
512 {
513 return readb (par->regbase + regindex);
514 }
515
516 static inline void _aty_st_8(unsigned int regindex, u8 val,
517 const struct aty128fb_par *par)
518 {
519 writeb (val, par->regbase + regindex);
520 }
521
522 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
523 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
524 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
525 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
526
527 /*
528 * Functions to read from/write to the pll registers
529 */
530
531 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
532 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
533
534
535 static u32 _aty_ld_pll(unsigned int pll_index,
536 const struct aty128fb_par *par)
537 {
538 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
539 return aty_ld_le32(CLOCK_CNTL_DATA);
540 }
541
542
543 static void _aty_st_pll(unsigned int pll_index, u32 val,
544 const struct aty128fb_par *par)
545 {
546 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
547 aty_st_le32(CLOCK_CNTL_DATA, val);
548 }
549
550
551 /* return true when the PLL has completed an atomic update */
552 static int aty_pll_readupdate(const struct aty128fb_par *par)
553 {
554 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
555 }
556
557
558 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
559 {
560 unsigned long timeout = jiffies + HZ/100; // should be more than enough
561 int reset = 1;
562
563 while (time_before(jiffies, timeout))
564 if (aty_pll_readupdate(par)) {
565 reset = 0;
566 break;
567 }
568
569 if (reset) /* reset engine?? */
570 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
571 }
572
573
574 /* tell PLL to update */
575 static void aty_pll_writeupdate(const struct aty128fb_par *par)
576 {
577 aty_pll_wait_readupdate(par);
578
579 aty_st_pll(PPLL_REF_DIV,
580 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
581 }
582
583
584 /* write to the scratch register to test r/w functionality */
585 static int __devinit register_test(const struct aty128fb_par *par)
586 {
587 u32 val;
588 int flag = 0;
589
590 val = aty_ld_le32(BIOS_0_SCRATCH);
591
592 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
593 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
594 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
595
596 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
597 flag = 1;
598 }
599
600 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
601 return flag;
602 }
603
604
605 /*
606 * Accelerator engine functions
607 */
608 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
609 {
610 int i;
611
612 for (;;) {
613 for (i = 0; i < 2000000; i++) {
614 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
615 if (par->fifo_slots >= entries)
616 return;
617 }
618 aty128_reset_engine(par);
619 }
620 }
621
622
623 static void wait_for_idle(struct aty128fb_par *par)
624 {
625 int i;
626
627 do_wait_for_fifo(64, par);
628
629 for (;;) {
630 for (i = 0; i < 2000000; i++) {
631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
632 aty128_flush_pixel_cache(par);
633 par->blitter_may_be_busy = 0;
634 return;
635 }
636 }
637 aty128_reset_engine(par);
638 }
639 }
640
641
642 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
643 {
644 if (par->fifo_slots < entries)
645 do_wait_for_fifo(64, par);
646 par->fifo_slots -= entries;
647 }
648
649
650 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
651 {
652 int i;
653 u32 tmp;
654
655 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
656 tmp &= ~(0x00ff);
657 tmp |= 0x00ff;
658 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
659
660 for (i = 0; i < 2000000; i++)
661 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
662 break;
663 }
664
665
666 static void aty128_reset_engine(const struct aty128fb_par *par)
667 {
668 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
669
670 aty128_flush_pixel_cache(par);
671
672 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
673 mclk_cntl = aty_ld_pll(MCLK_CNTL);
674
675 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
676
677 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
678 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
679 aty_ld_le32(GEN_RESET_CNTL);
680 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
681 aty_ld_le32(GEN_RESET_CNTL);
682
683 aty_st_pll(MCLK_CNTL, mclk_cntl);
684 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
685 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
686
687 /* use old pio mode */
688 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
689
690 DBG("engine reset");
691 }
692
693
694 static void aty128_init_engine(struct aty128fb_par *par)
695 {
696 u32 pitch_value;
697
698 wait_for_idle(par);
699
700 /* 3D scaler not spoken here */
701 wait_for_fifo(1, par);
702 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
703
704 aty128_reset_engine(par);
705
706 pitch_value = par->crtc.pitch;
707 if (par->crtc.bpp == 24) {
708 pitch_value = pitch_value * 3;
709 }
710
711 wait_for_fifo(4, par);
712 /* setup engine offset registers */
713 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
714
715 /* setup engine pitch registers */
716 aty_st_le32(DEFAULT_PITCH, pitch_value);
717
718 /* set the default scissor register to max dimensions */
719 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
720
721 /* set the drawing controls registers */
722 aty_st_le32(DP_GUI_MASTER_CNTL,
723 GMC_SRC_PITCH_OFFSET_DEFAULT |
724 GMC_DST_PITCH_OFFSET_DEFAULT |
725 GMC_SRC_CLIP_DEFAULT |
726 GMC_DST_CLIP_DEFAULT |
727 GMC_BRUSH_SOLIDCOLOR |
728 (depth_to_dst(par->crtc.depth) << 8) |
729 GMC_SRC_DSTCOLOR |
730 GMC_BYTE_ORDER_MSB_TO_LSB |
731 GMC_DP_CONVERSION_TEMP_6500 |
732 ROP3_PATCOPY |
733 GMC_DP_SRC_RECT |
734 GMC_3D_FCN_EN_CLR |
735 GMC_DST_CLR_CMP_FCN_CLEAR |
736 GMC_AUX_CLIP_CLEAR |
737 GMC_WRITE_MASK_SET);
738
739 wait_for_fifo(8, par);
740 /* clear the line drawing registers */
741 aty_st_le32(DST_BRES_ERR, 0);
742 aty_st_le32(DST_BRES_INC, 0);
743 aty_st_le32(DST_BRES_DEC, 0);
744
745 /* set brush color registers */
746 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
747 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
748
749 /* set source color registers */
750 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
751 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
752
753 /* default write mask */
754 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
755
756 /* Wait for all the writes to be completed before returning */
757 wait_for_idle(par);
758 }
759
760
761 /* convert depth values to their register representation */
762 static u32 depth_to_dst(u32 depth)
763 {
764 if (depth <= 8)
765 return DST_8BPP;
766 else if (depth <= 15)
767 return DST_15BPP;
768 else if (depth == 16)
769 return DST_16BPP;
770 else if (depth <= 24)
771 return DST_24BPP;
772 else if (depth <= 32)
773 return DST_32BPP;
774
775 return -EINVAL;
776 }
777
778 /*
779 * PLL informations retreival
780 */
781
782
783 #ifndef __sparc__
784 static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par,
785 struct pci_dev *dev)
786 {
787 u16 dptr;
788 u8 rom_type;
789 void __iomem *bios;
790 size_t rom_size;
791
792 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
793 unsigned int temp;
794 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
795 temp &= 0x00ffffffu;
796 temp |= 0x04 << 24;
797 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
798 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
799
800 bios = pci_map_rom(dev, &rom_size);
801
802 if (!bios) {
803 printk(KERN_ERR "aty128fb: ROM failed to map\n");
804 return NULL;
805 }
806
807 /* Very simple test to make sure it appeared */
808 if (BIOS_IN16(0) != 0xaa55) {
809 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
810 " be 0xaa55\n", BIOS_IN16(0));
811 goto failed;
812 }
813
814 /* Look for the PCI data to check the ROM type */
815 dptr = BIOS_IN16(0x18);
816
817 /* Check the PCI data signature. If it's wrong, we still assume a normal
818 * x86 ROM for now, until I've verified this works everywhere.
819 * The goal here is more to phase out Open Firmware images.
820 *
821 * Currently, we only look at the first PCI data, we could iteratre and
822 * deal with them all, and we should use fb_bios_start relative to start
823 * of image and not relative start of ROM, but so far, I never found a
824 * dual-image ATI card.
825 *
826 * typedef struct {
827 * u32 signature; + 0x00
828 * u16 vendor; + 0x04
829 * u16 device; + 0x06
830 * u16 reserved_1; + 0x08
831 * u16 dlen; + 0x0a
832 * u8 drevision; + 0x0c
833 * u8 class_hi; + 0x0d
834 * u16 class_lo; + 0x0e
835 * u16 ilen; + 0x10
836 * u16 irevision; + 0x12
837 * u8 type; + 0x14
838 * u8 indicator; + 0x15
839 * u16 reserved_2; + 0x16
840 * } pci_data_t;
841 */
842 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
843 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
844 BIOS_IN32(dptr));
845 goto anyway;
846 }
847 rom_type = BIOS_IN8(dptr + 0x14);
848 switch(rom_type) {
849 case 0:
850 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
851 break;
852 case 1:
853 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
854 goto failed;
855 case 2:
856 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
857 goto failed;
858 default:
859 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
860 rom_type);
861 goto failed;
862 }
863 anyway:
864 return bios;
865
866 failed:
867 pci_unmap_rom(dev, bios);
868 return NULL;
869 }
870
871 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
872 unsigned char __iomem *bios)
873 {
874 unsigned int bios_hdr;
875 unsigned int bios_pll;
876
877 bios_hdr = BIOS_IN16(0x48);
878 bios_pll = BIOS_IN16(bios_hdr + 0x30);
879
880 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
881 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
882 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
883 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
884 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
885
886 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
887 par->constants.ppll_max, par->constants.ppll_min,
888 par->constants.xclk, par->constants.ref_divider,
889 par->constants.ref_clk);
890
891 }
892
893 #ifdef CONFIG_X86
894 static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
895 {
896 /* I simplified this code as we used to miss the signatures in
897 * a lot of case. It's now closer to XFree, we just don't check
898 * for signatures at all... Something better will have to be done
899 * if we end up having conflicts
900 */
901 u32 segstart;
902 unsigned char __iomem *rom_base = NULL;
903
904 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
905 rom_base = ioremap(segstart, 0x10000);
906 if (rom_base == NULL)
907 return NULL;
908 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
909 break;
910 iounmap(rom_base);
911 rom_base = NULL;
912 }
913 return rom_base;
914 }
915 #endif
916 #endif /* ndef(__sparc__) */
917
918 /* fill in known card constants if pll_block is not available */
919 static void __devinit aty128_timings(struct aty128fb_par *par)
920 {
921 #ifdef CONFIG_PPC_OF
922 /* instead of a table lookup, assume OF has properly
923 * setup the PLL registers and use their values
924 * to set the XCLK values and reference divider values */
925
926 u32 x_mpll_ref_fb_div;
927 u32 xclk_cntl;
928 u32 Nx, M;
929 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
930 #endif
931
932 if (!par->constants.ref_clk)
933 par->constants.ref_clk = 2950;
934
935 #ifdef CONFIG_PPC_OF
936 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
937 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
938 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
939 M = x_mpll_ref_fb_div & 0x0000ff;
940
941 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
942 (M * PostDivSet[xclk_cntl]));
943
944 par->constants.ref_divider =
945 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
946 #endif
947
948 if (!par->constants.ref_divider) {
949 par->constants.ref_divider = 0x3b;
950
951 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
952 aty_pll_writeupdate(par);
953 }
954 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
955 aty_pll_writeupdate(par);
956
957 /* from documentation */
958 if (!par->constants.ppll_min)
959 par->constants.ppll_min = 12500;
960 if (!par->constants.ppll_max)
961 par->constants.ppll_max = 25000; /* 23000 on some cards? */
962 if (!par->constants.xclk)
963 par->constants.xclk = 0x1d4d; /* same as mclk */
964
965 par->constants.fifo_width = 128;
966 par->constants.fifo_depth = 32;
967
968 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
969 case 0:
970 par->mem = &sdr_128;
971 break;
972 case 1:
973 par->mem = &sdr_sgram;
974 break;
975 case 2:
976 par->mem = &ddr_sgram;
977 break;
978 default:
979 par->mem = &sdr_sgram;
980 }
981 }
982
983
984
985 /*
986 * CRTC programming
987 */
988
989 /* Program the CRTC registers */
990 static void aty128_set_crtc(const struct aty128_crtc *crtc,
991 const struct aty128fb_par *par)
992 {
993 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
994 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
995 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
996 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
997 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
998 aty_st_le32(CRTC_PITCH, crtc->pitch);
999 aty_st_le32(CRTC_OFFSET, crtc->offset);
1000 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1001 /* Disable ATOMIC updating. Is this the right place? */
1002 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1003 }
1004
1005
1006 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1007 struct aty128_crtc *crtc,
1008 const struct aty128fb_par *par)
1009 {
1010 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1011 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1012 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1013 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1014 u32 depth, bytpp;
1015 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1016
1017 /* input */
1018 xres = var->xres;
1019 yres = var->yres;
1020 vxres = var->xres_virtual;
1021 vyres = var->yres_virtual;
1022 xoffset = var->xoffset;
1023 yoffset = var->yoffset;
1024 bpp = var->bits_per_pixel;
1025 left = var->left_margin;
1026 right = var->right_margin;
1027 upper = var->upper_margin;
1028 lower = var->lower_margin;
1029 hslen = var->hsync_len;
1030 vslen = var->vsync_len;
1031 sync = var->sync;
1032 vmode = var->vmode;
1033
1034 if (bpp != 16)
1035 depth = bpp;
1036 else
1037 depth = (var->green.length == 6) ? 16 : 15;
1038
1039 /* check for mode eligibility
1040 * accept only non interlaced modes */
1041 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1042 return -EINVAL;
1043
1044 /* convert (and round up) and validate */
1045 xres = (xres + 7) & ~7;
1046 xoffset = (xoffset + 7) & ~7;
1047
1048 if (vxres < xres + xoffset)
1049 vxres = xres + xoffset;
1050
1051 if (vyres < yres + yoffset)
1052 vyres = yres + yoffset;
1053
1054 /* convert depth into ATI register depth */
1055 dst = depth_to_dst(depth);
1056
1057 if (dst == -EINVAL) {
1058 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1059 return -EINVAL;
1060 }
1061
1062 /* convert register depth to bytes per pixel */
1063 bytpp = mode_bytpp[dst];
1064
1065 /* make sure there is enough video ram for the mode */
1066 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1067 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1068 return -EINVAL;
1069 }
1070
1071 h_disp = (xres >> 3) - 1;
1072 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1073
1074 v_disp = yres - 1;
1075 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1076
1077 /* check to make sure h_total and v_total are in range */
1078 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1079 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1080 return -EINVAL;
1081 }
1082
1083 h_sync_wid = (hslen + 7) >> 3;
1084 if (h_sync_wid == 0)
1085 h_sync_wid = 1;
1086 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1087 h_sync_wid = 0x3f;
1088
1089 h_sync_strt = (h_disp << 3) + right;
1090
1091 v_sync_wid = vslen;
1092 if (v_sync_wid == 0)
1093 v_sync_wid = 1;
1094 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1095 v_sync_wid = 0x1f;
1096
1097 v_sync_strt = v_disp + lower;
1098
1099 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1100 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1101
1102 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1103
1104 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1105
1106 crtc->h_total = h_total | (h_disp << 16);
1107 crtc->v_total = v_total | (v_disp << 16);
1108
1109 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1110 (h_sync_pol << 23);
1111 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1112 (v_sync_pol << 23);
1113
1114 crtc->pitch = vxres >> 3;
1115
1116 crtc->offset = 0;
1117
1118 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1119 crtc->offset_cntl = 0x00010000;
1120 else
1121 crtc->offset_cntl = 0;
1122
1123 crtc->vxres = vxres;
1124 crtc->vyres = vyres;
1125 crtc->xoffset = xoffset;
1126 crtc->yoffset = yoffset;
1127 crtc->depth = depth;
1128 crtc->bpp = bpp;
1129
1130 return 0;
1131 }
1132
1133
1134 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1135 {
1136
1137 /* fill in pixel info */
1138 var->red.msb_right = 0;
1139 var->green.msb_right = 0;
1140 var->blue.offset = 0;
1141 var->blue.msb_right = 0;
1142 var->transp.offset = 0;
1143 var->transp.length = 0;
1144 var->transp.msb_right = 0;
1145 switch (pix_width) {
1146 case CRTC_PIX_WIDTH_8BPP:
1147 var->bits_per_pixel = 8;
1148 var->red.offset = 0;
1149 var->red.length = 8;
1150 var->green.offset = 0;
1151 var->green.length = 8;
1152 var->blue.length = 8;
1153 break;
1154 case CRTC_PIX_WIDTH_15BPP:
1155 var->bits_per_pixel = 16;
1156 var->red.offset = 10;
1157 var->red.length = 5;
1158 var->green.offset = 5;
1159 var->green.length = 5;
1160 var->blue.length = 5;
1161 break;
1162 case CRTC_PIX_WIDTH_16BPP:
1163 var->bits_per_pixel = 16;
1164 var->red.offset = 11;
1165 var->red.length = 5;
1166 var->green.offset = 5;
1167 var->green.length = 6;
1168 var->blue.length = 5;
1169 break;
1170 case CRTC_PIX_WIDTH_24BPP:
1171 var->bits_per_pixel = 24;
1172 var->red.offset = 16;
1173 var->red.length = 8;
1174 var->green.offset = 8;
1175 var->green.length = 8;
1176 var->blue.length = 8;
1177 break;
1178 case CRTC_PIX_WIDTH_32BPP:
1179 var->bits_per_pixel = 32;
1180 var->red.offset = 16;
1181 var->red.length = 8;
1182 var->green.offset = 8;
1183 var->green.length = 8;
1184 var->blue.length = 8;
1185 var->transp.offset = 24;
1186 var->transp.length = 8;
1187 break;
1188 default:
1189 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1190 return -EINVAL;
1191 }
1192
1193 return 0;
1194 }
1195
1196
1197 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1198 struct fb_var_screeninfo *var)
1199 {
1200 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1201 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1202 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1203 u32 pix_width;
1204
1205 /* fun with masking */
1206 h_total = crtc->h_total & 0x1ff;
1207 h_disp = (crtc->h_total >> 16) & 0xff;
1208 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1209 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1210 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1211 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1212 v_total = crtc->v_total & 0x7ff;
1213 v_disp = (crtc->v_total >> 16) & 0x7ff;
1214 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1215 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1216 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1217 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1218 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1219
1220 /* do conversions */
1221 xres = (h_disp + 1) << 3;
1222 yres = v_disp + 1;
1223 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1224 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1225 hslen = h_sync_wid << 3;
1226 upper = v_total - v_sync_strt - v_sync_wid;
1227 lower = v_sync_strt - v_disp;
1228 vslen = v_sync_wid;
1229 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1230 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1231 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1232
1233 aty128_pix_width_to_var(pix_width, var);
1234
1235 var->xres = xres;
1236 var->yres = yres;
1237 var->xres_virtual = crtc->vxres;
1238 var->yres_virtual = crtc->vyres;
1239 var->xoffset = crtc->xoffset;
1240 var->yoffset = crtc->yoffset;
1241 var->left_margin = left;
1242 var->right_margin = right;
1243 var->upper_margin = upper;
1244 var->lower_margin = lower;
1245 var->hsync_len = hslen;
1246 var->vsync_len = vslen;
1247 var->sync = sync;
1248 var->vmode = FB_VMODE_NONINTERLACED;
1249
1250 return 0;
1251 }
1252
1253 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1254 {
1255 if (on) {
1256 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1257 CRT_CRTC_ON);
1258 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1259 DAC_PALETTE2_SNOOP_EN));
1260 } else
1261 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1262 ~CRT_CRTC_ON);
1263 }
1264
1265 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1266 {
1267 u32 reg;
1268 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1269 struct fb_info *info = pci_get_drvdata(par->pdev);
1270 #endif
1271
1272 if (on) {
1273 reg = aty_ld_le32(LVDS_GEN_CNTL);
1274 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1275 reg &= ~LVDS_DISPLAY_DIS;
1276 aty_st_le32(LVDS_GEN_CNTL, reg);
1277 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1278 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1279 #endif
1280 } else {
1281 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1282 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1283 #endif
1284 reg = aty_ld_le32(LVDS_GEN_CNTL);
1285 reg |= LVDS_DISPLAY_DIS;
1286 aty_st_le32(LVDS_GEN_CNTL, reg);
1287 mdelay(100);
1288 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1289 aty_st_le32(LVDS_GEN_CNTL, reg);
1290 }
1291 }
1292
1293 static void aty128_set_pll(struct aty128_pll *pll,
1294 const struct aty128fb_par *par)
1295 {
1296 u32 div3;
1297
1298 unsigned char post_conv[] = /* register values for post dividers */
1299 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1300
1301 /* select PPLL_DIV_3 */
1302 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1303
1304 /* reset PLL */
1305 aty_st_pll(PPLL_CNTL,
1306 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1307
1308 /* write the reference divider */
1309 aty_pll_wait_readupdate(par);
1310 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1311 aty_pll_writeupdate(par);
1312
1313 div3 = aty_ld_pll(PPLL_DIV_3);
1314 div3 &= ~PPLL_FB3_DIV_MASK;
1315 div3 |= pll->feedback_divider;
1316 div3 &= ~PPLL_POST3_DIV_MASK;
1317 div3 |= post_conv[pll->post_divider] << 16;
1318
1319 /* write feedback and post dividers */
1320 aty_pll_wait_readupdate(par);
1321 aty_st_pll(PPLL_DIV_3, div3);
1322 aty_pll_writeupdate(par);
1323
1324 aty_pll_wait_readupdate(par);
1325 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1326 aty_pll_writeupdate(par);
1327
1328 /* clear the reset, just in case */
1329 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1330 }
1331
1332
1333 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1334 const struct aty128fb_par *par)
1335 {
1336 const struct aty128_constants c = par->constants;
1337 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1338 u32 output_freq;
1339 u32 vclk; /* in .01 MHz */
1340 int i = 0;
1341 u32 n, d;
1342
1343 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1344
1345 /* adjust pixel clock if necessary */
1346 if (vclk > c.ppll_max)
1347 vclk = c.ppll_max;
1348 if (vclk * 12 < c.ppll_min)
1349 vclk = c.ppll_min/12;
1350
1351 /* now, find an acceptable divider */
1352 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1353 output_freq = post_dividers[i] * vclk;
1354 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1355 pll->post_divider = post_dividers[i];
1356 break;
1357 }
1358 }
1359
1360 if (i == ARRAY_SIZE(post_dividers))
1361 return -EINVAL;
1362
1363 /* calculate feedback divider */
1364 n = c.ref_divider * output_freq;
1365 d = c.ref_clk;
1366
1367 pll->feedback_divider = round_div(n, d);
1368 pll->vclk = vclk;
1369
1370 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1371 "vclk_per: %d\n", pll->post_divider,
1372 pll->feedback_divider, vclk, output_freq,
1373 c.ref_divider, period_in_ps);
1374
1375 return 0;
1376 }
1377
1378
1379 static int aty128_pll_to_var(const struct aty128_pll *pll,
1380 struct fb_var_screeninfo *var)
1381 {
1382 var->pixclock = 100000000 / pll->vclk;
1383
1384 return 0;
1385 }
1386
1387
1388 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1389 const struct aty128fb_par *par)
1390 {
1391 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1392 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1393 }
1394
1395
1396 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1397 const struct aty128_pll *pll,
1398 u32 depth,
1399 const struct aty128fb_par *par)
1400 {
1401 const struct aty128_meminfo *m = par->mem;
1402 u32 xclk = par->constants.xclk;
1403 u32 fifo_width = par->constants.fifo_width;
1404 u32 fifo_depth = par->constants.fifo_depth;
1405 s32 x, b, p, ron, roff;
1406 u32 n, d, bpp;
1407
1408 /* round up to multiple of 8 */
1409 bpp = (depth+7) & ~7;
1410
1411 n = xclk * fifo_width;
1412 d = pll->vclk * bpp;
1413 x = round_div(n, d);
1414
1415 ron = 4 * m->MB +
1416 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1417 2 * m->Trp +
1418 m->Twr +
1419 m->CL +
1420 m->Tr2w +
1421 x;
1422
1423 DBG("x %x\n", x);
1424
1425 b = 0;
1426 while (x) {
1427 x >>= 1;
1428 b++;
1429 }
1430 p = b + 1;
1431
1432 ron <<= (11 - p);
1433
1434 n <<= (11 - p);
1435 x = round_div(n, d);
1436 roff = x * (fifo_depth - 4);
1437
1438 if ((ron + m->Rloop) >= roff) {
1439 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1440 return -EINVAL;
1441 }
1442
1443 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1444 p, m->Rloop, x, ron, roff);
1445
1446 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1447 dsp->dda_on_off = ron << 16 | roff;
1448
1449 return 0;
1450 }
1451
1452
1453 /*
1454 * This actually sets the video mode.
1455 */
1456 static int aty128fb_set_par(struct fb_info *info)
1457 {
1458 struct aty128fb_par *par = info->par;
1459 u32 config;
1460 int err;
1461
1462 if ((err = aty128_decode_var(&info->var, par)) != 0)
1463 return err;
1464
1465 if (par->blitter_may_be_busy)
1466 wait_for_idle(par);
1467
1468 /* clear all registers that may interfere with mode setting */
1469 aty_st_le32(OVR_CLR, 0);
1470 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1471 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1472 aty_st_le32(OV0_SCALE_CNTL, 0);
1473 aty_st_le32(MPP_TB_CONFIG, 0);
1474 aty_st_le32(MPP_GP_CONFIG, 0);
1475 aty_st_le32(SUBPIC_CNTL, 0);
1476 aty_st_le32(VIPH_CONTROL, 0);
1477 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1478 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1479 aty_st_le32(CAP0_TRIG_CNTL, 0);
1480 aty_st_le32(CAP1_TRIG_CNTL, 0);
1481
1482 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1483
1484 aty128_set_crtc(&par->crtc, par);
1485 aty128_set_pll(&par->pll, par);
1486 aty128_set_fifo(&par->fifo_reg, par);
1487
1488 config = aty_ld_le32(CNFG_CNTL) & ~3;
1489
1490 #if defined(__BIG_ENDIAN)
1491 if (par->crtc.bpp == 32)
1492 config |= 2; /* make aperture do 32 bit swapping */
1493 else if (par->crtc.bpp == 16)
1494 config |= 1; /* make aperture do 16 bit swapping */
1495 #endif
1496
1497 aty_st_le32(CNFG_CNTL, config);
1498 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1499
1500 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1501 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1502 : FB_VISUAL_DIRECTCOLOR;
1503
1504 if (par->chip_gen == rage_M3) {
1505 aty128_set_crt_enable(par, par->crt_on);
1506 aty128_set_lcd_enable(par, par->lcd_on);
1507 }
1508 if (par->accel_flags & FB_ACCELF_TEXT)
1509 aty128_init_engine(par);
1510
1511 #ifdef CONFIG_BOOTX_TEXT
1512 btext_update_display(info->fix.smem_start,
1513 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1514 ((par->crtc.v_total>>16) & 0x7ff)+1,
1515 par->crtc.bpp,
1516 par->crtc.vxres*par->crtc.bpp/8);
1517 #endif /* CONFIG_BOOTX_TEXT */
1518
1519 return 0;
1520 }
1521
1522 /*
1523 * encode/decode the User Defined Part of the Display
1524 */
1525
1526 static int aty128_decode_var(struct fb_var_screeninfo *var,
1527 struct aty128fb_par *par)
1528 {
1529 int err;
1530 struct aty128_crtc crtc;
1531 struct aty128_pll pll;
1532 struct aty128_ddafifo fifo_reg;
1533
1534 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1535 return err;
1536
1537 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1538 return err;
1539
1540 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1541 return err;
1542
1543 par->crtc = crtc;
1544 par->pll = pll;
1545 par->fifo_reg = fifo_reg;
1546 par->accel_flags = var->accel_flags;
1547
1548 return 0;
1549 }
1550
1551
1552 static int aty128_encode_var(struct fb_var_screeninfo *var,
1553 const struct aty128fb_par *par)
1554 {
1555 int err;
1556
1557 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1558 return err;
1559
1560 if ((err = aty128_pll_to_var(&par->pll, var)))
1561 return err;
1562
1563 var->nonstd = 0;
1564 var->activate = 0;
1565
1566 var->height = -1;
1567 var->width = -1;
1568 var->accel_flags = par->accel_flags;
1569
1570 return 0;
1571 }
1572
1573
1574 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1575 struct fb_info *info)
1576 {
1577 struct aty128fb_par par;
1578 int err;
1579
1580 par = *(struct aty128fb_par *)info->par;
1581 if ((err = aty128_decode_var(var, &par)) != 0)
1582 return err;
1583 aty128_encode_var(var, &par);
1584 return 0;
1585 }
1586
1587
1588 /*
1589 * Pan or Wrap the Display
1590 */
1591 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1592 struct fb_info *fb)
1593 {
1594 struct aty128fb_par *par = fb->par;
1595 u32 xoffset, yoffset;
1596 u32 offset;
1597 u32 xres, yres;
1598
1599 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1600 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1601
1602 xoffset = (var->xoffset +7) & ~7;
1603 yoffset = var->yoffset;
1604
1605 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1606 return -EINVAL;
1607
1608 par->crtc.xoffset = xoffset;
1609 par->crtc.yoffset = yoffset;
1610
1611 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1612 & ~7;
1613
1614 if (par->crtc.bpp == 24)
1615 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1616
1617 aty_st_le32(CRTC_OFFSET, offset);
1618
1619 return 0;
1620 }
1621
1622
1623 /*
1624 * Helper function to store a single palette register
1625 */
1626 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1627 struct aty128fb_par *par)
1628 {
1629 if (par->chip_gen == rage_M3) {
1630 #if 0
1631 /* Note: For now, on M3, we set palette on both heads, which may
1632 * be useless. Can someone with a M3 check this ?
1633 *
1634 * This code would still be useful if using the second CRTC to
1635 * do mirroring
1636 */
1637
1638 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1639 DAC_PALETTE_ACCESS_CNTL);
1640 aty_st_8(PALETTE_INDEX, regno);
1641 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1642 #endif
1643 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1644 ~DAC_PALETTE_ACCESS_CNTL);
1645 }
1646
1647 aty_st_8(PALETTE_INDEX, regno);
1648 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1649 }
1650
1651 static int aty128fb_sync(struct fb_info *info)
1652 {
1653 struct aty128fb_par *par = info->par;
1654
1655 if (par->blitter_may_be_busy)
1656 wait_for_idle(par);
1657 return 0;
1658 }
1659
1660 #ifndef MODULE
1661 static int __devinit aty128fb_setup(char *options)
1662 {
1663 char *this_opt;
1664
1665 if (!options || !*options)
1666 return 0;
1667
1668 while ((this_opt = strsep(&options, ",")) != NULL) {
1669 if (!strncmp(this_opt, "lcd:", 4)) {
1670 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1671 continue;
1672 } else if (!strncmp(this_opt, "crt:", 4)) {
1673 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1674 continue;
1675 } else if (!strncmp(this_opt, "backlight:", 10)) {
1676 backlight = simple_strtoul(this_opt+10, NULL, 0);
1677 continue;
1678 }
1679 #ifdef CONFIG_MTRR
1680 if(!strncmp(this_opt, "nomtrr", 6)) {
1681 mtrr = 0;
1682 continue;
1683 }
1684 #endif
1685 #ifdef CONFIG_PPC_PMAC
1686 /* vmode and cmode deprecated */
1687 if (!strncmp(this_opt, "vmode:", 6)) {
1688 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1689 if (vmode > 0 && vmode <= VMODE_MAX)
1690 default_vmode = vmode;
1691 continue;
1692 } else if (!strncmp(this_opt, "cmode:", 6)) {
1693 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1694 switch (cmode) {
1695 case 0:
1696 case 8:
1697 default_cmode = CMODE_8;
1698 break;
1699 case 15:
1700 case 16:
1701 default_cmode = CMODE_16;
1702 break;
1703 case 24:
1704 case 32:
1705 default_cmode = CMODE_32;
1706 break;
1707 }
1708 continue;
1709 }
1710 #endif /* CONFIG_PPC_PMAC */
1711 mode_option = this_opt;
1712 }
1713 return 0;
1714 }
1715 #endif /* MODULE */
1716
1717 /* Backlight */
1718 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1719 #define MAX_LEVEL 0xFF
1720
1721 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1722 int level)
1723 {
1724 struct fb_info *info = pci_get_drvdata(par->pdev);
1725 int atylevel;
1726
1727 /* Get and convert the value */
1728 /* No locking of bl_curve since we read a single value */
1729 atylevel = MAX_LEVEL -
1730 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1731
1732 if (atylevel < 0)
1733 atylevel = 0;
1734 else if (atylevel > MAX_LEVEL)
1735 atylevel = MAX_LEVEL;
1736
1737 return atylevel;
1738 }
1739
1740 /* We turn off the LCD completely instead of just dimming the backlight.
1741 * This provides greater power saving and the display is useless without
1742 * backlight anyway
1743 */
1744 #define BACKLIGHT_LVDS_OFF
1745 /* That one prevents proper CRT output with LCD off */
1746 #undef BACKLIGHT_DAC_OFF
1747
1748 static int aty128_bl_update_status(struct backlight_device *bd)
1749 {
1750 struct aty128fb_par *par = bl_get_data(bd);
1751 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1752 int level;
1753
1754 if (bd->props.power != FB_BLANK_UNBLANK ||
1755 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1756 !par->lcd_on)
1757 level = 0;
1758 else
1759 level = bd->props.brightness;
1760
1761 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1762 if (level > 0) {
1763 reg |= LVDS_DIGION;
1764 if (!(reg & LVDS_ON)) {
1765 reg &= ~LVDS_BLON;
1766 aty_st_le32(LVDS_GEN_CNTL, reg);
1767 aty_ld_le32(LVDS_GEN_CNTL);
1768 mdelay(10);
1769 reg |= LVDS_BLON;
1770 aty_st_le32(LVDS_GEN_CNTL, reg);
1771 }
1772 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1773 reg |= (aty128_bl_get_level_brightness(par, level) <<
1774 LVDS_BL_MOD_LEVEL_SHIFT);
1775 #ifdef BACKLIGHT_LVDS_OFF
1776 reg |= LVDS_ON | LVDS_EN;
1777 reg &= ~LVDS_DISPLAY_DIS;
1778 #endif
1779 aty_st_le32(LVDS_GEN_CNTL, reg);
1780 #ifdef BACKLIGHT_DAC_OFF
1781 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1782 #endif
1783 } else {
1784 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1785 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1786 LVDS_BL_MOD_LEVEL_SHIFT);
1787 #ifdef BACKLIGHT_LVDS_OFF
1788 reg |= LVDS_DISPLAY_DIS;
1789 aty_st_le32(LVDS_GEN_CNTL, reg);
1790 aty_ld_le32(LVDS_GEN_CNTL);
1791 udelay(10);
1792 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1793 #endif
1794 aty_st_le32(LVDS_GEN_CNTL, reg);
1795 #ifdef BACKLIGHT_DAC_OFF
1796 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1797 #endif
1798 }
1799
1800 return 0;
1801 }
1802
1803 static int aty128_bl_get_brightness(struct backlight_device *bd)
1804 {
1805 return bd->props.brightness;
1806 }
1807
1808 static const struct backlight_ops aty128_bl_data = {
1809 .get_brightness = aty128_bl_get_brightness,
1810 .update_status = aty128_bl_update_status,
1811 };
1812
1813 static void aty128_bl_set_power(struct fb_info *info, int power)
1814 {
1815 if (info->bl_dev) {
1816 info->bl_dev->props.power = power;
1817 backlight_update_status(info->bl_dev);
1818 }
1819 }
1820
1821 static void aty128_bl_init(struct aty128fb_par *par)
1822 {
1823 struct backlight_properties props;
1824 struct fb_info *info = pci_get_drvdata(par->pdev);
1825 struct backlight_device *bd;
1826 char name[12];
1827
1828 /* Could be extended to Rage128Pro LVDS output too */
1829 if (par->chip_gen != rage_M3)
1830 return;
1831
1832 #ifdef CONFIG_PMAC_BACKLIGHT
1833 if (!pmac_has_backlight_type("ati"))
1834 return;
1835 #endif
1836
1837 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1838
1839 memset(&props, 0, sizeof(struct backlight_properties));
1840 props.type = BACKLIGHT_RAW;
1841 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1842 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1843 &props);
1844 if (IS_ERR(bd)) {
1845 info->bl_dev = NULL;
1846 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1847 goto error;
1848 }
1849
1850 info->bl_dev = bd;
1851 fb_bl_default_curve(info, 0,
1852 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1853 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1854
1855 bd->props.brightness = bd->props.max_brightness;
1856 bd->props.power = FB_BLANK_UNBLANK;
1857 backlight_update_status(bd);
1858
1859 printk("aty128: Backlight initialized (%s)\n", name);
1860
1861 return;
1862
1863 error:
1864 return;
1865 }
1866
1867 static void aty128_bl_exit(struct backlight_device *bd)
1868 {
1869 backlight_device_unregister(bd);
1870 printk("aty128: Backlight unloaded\n");
1871 }
1872 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1873
1874 /*
1875 * Initialisation
1876 */
1877
1878 #ifdef CONFIG_PPC_PMAC__disabled
1879 static void aty128_early_resume(void *data)
1880 {
1881 struct aty128fb_par *par = data;
1882
1883 if (!console_trylock())
1884 return;
1885 pci_restore_state(par->pdev);
1886 aty128_do_resume(par->pdev);
1887 console_unlock();
1888 }
1889 #endif /* CONFIG_PPC_PMAC */
1890
1891 static int __devinit aty128_init(struct pci_dev *pdev,
1892 const struct pci_device_id *ent)
1893 {
1894 struct fb_info *info = pci_get_drvdata(pdev);
1895 struct aty128fb_par *par = info->par;
1896 struct fb_var_screeninfo var;
1897 char video_card[50];
1898 u8 chip_rev;
1899 u32 dac;
1900
1901 /* Get the chip revision */
1902 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1903
1904 strcpy(video_card, "Rage128 XX ");
1905 video_card[8] = ent->device >> 8;
1906 video_card[9] = ent->device & 0xFF;
1907
1908 /* range check to make sure */
1909 if (ent->driver_data < ARRAY_SIZE(r128_family))
1910 strlcat(video_card, r128_family[ent->driver_data],
1911 sizeof(video_card));
1912
1913 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1914
1915 if (par->vram_size % (1024 * 1024) == 0)
1916 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1917 else
1918 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1919
1920 par->chip_gen = ent->driver_data;
1921
1922 /* fill in info */
1923 info->fbops = &aty128fb_ops;
1924 info->flags = FBINFO_FLAG_DEFAULT;
1925
1926 par->lcd_on = default_lcd_on;
1927 par->crt_on = default_crt_on;
1928
1929 var = default_var;
1930 #ifdef CONFIG_PPC_PMAC
1931 if (machine_is(powermac)) {
1932 /* Indicate sleep capability */
1933 if (par->chip_gen == rage_M3) {
1934 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1935 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1936 * among others we now rely on the PCI core restoring the config space
1937 * for us, which isn't the case with that hack, and that code path causes
1938 * various things to be called with interrupts off while they shouldn't.
1939 * I'm leaving the code in as it can be useful for debugging purposes
1940 */
1941 pmac_set_early_video_resume(aty128_early_resume, par);
1942 #endif
1943 }
1944
1945 /* Find default mode */
1946 if (mode_option) {
1947 if (!mac_find_mode(&var, info, mode_option, 8))
1948 var = default_var;
1949 } else {
1950 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1951 default_vmode = VMODE_1024_768_60;
1952
1953 /* iMacs need that resolution
1954 * PowerMac2,1 first r128 iMacs
1955 * PowerMac2,2 summer 2000 iMacs
1956 * PowerMac4,1 january 2001 iMacs "flower power"
1957 */
1958 if (of_machine_is_compatible("PowerMac2,1") ||
1959 of_machine_is_compatible("PowerMac2,2") ||
1960 of_machine_is_compatible("PowerMac4,1"))
1961 default_vmode = VMODE_1024_768_75;
1962
1963 /* iBook SE */
1964 if (of_machine_is_compatible("PowerBook2,2"))
1965 default_vmode = VMODE_800_600_60;
1966
1967 /* PowerBook Firewire (Pismo), iBook Dual USB */
1968 if (of_machine_is_compatible("PowerBook3,1") ||
1969 of_machine_is_compatible("PowerBook4,1"))
1970 default_vmode = VMODE_1024_768_60;
1971
1972 /* PowerBook Titanium */
1973 if (of_machine_is_compatible("PowerBook3,2"))
1974 default_vmode = VMODE_1152_768_60;
1975
1976 if (default_cmode > 16)
1977 default_cmode = CMODE_32;
1978 else if (default_cmode > 8)
1979 default_cmode = CMODE_16;
1980 else
1981 default_cmode = CMODE_8;
1982
1983 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1984 var = default_var;
1985 }
1986 } else
1987 #endif /* CONFIG_PPC_PMAC */
1988 {
1989 if (mode_option)
1990 if (fb_find_mode(&var, info, mode_option, NULL,
1991 0, &defaultmode, 8) == 0)
1992 var = default_var;
1993 }
1994
1995 var.accel_flags &= ~FB_ACCELF_TEXT;
1996 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1997
1998 if (aty128fb_check_var(&var, info)) {
1999 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2000 return 0;
2001 }
2002
2003 /* setup the DAC the way we like it */
2004 dac = aty_ld_le32(DAC_CNTL);
2005 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2006 dac |= DAC_MASK;
2007 if (par->chip_gen == rage_M3)
2008 dac |= DAC_PALETTE2_SNOOP_EN;
2009 aty_st_le32(DAC_CNTL, dac);
2010
2011 /* turn off bus mastering, just in case */
2012 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2013
2014 info->var = var;
2015 fb_alloc_cmap(&info->cmap, 256, 0);
2016
2017 var.activate = FB_ACTIVATE_NOW;
2018
2019 aty128_init_engine(par);
2020
2021 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2022 par->pdev = pdev;
2023 par->asleep = 0;
2024 par->lock_blank = 0;
2025
2026 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2027 if (backlight)
2028 aty128_bl_init(par);
2029 #endif
2030
2031 if (register_framebuffer(info) < 0)
2032 return 0;
2033
2034 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
2035 info->node, info->fix.id, video_card);
2036
2037 return 1; /* success! */
2038 }
2039
2040 #ifdef CONFIG_PCI
2041 /* register a card ++ajoshi */
2042 static int __devinit aty128_probe(struct pci_dev *pdev,
2043 const struct pci_device_id *ent)
2044 {
2045 unsigned long fb_addr, reg_addr;
2046 struct aty128fb_par *par;
2047 struct fb_info *info;
2048 int err;
2049 #ifndef __sparc__
2050 void __iomem *bios = NULL;
2051 #endif
2052
2053 /* Enable device in PCI config */
2054 if ((err = pci_enable_device(pdev))) {
2055 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2056 err);
2057 return -ENODEV;
2058 }
2059
2060 fb_addr = pci_resource_start(pdev, 0);
2061 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2062 "aty128fb FB")) {
2063 printk(KERN_ERR "aty128fb: cannot reserve frame "
2064 "buffer memory\n");
2065 return -ENODEV;
2066 }
2067
2068 reg_addr = pci_resource_start(pdev, 2);
2069 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2070 "aty128fb MMIO")) {
2071 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2072 goto err_free_fb;
2073 }
2074
2075 /* We have the resources. Now virtualize them */
2076 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2077 if (info == NULL) {
2078 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2079 goto err_free_mmio;
2080 }
2081 par = info->par;
2082
2083 info->pseudo_palette = par->pseudo_palette;
2084
2085 /* Virtualize mmio region */
2086 info->fix.mmio_start = reg_addr;
2087 par->regbase = pci_ioremap_bar(pdev, 2);
2088 if (!par->regbase)
2089 goto err_free_info;
2090
2091 /* Grab memory size from the card */
2092 // How does this relate to the resource length from the PCI hardware?
2093 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2094
2095 /* Virtualize the framebuffer */
2096 info->screen_base = ioremap(fb_addr, par->vram_size);
2097 if (!info->screen_base)
2098 goto err_unmap_out;
2099
2100 /* Set up info->fix */
2101 info->fix = aty128fb_fix;
2102 info->fix.smem_start = fb_addr;
2103 info->fix.smem_len = par->vram_size;
2104 info->fix.mmio_start = reg_addr;
2105
2106 /* If we can't test scratch registers, something is seriously wrong */
2107 if (!register_test(par)) {
2108 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2109 goto err_out;
2110 }
2111
2112 #ifndef __sparc__
2113 bios = aty128_map_ROM(par, pdev);
2114 #ifdef CONFIG_X86
2115 if (bios == NULL)
2116 bios = aty128_find_mem_vbios(par);
2117 #endif
2118 if (bios == NULL)
2119 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2120 else {
2121 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2122 aty128_get_pllinfo(par, bios);
2123 pci_unmap_rom(pdev, bios);
2124 }
2125 #endif /* __sparc__ */
2126
2127 aty128_timings(par);
2128 pci_set_drvdata(pdev, info);
2129
2130 if (!aty128_init(pdev, ent))
2131 goto err_out;
2132
2133 #ifdef CONFIG_MTRR
2134 if (mtrr) {
2135 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2136 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2137 par->mtrr.vram_valid = 1;
2138 /* let there be speed */
2139 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2140 }
2141 #endif /* CONFIG_MTRR */
2142 return 0;
2143
2144 err_out:
2145 iounmap(info->screen_base);
2146 err_unmap_out:
2147 iounmap(par->regbase);
2148 err_free_info:
2149 framebuffer_release(info);
2150 err_free_mmio:
2151 release_mem_region(pci_resource_start(pdev, 2),
2152 pci_resource_len(pdev, 2));
2153 err_free_fb:
2154 release_mem_region(pci_resource_start(pdev, 0),
2155 pci_resource_len(pdev, 0));
2156 return -ENODEV;
2157 }
2158
2159 static void __devexit aty128_remove(struct pci_dev *pdev)
2160 {
2161 struct fb_info *info = pci_get_drvdata(pdev);
2162 struct aty128fb_par *par;
2163
2164 if (!info)
2165 return;
2166
2167 par = info->par;
2168
2169 unregister_framebuffer(info);
2170
2171 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2172 aty128_bl_exit(info->bl_dev);
2173 #endif
2174
2175 #ifdef CONFIG_MTRR
2176 if (par->mtrr.vram_valid)
2177 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2178 par->vram_size);
2179 #endif /* CONFIG_MTRR */
2180 iounmap(par->regbase);
2181 iounmap(info->screen_base);
2182
2183 release_mem_region(pci_resource_start(pdev, 0),
2184 pci_resource_len(pdev, 0));
2185 release_mem_region(pci_resource_start(pdev, 2),
2186 pci_resource_len(pdev, 2));
2187 framebuffer_release(info);
2188 }
2189 #endif /* CONFIG_PCI */
2190
2191
2192
2193 /*
2194 * Blank the display.
2195 */
2196 static int aty128fb_blank(int blank, struct fb_info *fb)
2197 {
2198 struct aty128fb_par *par = fb->par;
2199 u8 state;
2200
2201 if (par->lock_blank || par->asleep)
2202 return 0;
2203
2204 switch (blank) {
2205 case FB_BLANK_NORMAL:
2206 state = 4;
2207 break;
2208 case FB_BLANK_VSYNC_SUSPEND:
2209 state = 6;
2210 break;
2211 case FB_BLANK_HSYNC_SUSPEND:
2212 state = 5;
2213 break;
2214 case FB_BLANK_POWERDOWN:
2215 state = 7;
2216 break;
2217 case FB_BLANK_UNBLANK:
2218 default:
2219 state = 0;
2220 break;
2221 }
2222 aty_st_8(CRTC_EXT_CNTL+1, state);
2223
2224 if (par->chip_gen == rage_M3) {
2225 aty128_set_crt_enable(par, par->crt_on && !blank);
2226 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2227 }
2228
2229 return 0;
2230 }
2231
2232 /*
2233 * Set a single color register. The values supplied are already
2234 * rounded down to the hardware's capabilities (according to the
2235 * entries in the var structure). Return != 0 for invalid regno.
2236 */
2237 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2238 u_int transp, struct fb_info *info)
2239 {
2240 struct aty128fb_par *par = info->par;
2241
2242 if (regno > 255
2243 || (par->crtc.depth == 16 && regno > 63)
2244 || (par->crtc.depth == 15 && regno > 31))
2245 return 1;
2246
2247 red >>= 8;
2248 green >>= 8;
2249 blue >>= 8;
2250
2251 if (regno < 16) {
2252 int i;
2253 u32 *pal = info->pseudo_palette;
2254
2255 switch (par->crtc.depth) {
2256 case 15:
2257 pal[regno] = (regno << 10) | (regno << 5) | regno;
2258 break;
2259 case 16:
2260 pal[regno] = (regno << 11) | (regno << 6) | regno;
2261 break;
2262 case 24:
2263 pal[regno] = (regno << 16) | (regno << 8) | regno;
2264 break;
2265 case 32:
2266 i = (regno << 8) | regno;
2267 pal[regno] = (i << 16) | i;
2268 break;
2269 }
2270 }
2271
2272 if (par->crtc.depth == 16 && regno > 0) {
2273 /*
2274 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2275 * have 32 slots for R and B values but 64 slots for G values.
2276 * Thus the R and B values go in one slot but the G value
2277 * goes in a different slot, and we have to avoid disturbing
2278 * the other fields in the slots we touch.
2279 */
2280 par->green[regno] = green;
2281 if (regno < 32) {
2282 par->red[regno] = red;
2283 par->blue[regno] = blue;
2284 aty128_st_pal(regno * 8, red, par->green[regno*2],
2285 blue, par);
2286 }
2287 red = par->red[regno/2];
2288 blue = par->blue[regno/2];
2289 regno <<= 2;
2290 } else if (par->crtc.bpp == 16)
2291 regno <<= 3;
2292 aty128_st_pal(regno, red, green, blue, par);
2293
2294 return 0;
2295 }
2296
2297 #define ATY_MIRROR_LCD_ON 0x00000001
2298 #define ATY_MIRROR_CRT_ON 0x00000002
2299
2300 /* out param: u32* backlight value: 0 to 15 */
2301 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2302 /* in param: u32* backlight value: 0 to 15 */
2303 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2304
2305 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2306 {
2307 struct aty128fb_par *par = info->par;
2308 u32 value;
2309 int rc;
2310
2311 switch (cmd) {
2312 case FBIO_ATY128_SET_MIRROR:
2313 if (par->chip_gen != rage_M3)
2314 return -EINVAL;
2315 rc = get_user(value, (__u32 __user *)arg);
2316 if (rc)
2317 return rc;
2318 par->lcd_on = (value & 0x01) != 0;
2319 par->crt_on = (value & 0x02) != 0;
2320 if (!par->crt_on && !par->lcd_on)
2321 par->lcd_on = 1;
2322 aty128_set_crt_enable(par, par->crt_on);
2323 aty128_set_lcd_enable(par, par->lcd_on);
2324 return 0;
2325 case FBIO_ATY128_GET_MIRROR:
2326 if (par->chip_gen != rage_M3)
2327 return -EINVAL;
2328 value = (par->crt_on << 1) | par->lcd_on;
2329 return put_user(value, (__u32 __user *)arg);
2330 }
2331 return -EINVAL;
2332 }
2333
2334 #if 0
2335 /*
2336 * Accelerated functions
2337 */
2338
2339 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2340 u_int width, u_int height,
2341 struct fb_info_aty128 *par)
2342 {
2343 u32 save_dp_datatype, save_dp_cntl, dstval;
2344
2345 if (!width || !height)
2346 return;
2347
2348 dstval = depth_to_dst(par->current_par.crtc.depth);
2349 if (dstval == DST_24BPP) {
2350 srcx *= 3;
2351 dstx *= 3;
2352 width *= 3;
2353 } else if (dstval == -EINVAL) {
2354 printk("aty128fb: invalid depth or RGBA\n");
2355 return;
2356 }
2357
2358 wait_for_fifo(2, par);
2359 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2360 save_dp_cntl = aty_ld_le32(DP_CNTL);
2361
2362 wait_for_fifo(6, par);
2363 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2364 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2365 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2366 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2367
2368 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2369 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2370
2371 par->blitter_may_be_busy = 1;
2372
2373 wait_for_fifo(2, par);
2374 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2375 aty_st_le32(DP_CNTL, save_dp_cntl);
2376 }
2377
2378
2379 /*
2380 * Text mode accelerated functions
2381 */
2382
2383 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy,
2384 int dx, int height, int width)
2385 {
2386 sx *= fontwidth(p);
2387 sy *= fontheight(p);
2388 dx *= fontwidth(p);
2389 dy *= fontheight(p);
2390 width *= fontwidth(p);
2391 height *= fontheight(p);
2392
2393 aty128_rectcopy(sx, sy, dx, dy, width, height,
2394 (struct fb_info_aty128 *)p->fb_info);
2395 }
2396 #endif /* 0 */
2397
2398 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2399 {
2400 u32 pmgt;
2401 struct pci_dev *pdev = par->pdev;
2402
2403 if (!par->pm_reg)
2404 return;
2405
2406 /* Set the chip into the appropriate suspend mode (we use D2,
2407 * D3 would require a complete re-initialisation of the chip,
2408 * including PCI config registers, clocks, AGP configuration, ...)
2409 *
2410 * For resume, the core will have already brought us back to D0
2411 */
2412 if (suspend) {
2413 /* Make sure CRTC2 is reset. Remove that the day we decide to
2414 * actually use CRTC2 and replace it with real code for disabling
2415 * the CRTC2 output during sleep
2416 */
2417 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2418 ~(CRTC2_EN));
2419
2420 /* Set the power management mode to be PCI based */
2421 /* Use this magic value for now */
2422 pmgt = 0x0c005407;
2423 aty_st_pll(POWER_MANAGEMENT, pmgt);
2424 (void)aty_ld_pll(POWER_MANAGEMENT);
2425 aty_st_le32(BUS_CNTL1, 0x00000010);
2426 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2427 mdelay(100);
2428
2429 /* Switch PCI power management to D2 */
2430 pci_set_power_state(pdev, PCI_D2);
2431 }
2432 }
2433
2434 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2435 {
2436 struct fb_info *info = pci_get_drvdata(pdev);
2437 struct aty128fb_par *par = info->par;
2438
2439 /* Because we may change PCI D state ourselves, we need to
2440 * first save the config space content so the core can
2441 * restore it properly on resume.
2442 */
2443 pci_save_state(pdev);
2444
2445 /* We don't do anything but D2, for now we return 0, but
2446 * we may want to change that. How do we know if the BIOS
2447 * can properly take care of D3 ? Also, with swsusp, we
2448 * know we'll be rebooted, ...
2449 */
2450 #ifndef CONFIG_PPC_PMAC
2451 /* HACK ALERT ! Once I find a proper way to say to each driver
2452 * individually what will happen with it's PCI slot, I'll change
2453 * that. On laptops, the AGP slot is just unclocked, so D2 is
2454 * expected, while on desktops, the card is powered off
2455 */
2456 return 0;
2457 #endif /* CONFIG_PPC_PMAC */
2458
2459 if (state.event == pdev->dev.power.power_state.event)
2460 return 0;
2461
2462 printk(KERN_DEBUG "aty128fb: suspending...\n");
2463
2464 console_lock();
2465
2466 fb_set_suspend(info, 1);
2467
2468 /* Make sure engine is reset */
2469 wait_for_idle(par);
2470 aty128_reset_engine(par);
2471 wait_for_idle(par);
2472
2473 /* Blank display and LCD */
2474 aty128fb_blank(FB_BLANK_POWERDOWN, info);
2475
2476 /* Sleep */
2477 par->asleep = 1;
2478 par->lock_blank = 1;
2479
2480 #ifdef CONFIG_PPC_PMAC
2481 /* On powermac, we have hooks to properly suspend/resume AGP now,
2482 * use them here. We'll ultimately need some generic support here,
2483 * but the generic code isn't quite ready for that yet
2484 */
2485 pmac_suspend_agp_for_card(pdev);
2486 #endif /* CONFIG_PPC_PMAC */
2487
2488 /* We need a way to make sure the fbdev layer will _not_ touch the
2489 * framebuffer before we put the chip to suspend state. On 2.4, I
2490 * used dummy fb ops, 2.5 need proper support for this at the
2491 * fbdev level
2492 */
2493 if (state.event != PM_EVENT_ON)
2494 aty128_set_suspend(par, 1);
2495
2496 console_unlock();
2497
2498 pdev->dev.power.power_state = state;
2499
2500 return 0;
2501 }
2502
2503 static int aty128_do_resume(struct pci_dev *pdev)
2504 {
2505 struct fb_info *info = pci_get_drvdata(pdev);
2506 struct aty128fb_par *par = info->par;
2507
2508 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2509 return 0;
2510
2511 /* PCI state will have been restored by the core, so
2512 * we should be in D0 now with our config space fully
2513 * restored
2514 */
2515
2516 /* Wakeup chip */
2517 aty128_set_suspend(par, 0);
2518 par->asleep = 0;
2519
2520 /* Restore display & engine */
2521 aty128_reset_engine(par);
2522 wait_for_idle(par);
2523 aty128fb_set_par(info);
2524 fb_pan_display(info, &info->var);
2525 fb_set_cmap(&info->cmap, info);
2526
2527 /* Refresh */
2528 fb_set_suspend(info, 0);
2529
2530 /* Unblank */
2531 par->lock_blank = 0;
2532 aty128fb_blank(0, info);
2533
2534 #ifdef CONFIG_PPC_PMAC
2535 /* On powermac, we have hooks to properly suspend/resume AGP now,
2536 * use them here. We'll ultimately need some generic support here,
2537 * but the generic code isn't quite ready for that yet
2538 */
2539 pmac_resume_agp_for_card(pdev);
2540 #endif /* CONFIG_PPC_PMAC */
2541
2542 pdev->dev.power.power_state = PMSG_ON;
2543
2544 printk(KERN_DEBUG "aty128fb: resumed !\n");
2545
2546 return 0;
2547 }
2548
2549 static int aty128_pci_resume(struct pci_dev *pdev)
2550 {
2551 int rc;
2552
2553 console_lock();
2554 rc = aty128_do_resume(pdev);
2555 console_unlock();
2556
2557 return rc;
2558 }
2559
2560
2561 static int __devinit aty128fb_init(void)
2562 {
2563 #ifndef MODULE
2564 char *option = NULL;
2565
2566 if (fb_get_options("aty128fb", &option))
2567 return -ENODEV;
2568 aty128fb_setup(option);
2569 #endif
2570
2571 return pci_register_driver(&aty128fb_driver);
2572 }
2573
2574 static void __exit aty128fb_exit(void)
2575 {
2576 pci_unregister_driver(&aty128fb_driver);
2577 }
2578
2579 module_init(aty128fb_init);
2580
2581 module_exit(aty128fb_exit);
2582
2583 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2584 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2585 MODULE_LICENSE("GPL");
2586 module_param(mode_option, charp, 0);
2587 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2588 #ifdef CONFIG_MTRR
2589 module_param_named(nomtrr, mtrr, invbool, 0);
2590 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2591 #endif
2592
kernel source for telekom puls (alcatel/mediatek)