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Merge tag 'md-3.3-fixes' of git://neil.brown.name/md
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / musb / tusb6010.c
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/prefetch.h>
22 #include <linux/usb.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26
27 #include "musb_core.h"
28
29 struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32 };
33
34 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
35
36 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
37 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
38
39 /*
40 * Checks the revision. We need to use the DMA register as 3.0 does not
41 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
42 */
43 u8 tusb_get_revision(struct musb *musb)
44 {
45 void __iomem *tbase = musb->ctrl_base;
46 u32 die_id;
47 u8 rev;
48
49 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
50 if (TUSB_REV_MAJOR(rev) == 3) {
51 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
52 TUSB_DIDR1_HI));
53 if (die_id >= TUSB_DIDR1_HI_REV_31)
54 rev |= 1;
55 }
56
57 return rev;
58 }
59 EXPORT_SYMBOL_GPL(tusb_get_revision);
60
61 static int tusb_print_revision(struct musb *musb)
62 {
63 void __iomem *tbase = musb->ctrl_base;
64 u8 rev;
65
66 rev = tusb_get_revision(musb);
67
68 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
69 "prcm",
70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
72 "int",
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
75 "gpio",
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
78 "dma",
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
81 "dieid",
82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
83 "rev",
84 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
85
86 return tusb_get_revision(musb);
87 }
88
89 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
90 | TUSB_PHY_OTG_CTRL_TESTM0)
91
92 /*
93 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
94 * Disables power detection in PHY for the duration of idle.
95 */
96 static void tusb_wbus_quirk(struct musb *musb, int enabled)
97 {
98 void __iomem *tbase = musb->ctrl_base;
99 static u32 phy_otg_ctrl, phy_otg_ena;
100 u32 tmp;
101
102 if (enabled) {
103 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
104 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
105 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
106 | phy_otg_ena | WBUS_QUIRK_MASK;
107 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
108 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
109 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
110 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
111 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
112 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
113 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
114 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
115 & TUSB_PHY_OTG_CTRL_TESTM2) {
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
118 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
119 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
120 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
121 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
122 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
123 phy_otg_ctrl = 0;
124 phy_otg_ena = 0;
125 }
126 }
127
128 /*
129 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
130 * so both loading and unloading FIFOs need explicit byte counts.
131 */
132
133 static inline void
134 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
135 {
136 u32 val;
137 int i;
138
139 if (len > 4) {
140 for (i = 0; i < (len >> 2); i++) {
141 memcpy(&val, buf, 4);
142 musb_writel(fifo, 0, val);
143 buf += 4;
144 }
145 len %= 4;
146 }
147 if (len > 0) {
148 /* Write the rest 1 - 3 bytes to FIFO */
149 memcpy(&val, buf, len);
150 musb_writel(fifo, 0, val);
151 }
152 }
153
154 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
155 void __iomem *buf, u16 len)
156 {
157 u32 val;
158 int i;
159
160 if (len > 4) {
161 for (i = 0; i < (len >> 2); i++) {
162 val = musb_readl(fifo, 0);
163 memcpy(buf, &val, 4);
164 buf += 4;
165 }
166 len %= 4;
167 }
168 if (len > 0) {
169 /* Read the rest 1 - 3 bytes from FIFO */
170 val = musb_readl(fifo, 0);
171 memcpy(buf, &val, len);
172 }
173 }
174
175 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
176 {
177 struct musb *musb = hw_ep->musb;
178 void __iomem *ep_conf = hw_ep->conf;
179 void __iomem *fifo = hw_ep->fifo;
180 u8 epnum = hw_ep->epnum;
181
182 prefetch(buf);
183
184 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
185 'T', epnum, fifo, len, buf);
186
187 if (epnum)
188 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
189 TUSB_EP_CONFIG_XFR_SIZE(len));
190 else
191 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
192 TUSB_EP0_CONFIG_XFR_SIZE(len));
193
194 if (likely((0x01 & (unsigned long) buf) == 0)) {
195
196 /* Best case is 32bit-aligned destination address */
197 if ((0x02 & (unsigned long) buf) == 0) {
198 if (len >= 4) {
199 writesl(fifo, buf, len >> 2);
200 buf += (len & ~0x03);
201 len &= 0x03;
202 }
203 } else {
204 if (len >= 2) {
205 u32 val;
206 int i;
207
208 /* Cannot use writesw, fifo is 32-bit */
209 for (i = 0; i < (len >> 2); i++) {
210 val = (u32)(*(u16 *)buf);
211 buf += 2;
212 val |= (*(u16 *)buf) << 16;
213 buf += 2;
214 musb_writel(fifo, 0, val);
215 }
216 len &= 0x03;
217 }
218 }
219 }
220
221 if (len > 0)
222 tusb_fifo_write_unaligned(fifo, buf, len);
223 }
224
225 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
226 {
227 struct musb *musb = hw_ep->musb;
228 void __iomem *ep_conf = hw_ep->conf;
229 void __iomem *fifo = hw_ep->fifo;
230 u8 epnum = hw_ep->epnum;
231
232 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
233 'R', epnum, fifo, len, buf);
234
235 if (epnum)
236 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
237 TUSB_EP_CONFIG_XFR_SIZE(len));
238 else
239 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
240
241 if (likely((0x01 & (unsigned long) buf) == 0)) {
242
243 /* Best case is 32bit-aligned destination address */
244 if ((0x02 & (unsigned long) buf) == 0) {
245 if (len >= 4) {
246 readsl(fifo, buf, len >> 2);
247 buf += (len & ~0x03);
248 len &= 0x03;
249 }
250 } else {
251 if (len >= 2) {
252 u32 val;
253 int i;
254
255 /* Cannot use readsw, fifo is 32-bit */
256 for (i = 0; i < (len >> 2); i++) {
257 val = musb_readl(fifo, 0);
258 *(u16 *)buf = (u16)(val & 0xffff);
259 buf += 2;
260 *(u16 *)buf = (u16)(val >> 16);
261 buf += 2;
262 }
263 len &= 0x03;
264 }
265 }
266 }
267
268 if (len > 0)
269 tusb_fifo_read_unaligned(fifo, buf, len);
270 }
271
272 static struct musb *the_musb;
273
274 /* This is used by gadget drivers, and OTG transceiver logic, allowing
275 * at most mA current to be drawn from VBUS during a Default-B session
276 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
277 * mode), or low power Default-B sessions, something else supplies power.
278 * Caller must take care of locking.
279 */
280 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
281 {
282 struct musb *musb = the_musb;
283 void __iomem *tbase = musb->ctrl_base;
284 u32 reg;
285
286 /* tps65030 seems to consume max 100mA, with maybe 60mA available
287 * (measured on one board) for things other than tps and tusb.
288 *
289 * Boards sharing the CPU clock with CLKIN will need to prevent
290 * certain idle sleep states while the USB link is active.
291 *
292 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
293 * The actual current usage would be very board-specific. For now,
294 * it's simpler to just use an aggregate (also board-specific).
295 */
296 if (x->default_a || mA < (musb->min_power << 1))
297 mA = 0;
298
299 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
300 if (mA) {
301 musb->is_bus_powered = 1;
302 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
303 } else {
304 musb->is_bus_powered = 0;
305 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
306 }
307 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
308
309 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
310 return 0;
311 }
312
313 /* workaround for issue 13: change clock during chip idle
314 * (to be fixed in rev3 silicon) ... symptoms include disconnect
315 * or looping suspend/resume cycles
316 */
317 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
318 {
319 void __iomem *tbase = musb->ctrl_base;
320 u32 reg;
321
322 reg = musb_readl(tbase, TUSB_PRCM_CONF);
323 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
324
325 /* 0 = refclk (clkin, XI)
326 * 1 = PHY 60 MHz (internal PLL)
327 * 2 = not supported
328 * 3 = what?
329 */
330 if (mode > 0)
331 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
332
333 musb_writel(tbase, TUSB_PRCM_CONF, reg);
334
335 /* FIXME tusb6010_platform_retime(mode == 0); */
336 }
337
338 /*
339 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
340 * Other code ensures that we idle unless we're connected _and_ the
341 * USB link is not suspended ... and tells us the relevant wakeup
342 * events. SW_EN for voltage is handled separately.
343 */
344 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
345 {
346 void __iomem *tbase = musb->ctrl_base;
347 u32 reg;
348
349 if ((wakeup_enables & TUSB_PRCM_WBUS)
350 && (tusb_get_revision(musb) == TUSB_REV_30))
351 tusb_wbus_quirk(musb, 1);
352
353 tusb_set_clock_source(musb, 0);
354
355 wakeup_enables |= TUSB_PRCM_WNORCS;
356 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
357
358 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
359 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
360 * Presumably that's mostly to save power, hence WID is immaterial ...
361 */
362
363 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
364 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
365 if (is_host_active(musb)) {
366 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
367 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
368 } else {
369 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
370 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
371 }
372 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
373 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
374
375 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
376 }
377
378 /*
379 * Updates cable VBUS status. Caller must take care of locking.
380 */
381 static int tusb_musb_vbus_status(struct musb *musb)
382 {
383 void __iomem *tbase = musb->ctrl_base;
384 u32 otg_stat, prcm_mngmt;
385 int ret = 0;
386
387 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
388 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
389
390 /* Temporarily enable VBUS detection if it was disabled for
391 * suspend mode. Unless it's enabled otg_stat and devctl will
392 * not show correct VBUS state.
393 */
394 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
395 u32 tmp = prcm_mngmt;
396 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
397 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
398 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
399 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
400 }
401
402 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
403 ret = 1;
404
405 return ret;
406 }
407
408 static struct timer_list musb_idle_timer;
409
410 static void musb_do_idle(unsigned long _musb)
411 {
412 struct musb *musb = (void *)_musb;
413 unsigned long flags;
414
415 spin_lock_irqsave(&musb->lock, flags);
416
417 switch (musb->xceiv->state) {
418 case OTG_STATE_A_WAIT_BCON:
419 if ((musb->a_wait_bcon != 0)
420 && (musb->idle_timeout == 0
421 || time_after(jiffies, musb->idle_timeout))) {
422 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
423 otg_state_string(musb->xceiv->state));
424 }
425 /* FALLTHROUGH */
426 case OTG_STATE_A_IDLE:
427 tusb_musb_set_vbus(musb, 0);
428 default:
429 break;
430 }
431
432 if (!musb->is_active) {
433 u32 wakeups;
434
435 /* wait until khubd handles port change status */
436 if (is_host_active(musb) && (musb->port1_status >> 16))
437 goto done;
438
439 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
440 wakeups = 0;
441 } else {
442 wakeups = TUSB_PRCM_WHOSTDISCON
443 | TUSB_PRCM_WBUS
444 | TUSB_PRCM_WVBUS;
445 if (is_otg_enabled(musb))
446 wakeups |= TUSB_PRCM_WID;
447 }
448 tusb_allow_idle(musb, wakeups);
449 }
450 done:
451 spin_unlock_irqrestore(&musb->lock, flags);
452 }
453
454 /*
455 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
456 * like "disconnected" or "suspended". We'll be woken out of it by
457 * connect, resume, or disconnect.
458 *
459 * Needs to be called as the last function everywhere where there is
460 * register access to TUSB6010 because of NOR flash wake-up.
461 * Caller should own controller spinlock.
462 *
463 * Delay because peripheral enables D+ pullup 3msec after SE0, and
464 * we don't want to treat that full speed J as a wakeup event.
465 * ... peripherals must draw only suspend current after 10 msec.
466 */
467 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
468 {
469 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
470 static unsigned long last_timer;
471
472 if (timeout == 0)
473 timeout = default_timeout;
474
475 /* Never idle if active, or when VBUS timeout is not set as host */
476 if (musb->is_active || ((musb->a_wait_bcon == 0)
477 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
478 dev_dbg(musb->controller, "%s active, deleting timer\n",
479 otg_state_string(musb->xceiv->state));
480 del_timer(&musb_idle_timer);
481 last_timer = jiffies;
482 return;
483 }
484
485 if (time_after(last_timer, timeout)) {
486 if (!timer_pending(&musb_idle_timer))
487 last_timer = timeout;
488 else {
489 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
490 return;
491 }
492 }
493 last_timer = timeout;
494
495 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
496 otg_state_string(musb->xceiv->state),
497 (unsigned long)jiffies_to_msecs(timeout - jiffies));
498 mod_timer(&musb_idle_timer, timeout);
499 }
500
501 /* ticks of 60 MHz clock */
502 #define DEVCLOCK 60000000
503 #define OTG_TIMER_MS(msecs) ((msecs) \
504 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
505 | TUSB_DEV_OTG_TIMER_ENABLE) \
506 : 0)
507
508 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
509 {
510 void __iomem *tbase = musb->ctrl_base;
511 u32 conf, prcm, timer;
512 u8 devctl;
513
514 /* HDRC controls CPEN, but beware current surges during device
515 * connect. They can trigger transient overcurrent conditions
516 * that must be ignored.
517 */
518
519 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
520 conf = musb_readl(tbase, TUSB_DEV_CONF);
521 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
522
523 if (is_on) {
524 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
525 musb->xceiv->default_a = 1;
526 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
527 devctl |= MUSB_DEVCTL_SESSION;
528
529 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
530 MUSB_HST_MODE(musb);
531 } else {
532 u32 otg_stat;
533
534 timer = 0;
535
536 /* If ID pin is grounded, we want to be a_idle */
537 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
538 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
539 switch (musb->xceiv->state) {
540 case OTG_STATE_A_WAIT_VRISE:
541 case OTG_STATE_A_WAIT_BCON:
542 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
543 break;
544 case OTG_STATE_A_WAIT_VFALL:
545 musb->xceiv->state = OTG_STATE_A_IDLE;
546 break;
547 default:
548 musb->xceiv->state = OTG_STATE_A_IDLE;
549 }
550 musb->is_active = 0;
551 musb->xceiv->default_a = 1;
552 MUSB_HST_MODE(musb);
553 } else {
554 musb->is_active = 0;
555 musb->xceiv->default_a = 0;
556 musb->xceiv->state = OTG_STATE_B_IDLE;
557 MUSB_DEV_MODE(musb);
558 }
559
560 devctl &= ~MUSB_DEVCTL_SESSION;
561 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
562 }
563 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
564
565 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
566 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
567 musb_writel(tbase, TUSB_DEV_CONF, conf);
568 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
569
570 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
571 otg_state_string(musb->xceiv->state),
572 musb_readb(musb->mregs, MUSB_DEVCTL),
573 musb_readl(tbase, TUSB_DEV_OTG_STAT),
574 conf, prcm);
575 }
576
577 /*
578 * Sets the mode to OTG, peripheral or host by changing the ID detection.
579 * Caller must take care of locking.
580 *
581 * Note that if a mini-A cable is plugged in the ID line will stay down as
582 * the weak ID pull-up is not able to pull the ID up.
583 *
584 * REVISIT: It would be possible to add support for changing between host
585 * and peripheral modes in non-OTG configurations by reconfiguring hardware
586 * and then setting musb->board_mode. For now, only support OTG mode.
587 */
588 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
589 {
590 void __iomem *tbase = musb->ctrl_base;
591 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
592
593 if (musb->board_mode != MUSB_OTG) {
594 ERR("Changing mode currently only supported in OTG mode\n");
595 return -EINVAL;
596 }
597
598 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
599 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
600 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
601 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
602
603 switch (musb_mode) {
604
605 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
606 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
607 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
608 dev_conf |= TUSB_DEV_CONF_ID_SEL;
609 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
610 break;
611 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
612 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
613 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
614 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
615 break;
616 case MUSB_OTG: /* Use PHY ID detection */
617 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
618 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
619 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
620 break;
621
622 default:
623 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
624 return -EINVAL;
625 }
626
627 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
628 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
629 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
630 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
631 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
632
633 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
634 if ((musb_mode == MUSB_PERIPHERAL) &&
635 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
636 INFO("Cannot be peripheral with mini-A cable "
637 "otg_stat: %08x\n", otg_stat);
638
639 return 0;
640 }
641
642 static inline unsigned long
643 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
644 {
645 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
646 unsigned long idle_timeout = 0;
647
648 /* ID pin */
649 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
650 int default_a;
651
652 if (is_otg_enabled(musb))
653 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
654 else
655 default_a = is_host_enabled(musb);
656 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
657 musb->xceiv->default_a = default_a;
658 tusb_musb_set_vbus(musb, default_a);
659
660 /* Don't allow idling immediately */
661 if (default_a)
662 idle_timeout = jiffies + (HZ * 3);
663 }
664
665 /* VBUS state change */
666 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
667
668 /* B-dev state machine: no vbus ~= disconnect */
669 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
670 || !is_host_enabled(musb)) {
671 /* ? musb_root_disconnect(musb); */
672 musb->port1_status &=
673 ~(USB_PORT_STAT_CONNECTION
674 | USB_PORT_STAT_ENABLE
675 | USB_PORT_STAT_LOW_SPEED
676 | USB_PORT_STAT_HIGH_SPEED
677 | USB_PORT_STAT_TEST
678 );
679
680 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
681 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
682 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
683 /* INTR_DISCONNECT can hide... */
684 musb->xceiv->state = OTG_STATE_B_IDLE;
685 musb->int_usb |= MUSB_INTR_DISCONNECT;
686 }
687 musb->is_active = 0;
688 }
689 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
690 otg_state_string(musb->xceiv->state), otg_stat);
691 idle_timeout = jiffies + (1 * HZ);
692 schedule_work(&musb->irq_work);
693
694 } else /* A-dev state machine */ {
695 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
696 otg_state_string(musb->xceiv->state), otg_stat);
697
698 switch (musb->xceiv->state) {
699 case OTG_STATE_A_IDLE:
700 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
701 musb_platform_set_vbus(musb, 1);
702
703 /* CONNECT can wake if a_wait_bcon is set */
704 if (musb->a_wait_bcon != 0)
705 musb->is_active = 0;
706 else
707 musb->is_active = 1;
708
709 /*
710 * OPT FS A TD.4.6 needs few seconds for
711 * A_WAIT_VRISE
712 */
713 idle_timeout = jiffies + (2 * HZ);
714
715 break;
716 case OTG_STATE_A_WAIT_VRISE:
717 /* ignore; A-session-valid < VBUS_VALID/2,
718 * we monitor this with the timer
719 */
720 break;
721 case OTG_STATE_A_WAIT_VFALL:
722 /* REVISIT this irq triggers during short
723 * spikes caused by enumeration ...
724 */
725 if (musb->vbuserr_retry) {
726 musb->vbuserr_retry--;
727 tusb_musb_set_vbus(musb, 1);
728 } else {
729 musb->vbuserr_retry
730 = VBUSERR_RETRY_COUNT;
731 tusb_musb_set_vbus(musb, 0);
732 }
733 break;
734 default:
735 break;
736 }
737 }
738 }
739
740 /* OTG timer expiration */
741 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
742 u8 devctl;
743
744 dev_dbg(musb->controller, "%s timer, %03x\n",
745 otg_state_string(musb->xceiv->state), otg_stat);
746
747 switch (musb->xceiv->state) {
748 case OTG_STATE_A_WAIT_VRISE:
749 /* VBUS has probably been valid for a while now,
750 * but may well have bounced out of range a bit
751 */
752 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
753 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
754 if ((devctl & MUSB_DEVCTL_VBUS)
755 != MUSB_DEVCTL_VBUS) {
756 dev_dbg(musb->controller, "devctl %02x\n", devctl);
757 break;
758 }
759 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
760 musb->is_active = 0;
761 idle_timeout = jiffies
762 + msecs_to_jiffies(musb->a_wait_bcon);
763 } else {
764 /* REVISIT report overcurrent to hub? */
765 ERR("vbus too slow, devctl %02x\n", devctl);
766 tusb_musb_set_vbus(musb, 0);
767 }
768 break;
769 case OTG_STATE_A_WAIT_BCON:
770 if (musb->a_wait_bcon != 0)
771 idle_timeout = jiffies
772 + msecs_to_jiffies(musb->a_wait_bcon);
773 break;
774 case OTG_STATE_A_SUSPEND:
775 break;
776 case OTG_STATE_B_WAIT_ACON:
777 break;
778 default:
779 break;
780 }
781 }
782 schedule_work(&musb->irq_work);
783
784 return idle_timeout;
785 }
786
787 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
788 {
789 struct musb *musb = __hci;
790 void __iomem *tbase = musb->ctrl_base;
791 unsigned long flags, idle_timeout = 0;
792 u32 int_mask, int_src;
793
794 spin_lock_irqsave(&musb->lock, flags);
795
796 /* Mask all interrupts to allow using both edge and level GPIO irq */
797 int_mask = musb_readl(tbase, TUSB_INT_MASK);
798 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
799
800 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
801 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
802
803 musb->int_usb = (u8) int_src;
804
805 /* Acknowledge wake-up source interrupts */
806 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
807 u32 reg;
808 u32 i;
809
810 if (tusb_get_revision(musb) == TUSB_REV_30)
811 tusb_wbus_quirk(musb, 0);
812
813 /* there are issues re-locking the PLL on wakeup ... */
814
815 /* work around issue 8 */
816 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
817 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
818 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
819 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
820 if (reg == i)
821 break;
822 dev_dbg(musb->controller, "TUSB NOR not ready\n");
823 }
824
825 /* work around issue 13 (2nd half) */
826 tusb_set_clock_source(musb, 1);
827
828 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
829 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
830 if (reg & ~TUSB_PRCM_WNORCS) {
831 musb->is_active = 1;
832 schedule_work(&musb->irq_work);
833 }
834 dev_dbg(musb->controller, "wake %sactive %02x\n",
835 musb->is_active ? "" : "in", reg);
836
837 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
838 }
839
840 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
841 del_timer(&musb_idle_timer);
842
843 /* OTG state change reports (annoyingly) not issued by Mentor core */
844 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
845 | TUSB_INT_SRC_OTG_TIMEOUT
846 | TUSB_INT_SRC_ID_STATUS_CHNG))
847 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
848
849 /* TX dma callback must be handled here, RX dma callback is
850 * handled in tusb_omap_dma_cb.
851 */
852 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
853 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
854 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
855
856 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
857 real_dma_src = ~real_dma_src & dma_src;
858 if (tusb_dma_omap() && real_dma_src) {
859 int tx_source = (real_dma_src & 0xffff);
860 int i;
861
862 for (i = 1; i <= 15; i++) {
863 if (tx_source & (1 << i)) {
864 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
865 musb_dma_completion(musb, i, 1);
866 }
867 }
868 }
869 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
870 }
871
872 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
873 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
874 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
875
876 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
877 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
878 musb->int_tx = (musb_src & 0xffff);
879 } else {
880 musb->int_rx = 0;
881 musb->int_tx = 0;
882 }
883
884 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
885 musb_interrupt(musb);
886
887 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
888 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
889 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
890
891 tusb_musb_try_idle(musb, idle_timeout);
892
893 musb_writel(tbase, TUSB_INT_MASK, int_mask);
894 spin_unlock_irqrestore(&musb->lock, flags);
895
896 return IRQ_HANDLED;
897 }
898
899 static int dma_off;
900
901 /*
902 * Enables TUSB6010. Caller must take care of locking.
903 * REVISIT:
904 * - Check what is unnecessary in MGC_HdrcStart()
905 */
906 static void tusb_musb_enable(struct musb *musb)
907 {
908 void __iomem *tbase = musb->ctrl_base;
909
910 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
911 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
912 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
913
914 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
915 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
916 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
917 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
918
919 /* Clear all subsystem interrups */
920 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
921 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
922 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
923
924 /* Acknowledge pending interrupt(s) */
925 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
926
927 /* Only 0 clock cycles for minimum interrupt de-assertion time and
928 * interrupt polarity active low seems to work reliably here */
929 musb_writel(tbase, TUSB_INT_CTRL_CONF,
930 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
931
932 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
933
934 /* maybe force into the Default-A OTG state machine */
935 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
936 & TUSB_DEV_OTG_STAT_ID_STATUS))
937 musb_writel(tbase, TUSB_INT_SRC_SET,
938 TUSB_INT_SRC_ID_STATUS_CHNG);
939
940 if (is_dma_capable() && dma_off)
941 printk(KERN_WARNING "%s %s: dma not reactivated\n",
942 __FILE__, __func__);
943 else
944 dma_off = 1;
945 }
946
947 /*
948 * Disables TUSB6010. Caller must take care of locking.
949 */
950 static void tusb_musb_disable(struct musb *musb)
951 {
952 void __iomem *tbase = musb->ctrl_base;
953
954 /* FIXME stop DMA, IRQs, timers, ... */
955
956 /* disable all IRQs */
957 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
958 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
959 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
960 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
961
962 del_timer(&musb_idle_timer);
963
964 if (is_dma_capable() && !dma_off) {
965 printk(KERN_WARNING "%s %s: dma still active\n",
966 __FILE__, __func__);
967 dma_off = 1;
968 }
969 }
970
971 /*
972 * Sets up TUSB6010 CPU interface specific signals and registers
973 * Note: Settings optimized for OMAP24xx
974 */
975 static void tusb_setup_cpu_interface(struct musb *musb)
976 {
977 void __iomem *tbase = musb->ctrl_base;
978
979 /*
980 * Disable GPIO[5:0] pullups (used as output DMA requests)
981 * Don't disable GPIO[7:6] as they are needed for wake-up.
982 */
983 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
984
985 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
986 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
987
988 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
989 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
990
991 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
992 * de-assertion time 2 system clocks p 62 */
993 musb_writel(tbase, TUSB_DMA_REQ_CONF,
994 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
995 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
996 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
997
998 /* Set 0 wait count for synchronous burst access */
999 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1000 }
1001
1002 static int tusb_musb_start(struct musb *musb)
1003 {
1004 void __iomem *tbase = musb->ctrl_base;
1005 int ret = 0;
1006 unsigned long flags;
1007 u32 reg;
1008
1009 if (musb->board_set_power)
1010 ret = musb->board_set_power(1);
1011 if (ret != 0) {
1012 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1013 return ret;
1014 }
1015
1016 spin_lock_irqsave(&musb->lock, flags);
1017
1018 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1019 TUSB_PROD_TEST_RESET_VAL) {
1020 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1021 goto err;
1022 }
1023
1024 ret = tusb_print_revision(musb);
1025 if (ret < 2) {
1026 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1027 ret);
1028 goto err;
1029 }
1030
1031 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1032 * NOR FLASH interface is used */
1033 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1034
1035 /* Select PHY free running 60MHz as a system clock */
1036 tusb_set_clock_source(musb, 1);
1037
1038 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1039 * power saving, enable VBus detect and session end comparators,
1040 * enable IDpullup, enable VBus charging */
1041 musb_writel(tbase, TUSB_PRCM_MNGMT,
1042 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1043 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1044 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1045 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1046 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1047 tusb_setup_cpu_interface(musb);
1048
1049 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1050 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1051 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1052 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1053
1054 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1055 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1056 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1057
1058 spin_unlock_irqrestore(&musb->lock, flags);
1059
1060 return 0;
1061
1062 err:
1063 spin_unlock_irqrestore(&musb->lock, flags);
1064
1065 if (musb->board_set_power)
1066 musb->board_set_power(0);
1067
1068 return -ENODEV;
1069 }
1070
1071 static int tusb_musb_init(struct musb *musb)
1072 {
1073 struct platform_device *pdev;
1074 struct resource *mem;
1075 void __iomem *sync = NULL;
1076 int ret;
1077
1078 usb_nop_xceiv_register();
1079 musb->xceiv = otg_get_transceiver();
1080 if (!musb->xceiv)
1081 return -ENODEV;
1082
1083 pdev = to_platform_device(musb->controller);
1084
1085 /* dma address for async dma */
1086 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087 musb->async = mem->start;
1088
1089 /* dma address for sync dma */
1090 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1091 if (!mem) {
1092 pr_debug("no sync dma resource?\n");
1093 ret = -ENODEV;
1094 goto done;
1095 }
1096 musb->sync = mem->start;
1097
1098 sync = ioremap(mem->start, resource_size(mem));
1099 if (!sync) {
1100 pr_debug("ioremap for sync failed\n");
1101 ret = -ENOMEM;
1102 goto done;
1103 }
1104 musb->sync_va = sync;
1105
1106 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1107 * FIFOs at 0x600, TUSB at 0x800
1108 */
1109 musb->mregs += TUSB_BASE_OFFSET;
1110
1111 ret = tusb_musb_start(musb);
1112 if (ret) {
1113 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1114 ret);
1115 goto done;
1116 }
1117 musb->isr = tusb_musb_interrupt;
1118
1119 if (is_peripheral_enabled(musb)) {
1120 musb->xceiv->set_power = tusb_draw_power;
1121 the_musb = musb;
1122 }
1123
1124 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1125
1126 done:
1127 if (ret < 0) {
1128 if (sync)
1129 iounmap(sync);
1130
1131 otg_put_transceiver(musb->xceiv);
1132 usb_nop_xceiv_unregister();
1133 }
1134 return ret;
1135 }
1136
1137 static int tusb_musb_exit(struct musb *musb)
1138 {
1139 del_timer_sync(&musb_idle_timer);
1140 the_musb = NULL;
1141
1142 if (musb->board_set_power)
1143 musb->board_set_power(0);
1144
1145 iounmap(musb->sync_va);
1146
1147 otg_put_transceiver(musb->xceiv);
1148 usb_nop_xceiv_unregister();
1149 return 0;
1150 }
1151
1152 static const struct musb_platform_ops tusb_ops = {
1153 .init = tusb_musb_init,
1154 .exit = tusb_musb_exit,
1155
1156 .enable = tusb_musb_enable,
1157 .disable = tusb_musb_disable,
1158
1159 .set_mode = tusb_musb_set_mode,
1160 .try_idle = tusb_musb_try_idle,
1161
1162 .vbus_status = tusb_musb_vbus_status,
1163 .set_vbus = tusb_musb_set_vbus,
1164 };
1165
1166 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1167
1168 static int __init tusb_probe(struct platform_device *pdev)
1169 {
1170 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1171 struct platform_device *musb;
1172 struct tusb6010_glue *glue;
1173
1174 int ret = -ENOMEM;
1175
1176 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1177 if (!glue) {
1178 dev_err(&pdev->dev, "failed to allocate glue context\n");
1179 goto err0;
1180 }
1181
1182 musb = platform_device_alloc("musb-hdrc", -1);
1183 if (!musb) {
1184 dev_err(&pdev->dev, "failed to allocate musb device\n");
1185 goto err1;
1186 }
1187
1188 musb->dev.parent = &pdev->dev;
1189 musb->dev.dma_mask = &tusb_dmamask;
1190 musb->dev.coherent_dma_mask = tusb_dmamask;
1191
1192 glue->dev = &pdev->dev;
1193 glue->musb = musb;
1194
1195 pdata->platform_ops = &tusb_ops;
1196
1197 platform_set_drvdata(pdev, glue);
1198
1199 ret = platform_device_add_resources(musb, pdev->resource,
1200 pdev->num_resources);
1201 if (ret) {
1202 dev_err(&pdev->dev, "failed to add resources\n");
1203 goto err2;
1204 }
1205
1206 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1207 if (ret) {
1208 dev_err(&pdev->dev, "failed to add platform_data\n");
1209 goto err2;
1210 }
1211
1212 ret = platform_device_add(musb);
1213 if (ret) {
1214 dev_err(&pdev->dev, "failed to register musb device\n");
1215 goto err1;
1216 }
1217
1218 return 0;
1219
1220 err2:
1221 platform_device_put(musb);
1222
1223 err1:
1224 kfree(glue);
1225
1226 err0:
1227 return ret;
1228 }
1229
1230 static int __exit tusb_remove(struct platform_device *pdev)
1231 {
1232 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1233
1234 platform_device_del(glue->musb);
1235 platform_device_put(glue->musb);
1236 kfree(glue);
1237
1238 return 0;
1239 }
1240
1241 static struct platform_driver tusb_driver = {
1242 .remove = __exit_p(tusb_remove),
1243 .driver = {
1244 .name = "musb-tusb",
1245 },
1246 };
1247
1248 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1249 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1250 MODULE_LICENSE("GPL v2");
1251
1252 static int __init tusb_init(void)
1253 {
1254 return platform_driver_probe(&tusb_driver, tusb_probe);
1255 }
1256 subsys_initcall(tusb_init);
1257
1258 static void __exit tusb_exit(void)
1259 {
1260 platform_driver_unregister(&tusb_driver);
1261 }
1262 module_exit(tusb_exit);
kernel source for telekom puls (alcatel/mediatek)