drivers/usb/musb/da8xx.c

   1 /*
   2  * Texas Instruments DA8xx/OMAP-L1x "glue layer"
   3  *
   4  * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * Based on the DaVinci "glue layer" code.
   7  * Copyright (C) 2005-2006 by Texas Instruments
   8  *
   9  * This file is part of the Inventra Controller Driver for Linux.
  10  *
  11  * The Inventra Controller Driver for Linux is free software; you
  12  * can redistribute it and/or modify it under the terms of the GNU
  13  * General Public License version 2 as published by the Free Software
  14  * Foundation.
  15  *
  16  * The Inventra Controller Driver for Linux is distributed in
  17  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18  * without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20  * License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with The Inventra Controller Driver for Linux ; if not,
  24  * write to the Free Software Foundation, Inc., 59 Temple Place,
  25  * Suite 330, Boston, MA  02111-1307  USA
  26  *
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/clk.h>
  32 #include <linux/io.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dma-mapping.h>
  35
  36 #include <mach/da8xx.h>
  37 #include <mach/usb.h>
  38
  39 #include "musb_core.h"
  40
  41 /*
  42  * DA8XX specific definitions
  43  */
  44
  45 /* USB 2.0 OTG module registers */
  46 #define DA8XX_USB_REVISION_REG  0x00
  47 #define DA8XX_USB_CTRL_REG      0x04
  48 #define DA8XX_USB_STAT_REG      0x08
  49 #define DA8XX_USB_EMULATION_REG 0x0c
  50 #define DA8XX_USB_MODE_REG      0x10    /* Transparent, CDC, [Generic] RNDIS */
  51 #define DA8XX_USB_AUTOREQ_REG   0x14
  52 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
  53 #define DA8XX_USB_TEARDOWN_REG  0x1c
  54 #define DA8XX_USB_INTR_SRC_REG  0x20
  55 #define DA8XX_USB_INTR_SRC_SET_REG 0x24
  56 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
  57 #define DA8XX_USB_INTR_MASK_REG 0x2c
  58 #define DA8XX_USB_INTR_MASK_SET_REG 0x30
  59 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
  60 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
  61 #define DA8XX_USB_END_OF_INTR_REG 0x3c
  62 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
  63
  64 /* Control register bits */
  65 #define DA8XX_SOFT_RESET_MASK   1
  66
  67 #define DA8XX_USB_TX_EP_MASK    0x1f            /* EP0 + 4 Tx EPs */
  68 #define DA8XX_USB_RX_EP_MASK    0x1e            /* 4 Rx EPs */
  69
  70 /* USB interrupt register bits */
  71 #define DA8XX_INTR_USB_SHIFT    16
  72 #define DA8XX_INTR_USB_MASK     (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
  73                                         /* interrupts and DRVVBUS interrupt */
  74 #define DA8XX_INTR_DRVVBUS      0x100
  75 #define DA8XX_INTR_RX_SHIFT     8
  76 #define DA8XX_INTR_RX_MASK      (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
  77 #define DA8XX_INTR_TX_SHIFT     0
  78 #define DA8XX_INTR_TX_MASK      (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
  79
  80 #define DA8XX_MENTOR_CORE_OFFSET 0x400
  81
  82 #define CFGCHIP2        IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
  83
  84 struct da8xx_glue {
  85         struct device           *dev;
  86         struct platform_device  *musb;
  87         struct clk              *clk;
  88 };
  89
  90 /*
  91  * REVISIT (PM): we should be able to keep the PHY in low power mode most
  92  * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
  93  * and, when in host mode, autosuspending idle root ports... PHY_PLLON
  94  * (overriding SUSPENDM?) then likely needs to stay off.
  95  */
  96
  97 static inline void phy_on(void)
  98 {
  99         u32 cfgchip2 = __raw_readl(CFGCHIP2);
 100
 101         /*
 102          * Start the on-chip PHY and its PLL.
 103          */
 104         cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
 105         cfgchip2 |= CFGCHIP2_PHY_PLLON;
 106         __raw_writel(cfgchip2, CFGCHIP2);
 107
 108         pr_info("Waiting for USB PHY clock good...\n");
 109         while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
 110                 cpu_relax();
 111 }
 112
 113 static inline void phy_off(void)
 114 {
 115         u32 cfgchip2 = __raw_readl(CFGCHIP2);
 116
 117         /*
 118          * Ensure that USB 1.1 reference clock is not being sourced from
 119          * USB 2.0 PHY.  Otherwise do not power down the PHY.
 120          */
 121         if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
 122              (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
 123                 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
 124                            "can't power it down\n");
 125                 return;
 126         }
 127
 128         /*
 129          * Power down the on-chip PHY.
 130          */
 131         cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
 132         __raw_writel(cfgchip2, CFGCHIP2);
 133 }
 134
 135 /*
 136  * Because we don't set CTRL.UINT, it's "important" to:
 137  *      - not read/write INTRUSB/INTRUSBE (except during
 138  *        initial setup, as a workaround);
 139  *      - use INTSET/INTCLR instead.
 140  */
 141
 142 /**
 143  * da8xx_musb_enable - enable interrupts
 144  */
 145 static void da8xx_musb_enable(struct musb *musb)
 146 {
 147         void __iomem *reg_base = musb->ctrl_base;
 148         u32 mask;
 149
 150         /* Workaround: setup IRQs through both register sets. */
 151         mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
 152                ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
 153                DA8XX_INTR_USB_MASK;
 154         musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
 155
 156         /* Force the DRVVBUS IRQ so we can start polling for ID change. */
 157         if (is_otg_enabled(musb))
 158                 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
 159                             DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
 160 }
 161
 162 /**
 163  * da8xx_musb_disable - disable HDRC and flush interrupts
 164  */
 165 static void da8xx_musb_disable(struct musb *musb)
 166 {
 167         void __iomem *reg_base = musb->ctrl_base;
 168
 169         musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
 170                     DA8XX_INTR_USB_MASK |
 171                     DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
 172         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 173         musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
 174 }
 175
 176 #define portstate(stmt)         stmt
 177
 178 static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
 179 {
 180         WARN_ON(is_on && is_peripheral_active(musb));
 181 }
 182
 183 #define POLL_SECONDS    2
 184
 185 static struct timer_list otg_workaround;
 186
 187 static void otg_timer(unsigned long _musb)
 188 {
 189         struct musb             *musb = (void *)_musb;
 190         void __iomem            *mregs = musb->mregs;
 191         u8                      devctl;
 192         unsigned long           flags;
 193
 194         /*
 195          * We poll because DaVinci's won't expose several OTG-critical
 196          * status change events (from the transceiver) otherwise.
 197          */
 198         devctl = musb_readb(mregs, MUSB_DEVCTL);
 199         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 200                 otg_state_string(musb->xceiv->state));
 201
 202         spin_lock_irqsave(&musb->lock, flags);
 203         switch (musb->xceiv->state) {
 204         case OTG_STATE_A_WAIT_BCON:
 205                 devctl &= ~MUSB_DEVCTL_SESSION;
 206                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 207
 208                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 209                 if (devctl & MUSB_DEVCTL_BDEVICE) {
 210                         musb->xceiv->state = OTG_STATE_B_IDLE;
 211                         MUSB_DEV_MODE(musb);
 212                 } else {
 213                         musb->xceiv->state = OTG_STATE_A_IDLE;
 214                         MUSB_HST_MODE(musb);
 215                 }
 216                 break;
 217         case OTG_STATE_A_WAIT_VFALL:
 218                 /*
 219                  * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
 220                  * RTL seems to mis-handle session "start" otherwise (or in
 221                  * our case "recover"), in routine "VBUS was valid by the time
 222                  * VBUSERR got reported during enumeration" cases.
 223                  */
 224                 if (devctl & MUSB_DEVCTL_VBUS) {
 225                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 226                         break;
 227                 }
 228                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 229                 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
 230                             MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
 231                 break;
 232         case OTG_STATE_B_IDLE:
 233                 if (!is_peripheral_enabled(musb))
 234                         break;
 235
 236                 /*
 237                  * There's no ID-changed IRQ, so we have no good way to tell
 238                  * when to switch to the A-Default state machine (by setting
 239                  * the DEVCTL.Session bit).
 240                  *
 241                  * Workaround:  whenever we're in B_IDLE, try setting the
 242                  * session flag every few seconds.  If it works, ID was
 243                  * grounded and we're now in the A-Default state machine.
 244                  *
 245                  * NOTE: setting the session flag is _supposed_ to trigger
 246                  * SRP but clearly it doesn't.
 247                  */
 248                 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
 249                 devctl = musb_readb(mregs, MUSB_DEVCTL);
 250                 if (devctl & MUSB_DEVCTL_BDEVICE)
 251                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 252                 else
 253                         musb->xceiv->state = OTG_STATE_A_IDLE;
 254                 break;
 255         default:
 256                 break;
 257         }
 258         spin_unlock_irqrestore(&musb->lock, flags);
 259 }
 260
 261 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
 262 {
 263         static unsigned long last_timer;
 264
 265         if (!is_otg_enabled(musb))
 266                 return;
 267
 268         if (timeout == 0)
 269                 timeout = jiffies + msecs_to_jiffies(3);
 270
 271         /* Never idle if active, or when VBUS timeout is not set as host */
 272         if (musb->is_active || (musb->a_wait_bcon == 0 &&
 273                                 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 274                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 275                         otg_state_string(musb->xceiv->state));
 276                 del_timer(&otg_workaround);
 277                 last_timer = jiffies;
 278                 return;
 279         }
 280
 281         if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 282                 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 283                 return;
 284         }
 285         last_timer = timeout;
 286
 287         dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 288                 otg_state_string(musb->xceiv->state),
 289                 jiffies_to_msecs(timeout - jiffies));
 290         mod_timer(&otg_workaround, timeout);
 291 }
 292
 293 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
 294 {
 295         struct musb             *musb = hci;
 296         void __iomem            *reg_base = musb->ctrl_base;
 297         struct usb_otg          *otg = musb->xceiv->otg;
 298         unsigned long           flags;
 299         irqreturn_t             ret = IRQ_NONE;
 300         u32                     status;
 301
 302         spin_lock_irqsave(&musb->lock, flags);
 303
 304         /*
 305          * NOTE: DA8XX shadows the Mentor IRQs.  Don't manage them through
 306          * the Mentor registers (except for setup), use the TI ones and EOI.
 307          */
 308
 309         /* Acknowledge and handle non-CPPI interrupts */
 310         status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
 311         if (!status)
 312                 goto eoi;
 313
 314         musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
 315         dev_dbg(musb->controller, "USB IRQ %08x\n", status);
 316
 317         musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
 318         musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
 319         musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
 320
 321         /*
 322          * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 323          * DA8xx's missing ID change IRQ.  We need an ID change IRQ to
 324          * switch appropriately between halves of the OTG state machine.
 325          * Managing DEVCTL.Session per Mentor docs requires that we know its
 326          * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
 327          * Also, DRVVBUS pulses for SRP (but not at 5 V)...
 328          */
 329         if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
 330                 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
 331                 void __iomem *mregs = musb->mregs;
 332                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 333                 int err;
 334
 335                 err = is_host_enabled(musb) && (musb->int_usb &
 336                                                 MUSB_INTR_VBUSERROR);
 337                 if (err) {
 338                         /*
 339                          * The Mentor core doesn't debounce VBUS as needed
 340                          * to cope with device connect current spikes. This
 341                          * means it's not uncommon for bus-powered devices
 342                          * to get VBUS errors during enumeration.
 343                          *
 344                          * This is a workaround, but newer RTL from Mentor
 345                          * seems to allow a better one: "re"-starting sessions
 346                          * without waiting for VBUS to stop registering in
 347                          * devctl.
 348                          */
 349                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 350                         musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 351                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 352                         WARNING("VBUS error workaround (delay coming)\n");
 353                 } else if (is_host_enabled(musb) && drvvbus) {
 354                         MUSB_HST_MODE(musb);
 355                         otg->default_a = 1;
 356                         musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 357                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 358                         del_timer(&otg_workaround);
 359                 } else {
 360                         musb->is_active = 0;
 361                         MUSB_DEV_MODE(musb);
 362                         otg->default_a = 0;
 363                         musb->xceiv->state = OTG_STATE_B_IDLE;
 364                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 365                 }
 366
 367                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 368                                 drvvbus ? "on" : "off",
 369                                 otg_state_string(musb->xceiv->state),
 370                                 err ? " ERROR" : "",
 371                                 devctl);
 372                 ret = IRQ_HANDLED;
 373         }
 374
 375         if (musb->int_tx || musb->int_rx || musb->int_usb)
 376                 ret |= musb_interrupt(musb);
 377
 378  eoi:
 379         /* EOI needs to be written for the IRQ to be re-asserted. */
 380         if (ret == IRQ_HANDLED || status)
 381                 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
 382
 383         /* Poll for ID change */
 384         if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
 385                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 386
 387         spin_unlock_irqrestore(&musb->lock, flags);
 388
 389         return ret;
 390 }
 391
 392 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
 393 {
 394         u32 cfgchip2 = __raw_readl(CFGCHIP2);
 395
 396         cfgchip2 &= ~CFGCHIP2_OTGMODE;
 397         switch (musb_mode) {
 398         case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
 399                 cfgchip2 |= CFGCHIP2_FORCE_HOST;
 400                 break;
 401         case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
 402                 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
 403                 break;
 404         case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
 405                 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
 406                 break;
 407         default:
 408                 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
 409         }
 410
 411         __raw_writel(cfgchip2, CFGCHIP2);
 412         return 0;
 413 }
 414
 415 static int da8xx_musb_init(struct musb *musb)
 416 {
 417         void __iomem *reg_base = musb->ctrl_base;
 418         u32 rev;
 419
 420         musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
 421
 422         /* Returns zero if e.g. not clocked */
 423         rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
 424         if (!rev)
 425                 goto fail;
 426
 427         usb_nop_xceiv_register();
 428         musb->xceiv = usb_get_transceiver();
 429         if (!musb->xceiv)
 430                 goto fail;
 431
 432         if (is_host_enabled(musb))
 433                 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
 434
 435         /* Reset the controller */
 436         musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
 437
 438         /* Start the on-chip PHY and its PLL. */
 439         phy_on();
 440
 441         msleep(5);
 442
 443         /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
 444         pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
 445                  rev, __raw_readl(CFGCHIP2),
 446                  musb_readb(reg_base, DA8XX_USB_CTRL_REG));
 447
 448         musb->isr = da8xx_musb_interrupt;
 449         return 0;
 450 fail:
 451         return -ENODEV;
 452 }
 453
 454 static int da8xx_musb_exit(struct musb *musb)
 455 {
 456         if (is_host_enabled(musb))
 457                 del_timer_sync(&otg_workaround);
 458
 459         phy_off();
 460
 461         usb_put_transceiver(musb->xceiv);
 462         usb_nop_xceiv_unregister();
 463
 464         return 0;
 465 }
 466
 467 static const struct musb_platform_ops da8xx_ops = {
 468         .init           = da8xx_musb_init,
 469         .exit           = da8xx_musb_exit,
 470
 471         .enable         = da8xx_musb_enable,
 472         .disable        = da8xx_musb_disable,
 473
 474         .set_mode       = da8xx_musb_set_mode,
 475         .try_idle       = da8xx_musb_try_idle,
 476
 477         .set_vbus       = da8xx_musb_set_vbus,
 478 };
 479
 480 static u64 da8xx_dmamask = DMA_BIT_MASK(32);
 481
 482 static int __devinit da8xx_probe(struct platform_device *pdev)
 483 {
 484         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
 485         struct platform_device          *musb;
 486         struct da8xx_glue               *glue;
 487
 488         struct clk                      *clk;
 489
 490         int                             ret = -ENOMEM;
 491
 492         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 493         if (!glue) {
 494                 dev_err(&pdev->dev, "failed to allocate glue context\n");
 495                 goto err0;
 496         }
 497
 498         musb = platform_device_alloc("musb-hdrc", -1);
 499         if (!musb) {
 500                 dev_err(&pdev->dev, "failed to allocate musb device\n");
 501                 goto err1;
 502         }
 503
 504         clk = clk_get(&pdev->dev, "usb20");
 505         if (IS_ERR(clk)) {
 506                 dev_err(&pdev->dev, "failed to get clock\n");
 507                 ret = PTR_ERR(clk);
 508                 goto err2;
 509         }
 510
 511         ret = clk_enable(clk);
 512         if (ret) {
 513                 dev_err(&pdev->dev, "failed to enable clock\n");
 514                 goto err3;
 515         }
 516
 517         musb->dev.parent                = &pdev->dev;
 518         musb->dev.dma_mask              = &da8xx_dmamask;
 519         musb->dev.coherent_dma_mask     = da8xx_dmamask;
 520
 521         glue->dev                       = &pdev->dev;
 522         glue->musb                      = musb;
 523         glue->clk                       = clk;
 524
 525         pdata->platform_ops             = &da8xx_ops;
 526
 527         platform_set_drvdata(pdev, glue);
 528
 529         ret = platform_device_add_resources(musb, pdev->resource,
 530                         pdev->num_resources);
 531         if (ret) {
 532                 dev_err(&pdev->dev, "failed to add resources\n");
 533                 goto err4;
 534         }
 535
 536         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 537         if (ret) {
 538                 dev_err(&pdev->dev, "failed to add platform_data\n");
 539                 goto err4;
 540         }
 541
 542         ret = platform_device_add(musb);
 543         if (ret) {
 544                 dev_err(&pdev->dev, "failed to register musb device\n");
 545                 goto err4;
 546         }
 547
 548         return 0;
 549
 550 err4:
 551         clk_disable(clk);
 552
 553 err3:
 554         clk_put(clk);
 555
 556 err2:
 557         platform_device_put(musb);
 558
 559 err1:
 560         kfree(glue);
 561
 562 err0:
 563         return ret;
 564 }
 565
 566 static int __devexit da8xx_remove(struct platform_device *pdev)
 567 {
 568         struct da8xx_glue               *glue = platform_get_drvdata(pdev);
 569
 570         platform_device_del(glue->musb);
 571         platform_device_put(glue->musb);
 572         clk_disable(glue->clk);
 573         clk_put(glue->clk);
 574         kfree(glue);
 575
 576         return 0;
 577 }
 578
 579 static struct platform_driver da8xx_driver = {
 580         .probe          = da8xx_probe,
 581         .remove         = __devexit_p(da8xx_remove),
 582         .driver         = {
 583                 .name   = "musb-da8xx",
 584         },
 585 };
 586
 587 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
 588 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
 589 MODULE_LICENSE("GPL v2");
 590
 591 static int __init da8xx_init(void)
 592 {
 593         return platform_driver_register(&da8xx_driver);
 594 }
 595 module_init(da8xx_init);
 596
 597 static void __exit da8xx_exit(void)
 598 {
 599         platform_driver_unregister(&da8xx_driver);
 600 }
 601 module_exit(da8xx_exit);