7f93dc26fb15ed06188bdb2ada806c295da2cf11
2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
10 #include <linux/irq.h>
11 #include <linux/slab.h>
13 static void urb_free_priv (struct ohci_hcd
*hc
, urb_priv_t
*urb_priv
)
15 int last
= urb_priv
->length
- 1;
21 for (i
= 0; i
<= last
; i
++) {
22 td
= urb_priv
->td
[i
];
28 list_del (&urb_priv
->pending
);
32 /*-------------------------------------------------------------------------*/
35 * URB goes back to driver, and isn't reissued.
36 * It's completely gone from HC data structures.
37 * PRECONDITION: ohci lock held, irqs blocked.
40 finish_urb(struct ohci_hcd
*ohci
, struct urb
*urb
, int status
)
41 __releases(ohci
->lock
)
42 __acquires(ohci
->lock
)
44 struct usb_host_endpoint
*ep
= urb
->ep
;
45 struct urb_priv
*urb_priv
;
47 // ASSERT (urb->hcpriv != 0);
50 urb_free_priv (ohci
, urb
->hcpriv
);
52 if (likely(status
== -EINPROGRESS
))
55 switch (usb_pipetype (urb
->pipe
)) {
56 case PIPE_ISOCHRONOUS
:
57 ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
--;
58 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
59 if (quirk_amdiso(ohci
))
60 usb_amd_quirk_pll_enable();
61 if (quirk_amdprefetch(ohci
))
62 sb800_prefetch(ohci
, 0);
66 ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
--;
70 #ifdef OHCI_VERBOSE_DEBUG
71 urb_print(urb
, "RET", usb_pipeout (urb
->pipe
), status
);
74 /* urb->complete() can reenter this HCD */
75 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci
), urb
);
76 spin_unlock (&ohci
->lock
);
77 usb_hcd_giveback_urb(ohci_to_hcd(ohci
), urb
, status
);
78 spin_lock (&ohci
->lock
);
80 /* stop periodic dma if it's not needed */
81 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0
82 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0) {
83 ohci
->hc_control
&= ~(OHCI_CTRL_PLE
|OHCI_CTRL_IE
);
84 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
88 * An isochronous URB that is sumitted too late won't have any TDs
89 * (marked by the fact that the td_cnt value is larger than the
90 * actual number of TDs). If the next URB on this endpoint is like
91 * that, give it back now.
93 if (!list_empty(&ep
->urb_list
)) {
94 urb
= list_first_entry(&ep
->urb_list
, struct urb
, urb_list
);
95 urb_priv
= urb
->hcpriv
;
96 if (urb_priv
->td_cnt
> urb_priv
->length
) {
104 /*-------------------------------------------------------------------------*
105 * ED handling functions
106 *-------------------------------------------------------------------------*/
108 /* search for the right schedule branch to use for a periodic ed.
109 * does some load balancing; returns the branch, or negative errno.
111 static int balance (struct ohci_hcd
*ohci
, int interval
, int load
)
113 int i
, branch
= -ENOSPC
;
115 /* iso periods can be huge; iso tds specify frame numbers */
116 if (interval
> NUM_INTS
)
119 /* search for the least loaded schedule branch of that period
120 * that has enough bandwidth left unreserved.
122 for (i
= 0; i
< interval
; i
++) {
123 if (branch
< 0 || ohci
->load
[branch
] > ohci
->load
[i
]) {
126 /* usb 1.1 says 90% of one frame */
127 for (j
= i
; j
< NUM_INTS
; j
+= interval
) {
128 if ((ohci
->load
[j
] + load
) > 900)
139 /*-------------------------------------------------------------------------*/
141 /* both iso and interrupt requests have periods; this routine puts them
142 * into the schedule tree in the apppropriate place. most iso devices use
143 * 1msec periods, but that's not required.
145 static void periodic_link (struct ohci_hcd
*ohci
, struct ed
*ed
)
149 ohci_vdbg (ohci
, "link %sed %p branch %d [%dus.], interval %d\n",
150 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
151 ed
, ed
->branch
, ed
->load
, ed
->interval
);
153 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
154 struct ed
**prev
= &ohci
->periodic
[i
];
155 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
156 struct ed
*here
= *prev
;
158 /* sorting each branch by period (slow before fast)
159 * lets us share the faster parts of the tree.
160 * (plus maybe: put interrupt eds before iso)
162 while (here
&& ed
!= here
) {
163 if (ed
->interval
> here
->interval
)
165 prev
= &here
->ed_next
;
166 prev_p
= &here
->hwNextED
;
172 ed
->hwNextED
= *prev_p
;
175 *prev_p
= cpu_to_hc32(ohci
, ed
->dma
);
178 ohci
->load
[i
] += ed
->load
;
180 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
+= ed
->load
/ ed
->interval
;
183 /* link an ed into one of the HC chains */
185 static int ed_schedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
193 if (quirk_zfmicro(ohci
)
194 && (ed
->type
== PIPE_INTERRUPT
)
195 && !(ohci
->eds_scheduled
++))
196 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
199 /* we care about rm_list when setting CLE/BLE in case the HC was at
200 * work on some TD when CLE/BLE was turned off, and isn't quiesced
201 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
203 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
204 * periodic ones are singly linked (ed_next). that's because the
205 * periodic schedule encodes a tree like figure 3-5 in the ohci
206 * spec: each qh can have several "previous" nodes, and the tree
207 * doesn't have unused/idle descriptors.
211 if (ohci
->ed_controltail
== NULL
) {
212 WARN_ON (ohci
->hc_control
& OHCI_CTRL_CLE
);
213 ohci_writel (ohci
, ed
->dma
,
214 &ohci
->regs
->ed_controlhead
);
216 ohci
->ed_controltail
->ed_next
= ed
;
217 ohci
->ed_controltail
->hwNextED
= cpu_to_hc32 (ohci
,
220 ed
->ed_prev
= ohci
->ed_controltail
;
221 if (!ohci
->ed_controltail
&& !ohci
->ed_rm_list
) {
223 ohci
->hc_control
|= OHCI_CTRL_CLE
;
224 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlcurrent
);
225 ohci_writel (ohci
, ohci
->hc_control
,
226 &ohci
->regs
->control
);
228 ohci
->ed_controltail
= ed
;
232 if (ohci
->ed_bulktail
== NULL
) {
233 WARN_ON (ohci
->hc_control
& OHCI_CTRL_BLE
);
234 ohci_writel (ohci
, ed
->dma
, &ohci
->regs
->ed_bulkhead
);
236 ohci
->ed_bulktail
->ed_next
= ed
;
237 ohci
->ed_bulktail
->hwNextED
= cpu_to_hc32 (ohci
,
240 ed
->ed_prev
= ohci
->ed_bulktail
;
241 if (!ohci
->ed_bulktail
&& !ohci
->ed_rm_list
) {
243 ohci
->hc_control
|= OHCI_CTRL_BLE
;
244 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkcurrent
);
245 ohci_writel (ohci
, ohci
->hc_control
,
246 &ohci
->regs
->control
);
248 ohci
->ed_bulktail
= ed
;
251 // case PIPE_INTERRUPT:
252 // case PIPE_ISOCHRONOUS:
254 branch
= balance (ohci
, ed
->interval
, ed
->load
);
257 "ERR %d, interval %d msecs, load %d\n",
258 branch
, ed
->interval
, ed
->load
);
259 // FIXME if there are TDs queued, fail them!
263 periodic_link (ohci
, ed
);
266 /* the HC may not see the schedule updates yet, but if it does
267 * then they'll be properly ordered.
272 /*-------------------------------------------------------------------------*/
274 /* scan the periodic table to find and unlink this ED */
275 static void periodic_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
279 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
281 struct ed
**prev
= &ohci
->periodic
[i
];
282 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
284 while (*prev
&& (temp
= *prev
) != ed
) {
285 prev_p
= &temp
->hwNextED
;
286 prev
= &temp
->ed_next
;
289 *prev_p
= ed
->hwNextED
;
292 ohci
->load
[i
] -= ed
->load
;
294 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
-= ed
->load
/ ed
->interval
;
296 ohci_vdbg (ohci
, "unlink %sed %p branch %d [%dus.], interval %d\n",
297 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
298 ed
, ed
->branch
, ed
->load
, ed
->interval
);
301 /* unlink an ed from one of the HC chains.
302 * just the link to the ed is unlinked.
303 * the link from the ed still points to another operational ed or 0
304 * so the HC can eventually finish the processing of the unlinked ed
305 * (assuming it already started that, which needn't be true).
307 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
308 * it won't. ED_SKIP means the HC will finish its current transaction,
309 * but won't start anything new. The TD queue may still grow; device
310 * drivers don't know about this HCD-internal state.
312 * When the HC can't see the ED, something changes ED_UNLINK to one of:
314 * - ED_OPER: when there's any request queued, the ED gets rescheduled
315 * immediately. HC should be working on them.
317 * - ED_IDLE: when there's no TD queue or the HC isn't running.
319 * When finish_unlinks() runs later, after SOF interrupt, it will often
320 * complete one or more URB unlinks before making that state change.
322 static void ed_deschedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
324 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
326 ed
->state
= ED_UNLINK
;
328 /* To deschedule something from the control or bulk list, just
329 * clear CLE/BLE and wait. There's no safe way to scrub out list
330 * head/current registers until later, and "later" isn't very
331 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
332 * the HC is reading the ED queues (while we modify them).
334 * For now, ed_schedule() is "later". It might be good paranoia
335 * to scrub those registers in finish_unlinks(), in case of bugs
336 * that make the HC try to use them.
340 /* remove ED from the HC's list: */
341 if (ed
->ed_prev
== NULL
) {
343 ohci
->hc_control
&= ~OHCI_CTRL_CLE
;
344 ohci_writel (ohci
, ohci
->hc_control
,
345 &ohci
->regs
->control
);
346 // a ohci_readl() later syncs CLE with the HC
349 hc32_to_cpup (ohci
, &ed
->hwNextED
),
350 &ohci
->regs
->ed_controlhead
);
352 ed
->ed_prev
->ed_next
= ed
->ed_next
;
353 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
355 /* remove ED from the HCD's list: */
356 if (ohci
->ed_controltail
== ed
) {
357 ohci
->ed_controltail
= ed
->ed_prev
;
358 if (ohci
->ed_controltail
)
359 ohci
->ed_controltail
->ed_next
= NULL
;
360 } else if (ed
->ed_next
) {
361 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
366 /* remove ED from the HC's list: */
367 if (ed
->ed_prev
== NULL
) {
369 ohci
->hc_control
&= ~OHCI_CTRL_BLE
;
370 ohci_writel (ohci
, ohci
->hc_control
,
371 &ohci
->regs
->control
);
372 // a ohci_readl() later syncs BLE with the HC
375 hc32_to_cpup (ohci
, &ed
->hwNextED
),
376 &ohci
->regs
->ed_bulkhead
);
378 ed
->ed_prev
->ed_next
= ed
->ed_next
;
379 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
381 /* remove ED from the HCD's list: */
382 if (ohci
->ed_bulktail
== ed
) {
383 ohci
->ed_bulktail
= ed
->ed_prev
;
384 if (ohci
->ed_bulktail
)
385 ohci
->ed_bulktail
->ed_next
= NULL
;
386 } else if (ed
->ed_next
) {
387 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
391 // case PIPE_INTERRUPT:
392 // case PIPE_ISOCHRONOUS:
394 periodic_unlink (ohci
, ed
);
400 /*-------------------------------------------------------------------------*/
402 /* get and maybe (re)init an endpoint. init _should_ be done only as part
403 * of enumeration, usb_set_configuration() or usb_set_interface().
405 static struct ed
*ed_get (
406 struct ohci_hcd
*ohci
,
407 struct usb_host_endpoint
*ep
,
408 struct usb_device
*udev
,
415 spin_lock_irqsave (&ohci
->lock
, flags
);
417 if (!(ed
= ep
->hcpriv
)) {
422 ed
= ed_alloc (ohci
, GFP_ATOMIC
);
428 /* dummy td; end of td list for ed */
429 td
= td_alloc (ohci
, GFP_ATOMIC
);
437 ed
->hwTailP
= cpu_to_hc32 (ohci
, td
->td_dma
);
438 ed
->hwHeadP
= ed
->hwTailP
; /* ED_C, ED_H zeroed */
441 is_out
= !(ep
->desc
.bEndpointAddress
& USB_DIR_IN
);
443 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
444 * succeeds ... otherwise we wouldn't need "pipe".
446 info
= usb_pipedevice (pipe
);
447 ed
->type
= usb_pipetype(pipe
);
449 info
|= (ep
->desc
.bEndpointAddress
& ~USB_DIR_IN
) << 7;
450 info
|= usb_endpoint_maxp(&ep
->desc
) << 16;
451 if (udev
->speed
== USB_SPEED_LOW
)
453 /* only control transfers store pids in tds */
454 if (ed
->type
!= PIPE_CONTROL
) {
455 info
|= is_out
? ED_OUT
: ED_IN
;
456 if (ed
->type
!= PIPE_BULK
) {
457 /* periodic transfers... */
458 if (ed
->type
== PIPE_ISOCHRONOUS
)
460 else if (interval
> 32) /* iso can be bigger */
462 ed
->interval
= interval
;
463 ed
->load
= usb_calc_bus_time (
464 udev
->speed
, !is_out
,
465 ed
->type
== PIPE_ISOCHRONOUS
,
466 usb_endpoint_maxp(&ep
->desc
))
470 ed
->hwINFO
= cpu_to_hc32(ohci
, info
);
476 spin_unlock_irqrestore (&ohci
->lock
, flags
);
480 /*-------------------------------------------------------------------------*/
482 /* request unlinking of an endpoint from an operational HC.
483 * put the ep on the rm_list
484 * real work is done at the next start frame (SF) hardware interrupt
485 * caller guarantees HCD is running, so hardware access is safe,
486 * and that ed->state is ED_OPER
488 static void start_ed_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
490 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_DEQUEUE
);
491 ed_deschedule (ohci
, ed
);
493 /* rm_list is just singly linked, for simplicity */
494 ed
->ed_next
= ohci
->ed_rm_list
;
496 ohci
->ed_rm_list
= ed
;
498 /* enable SOF interrupt */
499 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrstatus
);
500 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrenable
);
501 // flush those writes, and get latest HCCA contents
502 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
504 /* SF interrupt might get delayed; record the frame counter value that
505 * indicates when the HC isn't looking at it, so concurrent unlinks
506 * behave. frame_no wraps every 2^16 msec, and changes right before
509 ed
->tick
= ohci_frame_no(ohci
) + 1;
513 /*-------------------------------------------------------------------------*
514 * TD handling functions
515 *-------------------------------------------------------------------------*/
517 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
520 td_fill (struct ohci_hcd
*ohci
, u32 info
,
521 dma_addr_t data
, int len
,
522 struct urb
*urb
, int index
)
524 struct td
*td
, *td_pt
;
525 struct urb_priv
*urb_priv
= urb
->hcpriv
;
526 int is_iso
= info
& TD_ISO
;
529 // ASSERT (index < urb_priv->length);
531 /* aim for only one interrupt per urb. mostly applies to control
532 * and iso; other urbs rarely need more than one TD per urb.
533 * this way, only final tds (or ones with an error) cause IRQs.
534 * at least immediately; use DI=6 in case any control request is
535 * tempted to die part way through. (and to force the hc to flush
536 * its donelist soonish, even on unlink paths.)
538 * NOTE: could delay interrupts even for the last TD, and get fewer
539 * interrupts ... increasing per-urb latency by sharing interrupts.
540 * Drivers that queue bulk urbs may request that behavior.
542 if (index
!= (urb_priv
->length
- 1)
543 || (urb
->transfer_flags
& URB_NO_INTERRUPT
))
544 info
|= TD_DI_SET (6);
546 /* use this td as the next dummy */
547 td_pt
= urb_priv
->td
[index
];
549 /* fill the old dummy TD */
550 td
= urb_priv
->td
[index
] = urb_priv
->ed
->dummy
;
551 urb_priv
->ed
->dummy
= td_pt
;
553 td
->ed
= urb_priv
->ed
;
554 td
->next_dl_td
= NULL
;
561 td
->hwINFO
= cpu_to_hc32 (ohci
, info
);
563 td
->hwCBP
= cpu_to_hc32 (ohci
, data
& 0xFFFFF000);
564 *ohci_hwPSWp(ohci
, td
, 0) = cpu_to_hc16 (ohci
,
565 (data
& 0x0FFF) | 0xE000);
567 td
->hwCBP
= cpu_to_hc32 (ohci
, data
);
570 td
->hwBE
= cpu_to_hc32 (ohci
, data
+ len
- 1);
573 td
->hwNextTD
= cpu_to_hc32 (ohci
, td_pt
->td_dma
);
575 /* append to queue */
576 list_add_tail (&td
->td_list
, &td
->ed
->td_list
);
578 /* hash it for later reverse mapping */
579 hash
= TD_HASH_FUNC (td
->td_dma
);
580 td
->td_hash
= ohci
->td_hash
[hash
];
581 ohci
->td_hash
[hash
] = td
;
583 /* HC might read the TD (or cachelines) right away ... */
585 td
->ed
->hwTailP
= td
->hwNextTD
;
588 /*-------------------------------------------------------------------------*/
590 /* Prepare all TDs of a transfer, and queue them onto the ED.
591 * Caller guarantees HC is active.
592 * Usually the ED is already on the schedule, so TDs might be
593 * processed as soon as they're queued.
595 static void td_submit_urb (
596 struct ohci_hcd
*ohci
,
599 struct urb_priv
*urb_priv
= urb
->hcpriv
;
601 int data_len
= urb
->transfer_buffer_length
;
604 int is_out
= usb_pipeout (urb
->pipe
);
607 /* OHCI handles the bulk/interrupt data toggles itself. We just
608 * use the device toggle bits for resetting, and rely on the fact
609 * that resetting toggle is meaningless if the endpoint is active.
611 if (!usb_gettoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
), is_out
)) {
612 usb_settoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
),
614 urb_priv
->ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_C
);
617 list_add (&urb_priv
->pending
, &ohci
->pending
);
620 data
= urb
->transfer_dma
;
624 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
625 * using TD_CC_GET, as well as by seeing them on the done list.
626 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
628 switch (urb_priv
->ed
->type
) {
630 /* Bulk and interrupt are identical except for where in the schedule
634 /* ... and periodic urbs have extra accounting */
635 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
++ == 0
636 && ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0;
640 ? TD_T_TOGGLE
| TD_CC
| TD_DP_OUT
641 : TD_T_TOGGLE
| TD_CC
| TD_DP_IN
;
642 /* TDs _could_ transfer up to 8K each */
643 while (data_len
> 4096) {
644 td_fill (ohci
, info
, data
, 4096, urb
, cnt
);
649 /* maybe avoid ED halt on final TD short read */
650 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
652 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
);
654 if ((urb
->transfer_flags
& URB_ZERO_PACKET
)
655 && cnt
< urb_priv
->length
) {
656 td_fill (ohci
, info
, 0, 0, urb
, cnt
);
659 /* maybe kickstart bulk list */
660 if (urb_priv
->ed
->type
== PIPE_BULK
) {
662 ohci_writel (ohci
, OHCI_BLF
, &ohci
->regs
->cmdstatus
);
666 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
667 * any DATA phase works normally, and the STATUS ack is special.
670 info
= TD_CC
| TD_DP_SETUP
| TD_T_DATA0
;
671 td_fill (ohci
, info
, urb
->setup_dma
, 8, urb
, cnt
++);
673 info
= TD_CC
| TD_R
| TD_T_DATA1
;
674 info
|= is_out
? TD_DP_OUT
: TD_DP_IN
;
675 /* NOTE: mishandles transfers >8K, some >4K */
676 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
++);
678 info
= (is_out
|| data_len
== 0)
679 ? TD_CC
| TD_DP_IN
| TD_T_DATA1
680 : TD_CC
| TD_DP_OUT
| TD_T_DATA1
;
681 td_fill (ohci
, info
, data
, 0, urb
, cnt
++);
682 /* maybe kickstart control list */
684 ohci_writel (ohci
, OHCI_CLF
, &ohci
->regs
->cmdstatus
);
687 /* ISO has no retransmit, so no toggle; and it uses special TDs.
688 * Each TD could handle multiple consecutive frames (interval 1);
689 * we could often reduce the number of TDs here.
691 case PIPE_ISOCHRONOUS
:
692 for (cnt
= urb_priv
->td_cnt
; cnt
< urb
->number_of_packets
;
694 int frame
= urb
->start_frame
;
696 // FIXME scheduling should handle frame counter
697 // roll-around ... exotic case (and OHCI has
698 // a 2^16 iso range, vs other HCs max of 2^10)
699 frame
+= cnt
* urb
->interval
;
701 td_fill (ohci
, TD_CC
| TD_ISO
| frame
,
702 data
+ urb
->iso_frame_desc
[cnt
].offset
,
703 urb
->iso_frame_desc
[cnt
].length
, urb
, cnt
);
705 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
706 if (quirk_amdiso(ohci
))
707 usb_amd_quirk_pll_disable();
708 if (quirk_amdprefetch(ohci
))
709 sb800_prefetch(ohci
, 1);
711 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
++ == 0
712 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0;
716 /* start periodic dma if needed */
719 ohci
->hc_control
|= OHCI_CTRL_PLE
|OHCI_CTRL_IE
;
720 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
723 // ASSERT (urb_priv->length == cnt);
726 /*-------------------------------------------------------------------------*
727 * Done List handling functions
728 *-------------------------------------------------------------------------*/
730 /* calculate transfer length/status and update the urb */
731 static int td_done(struct ohci_hcd
*ohci
, struct urb
*urb
, struct td
*td
)
733 u32 tdINFO
= hc32_to_cpup (ohci
, &td
->hwINFO
);
735 int status
= -EINPROGRESS
;
737 list_del (&td
->td_list
);
739 /* ISO ... drivers see per-TD length/status */
740 if (tdINFO
& TD_ISO
) {
741 u16 tdPSW
= ohci_hwPSW(ohci
, td
, 0);
744 /* NOTE: assumes FC in tdINFO == 0, and that
745 * only the first of 0..MAXPSW psws is used.
748 cc
= (tdPSW
>> 12) & 0xF;
749 if (tdINFO
& TD_CC
) /* hc didn't touch? */
752 if (usb_pipeout (urb
->pipe
))
753 dlen
= urb
->iso_frame_desc
[td
->index
].length
;
755 /* short reads are always OK for ISO */
756 if (cc
== TD_DATAUNDERRUN
)
758 dlen
= tdPSW
& 0x3ff;
760 urb
->actual_length
+= dlen
;
761 urb
->iso_frame_desc
[td
->index
].actual_length
= dlen
;
762 urb
->iso_frame_desc
[td
->index
].status
= cc_to_error
[cc
];
764 if (cc
!= TD_CC_NOERROR
)
766 "urb %p iso td %p (%d) len %d cc %d\n",
767 urb
, td
, 1 + td
->index
, dlen
, cc
);
769 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
770 * except that "setup" bytes aren't counted and "short" transfers
771 * might not be reported as errors.
774 int type
= usb_pipetype (urb
->pipe
);
775 u32 tdBE
= hc32_to_cpup (ohci
, &td
->hwBE
);
777 cc
= TD_CC_GET (tdINFO
);
779 /* update packet status if needed (short is normally ok) */
780 if (cc
== TD_DATAUNDERRUN
781 && !(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
783 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
784 status
= cc_to_error
[cc
];
786 /* count all non-empty packets except control SETUP packet */
787 if ((type
!= PIPE_CONTROL
|| td
->index
!= 0) && tdBE
!= 0) {
789 urb
->actual_length
+= tdBE
- td
->data_dma
+ 1;
791 urb
->actual_length
+=
792 hc32_to_cpup (ohci
, &td
->hwCBP
)
796 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
798 "urb %p td %p (%d) cc %d, len=%d/%d\n",
799 urb
, td
, 1 + td
->index
, cc
,
801 urb
->transfer_buffer_length
);
806 /*-------------------------------------------------------------------------*/
808 static void ed_halted(struct ohci_hcd
*ohci
, struct td
*td
, int cc
)
810 struct urb
*urb
= td
->urb
;
811 urb_priv_t
*urb_priv
= urb
->hcpriv
;
812 struct ed
*ed
= td
->ed
;
813 struct list_head
*tmp
= td
->td_list
.next
;
814 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_C
);
816 /* clear ed halt; this is the td that caused it, but keep it inactive
817 * until its urb->complete() has a chance to clean up.
819 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
821 ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_H
);
823 /* Get rid of all later tds from this urb. We don't have
824 * to be careful: no errors and nothing was transferred.
825 * Also patch the ed so it looks as if those tds completed normally.
827 while (tmp
!= &ed
->td_list
) {
830 next
= list_entry (tmp
, struct td
, td_list
);
831 tmp
= next
->td_list
.next
;
833 if (next
->urb
!= urb
)
836 /* NOTE: if multi-td control DATA segments get supported,
837 * this urb had one of them, this td wasn't the last td
838 * in that segment (TD_R clear), this ed halted because
839 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
840 * then we need to leave the control STATUS packet queued
844 list_del(&next
->td_list
);
846 ed
->hwHeadP
= next
->hwNextTD
| toggle
;
849 /* help for troubleshooting: report anything that
850 * looks odd ... that doesn't include protocol stalls
851 * (or maybe some other things)
854 case TD_DATAUNDERRUN
:
855 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) == 0)
859 if (usb_pipecontrol (urb
->pipe
))
864 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
865 urb
, urb
->dev
->devpath
,
866 usb_pipeendpoint (urb
->pipe
),
867 usb_pipein (urb
->pipe
) ? "in" : "out",
868 hc32_to_cpu (ohci
, td
->hwINFO
),
869 cc
, cc_to_error
[cc
]);
873 /* replies to the request have to be on a FIFO basis so
874 * we unreverse the hc-reversed done-list
876 static struct td
*dl_reverse_done_list (struct ohci_hcd
*ohci
)
879 struct td
*td_rev
= NULL
;
880 struct td
*td
= NULL
;
882 td_dma
= hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
);
883 ohci
->hcca
->done_head
= 0;
886 /* get TD from hc's singly linked list, and
887 * prepend to ours. ed->td_list changes later.
892 td
= dma_to_td (ohci
, td_dma
);
894 ohci_err (ohci
, "bad entry %8x\n", td_dma
);
898 td
->hwINFO
|= cpu_to_hc32 (ohci
, TD_DONE
);
899 cc
= TD_CC_GET (hc32_to_cpup (ohci
, &td
->hwINFO
));
901 /* Non-iso endpoints can halt on error; un-halt,
902 * and dequeue any other TDs from this urb.
903 * No other TD could have caused the halt.
905 if (cc
!= TD_CC_NOERROR
906 && (td
->ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_H
)))
907 ed_halted(ohci
, td
, cc
);
909 td
->next_dl_td
= td_rev
;
911 td_dma
= hc32_to_cpup (ohci
, &td
->hwNextTD
);
916 /*-------------------------------------------------------------------------*/
918 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
920 finish_unlinks (struct ohci_hcd
*ohci
, u16 tick
)
922 struct ed
*ed
, **last
;
925 for (last
= &ohci
->ed_rm_list
, ed
= *last
; ed
!= NULL
; ed
= *last
) {
926 struct list_head
*entry
, *tmp
;
927 int completed
, modified
;
930 /* only take off EDs that the HC isn't using, accounting for
931 * frame counter wraps and EDs with partially retired TDs
933 if (likely(ohci
->rh_state
== OHCI_RH_RUNNING
)) {
934 if (tick_before (tick
, ed
->tick
)) {
940 if (!list_empty (&ed
->td_list
)) {
944 td
= list_entry (ed
->td_list
.next
, struct td
,
946 head
= hc32_to_cpu (ohci
, ed
->hwHeadP
) &
949 /* INTR_WDH may need to clean up first */
950 if (td
->td_dma
!= head
) {
951 if (ed
== ohci
->ed_to_check
)
952 ohci
->ed_to_check
= NULL
;
959 /* ED's now officially unlinked, hc doesn't see */
960 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
961 ohci
->eds_scheduled
--;
962 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_H
);
965 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
);
967 /* reentrancy: if we drop the schedule lock, someone might
968 * have modified this list. normally it's just prepending
969 * entries (which we'd ignore), but paranoia won't hurt.
973 /* unlink urbs as requested, but rescan the list after
974 * we call a completion since it might have unlinked
975 * another (earlier) urb
977 * When we get here, the HC doesn't see this ed. But it
978 * must not be rescheduled until all completed URBs have
979 * been given back to the driver.
984 list_for_each_safe (entry
, tmp
, &ed
->td_list
) {
987 urb_priv_t
*urb_priv
;
991 td
= list_entry (entry
, struct td
, td_list
);
993 urb_priv
= td
->urb
->hcpriv
;
995 if (!urb
->unlinked
) {
996 prev
= &td
->hwNextTD
;
1000 /* patch pointer hc uses */
1001 savebits
= *prev
& ~cpu_to_hc32 (ohci
, TD_MASK
);
1002 *prev
= td
->hwNextTD
| savebits
;
1004 /* If this was unlinked, the TD may not have been
1005 * retired ... so manually save the data toggle.
1006 * The controller ignores the value we save for
1007 * control and ISO endpoints.
1009 tdINFO
= hc32_to_cpup(ohci
, &td
->hwINFO
);
1010 if ((tdINFO
& TD_T
) == TD_T_DATA0
)
1011 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_C
);
1012 else if ((tdINFO
& TD_T
) == TD_T_DATA1
)
1013 ed
->hwHeadP
|= cpu_to_hc32(ohci
, ED_C
);
1015 /* HC may have partly processed this TD */
1016 td_done (ohci
, urb
, td
);
1019 /* if URB is done, clean up */
1020 if (urb_priv
->td_cnt
>= urb_priv
->length
) {
1021 modified
= completed
= 1;
1022 finish_urb(ohci
, urb
, 0);
1025 if (completed
&& !list_empty (&ed
->td_list
))
1029 * If no TDs are queued, take ED off the ed_rm_list.
1030 * Otherwise, if the HC is running, reschedule.
1031 * If not, leave it on the list for further dequeues.
1033 if (list_empty(&ed
->td_list
)) {
1034 *last
= ed
->ed_next
;
1036 ed
->state
= ED_IDLE
;
1037 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
1038 *last
= ed
->ed_next
;
1040 ed_schedule(ohci
, ed
);
1042 last
= &ed
->ed_next
;
1049 /* maybe reenable control and bulk lists */
1050 if (ohci
->rh_state
== OHCI_RH_RUNNING
&& !ohci
->ed_rm_list
) {
1051 u32 command
= 0, control
= 0;
1053 if (ohci
->ed_controltail
) {
1054 command
|= OHCI_CLF
;
1055 if (quirk_zfmicro(ohci
))
1057 if (!(ohci
->hc_control
& OHCI_CTRL_CLE
)) {
1058 control
|= OHCI_CTRL_CLE
;
1059 ohci_writel (ohci
, 0,
1060 &ohci
->regs
->ed_controlcurrent
);
1063 if (ohci
->ed_bulktail
) {
1064 command
|= OHCI_BLF
;
1065 if (quirk_zfmicro(ohci
))
1067 if (!(ohci
->hc_control
& OHCI_CTRL_BLE
)) {
1068 control
|= OHCI_CTRL_BLE
;
1069 ohci_writel (ohci
, 0,
1070 &ohci
->regs
->ed_bulkcurrent
);
1074 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1076 ohci
->hc_control
|= control
;
1077 if (quirk_zfmicro(ohci
))
1079 ohci_writel (ohci
, ohci
->hc_control
,
1080 &ohci
->regs
->control
);
1083 if (quirk_zfmicro(ohci
))
1085 ohci_writel (ohci
, command
, &ohci
->regs
->cmdstatus
);
1092 /*-------------------------------------------------------------------------*/
1095 * Used to take back a TD from the host controller. This would normally be
1096 * called from within dl_done_list, however it may be called directly if the
1097 * HC no longer sees the TD and it has not appeared on the donelist (after
1098 * two frames). This bug has been observed on ZF Micro systems.
1100 static void takeback_td(struct ohci_hcd
*ohci
, struct td
*td
)
1102 struct urb
*urb
= td
->urb
;
1103 urb_priv_t
*urb_priv
= urb
->hcpriv
;
1104 struct ed
*ed
= td
->ed
;
1107 /* update URB's length and status from TD */
1108 status
= td_done(ohci
, urb
, td
);
1111 /* If all this urb's TDs are done, call complete() */
1112 if (urb_priv
->td_cnt
>= urb_priv
->length
)
1113 finish_urb(ohci
, urb
, status
);
1115 /* clean schedule: unlink EDs that are no longer busy */
1116 if (list_empty(&ed
->td_list
)) {
1117 if (ed
->state
== ED_OPER
)
1118 start_ed_unlink(ohci
, ed
);
1120 /* ... reenabling halted EDs only after fault cleanup */
1121 } else if ((ed
->hwINFO
& cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
))
1122 == cpu_to_hc32(ohci
, ED_SKIP
)) {
1123 td
= list_entry(ed
->td_list
.next
, struct td
, td_list
);
1124 if (!(td
->hwINFO
& cpu_to_hc32(ohci
, TD_DONE
))) {
1125 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
);
1126 /* ... hc may need waking-up */
1129 ohci_writel(ohci
, OHCI_CLF
,
1130 &ohci
->regs
->cmdstatus
);
1133 ohci_writel(ohci
, OHCI_BLF
,
1134 &ohci
->regs
->cmdstatus
);
1142 * Process normal completions (error or success) and clean the schedules.
1144 * This is the main path for handing urbs back to drivers. The only other
1145 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1146 * instead of scanning the (re-reversed) donelist as this does. There's
1147 * an abnormal path too, handling a quirk in some Compaq silicon: URBs
1148 * with TDs that appear to be orphaned are directly reclaimed.
1151 dl_done_list (struct ohci_hcd
*ohci
)
1153 struct td
*td
= dl_reverse_done_list (ohci
);
1156 struct td
*td_next
= td
->next_dl_td
;
1157 struct ed
*ed
= td
->ed
;
1160 * Some OHCI controllers (NVIDIA for sure, maybe others)
1161 * occasionally forget to add TDs to the done queue. Since
1162 * TDs for a given endpoint are always processed in order,
1163 * if we find a TD on the donelist then all of its
1164 * predecessors must be finished as well.
1169 td2
= list_first_entry(&ed
->td_list
, struct td
,
1173 takeback_td(ohci
, td2
);
1176 takeback_td(ohci
, td
);