2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 #include "pci-quirks.h"
81 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
82 static int ohci_init (struct ohci_hcd
*ohci
);
83 static void ohci_stop (struct usb_hcd
*hcd
);
85 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
86 static int ohci_restart (struct ohci_hcd
*ohci
);
90 static void sb800_prefetch(struct ohci_hcd
*ohci
, int on
);
92 static inline void sb800_prefetch(struct ohci_hcd
*ohci
, int on
)
100 #include "ohci-dbg.c"
101 #include "ohci-mem.c"
106 * On architectures with edge-triggered interrupts we must never return
109 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
110 #define IRQ_NOTMINE IRQ_HANDLED
112 #define IRQ_NOTMINE IRQ_NONE
116 /* Some boards misreport power switching/overcurrent */
117 static bool distrust_firmware
= 1;
118 module_param (distrust_firmware
, bool, 0);
119 MODULE_PARM_DESC (distrust_firmware
,
120 "true to distrust firmware power/overcurrent setup");
122 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
123 static bool no_handshake
= 0;
124 module_param (no_handshake
, bool, 0);
125 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
127 /*-------------------------------------------------------------------------*/
130 * queue up an urb for anything except the root hub
132 static int ohci_urb_enqueue (
137 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
139 urb_priv_t
*urb_priv
;
140 unsigned int pipe
= urb
->pipe
;
145 #ifdef OHCI_VERBOSE_DEBUG
146 urb_print(urb
, "SUB", usb_pipein(pipe
), -EINPROGRESS
);
149 /* every endpoint has a ed, locate and maybe (re)initialize it */
150 if (! (ed
= ed_get (ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
)))
153 /* for the private part of the URB we need the number of TDs (size) */
156 /* td_submit_urb() doesn't yet handle these */
157 if (urb
->transfer_buffer_length
> 4096)
160 /* 1 TD for setup, 1 for ACK, plus ... */
163 // case PIPE_INTERRUPT:
166 /* one TD for every 4096 Bytes (can be up to 8K) */
167 size
+= urb
->transfer_buffer_length
/ 4096;
168 /* ... and for any remaining bytes ... */
169 if ((urb
->transfer_buffer_length
% 4096) != 0)
171 /* ... and maybe a zero length packet to wrap it up */
174 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
175 && (urb
->transfer_buffer_length
176 % usb_maxpacket (urb
->dev
, pipe
,
177 usb_pipeout (pipe
))) == 0)
180 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
181 size
= urb
->number_of_packets
;
185 /* allocate the private part of the URB */
186 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
190 INIT_LIST_HEAD (&urb_priv
->pending
);
191 urb_priv
->length
= size
;
194 /* allocate the TDs (deferring hash chain updates) */
195 for (i
= 0; i
< size
; i
++) {
196 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
197 if (!urb_priv
->td
[i
]) {
198 urb_priv
->length
= i
;
199 urb_free_priv (ohci
, urb_priv
);
204 spin_lock_irqsave (&ohci
->lock
, flags
);
206 /* don't submit to a dead HC */
207 if (!HCD_HW_ACCESSIBLE(hcd
)) {
211 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
215 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
219 /* schedule the ed if needed */
220 if (ed
->state
== ED_IDLE
) {
221 retval
= ed_schedule (ohci
, ed
);
223 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
226 if (ed
->type
== PIPE_ISOCHRONOUS
) {
227 u16 frame
= ohci_frame_no(ohci
);
229 /* delay a few frames before the first TD */
230 frame
+= max_t (u16
, 8, ed
->interval
);
231 frame
&= ~(ed
->interval
- 1);
233 urb
->start_frame
= frame
;
235 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
236 u16 next
= ohci_frame_no(ohci
) + 1;
237 u16 frame
= ed
->last_iso
+ ed
->interval
;
239 /* Behind the scheduling threshold? */
240 if (unlikely(tick_before(frame
, next
))) {
242 /* USB_ISO_ASAP: Round up to the first available slot */
243 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
244 frame
+= (next
- frame
+ ed
->interval
- 1) &
248 * Not ASAP: Use the next slot in the stream. If
249 * the entire URB falls before the threshold, fail.
252 if (tick_before(frame
+ ed
->interval
*
253 (urb
->number_of_packets
- 1), next
)) {
255 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
260 * Some OHCI hardware doesn't handle late TDs
261 * correctly. After retiring them it proceeds
262 * to the next ED instead of the next TD.
263 * Therefore we have to omit the late TDs
266 urb_priv
->td_cnt
= DIV_ROUND_UP(
267 (u16
) (next
- frame
),
271 urb
->start_frame
= frame
;
274 /* fill the TDs and link them to the ed; and
275 * enable that part of the schedule, if needed
276 * and update count of queued periodic urbs
278 urb
->hcpriv
= urb_priv
;
279 td_submit_urb (ohci
, urb
);
283 urb_free_priv (ohci
, urb_priv
);
284 spin_unlock_irqrestore (&ohci
->lock
, flags
);
289 * decouple the URB from the HC queues (TDs, urb_priv).
290 * reporting is always done
291 * asynchronously, and we might be dealing with an urb that's
292 * partially transferred, or an ED with other urbs being unlinked.
294 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
296 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
300 #ifdef OHCI_VERBOSE_DEBUG
301 urb_print(urb
, "UNLINK", 1, status
);
304 spin_lock_irqsave (&ohci
->lock
, flags
);
305 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
308 } else if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
309 urb_priv_t
*urb_priv
;
311 /* Unless an IRQ completed the unlink while it was being
312 * handed to us, flag it for unlink and giveback, and force
313 * some upcoming INTR_SF to call finish_unlinks()
315 urb_priv
= urb
->hcpriv
;
317 if (urb_priv
->ed
->state
== ED_OPER
)
318 start_ed_unlink (ohci
, urb_priv
->ed
);
322 * with HC dead, we won't respect hc queue pointers
323 * any more ... just clean up every urb's memory.
326 finish_urb(ohci
, urb
, status
);
328 spin_unlock_irqrestore (&ohci
->lock
, flags
);
332 /*-------------------------------------------------------------------------*/
334 /* frees config/altsetting state for endpoints,
335 * including ED memory, dummy TD, and bulk/intr data toggle
339 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
341 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
343 struct ed
*ed
= ep
->hcpriv
;
344 unsigned limit
= 1000;
346 /* ASSERT: any requests/urbs are being unlinked */
347 /* ASSERT: nobody can be submitting urbs for this any more */
353 spin_lock_irqsave (&ohci
->lock
, flags
);
355 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
358 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
359 ohci
->eds_scheduled
--;
360 finish_unlinks (ohci
, 0);
364 case ED_UNLINK
: /* wait for hw to finish? */
365 /* major IRQ delivery trouble loses INTR_SF too... */
367 ohci_warn(ohci
, "ED unlink timeout\n");
368 if (quirk_zfmicro(ohci
)) {
369 ohci_warn(ohci
, "Attempting ZF TD recovery\n");
370 ohci
->ed_to_check
= ed
;
375 spin_unlock_irqrestore (&ohci
->lock
, flags
);
376 schedule_timeout_uninterruptible(1);
378 case ED_IDLE
: /* fully unlinked */
379 if (list_empty (&ed
->td_list
)) {
380 td_free (ohci
, ed
->dummy
);
384 /* else FALL THROUGH */
386 /* caller was supposed to have unlinked any requests;
387 * that's not our job. can't recover; must leak ed.
389 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
390 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
391 list_empty (&ed
->td_list
) ? "" : " (has tds)");
392 td_free (ohci
, ed
->dummy
);
396 spin_unlock_irqrestore (&ohci
->lock
, flags
);
399 static int ohci_get_frame (struct usb_hcd
*hcd
)
401 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
403 return ohci_frame_no(ohci
);
406 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
408 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
409 ohci
->hc_control
&= OHCI_CTRL_RWC
;
410 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
411 ohci
->rh_state
= OHCI_RH_HALTED
;
414 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
415 * other cases where the next software may expect clean state from the
416 * "firmware". this is bus-neutral, unlike shutdown() methods.
419 ohci_shutdown (struct usb_hcd
*hcd
)
421 struct ohci_hcd
*ohci
;
423 ohci
= hcd_to_ohci (hcd
);
424 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
426 /* Software reset, after which the controller goes into SUSPEND */
427 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
428 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
431 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
434 static int check_ed(struct ohci_hcd
*ohci
, struct ed
*ed
)
436 return (hc32_to_cpu(ohci
, ed
->hwINFO
) & ED_IN
) != 0
437 && (hc32_to_cpu(ohci
, ed
->hwHeadP
) & TD_MASK
)
438 == (hc32_to_cpu(ohci
, ed
->hwTailP
) & TD_MASK
)
439 && !list_empty(&ed
->td_list
);
442 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
443 * an interrupt TD but neglects to add it to the donelist. On systems with
444 * this chipset, we need to periodically check the state of the queues to look
445 * for such "lost" TDs.
447 static void unlink_watchdog_func(unsigned long _ohci
)
451 unsigned seen_count
= 0;
453 struct ed
**seen
= NULL
;
454 struct ohci_hcd
*ohci
= (struct ohci_hcd
*) _ohci
;
456 spin_lock_irqsave(&ohci
->lock
, flags
);
457 max
= ohci
->eds_scheduled
;
461 if (ohci
->ed_to_check
)
464 seen
= kcalloc(max
, sizeof *seen
, GFP_ATOMIC
);
468 for (i
= 0; i
< NUM_INTS
; i
++) {
469 struct ed
*ed
= ohci
->periodic
[i
];
474 /* scan this branch of the periodic schedule tree */
475 for (temp
= 0; temp
< seen_count
; temp
++) {
476 if (seen
[temp
] == ed
) {
477 /* we've checked it and what's after */
484 seen
[seen_count
++] = ed
;
485 if (!check_ed(ohci
, ed
)) {
490 /* HC's TD list is empty, but HCD sees at least one
491 * TD that's not been sent through the donelist.
493 ohci
->ed_to_check
= ed
;
496 /* The HC may wait until the next frame to report the
497 * TD as done through the donelist and INTR_WDH. (We
498 * just *assume* it's not a multi-TD interrupt URB;
499 * those could defer the IRQ more than one frame, using
500 * DI...) Check again after the next INTR_SF.
502 ohci_writel(ohci
, OHCI_INTR_SF
,
503 &ohci
->regs
->intrstatus
);
504 ohci_writel(ohci
, OHCI_INTR_SF
,
505 &ohci
->regs
->intrenable
);
507 /* flush those writes */
508 (void) ohci_readl(ohci
, &ohci
->regs
->control
);
515 if (ohci
->eds_scheduled
)
516 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
518 spin_unlock_irqrestore(&ohci
->lock
, flags
);
521 /*-------------------------------------------------------------------------*
523 *-------------------------------------------------------------------------*/
525 /* init memory, and kick BIOS/SMM off */
527 static int ohci_init (struct ohci_hcd
*ohci
)
530 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
532 if (distrust_firmware
)
533 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
535 ohci
->rh_state
= OHCI_RH_HALTED
;
536 ohci
->regs
= hcd
->regs
;
538 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
539 * was never needed for most non-PCI systems ... remove the code?
543 /* SMM owns the HC? not for long! */
544 if (!no_handshake
&& ohci_readl (ohci
,
545 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
548 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
550 /* this timeout is arbitrary. we make it long, so systems
551 * depending on usb keyboards may be usable even if the
552 * BIOS/SMM code seems pretty broken.
554 temp
= 500; /* arbitrary: five seconds */
556 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
557 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
558 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
561 ohci_err (ohci
, "USB HC takeover failed!"
562 " (BIOS/SMM bug)\n");
566 ohci_usb_reset (ohci
);
570 /* Disable HC interrupts */
571 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
573 /* flush the writes, and save key bits like RWC */
574 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
575 ohci
->hc_control
|= OHCI_CTRL_RWC
;
577 /* Read the number of ports unless overridden */
578 if (ohci
->num_ports
== 0)
579 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
584 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
585 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
589 if ((ret
= ohci_mem_init (ohci
)) < 0)
592 create_debug_files (ohci
);
598 /*-------------------------------------------------------------------------*/
600 /* Start an OHCI controller, set the BUS operational
601 * resets USB and controller
604 static int ohci_run (struct ohci_hcd
*ohci
)
607 int first
= ohci
->fminterval
== 0;
608 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
610 ohci
->rh_state
= OHCI_RH_HALTED
;
612 /* boot firmware should have set this up (5.1.1.3.1) */
615 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
616 ohci
->fminterval
= val
& 0x3fff;
617 if (ohci
->fminterval
!= FI
)
618 ohci_dbg (ohci
, "fminterval delta %d\n",
619 ohci
->fminterval
- FI
);
620 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
621 /* also: power/overcurrent flags in roothub.a */
624 /* Reset USB nearly "by the book". RemoteWakeupConnected has
625 * to be checked in case boot firmware (BIOS/SMM/...) has set up
626 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
627 * If the bus glue detected wakeup capability then it should
628 * already be enabled; if so we'll just enable it again.
630 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
631 device_set_wakeup_capable(hcd
->self
.controller
, 1);
633 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
637 case OHCI_USB_SUSPEND
:
638 case OHCI_USB_RESUME
:
639 ohci
->hc_control
&= OHCI_CTRL_RWC
;
640 ohci
->hc_control
|= OHCI_USB_RESUME
;
641 val
= 10 /* msec wait */;
643 // case OHCI_USB_RESET:
645 ohci
->hc_control
&= OHCI_CTRL_RWC
;
646 ohci
->hc_control
|= OHCI_USB_RESET
;
647 val
= 50 /* msec wait */;
650 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
652 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
655 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
657 /* 2msec timelimit here means no irqs/preempt */
658 spin_lock_irq (&ohci
->lock
);
661 /* HC Reset requires max 10 us delay */
662 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
663 val
= 30; /* ... allow extra time */
664 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
666 spin_unlock_irq (&ohci
->lock
);
667 ohci_err (ohci
, "USB HC reset timed out!\n");
673 /* now we're in the SUSPEND state ... must go OPERATIONAL
674 * within 2msec else HC enters RESUME
676 * ... but some hardware won't init fmInterval "by the book"
677 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
678 * this if we write fmInterval after we're OPERATIONAL.
679 * Unclear about ALi, ServerWorks, and others ... this could
680 * easily be a longstanding bug in chip init on Linux.
682 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
683 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
684 // flush those writes
685 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
688 /* Tell the controller where the control and bulk lists are
689 * The lists are empty now. */
690 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
691 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
693 /* a reset clears this */
694 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
696 periodic_reinit (ohci
);
698 /* some OHCI implementations are finicky about how they init.
699 * bogus values here mean not even enumeration could work.
701 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
702 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
703 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
704 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
705 ohci_dbg (ohci
, "enabling initreset quirk\n");
708 spin_unlock_irq (&ohci
->lock
);
709 ohci_err (ohci
, "init err (%08x %04x)\n",
710 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
711 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
715 /* use rhsc irqs after khubd is fully initialized */
716 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
717 hcd
->uses_new_polling
= 1;
719 /* start controller operations */
720 ohci
->hc_control
&= OHCI_CTRL_RWC
;
721 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
722 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
723 ohci
->rh_state
= OHCI_RH_RUNNING
;
725 /* wake on ConnectStatusChange, matching external hubs */
726 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
728 /* Choose the interrupts we care about now, others later on demand */
729 mask
= OHCI_INTR_INIT
;
730 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
731 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
733 /* handle root hub init quirks ... */
734 val
= roothub_a (ohci
);
735 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
736 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
737 /* NSC 87560 and maybe others */
739 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
740 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
741 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
742 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
743 /* hub power always on; required for AMD-756 and some
744 * Mac platforms. ganged overcurrent reporting, if any.
747 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
749 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
750 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
751 &ohci
->regs
->roothub
.b
);
752 // flush those writes
753 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
755 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
756 spin_unlock_irq (&ohci
->lock
);
758 // POTPGT delay is bits 24-31, in 2 ms units.
759 mdelay ((val
>> 23) & 0x1fe);
761 if (quirk_zfmicro(ohci
)) {
762 /* Create timer to watch for bad queue state on ZF Micro */
763 setup_timer(&ohci
->unlink_watchdog
, unlink_watchdog_func
,
764 (unsigned long) ohci
);
766 ohci
->eds_scheduled
= 0;
767 ohci
->ed_to_check
= NULL
;
775 /*-------------------------------------------------------------------------*/
777 /* an interrupt happens */
779 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
781 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
782 struct ohci_regs __iomem
*regs
= ohci
->regs
;
785 /* Read interrupt status (and flush pending writes). We ignore the
786 * optimization of checking the LSB of hcca->done_head; it doesn't
787 * work on all systems (edge triggering for OHCI can be a factor).
789 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
791 /* Check for an all 1's result which is a typical consequence
792 * of dead, unclocked, or unplugged (CardBus...) devices
794 if (ints
== ~(u32
)0) {
795 ohci
->rh_state
= OHCI_RH_HALTED
;
796 ohci_dbg (ohci
, "device removed!\n");
801 /* We only care about interrupts that are enabled */
802 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
804 /* interrupt for some other device? */
805 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
808 if (ints
& OHCI_INTR_UE
) {
809 // e.g. due to PCI Master/Target Abort
810 if (quirk_nec(ohci
)) {
811 /* Workaround for a silicon bug in some NEC chips used
812 * in Apple's PowerBooks. Adapted from Darwin code.
814 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
816 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
818 schedule_work (&ohci
->nec_work
);
820 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
821 ohci
->rh_state
= OHCI_RH_HALTED
;
826 ohci_usb_reset (ohci
);
829 if (ints
& OHCI_INTR_RHSC
) {
830 ohci_vdbg(ohci
, "rhsc\n");
831 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
832 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
835 /* NOTE: Vendors didn't always make the same implementation
836 * choices for RHSC. Many followed the spec; RHSC triggers
837 * on an edge, like setting and maybe clearing a port status
838 * change bit. With others it's level-triggered, active
839 * until khubd clears all the port status change bits. We'll
840 * always disable it here and rely on polling until khubd
843 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
844 usb_hcd_poll_rh_status(hcd
);
847 /* For connect and disconnect events, we expect the controller
848 * to turn on RHSC along with RD. But for remote wakeup events
849 * this might not happen.
851 else if (ints
& OHCI_INTR_RD
) {
852 ohci_vdbg(ohci
, "resume detect\n");
853 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
854 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
855 if (ohci
->autostop
) {
856 spin_lock (&ohci
->lock
);
857 ohci_rh_resume (ohci
);
858 spin_unlock (&ohci
->lock
);
860 usb_hcd_resume_root_hub(hcd
);
863 if (ints
& OHCI_INTR_WDH
) {
864 spin_lock (&ohci
->lock
);
866 spin_unlock (&ohci
->lock
);
869 if (quirk_zfmicro(ohci
) && (ints
& OHCI_INTR_SF
)) {
870 spin_lock(&ohci
->lock
);
871 if (ohci
->ed_to_check
) {
872 struct ed
*ed
= ohci
->ed_to_check
;
874 if (check_ed(ohci
, ed
)) {
875 /* HC thinks the TD list is empty; HCD knows
876 * at least one TD is outstanding
878 if (--ohci
->zf_delay
== 0) {
879 struct td
*td
= list_entry(
883 "Reclaiming orphan TD %p\n",
885 takeback_td(ohci
, td
);
886 ohci
->ed_to_check
= NULL
;
889 ohci
->ed_to_check
= NULL
;
891 spin_unlock(&ohci
->lock
);
894 /* could track INTR_SO to reduce available PCI/... bandwidth */
896 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
897 * when there's still unlinking to be done (next frame).
899 spin_lock (&ohci
->lock
);
900 if (ohci
->ed_rm_list
)
901 finish_unlinks (ohci
, ohci_frame_no(ohci
));
902 if ((ints
& OHCI_INTR_SF
) != 0
904 && !ohci
->ed_to_check
905 && ohci
->rh_state
== OHCI_RH_RUNNING
)
906 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
907 spin_unlock (&ohci
->lock
);
909 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
910 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
911 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
912 // flush those writes
913 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
919 /*-------------------------------------------------------------------------*/
921 static void ohci_stop (struct usb_hcd
*hcd
)
923 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
928 flush_work(&ohci
->nec_work
);
930 ohci_usb_reset (ohci
);
931 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
932 free_irq(hcd
->irq
, hcd
);
935 if (quirk_zfmicro(ohci
))
936 del_timer(&ohci
->unlink_watchdog
);
937 if (quirk_amdiso(ohci
))
940 remove_debug_files (ohci
);
941 ohci_mem_cleanup (ohci
);
943 dma_free_coherent (hcd
->self
.controller
,
945 ohci
->hcca
, ohci
->hcca_dma
);
951 /*-------------------------------------------------------------------------*/
953 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
955 /* must not be called from interrupt context */
956 static int ohci_restart (struct ohci_hcd
*ohci
)
960 struct urb_priv
*priv
;
962 spin_lock_irq(&ohci
->lock
);
963 ohci
->rh_state
= OHCI_RH_HALTED
;
965 /* Recycle any "live" eds/tds (and urbs). */
966 if (!list_empty (&ohci
->pending
))
967 ohci_dbg(ohci
, "abort schedule...\n");
968 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
969 struct urb
*urb
= priv
->td
[0]->urb
;
970 struct ed
*ed
= priv
->ed
;
974 ed
->state
= ED_UNLINK
;
975 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
976 ed_deschedule (ohci
, ed
);
978 ed
->ed_next
= ohci
->ed_rm_list
;
980 ohci
->ed_rm_list
= ed
;
985 ohci_dbg(ohci
, "bogus ed %p state %d\n",
990 urb
->unlinked
= -ESHUTDOWN
;
992 finish_unlinks (ohci
, 0);
993 spin_unlock_irq(&ohci
->lock
);
995 /* paranoia, in case that didn't work: */
997 /* empty the interrupt branches */
998 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
999 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
1001 /* no EDs to remove */
1002 ohci
->ed_rm_list
= NULL
;
1004 /* empty control and bulk lists */
1005 ohci
->ed_controltail
= NULL
;
1006 ohci
->ed_bulktail
= NULL
;
1008 if ((temp
= ohci_run (ohci
)) < 0) {
1009 ohci_err (ohci
, "can't restart, %d\n", temp
);
1012 ohci_dbg(ohci
, "restart complete\n");
1020 static int __maybe_unused
ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1022 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1023 unsigned long flags
;
1025 /* Disable irq emission and mark HW unaccessible. Use
1026 * the spinlock to properly synchronize with possible pending
1027 * RH suspend or resume activity.
1029 spin_lock_irqsave (&ohci
->lock
, flags
);
1030 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1031 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1033 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1034 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1040 static int __maybe_unused
ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1042 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
1044 bool need_reinit
= false;
1046 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1048 /* Make sure resume from hibernation re-enumerates everything */
1050 ohci_usb_reset(ohci
);
1052 /* See if the controller is already running or has been reset */
1053 ohci
->hc_control
= ohci_readl(ohci
, &ohci
->regs
->control
);
1054 if (ohci
->hc_control
& (OHCI_CTRL_IR
| OHCI_SCHED_ENABLES
)) {
1057 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
1059 case OHCI_USB_RESET
:
1064 /* If needed, reinitialize and suspend the root hub */
1066 spin_lock_irq(&ohci
->lock
);
1067 ohci_rh_resume(ohci
);
1068 ohci_rh_suspend(ohci
, 0);
1069 spin_unlock_irq(&ohci
->lock
);
1072 /* Normally just turn on port power and enable interrupts */
1074 ohci_dbg(ohci
, "powerup ports\n");
1075 for (port
= 0; port
< ohci
->num_ports
; port
++)
1076 ohci_writel(ohci
, RH_PS_PPS
,
1077 &ohci
->regs
->roothub
.portstatus
[port
]);
1079 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrenable
);
1080 ohci_readl(ohci
, &ohci
->regs
->intrenable
);
1084 usb_hcd_resume_root_hub(hcd
);
1091 /*-------------------------------------------------------------------------*/
1093 MODULE_AUTHOR (DRIVER_AUTHOR
);
1094 MODULE_DESCRIPTION(DRIVER_DESC
);
1095 MODULE_LICENSE ("GPL");
1098 #include "ohci-pci.c"
1099 #define PCI_DRIVER ohci_pci_driver
1102 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1103 #include "ohci-sa1111.c"
1104 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1107 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1108 #include "ohci-s3c2410.c"
1109 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1112 #ifdef CONFIG_USB_OHCI_EXYNOS
1113 #include "ohci-exynos.c"
1114 #define EXYNOS_PLATFORM_DRIVER exynos_ohci_driver
1117 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1118 #include "ohci-omap.c"
1119 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1122 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1123 #include "ohci-omap3.c"
1124 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1127 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1128 #include "ohci-pxa27x.c"
1129 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1132 #ifdef CONFIG_ARCH_EP93XX
1133 #include "ohci-ep93xx.c"
1134 #define EP93XX_PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1137 #ifdef CONFIG_ARCH_AT91
1138 #include "ohci-at91.c"
1139 #define AT91_PLATFORM_DRIVER ohci_hcd_at91_driver
1142 #ifdef CONFIG_ARCH_LPC32XX
1143 #include "ohci-nxp.c"
1144 #define NXP_PLATFORM_DRIVER usb_hcd_nxp_driver
1147 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1148 #include "ohci-da8xx.c"
1149 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1152 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1153 #include "ohci-ppc-of.c"
1154 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1157 #ifdef CONFIG_PLAT_SPEAR
1158 #include "ohci-spear.c"
1159 #define SPEAR_PLATFORM_DRIVER spear_ohci_hcd_driver
1162 #ifdef CONFIG_PPC_PS3
1163 #include "ohci-ps3.c"
1164 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1167 #ifdef CONFIG_MFD_SM501
1168 #include "ohci-sm501.c"
1169 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1172 #ifdef CONFIG_MFD_TC6393XB
1173 #include "ohci-tmio.c"
1174 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1177 #ifdef CONFIG_MACH_JZ4740
1178 #include "ohci-jz4740.c"
1179 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1182 #ifdef CONFIG_USB_OCTEON_OHCI
1183 #include "ohci-octeon.c"
1184 #define PLATFORM_DRIVER ohci_octeon_driver
1187 #ifdef CONFIG_TILE_USB
1188 #include "ohci-tilegx.c"
1189 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1192 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
1193 #include "ohci-platform.c"
1194 #define PLATFORM_DRIVER ohci_platform_driver
1197 #if !defined(PCI_DRIVER) && \
1198 !defined(PLATFORM_DRIVER) && \
1199 !defined(OMAP1_PLATFORM_DRIVER) && \
1200 !defined(OMAP3_PLATFORM_DRIVER) && \
1201 !defined(OF_PLATFORM_DRIVER) && \
1202 !defined(SA1111_DRIVER) && \
1203 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1204 !defined(SM501_OHCI_DRIVER) && \
1205 !defined(TMIO_OHCI_DRIVER) && \
1206 !defined(S3C2410_PLATFORM_DRIVER) && \
1207 !defined(EXYNOS_PLATFORM_DRIVER) && \
1208 !defined(EP93XX_PLATFORM_DRIVER) && \
1209 !defined(AT91_PLATFORM_DRIVER) && \
1210 !defined(NXP_PLATFORM_DRIVER) && \
1211 !defined(DAVINCI_PLATFORM_DRIVER) && \
1212 !defined(SPEAR_PLATFORM_DRIVER)
1213 #error "missing bus glue for ohci-hcd"
1216 static int __init
ohci_hcd_mod_init(void)
1223 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1224 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
1225 sizeof (struct ed
), sizeof (struct td
));
1226 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1229 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1230 if (!ohci_debug_root
) {
1236 #ifdef PS3_SYSTEM_BUS_DRIVER
1237 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1242 #ifdef PLATFORM_DRIVER
1243 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1245 goto error_platform
;
1248 #ifdef OMAP1_PLATFORM_DRIVER
1249 retval
= platform_driver_register(&OMAP1_PLATFORM_DRIVER
);
1251 goto error_omap1_platform
;
1254 #ifdef OMAP3_PLATFORM_DRIVER
1255 retval
= platform_driver_register(&OMAP3_PLATFORM_DRIVER
);
1257 goto error_omap3_platform
;
1260 #ifdef OF_PLATFORM_DRIVER
1261 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1263 goto error_of_platform
;
1266 #ifdef SA1111_DRIVER
1267 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1273 retval
= pci_register_driver(&PCI_DRIVER
);
1278 #ifdef SM501_OHCI_DRIVER
1279 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1284 #ifdef TMIO_OHCI_DRIVER
1285 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1290 #ifdef S3C2410_PLATFORM_DRIVER
1291 retval
= platform_driver_register(&S3C2410_PLATFORM_DRIVER
);
1296 #ifdef EXYNOS_PLATFORM_DRIVER
1297 retval
= platform_driver_register(&EXYNOS_PLATFORM_DRIVER
);
1302 #ifdef EP93XX_PLATFORM_DRIVER
1303 retval
= platform_driver_register(&EP93XX_PLATFORM_DRIVER
);
1308 #ifdef AT91_PLATFORM_DRIVER
1309 retval
= platform_driver_register(&AT91_PLATFORM_DRIVER
);
1314 #ifdef NXP_PLATFORM_DRIVER
1315 retval
= platform_driver_register(&NXP_PLATFORM_DRIVER
);
1320 #ifdef DAVINCI_PLATFORM_DRIVER
1321 retval
= platform_driver_register(&DAVINCI_PLATFORM_DRIVER
);
1326 #ifdef SPEAR_PLATFORM_DRIVER
1327 retval
= platform_driver_register(&SPEAR_PLATFORM_DRIVER
);
1335 #ifdef SPEAR_PLATFORM_DRIVER
1336 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER
);
1339 #ifdef DAVINCI_PLATFORM_DRIVER
1340 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER
);
1343 #ifdef NXP_PLATFORM_DRIVER
1344 platform_driver_unregister(&NXP_PLATFORM_DRIVER
);
1347 #ifdef AT91_PLATFORM_DRIVER
1348 platform_driver_unregister(&AT91_PLATFORM_DRIVER
);
1351 #ifdef EP93XX_PLATFORM_DRIVER
1352 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER
);
1355 #ifdef EXYNOS_PLATFORM_DRIVER
1356 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER
);
1359 #ifdef S3C2410_PLATFORM_DRIVER
1360 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER
);
1363 #ifdef TMIO_OHCI_DRIVER
1364 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1367 #ifdef SM501_OHCI_DRIVER
1368 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1372 pci_unregister_driver(&PCI_DRIVER
);
1375 #ifdef SA1111_DRIVER
1376 sa1111_driver_unregister(&SA1111_DRIVER
);
1379 #ifdef OF_PLATFORM_DRIVER
1380 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1383 #ifdef OMAP3_PLATFORM_DRIVER
1384 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1385 error_omap3_platform
:
1387 #ifdef OMAP1_PLATFORM_DRIVER
1388 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER
);
1389 error_omap1_platform
:
1391 #ifdef PLATFORM_DRIVER
1392 platform_driver_unregister(&PLATFORM_DRIVER
);
1395 #ifdef PS3_SYSTEM_BUS_DRIVER
1396 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1400 debugfs_remove(ohci_debug_root
);
1401 ohci_debug_root
= NULL
;
1405 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1408 module_init(ohci_hcd_mod_init
);
1410 static void __exit
ohci_hcd_mod_exit(void)
1412 #ifdef SPEAR_PLATFORM_DRIVER
1413 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER
);
1415 #ifdef DAVINCI_PLATFORM_DRIVER
1416 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER
);
1418 #ifdef NXP_PLATFORM_DRIVER
1419 platform_driver_unregister(&NXP_PLATFORM_DRIVER
);
1421 #ifdef AT91_PLATFORM_DRIVER
1422 platform_driver_unregister(&AT91_PLATFORM_DRIVER
);
1424 #ifdef EP93XX_PLATFORM_DRIVER
1425 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER
);
1427 #ifdef EXYNOS_PLATFORM_DRIVER
1428 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER
);
1430 #ifdef S3C2410_PLATFORM_DRIVER
1431 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER
);
1433 #ifdef TMIO_OHCI_DRIVER
1434 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1436 #ifdef SM501_OHCI_DRIVER
1437 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1440 pci_unregister_driver(&PCI_DRIVER
);
1442 #ifdef SA1111_DRIVER
1443 sa1111_driver_unregister(&SA1111_DRIVER
);
1445 #ifdef OF_PLATFORM_DRIVER
1446 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1448 #ifdef OMAP3_PLATFORM_DRIVER
1449 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER
);
1451 #ifdef OMAP1_PLATFORM_DRIVER
1452 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER
);
1454 #ifdef PLATFORM_DRIVER
1455 platform_driver_unregister(&PLATFORM_DRIVER
);
1457 #ifdef PS3_SYSTEM_BUS_DRIVER
1458 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1461 debugfs_remove(ohci_debug_root
);
1463 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1465 module_exit(ohci_hcd_mod_exit
);