2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32
;
34 typedef __u16 __bitwise __hc16
;
40 /* statistics can be kept for tuning/monitoring */
50 unsigned long lost_iaa
;
52 /* termination of urbs from core */
53 unsigned long complete
;
57 /* ehci_hcd->lock guards shared data against other CPUs:
58 * ehci_hcd: async, unlink, periodic (and shadow), ...
59 * usb_host_endpoint: hcpriv
60 * ehci_qh: qh_next, qtd_list
63 * Also, hold this lock when talking to HC registers or
64 * when updating hw_* fields in shared qh/qtd/... structures.
67 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
70 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
71 * controller may be doing DMA. Lower values mean there's no DMA.
81 * Timer events, ordered by increasing delay length.
82 * Always update event_delays_ns[] and event_handlers[] (defined in
83 * ehci-timer.c) in parallel with this list.
85 enum ehci_hrtimer_event
{
86 EHCI_HRTIMER_POLL_ASS
, /* Poll for async schedule off */
87 EHCI_HRTIMER_POLL_PSS
, /* Poll for periodic schedule off */
88 EHCI_HRTIMER_POLL_DEAD
, /* Wait for dead controller to stop */
89 EHCI_HRTIMER_UNLINK_INTR
, /* Wait for interrupt QH unlink */
90 EHCI_HRTIMER_FREE_ITDS
, /* Wait for unused iTDs and siTDs */
91 EHCI_HRTIMER_ASYNC_UNLINKS
, /* Unlink empty async QHs */
92 EHCI_HRTIMER_IAA_WATCHDOG
, /* Handle lost IAA interrupts */
93 EHCI_HRTIMER_DISABLE_PERIODIC
, /* Wait to disable periodic sched */
94 EHCI_HRTIMER_DISABLE_ASYNC
, /* Wait to disable async sched */
95 EHCI_HRTIMER_IO_WATCHDOG
, /* Check for missing IRQs */
96 EHCI_HRTIMER_NUM_EVENTS
/* Must come last */
98 #define EHCI_HRTIMER_NO_EVENT 99
100 struct ehci_hcd
{ /* one per controller */
102 enum ehci_hrtimer_event next_hrtimer_event
;
103 unsigned enabled_hrtimer_events
;
104 ktime_t hr_timeouts
[EHCI_HRTIMER_NUM_EVENTS
];
105 struct hrtimer hrtimer
;
111 /* glue to PCI and HCD framework */
112 struct ehci_caps __iomem
*caps
;
113 struct ehci_regs __iomem
*regs
;
114 struct ehci_dbg_port __iomem
*debug
;
116 __u32 hcs_params
; /* cached register copy */
118 enum ehci_rh_state rh_state
;
120 /* general schedule support */
123 bool intr_unlinking
:1;
124 bool iaa_in_progress
:1;
125 bool async_unlinking
:1;
127 struct ehci_qh
*qh_scan_next
;
129 /* async schedule support */
130 struct ehci_qh
*async
;
131 struct ehci_qh
*dummy
; /* For AMD quirk use */
132 struct list_head async_unlink
;
133 struct list_head async_idle
;
134 unsigned async_unlink_cycle
;
135 unsigned async_count
; /* async activity count */
137 /* periodic schedule support */
138 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
139 unsigned periodic_size
;
140 __hc32
*periodic
; /* hw periodic table */
141 dma_addr_t periodic_dma
;
142 struct list_head intr_qh_list
;
143 unsigned i_thresh
; /* uframes HC might cache */
145 union ehci_shadow
*pshadow
; /* mirror hw periodic table */
146 struct list_head intr_unlink
;
147 unsigned intr_unlink_cycle
;
148 unsigned now_frame
; /* frame from HC hardware */
149 unsigned last_iso_frame
; /* last frame scanned for iso */
150 unsigned intr_count
; /* intr activity count */
151 unsigned isoc_count
; /* isoc activity count */
152 unsigned periodic_count
; /* periodic activity count */
153 unsigned uframe_periodic_max
; /* max periodic time per uframe */
156 /* list of itds & sitds completed while now_frame was still active */
157 struct list_head cached_itd_list
;
158 struct ehci_itd
*last_itd_to_free
;
159 struct list_head cached_sitd_list
;
160 struct ehci_sitd
*last_sitd_to_free
;
162 /* per root hub port */
163 unsigned long reset_done
[EHCI_MAX_ROOT_PORTS
];
165 /* bit vectors (one bit per port) */
166 unsigned long bus_suspended
; /* which ports were
167 already suspended at the start of a bus suspend */
168 unsigned long companion_ports
; /* which ports are
169 dedicated to the companion controller */
170 unsigned long owned_ports
; /* which ports are
171 owned by the companion during a bus suspend */
172 unsigned long port_c_suspend
; /* which ports have
173 the change-suspend feature turned on */
174 unsigned long suspended_ports
; /* which ports are
176 unsigned long resuming_ports
; /* which ports have
179 /* per-HC memory pools (could be per-bus, but ...) */
180 struct dma_pool
*qh_pool
; /* qh per active urb */
181 struct dma_pool
*qtd_pool
; /* one or more per qh */
182 struct dma_pool
*itd_pool
; /* itd per iso urb */
183 struct dma_pool
*sitd_pool
; /* sitd per split iso urb */
185 unsigned random_frame
;
186 unsigned long next_statechange
;
187 ktime_t last_periodic_enable
;
191 unsigned no_selective_suspend
:1;
192 unsigned has_fsl_port_bug
:1; /* FreeScale */
193 unsigned big_endian_mmio
:1;
194 unsigned big_endian_desc
:1;
195 unsigned big_endian_capbase
:1;
196 unsigned has_amcc_usb23
:1;
197 unsigned need_io_watchdog
:1;
198 unsigned amd_pll_fix
:1;
199 unsigned use_dummy_qh
:1; /* AMD Frame List table quirk*/
200 unsigned has_synopsys_hc_bug
:1; /* Synopsys HC */
201 unsigned frame_index_bug
:1; /* MosChip (AKA NetMos) */
202 unsigned need_oc_pp_cycle
:1; /* MPC834X port power */
203 unsigned imx28_write_fix
:1; /* For Freescale i.MX28 */
205 /* required for usb32 quirk */
206 #define OHCI_CTRL_HCFS (3 << 6)
207 #define OHCI_USB_OPER (2 << 6)
208 #define OHCI_USB_SUSPEND (3 << 6)
210 #define OHCI_HCCTRL_OFFSET 0x4
211 #define OHCI_HCCTRL_LEN 0x4
212 __hc32
*ohci_hcctrl_reg
;
213 unsigned has_hostpc
:1;
214 unsigned has_ppcd
:1; /* support per-port change bits */
215 u8 sbrn
; /* packed release number */
219 struct ehci_stats stats
;
220 # define COUNT(x) do { (x)++; } while (0)
222 # define COUNT(x) do {} while (0)
227 struct dentry
*debug_dir
;
230 /* platform-specific data -- must come last */
231 unsigned long priv
[0] __aligned(sizeof(s64
));
234 /* convert between an HCD pointer and the corresponding EHCI_HCD */
235 static inline struct ehci_hcd
*hcd_to_ehci (struct usb_hcd
*hcd
)
237 return (struct ehci_hcd
*) (hcd
->hcd_priv
);
239 static inline struct usb_hcd
*ehci_to_hcd (struct ehci_hcd
*ehci
)
241 return container_of ((void *) ehci
, struct usb_hcd
, hcd_priv
);
244 /*-------------------------------------------------------------------------*/
246 #include <linux/usb/ehci_def.h>
248 /*-------------------------------------------------------------------------*/
250 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
253 * EHCI Specification 0.95 Section 3.5
254 * QTD: describe data transfer components (buffer, direction, ...)
255 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
257 * These are associated only with "QH" (Queue Head) structures,
258 * used with control, bulk, and interrupt transfers.
261 /* first part defined by EHCI spec */
262 __hc32 hw_next
; /* see EHCI 3.5.1 */
263 __hc32 hw_alt_next
; /* see EHCI 3.5.2 */
264 __hc32 hw_token
; /* see EHCI 3.5.3 */
265 #define QTD_TOGGLE (1 << 31) /* data toggle */
266 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
267 #define QTD_IOC (1 << 15) /* interrupt on complete */
268 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
269 #define QTD_PID(tok) (((tok)>>8) & 0x3)
270 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
271 #define QTD_STS_HALT (1 << 6) /* halted on error */
272 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
273 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
274 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
275 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
276 #define QTD_STS_STS (1 << 1) /* split transaction state */
277 #define QTD_STS_PING (1 << 0) /* issue PING? */
279 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
280 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
281 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
283 __hc32 hw_buf
[5]; /* see EHCI 3.5.4 */
284 __hc32 hw_buf_hi
[5]; /* Appendix B */
286 /* the rest is HCD-private */
287 dma_addr_t qtd_dma
; /* qtd address */
288 struct list_head qtd_list
; /* sw qtd list */
289 struct urb
*urb
; /* qtd's urb */
290 size_t length
; /* length of buffer */
291 } __attribute__ ((aligned (32)));
293 /* mask NakCnt+T in qh->hw_alt_next */
294 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
296 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
298 /*-------------------------------------------------------------------------*/
300 /* type tag from {qh,itd,sitd,fstn}->hw_next */
301 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
304 * Now the following defines are not converted using the
305 * cpu_to_le32() macro anymore, since we have to support
306 * "dynamic" switching between be and le support, so that the driver
307 * can be used on one system with SoC EHCI controller using big-endian
308 * descriptors as well as a normal little-endian PCI EHCI controller.
310 /* values for that type tag */
311 #define Q_TYPE_ITD (0 << 1)
312 #define Q_TYPE_QH (1 << 1)
313 #define Q_TYPE_SITD (2 << 1)
314 #define Q_TYPE_FSTN (3 << 1)
316 /* next async queue entry, or pointer to interrupt/periodic QH */
317 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
319 /* for periodic/async schedules and qtd lists, mark end of list */
320 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
323 * Entries in periodic shadow table are pointers to one of four kinds
324 * of data structure. That's dictated by the hardware; a type tag is
325 * encoded in the low bits of the hardware's periodic schedule. Use
326 * Q_NEXT_TYPE to get the tag.
328 * For entries in the async schedule, the type tag always says "qh".
331 struct ehci_qh
*qh
; /* Q_TYPE_QH */
332 struct ehci_itd
*itd
; /* Q_TYPE_ITD */
333 struct ehci_sitd
*sitd
; /* Q_TYPE_SITD */
334 struct ehci_fstn
*fstn
; /* Q_TYPE_FSTN */
335 __hc32
*hw_next
; /* (all types) */
339 /*-------------------------------------------------------------------------*/
342 * EHCI Specification 0.95 Section 3.6
343 * QH: describes control/bulk/interrupt endpoints
344 * See Fig 3-7 "Queue Head Structure Layout".
346 * These appear in both the async and (for interrupt) periodic schedules.
349 /* first part defined by EHCI spec */
351 __hc32 hw_next
; /* see EHCI 3.6.1 */
352 __hc32 hw_info1
; /* see EHCI 3.6.2 */
353 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
354 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
355 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
356 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
357 #define QH_LOW_SPEED (1 << 12)
358 #define QH_FULL_SPEED (0 << 12)
359 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
360 __hc32 hw_info2
; /* see EHCI 3.6.2 */
361 #define QH_SMASK 0x000000ff
362 #define QH_CMASK 0x0000ff00
363 #define QH_HUBADDR 0x007f0000
364 #define QH_HUBPORT 0x3f800000
365 #define QH_MULT 0xc0000000
366 __hc32 hw_current
; /* qtd list - see EHCI 3.6.4 */
368 /* qtd overlay (hardware parts of a struct ehci_qtd) */
373 __hc32 hw_buf_hi
[5];
374 } __attribute__ ((aligned(32)));
377 struct ehci_qh_hw
*hw
; /* Must come first */
378 /* the rest is HCD-private */
379 dma_addr_t qh_dma
; /* address of qh */
380 union ehci_shadow qh_next
; /* ptr to qh; or periodic */
381 struct list_head qtd_list
; /* sw qtd list */
382 struct list_head intr_node
; /* list of intr QHs */
383 struct ehci_qtd
*dummy
;
384 struct list_head unlink_node
;
386 unsigned unlink_cycle
;
389 #define QH_STATE_LINKED 1 /* HC sees this */
390 #define QH_STATE_UNLINK 2 /* HC may still see this */
391 #define QH_STATE_IDLE 3 /* HC doesn't see this */
392 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
393 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
395 u8 xacterrs
; /* XactErr retry counter */
396 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
398 /* periodic schedule info */
399 u8 usecs
; /* intr bandwidth */
400 u8 gap_uf
; /* uframes split/csplit gap */
401 u8 c_usecs
; /* ... split completion bw */
402 u16 tt_usecs
; /* tt downstream bandwidth */
403 unsigned short period
; /* polling interval */
404 unsigned short start
; /* where polling starts */
405 #define NO_FRAME ((unsigned short)~0) /* pick new start */
407 struct usb_device
*dev
; /* access to TT */
408 unsigned is_out
:1; /* bulk or intr OUT */
409 unsigned clearing_tt
:1; /* Clear-TT-Buf in progress */
410 unsigned dequeue_during_giveback
:1;
411 unsigned exception
:1; /* got a fault, or an unlink
415 /*-------------------------------------------------------------------------*/
417 /* description of one iso transaction (up to 3 KB data if highspeed) */
418 struct ehci_iso_packet
{
419 /* These will be copied to iTD when scheduling */
420 u64 bufp
; /* itd->hw_bufp{,_hi}[pg] |= */
421 __hc32 transaction
; /* itd->hw_transaction[i] |= */
422 u8 cross
; /* buf crosses pages */
423 /* for full speed OUT splits */
427 /* temporary schedule data for packets from iso urbs (both speeds)
428 * each packet is one logical usb transaction to the device (not TT),
429 * beginning at stream->next_uframe
431 struct ehci_iso_sched
{
432 struct list_head td_list
;
434 struct ehci_iso_packet packet
[0];
438 * ehci_iso_stream - groups all (s)itds for this endpoint.
439 * acts like a qh would, if EHCI had them for ISO.
441 struct ehci_iso_stream
{
442 /* first field matches ehci_hq, but is NULL */
443 struct ehci_qh_hw
*hw
;
447 struct list_head td_list
; /* queued itds/sitds */
448 struct list_head free_list
; /* list of unused itds/sitds */
449 struct usb_device
*udev
;
450 struct usb_host_endpoint
*ep
;
452 /* output of (re)scheduling */
456 /* the rest is derived from the endpoint descriptor,
457 * trusting urb->interval == f(epdesc->bInterval) and
458 * including the extra info for hw_bufp[0..2]
467 /* This is used to initialize iTD's hw_bufp fields */
472 /* this is used to initialize sITD's tt info */
476 /*-------------------------------------------------------------------------*/
479 * EHCI Specification 0.95 Section 3.3
480 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
482 * Schedule records for high speed iso xfers
485 /* first part defined by EHCI spec */
486 __hc32 hw_next
; /* see EHCI 3.3.1 */
487 __hc32 hw_transaction
[8]; /* see EHCI 3.3.2 */
488 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
489 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
490 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
491 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
492 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
493 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
495 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
497 __hc32 hw_bufp
[7]; /* see EHCI 3.3.3 */
498 __hc32 hw_bufp_hi
[7]; /* Appendix B */
500 /* the rest is HCD-private */
501 dma_addr_t itd_dma
; /* for this itd */
502 union ehci_shadow itd_next
; /* ptr to periodic q entry */
505 struct ehci_iso_stream
*stream
; /* endpoint's queue */
506 struct list_head itd_list
; /* list of stream's itds */
508 /* any/all hw_transactions here may be used by that urb */
509 unsigned frame
; /* where scheduled */
511 unsigned index
[8]; /* in urb->iso_frame_desc */
512 } __attribute__ ((aligned (32)));
514 /*-------------------------------------------------------------------------*/
517 * EHCI Specification 0.95 Section 3.4
518 * siTD, aka split-transaction isochronous Transfer Descriptor
519 * ... describe full speed iso xfers through TT in hubs
520 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
523 /* first part defined by EHCI spec */
525 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
526 __hc32 hw_fullspeed_ep
; /* EHCI table 3-9 */
527 __hc32 hw_uframe
; /* EHCI table 3-10 */
528 __hc32 hw_results
; /* EHCI table 3-11 */
529 #define SITD_IOC (1 << 31) /* interrupt on completion */
530 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
531 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
532 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
533 #define SITD_STS_ERR (1 << 6) /* error from TT */
534 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
535 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
536 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
537 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
538 #define SITD_STS_STS (1 << 1) /* split transaction state */
540 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
542 __hc32 hw_buf
[2]; /* EHCI table 3-12 */
543 __hc32 hw_backpointer
; /* EHCI table 3-13 */
544 __hc32 hw_buf_hi
[2]; /* Appendix B */
546 /* the rest is HCD-private */
548 union ehci_shadow sitd_next
; /* ptr to periodic q entry */
551 struct ehci_iso_stream
*stream
; /* endpoint's queue */
552 struct list_head sitd_list
; /* list of stream's sitds */
555 } __attribute__ ((aligned (32)));
557 /*-------------------------------------------------------------------------*/
560 * EHCI Specification 0.96 Section 3.7
561 * Periodic Frame Span Traversal Node (FSTN)
563 * Manages split interrupt transactions (using TT) that span frame boundaries
564 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
565 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
566 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
569 __hc32 hw_next
; /* any periodic q entry */
570 __hc32 hw_prev
; /* qh or EHCI_LIST_END */
572 /* the rest is HCD-private */
574 union ehci_shadow fstn_next
; /* ptr to periodic q entry */
575 } __attribute__ ((aligned (32)));
577 /*-------------------------------------------------------------------------*/
579 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
581 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
582 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
584 #define ehci_prepare_ports_for_controller_resume(ehci) \
585 ehci_adjust_port_wakeup_flags(ehci, false, false);
587 /*-------------------------------------------------------------------------*/
589 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
592 * Some EHCI controllers have a Transaction Translator built into the
593 * root hub. This is a non-standard feature. Each controller will need
594 * to add code to the following inline functions, and call them as
595 * needed (mostly in root hub code).
598 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
600 /* Returns the speed of a device attached to a port on the root hub. */
601 static inline unsigned int
602 ehci_port_speed(struct ehci_hcd
*ehci
, unsigned int portsc
)
604 if (ehci_is_TDI(ehci
)) {
605 switch ((portsc
>> (ehci
->has_hostpc
? 25 : 26)) & 3) {
609 return USB_PORT_STAT_LOW_SPEED
;
612 return USB_PORT_STAT_HIGH_SPEED
;
615 return USB_PORT_STAT_HIGH_SPEED
;
620 #define ehci_is_TDI(e) (0)
622 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
625 /*-------------------------------------------------------------------------*/
627 #ifdef CONFIG_PPC_83xx
628 /* Some Freescale processors have an erratum in which the TT
629 * port number in the queue head was 0..N-1 instead of 1..N.
631 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
633 #define ehci_has_fsl_portno_bug(e) (0)
637 * While most USB host controllers implement their registers in
638 * little-endian format, a minority (celleb companion chip) implement
639 * them in big endian format.
641 * This attempts to support either format at compile time without a
642 * runtime penalty, or both formats with the additional overhead
643 * of checking a flag bit.
645 * ehci_big_endian_capbase is a special quirk for controllers that
646 * implement the HC capability registers as separate registers and not
647 * as fields of a 32-bit register.
650 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
651 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
652 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
654 #define ehci_big_endian_mmio(e) 0
655 #define ehci_big_endian_capbase(e) 0
659 * Big-endian read/write functions are arch-specific.
660 * Other arches can be added if/when they're needed.
662 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
663 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
664 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
667 static inline unsigned int ehci_readl(const struct ehci_hcd
*ehci
,
668 __u32 __iomem
* regs
)
670 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
671 return ehci_big_endian_mmio(ehci
) ?
679 #ifdef CONFIG_SOC_IMX28
680 static inline void imx28_ehci_writel(const unsigned int val
,
681 volatile __u32 __iomem
*addr
)
683 __asm__ ("swp %0, %0, [%1]" : : "r"(val
), "r"(addr
));
686 static inline void imx28_ehci_writel(const unsigned int val
,
687 volatile __u32 __iomem
*addr
)
691 static inline void ehci_writel(const struct ehci_hcd
*ehci
,
692 const unsigned int val
, __u32 __iomem
*regs
)
694 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
695 ehci_big_endian_mmio(ehci
) ?
696 writel_be(val
, regs
) :
699 if (ehci
->imx28_write_fix
)
700 imx28_ehci_writel(val
, regs
);
707 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
708 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
709 * Other common bits are dependent on has_amcc_usb23 quirk flag.
712 static inline void set_ohci_hcfs(struct ehci_hcd
*ehci
, int operational
)
716 hc_control
= (readl_be(ehci
->ohci_hcctrl_reg
) & ~OHCI_CTRL_HCFS
);
718 hc_control
|= OHCI_USB_OPER
;
720 hc_control
|= OHCI_USB_SUSPEND
;
722 writel_be(hc_control
, ehci
->ohci_hcctrl_reg
);
723 (void) readl_be(ehci
->ohci_hcctrl_reg
);
726 static inline void set_ohci_hcfs(struct ehci_hcd
*ehci
, int operational
)
730 /*-------------------------------------------------------------------------*/
733 * The AMCC 440EPx not only implements its EHCI registers in big-endian
734 * format, but also its DMA data structures (descriptors).
736 * EHCI controllers accessed through PCI work normally (little-endian
737 * everywhere), so we won't bother supporting a BE-only mode for now.
739 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
740 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
743 static inline __hc32
cpu_to_hc32 (const struct ehci_hcd
*ehci
, const u32 x
)
745 return ehci_big_endian_desc(ehci
)
746 ? (__force __hc32
)cpu_to_be32(x
)
747 : (__force __hc32
)cpu_to_le32(x
);
751 static inline u32
hc32_to_cpu (const struct ehci_hcd
*ehci
, const __hc32 x
)
753 return ehci_big_endian_desc(ehci
)
754 ? be32_to_cpu((__force __be32
)x
)
755 : le32_to_cpu((__force __le32
)x
);
758 static inline u32
hc32_to_cpup (const struct ehci_hcd
*ehci
, const __hc32
*x
)
760 return ehci_big_endian_desc(ehci
)
761 ? be32_to_cpup((__force __be32
*)x
)
762 : le32_to_cpup((__force __le32
*)x
);
768 static inline __hc32
cpu_to_hc32 (const struct ehci_hcd
*ehci
, const u32 x
)
770 return cpu_to_le32(x
);
774 static inline u32
hc32_to_cpu (const struct ehci_hcd
*ehci
, const __hc32 x
)
776 return le32_to_cpu(x
);
779 static inline u32
hc32_to_cpup (const struct ehci_hcd
*ehci
, const __hc32
*x
)
781 return le32_to_cpup(x
);
786 /*-------------------------------------------------------------------------*/
788 #define ehci_dbg(ehci, fmt, args...) \
789 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
790 #define ehci_err(ehci, fmt, args...) \
791 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
792 #define ehci_info(ehci, fmt, args...) \
793 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
794 #define ehci_warn(ehci, fmt, args...) \
795 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
798 # define ehci_vdbg ehci_dbg
800 static inline void ehci_vdbg(struct ehci_hcd
*ehci
, ...) {}
804 #define STUB_DEBUG_FILES
807 /*-------------------------------------------------------------------------*/
809 /* Declarations of things exported for use by ehci platform drivers */
811 struct ehci_driver_overrides
{
812 size_t extra_priv_size
;
813 int (*reset
)(struct usb_hcd
*hcd
);
816 extern void ehci_init_driver(struct hc_driver
*drv
,
817 const struct ehci_driver_overrides
*over
);
818 extern int ehci_setup(struct usb_hcd
*hcd
);
821 extern int ehci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
);
822 extern int ehci_resume(struct usb_hcd
*hcd
, bool hibernated
);
823 #endif /* CONFIG_PM */
825 #endif /* __LINUX_EHCI_HCD_H */