2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32
;
34 typedef __u16 __bitwise __hc16
;
40 /* statistics can be kept for tuning/monitoring */
45 unsigned long reclaim
;
46 unsigned long lost_iaa
;
48 /* termination of urbs from core */
49 unsigned long complete
;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
65 struct ehci_hcd
{ /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem
*caps
;
68 struct ehci_regs __iomem
*regs
;
69 struct ehci_dbg_port __iomem
*debug
;
71 __u32 hcs_params
; /* cached register copy */
74 /* async schedule support */
75 struct ehci_qh
*async
;
76 struct ehci_qh
*reclaim
;
77 unsigned scanning
: 1;
79 /* periodic schedule support */
80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
81 unsigned periodic_size
;
82 __hc32
*periodic
; /* hw periodic table */
83 dma_addr_t periodic_dma
;
84 unsigned i_thresh
; /* uframes HC might cache */
86 union ehci_shadow
*pshadow
; /* mirror hw periodic table */
87 int next_uframe
; /* scan periodic, start here */
88 unsigned periodic_sched
; /* periodic activity count */
90 /* list of itds completed while clock_frame was still active */
91 struct list_head cached_itd_list
;
94 /* per root hub port */
95 unsigned long reset_done
[EHCI_MAX_ROOT_PORTS
];
97 /* bit vectors (one bit per port) */
98 unsigned long bus_suspended
; /* which ports were
99 already suspended at the start of a bus suspend */
100 unsigned long companion_ports
; /* which ports are
101 dedicated to the companion controller */
102 unsigned long owned_ports
; /* which ports are
103 owned by the companion during a bus suspend */
104 unsigned long port_c_suspend
; /* which ports have
105 the change-suspend feature turned on */
106 unsigned long suspended_ports
; /* which ports are
109 /* per-HC memory pools (could be per-bus, but ...) */
110 struct dma_pool
*qh_pool
; /* qh per active urb */
111 struct dma_pool
*qtd_pool
; /* one or more per qh */
112 struct dma_pool
*itd_pool
; /* itd per iso urb */
113 struct dma_pool
*sitd_pool
; /* sitd per split iso urb */
115 struct timer_list iaa_watchdog
;
116 struct timer_list watchdog
;
117 unsigned long actions
;
119 unsigned random_frame
;
120 unsigned long next_statechange
;
121 ktime_t last_periodic_enable
;
125 unsigned no_selective_suspend
:1;
126 unsigned has_fsl_port_bug
:1; /* FreeScale */
127 unsigned big_endian_mmio
:1;
128 unsigned big_endian_desc
:1;
129 unsigned has_amcc_usb23
:1;
130 unsigned need_io_watchdog
:1;
131 unsigned broken_periodic
:1;
133 /* required for usb32 quirk */
134 #define OHCI_CTRL_HCFS (3 << 6)
135 #define OHCI_USB_OPER (2 << 6)
136 #define OHCI_USB_SUSPEND (3 << 6)
138 #define OHCI_HCCTRL_OFFSET 0x4
139 #define OHCI_HCCTRL_LEN 0x4
140 __hc32
*ohci_hcctrl_reg
;
141 unsigned has_hostpc
:1;
143 u8 sbrn
; /* packed release number */
147 struct ehci_stats stats
;
148 # define COUNT(x) do { (x)++; } while (0)
150 # define COUNT(x) do {} while (0)
155 struct dentry
*debug_dir
;
156 struct dentry
*debug_async
;
157 struct dentry
*debug_periodic
;
158 struct dentry
*debug_registers
;
162 /* convert between an HCD pointer and the corresponding EHCI_HCD */
163 static inline struct ehci_hcd
*hcd_to_ehci (struct usb_hcd
*hcd
)
165 return (struct ehci_hcd
*) (hcd
->hcd_priv
);
167 static inline struct usb_hcd
*ehci_to_hcd (struct ehci_hcd
*ehci
)
169 return container_of ((void *) ehci
, struct usb_hcd
, hcd_priv
);
174 iaa_watchdog_start(struct ehci_hcd
*ehci
)
176 WARN_ON(timer_pending(&ehci
->iaa_watchdog
));
177 mod_timer(&ehci
->iaa_watchdog
,
178 jiffies
+ msecs_to_jiffies(EHCI_IAA_MSECS
));
181 static inline void iaa_watchdog_done(struct ehci_hcd
*ehci
)
183 del_timer(&ehci
->iaa_watchdog
);
186 enum ehci_timer_action
{
193 timer_action_done (struct ehci_hcd
*ehci
, enum ehci_timer_action action
)
195 clear_bit (action
, &ehci
->actions
);
198 static void free_cached_itd_list(struct ehci_hcd
*ehci
);
200 /*-------------------------------------------------------------------------*/
202 #include <linux/usb/ehci_def.h>
204 /*-------------------------------------------------------------------------*/
206 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
209 * EHCI Specification 0.95 Section 3.5
210 * QTD: describe data transfer components (buffer, direction, ...)
211 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
213 * These are associated only with "QH" (Queue Head) structures,
214 * used with control, bulk, and interrupt transfers.
217 /* first part defined by EHCI spec */
218 __hc32 hw_next
; /* see EHCI 3.5.1 */
219 __hc32 hw_alt_next
; /* see EHCI 3.5.2 */
220 __hc32 hw_token
; /* see EHCI 3.5.3 */
221 #define QTD_TOGGLE (1 << 31) /* data toggle */
222 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
223 #define QTD_IOC (1 << 15) /* interrupt on complete */
224 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
225 #define QTD_PID(tok) (((tok)>>8) & 0x3)
226 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
227 #define QTD_STS_HALT (1 << 6) /* halted on error */
228 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
229 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
230 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
231 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
232 #define QTD_STS_STS (1 << 1) /* split transaction state */
233 #define QTD_STS_PING (1 << 0) /* issue PING? */
235 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
236 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
237 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
239 __hc32 hw_buf
[5]; /* see EHCI 3.5.4 */
240 __hc32 hw_buf_hi
[5]; /* Appendix B */
242 /* the rest is HCD-private */
243 dma_addr_t qtd_dma
; /* qtd address */
244 struct list_head qtd_list
; /* sw qtd list */
245 struct urb
*urb
; /* qtd's urb */
246 size_t length
; /* length of buffer */
247 } __attribute__ ((aligned (32)));
249 /* mask NakCnt+T in qh->hw_alt_next */
250 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
252 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
254 /*-------------------------------------------------------------------------*/
256 /* type tag from {qh,itd,sitd,fstn}->hw_next */
257 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
260 * Now the following defines are not converted using the
261 * cpu_to_le32() macro anymore, since we have to support
262 * "dynamic" switching between be and le support, so that the driver
263 * can be used on one system with SoC EHCI controller using big-endian
264 * descriptors as well as a normal little-endian PCI EHCI controller.
266 /* values for that type tag */
267 #define Q_TYPE_ITD (0 << 1)
268 #define Q_TYPE_QH (1 << 1)
269 #define Q_TYPE_SITD (2 << 1)
270 #define Q_TYPE_FSTN (3 << 1)
272 /* next async queue entry, or pointer to interrupt/periodic QH */
273 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
275 /* for periodic/async schedules and qtd lists, mark end of list */
276 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
279 * Entries in periodic shadow table are pointers to one of four kinds
280 * of data structure. That's dictated by the hardware; a type tag is
281 * encoded in the low bits of the hardware's periodic schedule. Use
282 * Q_NEXT_TYPE to get the tag.
284 * For entries in the async schedule, the type tag always says "qh".
287 struct ehci_qh
*qh
; /* Q_TYPE_QH */
288 struct ehci_itd
*itd
; /* Q_TYPE_ITD */
289 struct ehci_sitd
*sitd
; /* Q_TYPE_SITD */
290 struct ehci_fstn
*fstn
; /* Q_TYPE_FSTN */
291 __hc32
*hw_next
; /* (all types) */
295 /*-------------------------------------------------------------------------*/
298 * EHCI Specification 0.95 Section 3.6
299 * QH: describes control/bulk/interrupt endpoints
300 * See Fig 3-7 "Queue Head Structure Layout".
302 * These appear in both the async and (for interrupt) periodic schedules.
305 /* first part defined by EHCI spec */
307 __hc32 hw_next
; /* see EHCI 3.6.1 */
308 __hc32 hw_info1
; /* see EHCI 3.6.2 */
309 #define QH_HEAD 0x00008000
310 __hc32 hw_info2
; /* see EHCI 3.6.2 */
311 #define QH_SMASK 0x000000ff
312 #define QH_CMASK 0x0000ff00
313 #define QH_HUBADDR 0x007f0000
314 #define QH_HUBPORT 0x3f800000
315 #define QH_MULT 0xc0000000
316 __hc32 hw_current
; /* qtd list - see EHCI 3.6.4 */
318 /* qtd overlay (hardware parts of a struct ehci_qtd) */
323 __hc32 hw_buf_hi
[5];
324 } __attribute__ ((aligned(32)));
327 struct ehci_qh_hw
*hw
;
328 /* the rest is HCD-private */
329 dma_addr_t qh_dma
; /* address of qh */
330 union ehci_shadow qh_next
; /* ptr to qh; or periodic */
331 struct list_head qtd_list
; /* sw qtd list */
332 struct ehci_qtd
*dummy
;
333 struct ehci_qh
*reclaim
; /* next to reclaim */
335 struct ehci_hcd
*ehci
;
338 * Do NOT use atomic operations for QH refcounting. On some CPUs
339 * (PPC7448 for example), atomic operations cannot be performed on
340 * memory that is cache-inhibited (i.e. being used for DMA).
341 * Spinlocks are used to protect all QH fields.
346 u8 needs_rescan
; /* Dequeue during giveback */
348 #define QH_STATE_LINKED 1 /* HC sees this */
349 #define QH_STATE_UNLINK 2 /* HC may still see this */
350 #define QH_STATE_IDLE 3 /* HC doesn't see this */
351 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
352 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
354 u8 xacterrs
; /* XactErr retry counter */
355 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
357 /* periodic schedule info */
358 u8 usecs
; /* intr bandwidth */
359 u8 gap_uf
; /* uframes split/csplit gap */
360 u8 c_usecs
; /* ... split completion bw */
361 u16 tt_usecs
; /* tt downstream bandwidth */
362 unsigned short period
; /* polling interval */
363 unsigned short start
; /* where polling starts */
364 #define NO_FRAME ((unsigned short)~0) /* pick new start */
366 struct usb_device
*dev
; /* access to TT */
367 unsigned clearing_tt
:1; /* Clear-TT-Buf in progress */
370 /*-------------------------------------------------------------------------*/
372 /* description of one iso transaction (up to 3 KB data if highspeed) */
373 struct ehci_iso_packet
{
374 /* These will be copied to iTD when scheduling */
375 u64 bufp
; /* itd->hw_bufp{,_hi}[pg] |= */
376 __hc32 transaction
; /* itd->hw_transaction[i] |= */
377 u8 cross
; /* buf crosses pages */
378 /* for full speed OUT splits */
382 /* temporary schedule data for packets from iso urbs (both speeds)
383 * each packet is one logical usb transaction to the device (not TT),
384 * beginning at stream->next_uframe
386 struct ehci_iso_sched
{
387 struct list_head td_list
;
389 struct ehci_iso_packet packet
[0];
393 * ehci_iso_stream - groups all (s)itds for this endpoint.
394 * acts like a qh would, if EHCI had them for ISO.
396 struct ehci_iso_stream
{
397 /* first field matches ehci_hq, but is NULL */
398 struct ehci_qh_hw
*hw
;
403 u16 depth
; /* depth in uframes */
404 struct list_head td_list
; /* queued itds/sitds */
405 struct list_head free_list
; /* list of unused itds/sitds */
406 struct usb_device
*udev
;
407 struct usb_host_endpoint
*ep
;
409 /* output of (re)scheduling */
410 unsigned long start
; /* jiffies */
411 unsigned long rescheduled
;
415 /* the rest is derived from the endpoint descriptor,
416 * trusting urb->interval == f(epdesc->bInterval) and
417 * including the extra info for hw_bufp[0..2]
426 /* This is used to initialize iTD's hw_bufp fields */
431 /* this is used to initialize sITD's tt info */
435 /*-------------------------------------------------------------------------*/
438 * EHCI Specification 0.95 Section 3.3
439 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
441 * Schedule records for high speed iso xfers
444 /* first part defined by EHCI spec */
445 __hc32 hw_next
; /* see EHCI 3.3.1 */
446 __hc32 hw_transaction
[8]; /* see EHCI 3.3.2 */
447 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
448 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
449 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
450 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
451 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
452 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
454 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
456 __hc32 hw_bufp
[7]; /* see EHCI 3.3.3 */
457 __hc32 hw_bufp_hi
[7]; /* Appendix B */
459 /* the rest is HCD-private */
460 dma_addr_t itd_dma
; /* for this itd */
461 union ehci_shadow itd_next
; /* ptr to periodic q entry */
464 struct ehci_iso_stream
*stream
; /* endpoint's queue */
465 struct list_head itd_list
; /* list of stream's itds */
467 /* any/all hw_transactions here may be used by that urb */
468 unsigned frame
; /* where scheduled */
470 unsigned index
[8]; /* in urb->iso_frame_desc */
471 } __attribute__ ((aligned (32)));
473 /*-------------------------------------------------------------------------*/
476 * EHCI Specification 0.95 Section 3.4
477 * siTD, aka split-transaction isochronous Transfer Descriptor
478 * ... describe full speed iso xfers through TT in hubs
479 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
482 /* first part defined by EHCI spec */
484 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
485 __hc32 hw_fullspeed_ep
; /* EHCI table 3-9 */
486 __hc32 hw_uframe
; /* EHCI table 3-10 */
487 __hc32 hw_results
; /* EHCI table 3-11 */
488 #define SITD_IOC (1 << 31) /* interrupt on completion */
489 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
490 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
491 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
492 #define SITD_STS_ERR (1 << 6) /* error from TT */
493 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
494 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
495 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
496 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
497 #define SITD_STS_STS (1 << 1) /* split transaction state */
499 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
501 __hc32 hw_buf
[2]; /* EHCI table 3-12 */
502 __hc32 hw_backpointer
; /* EHCI table 3-13 */
503 __hc32 hw_buf_hi
[2]; /* Appendix B */
505 /* the rest is HCD-private */
507 union ehci_shadow sitd_next
; /* ptr to periodic q entry */
510 struct ehci_iso_stream
*stream
; /* endpoint's queue */
511 struct list_head sitd_list
; /* list of stream's sitds */
514 } __attribute__ ((aligned (32)));
516 /*-------------------------------------------------------------------------*/
519 * EHCI Specification 0.96 Section 3.7
520 * Periodic Frame Span Traversal Node (FSTN)
522 * Manages split interrupt transactions (using TT) that span frame boundaries
523 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
524 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
525 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
528 __hc32 hw_next
; /* any periodic q entry */
529 __hc32 hw_prev
; /* qh or EHCI_LIST_END */
531 /* the rest is HCD-private */
533 union ehci_shadow fstn_next
; /* ptr to periodic q entry */
534 } __attribute__ ((aligned (32)));
536 /*-------------------------------------------------------------------------*/
538 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
541 * Some EHCI controllers have a Transaction Translator built into the
542 * root hub. This is a non-standard feature. Each controller will need
543 * to add code to the following inline functions, and call them as
544 * needed (mostly in root hub code).
547 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
549 /* Returns the speed of a device attached to a port on the root hub. */
550 static inline unsigned int
551 ehci_port_speed(struct ehci_hcd
*ehci
, unsigned int portsc
)
553 if (ehci_is_TDI(ehci
)) {
554 switch ((portsc
>> (ehci
->has_hostpc
? 25 : 26)) & 3) {
558 return (1<<USB_PORT_FEAT_LOWSPEED
);
561 return (1<<USB_PORT_FEAT_HIGHSPEED
);
564 return (1<<USB_PORT_FEAT_HIGHSPEED
);
569 #define ehci_is_TDI(e) (0)
571 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
574 /*-------------------------------------------------------------------------*/
576 #ifdef CONFIG_PPC_83xx
577 /* Some Freescale processors have an erratum in which the TT
578 * port number in the queue head was 0..N-1 instead of 1..N.
580 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
582 #define ehci_has_fsl_portno_bug(e) (0)
586 * While most USB host controllers implement their registers in
587 * little-endian format, a minority (celleb companion chip) implement
588 * them in big endian format.
590 * This attempts to support either format at compile time without a
591 * runtime penalty, or both formats with the additional overhead
592 * of checking a flag bit.
595 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
596 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
598 #define ehci_big_endian_mmio(e) 0
602 * Big-endian read/write functions are arch-specific.
603 * Other arches can be added if/when they're needed.
605 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
606 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
607 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
610 static inline unsigned int ehci_readl(const struct ehci_hcd
*ehci
,
611 __u32 __iomem
* regs
)
613 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
614 return ehci_big_endian_mmio(ehci
) ?
622 static inline void ehci_writel(const struct ehci_hcd
*ehci
,
623 const unsigned int val
, __u32 __iomem
*regs
)
625 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
626 ehci_big_endian_mmio(ehci
) ?
627 writel_be(val
, regs
) :
635 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
636 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
637 * Other common bits are dependant on has_amcc_usb23 quirk flag.
640 static inline void set_ohci_hcfs(struct ehci_hcd
*ehci
, int operational
)
644 hc_control
= (readl_be(ehci
->ohci_hcctrl_reg
) & ~OHCI_CTRL_HCFS
);
646 hc_control
|= OHCI_USB_OPER
;
648 hc_control
|= OHCI_USB_SUSPEND
;
650 writel_be(hc_control
, ehci
->ohci_hcctrl_reg
);
651 (void) readl_be(ehci
->ohci_hcctrl_reg
);
654 static inline void set_ohci_hcfs(struct ehci_hcd
*ehci
, int operational
)
658 /*-------------------------------------------------------------------------*/
661 * The AMCC 440EPx not only implements its EHCI registers in big-endian
662 * format, but also its DMA data structures (descriptors).
664 * EHCI controllers accessed through PCI work normally (little-endian
665 * everywhere), so we won't bother supporting a BE-only mode for now.
667 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
668 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
671 static inline __hc32
cpu_to_hc32 (const struct ehci_hcd
*ehci
, const u32 x
)
673 return ehci_big_endian_desc(ehci
)
674 ? (__force __hc32
)cpu_to_be32(x
)
675 : (__force __hc32
)cpu_to_le32(x
);
679 static inline u32
hc32_to_cpu (const struct ehci_hcd
*ehci
, const __hc32 x
)
681 return ehci_big_endian_desc(ehci
)
682 ? be32_to_cpu((__force __be32
)x
)
683 : le32_to_cpu((__force __le32
)x
);
686 static inline u32
hc32_to_cpup (const struct ehci_hcd
*ehci
, const __hc32
*x
)
688 return ehci_big_endian_desc(ehci
)
689 ? be32_to_cpup((__force __be32
*)x
)
690 : le32_to_cpup((__force __le32
*)x
);
696 static inline __hc32
cpu_to_hc32 (const struct ehci_hcd
*ehci
, const u32 x
)
698 return cpu_to_le32(x
);
702 static inline u32
hc32_to_cpu (const struct ehci_hcd
*ehci
, const __hc32 x
)
704 return le32_to_cpu(x
);
707 static inline u32
hc32_to_cpup (const struct ehci_hcd
*ehci
, const __hc32
*x
)
709 return le32_to_cpup(x
);
714 /*-------------------------------------------------------------------------*/
717 #define STUB_DEBUG_FILES
720 /*-------------------------------------------------------------------------*/
722 #endif /* __LINUX_EHCI_HCD_H */