drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/usb.h>
  25 #include <linux/usb/hcd.h>
  26
  27 #include "ehci.h"
  28 #include "pci-quirks.h"
  29
  30 #define DRIVER_DESC "EHCI PCI platform driver"
  31
  32 static const char hcd_name[] = "ehci-pci";
  33
  34 /* defined here to avoid adding to pci_ids.h for single instance use */
  35 #define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  36
  37 /*-------------------------------------------------------------------------*/
  38
  39 /* called after powerup, by probe or system-pm "wakeup" */
  40 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  41 {
  42         int                     retval;
  43
  44         /* we expect static quirk code to handle the "extended capabilities"
  45          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  46          */
  47
  48         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  49         retval = pci_set_mwi(pdev);
  50         if (!retval)
  51                 ehci_dbg(ehci, "MWI active\n");
  52
  53         return 0;
  54 }
  55
  56 /* called during probe() after chip reset completes */
  57 static int ehci_pci_setup(struct usb_hcd *hcd)
  58 {
  59         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  60         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  61         struct pci_dev          *p_smbus;
  62         u8                      rev;
  63         u32                     temp;
  64         int                     retval;
  65
  66         ehci->caps = hcd->regs;
  67
  68         /*
  69          * ehci_init() causes memory for DMA transfers to be
  70          * allocated.  Thus, any vendor-specific workarounds based on
  71          * limiting the type of memory used for DMA transfers must
  72          * happen before ehci_setup() is called.
  73          *
  74          * Most other workarounds can be done either before or after
  75          * init and reset; they are located here too.
  76          */
  77         switch (pdev->vendor) {
  78         case PCI_VENDOR_ID_TOSHIBA_2:
  79                 /* celleb's companion chip */
  80                 if (pdev->device == 0x01b5) {
  81 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  82                         ehci->big_endian_mmio = 1;
  83 #else
  84                         ehci_warn(ehci,
  85                                   "unsupported big endian Toshiba quirk\n");
  86 #endif
  87                 }
  88                 break;
  89         case PCI_VENDOR_ID_NVIDIA:
  90                 /* NVidia reports that certain chips don't handle
  91                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  92                  * data buffer, and periodic schedule are normal.)
  93                  */
  94                 switch (pdev->device) {
  95                 case 0x003c:    /* MCP04 */
  96                 case 0x005b:    /* CK804 */
  97                 case 0x00d8:    /* CK8 */
  98                 case 0x00e8:    /* CK8S */
  99                         if (pci_set_consistent_dma_mask(pdev,
 100                                                 DMA_BIT_MASK(31)) < 0)
 101                                 ehci_warn(ehci, "can't enable NVidia "
 102                                         "workaround for >2GB RAM\n");
 103                         break;
 104
 105                 /* Some NForce2 chips have problems with selective suspend;
 106                  * fixed in newer silicon.
 107                  */
 108                 case 0x0068:
 109                         if (pdev->revision < 0xa4)
 110                                 ehci->no_selective_suspend = 1;
 111                         break;
 112                 }
 113                 break;
 114         case PCI_VENDOR_ID_INTEL:
 115                 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
 116                         hcd->has_tt = 1;
 117                 break;
 118         case PCI_VENDOR_ID_TDI:
 119                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
 120                         hcd->has_tt = 1;
 121                 break;
 122         case PCI_VENDOR_ID_AMD:
 123                 /* AMD PLL quirk */
 124                 if (usb_amd_find_chipset_info())
 125                         ehci->amd_pll_fix = 1;
 126                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 127                 if (pdev->device == 0x7463) {
 128                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 129                         retval = -EIO;
 130                         goto done;
 131                 }
 132
 133                 /*
 134                  * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 135                  * read/write memory space which does not belong to it when
 136                  * there is NULL pointer with T-bit set to 1 in the frame list
 137                  * table. To avoid the issue, the frame list link pointer
 138                  * should always contain a valid pointer to a inactive qh.
 139                  */
 140                 if (pdev->device == 0x7808) {
 141                         ehci->use_dummy_qh = 1;
 142                         ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 143                 }
 144                 break;
 145         case PCI_VENDOR_ID_VIA:
 146                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 147                         u8 tmp;
 148
 149                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 150                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 151                          * that sleep time use the conventional 10 usec.
 152                          */
 153                         pci_read_config_byte(pdev, 0x4b, &tmp);
 154                         if (tmp & 0x20)
 155                                 break;
 156                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 157                 }
 158                 break;
 159         case PCI_VENDOR_ID_ATI:
 160                 /* AMD PLL quirk */
 161                 if (usb_amd_find_chipset_info())
 162                         ehci->amd_pll_fix = 1;
 163
 164                 /*
 165                  * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 166                  * read/write memory space which does not belong to it when
 167                  * there is NULL pointer with T-bit set to 1 in the frame list
 168                  * table. To avoid the issue, the frame list link pointer
 169                  * should always contain a valid pointer to a inactive qh.
 170                  */
 171                 if (pdev->device == 0x4396) {
 172                         ehci->use_dummy_qh = 1;
 173                         ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 174                 }
 175                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 176                  * which causes usb devices lose response in some cases.
 177                  */
 178                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 179                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 180                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 181                                                  NULL);
 182                         if (!p_smbus)
 183                                 break;
 184                         rev = p_smbus->revision;
 185                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 186                             || (rev == 0x3b)) {
 187                                 u8 tmp;
 188                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 189                                         "freeze workaround\n");
 190                                 pci_read_config_byte(pdev, 0x53, &tmp);
 191                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 192                         }
 193                         pci_dev_put(p_smbus);
 194                 }
 195                 break;
 196         case PCI_VENDOR_ID_NETMOS:
 197                 /* MosChip frame-index-register bug */
 198                 ehci_info(ehci, "applying MosChip frame-index workaround\n");
 199                 ehci->frame_index_bug = 1;
 200                 break;
 201         }
 202
 203         /* optional debug port, normally in the first BAR */
 204         temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
 205         if (temp) {
 206                 pci_read_config_dword(pdev, temp, &temp);
 207                 temp >>= 16;
 208                 if (((temp >> 13) & 7) == 1) {
 209                         u32 hcs_params = ehci_readl(ehci,
 210                                                     &ehci->caps->hcs_params);
 211
 212                         temp &= 0x1fff;
 213                         ehci->debug = hcd->regs + temp;
 214                         temp = ehci_readl(ehci, &ehci->debug->control);
 215                         ehci_info(ehci, "debug port %d%s\n",
 216                                   HCS_DEBUG_PORT(hcs_params),
 217                                   (temp & DBGP_ENABLED) ? " IN USE" : "");
 218                         if (!(temp & DBGP_ENABLED))
 219                                 ehci->debug = NULL;
 220                 }
 221         }
 222
 223         retval = ehci_setup(hcd);
 224         if (retval)
 225                 return retval;
 226
 227         /* These workarounds need to be applied after ehci_setup() */
 228         switch (pdev->vendor) {
 229         case PCI_VENDOR_ID_NEC:
 230                 ehci->need_io_watchdog = 0;
 231                 break;
 232         case PCI_VENDOR_ID_INTEL:
 233                 ehci->need_io_watchdog = 0;
 234                 break;
 235         case PCI_VENDOR_ID_NVIDIA:
 236                 switch (pdev->device) {
 237                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 238                  * fetching device descriptors unless LPM is disabled.
 239                  * There are also intermittent problems enumerating
 240                  * devices with PPCD enabled.
 241                  */
 242                 case 0x0d9d:
 243                         ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
 244                         ehci->has_ppcd = 0;
 245                         ehci->command &= ~CMD_PPCEE;
 246                         break;
 247                 }
 248                 break;
 249         }
 250
 251         /* at least the Genesys GL880S needs fixup here */
 252         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 253         temp &= 0x0f;
 254         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 255                 ehci_dbg(ehci, "bogus port configuration: "
 256                         "cc=%d x pcc=%d < ports=%d\n",
 257                         HCS_N_CC(ehci->hcs_params),
 258                         HCS_N_PCC(ehci->hcs_params),
 259                         HCS_N_PORTS(ehci->hcs_params));
 260
 261                 switch (pdev->vendor) {
 262                 case 0x17a0:            /* GENESYS */
 263                         /* GL880S: should be PORTS=2 */
 264                         temp |= (ehci->hcs_params & ~0xf);
 265                         ehci->hcs_params = temp;
 266                         break;
 267                 case PCI_VENDOR_ID_NVIDIA:
 268                         /* NF4: should be PCC=10 */
 269                         break;
 270                 }
 271         }
 272
 273         /* Serial Bus Release Number is at PCI 0x60 offset */
 274         if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 275             && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 276                 ;       /* ConneXT has no sbrn register */
 277         else
 278                 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 279
 280         /* Keep this around for a while just in case some EHCI
 281          * implementation uses legacy PCI PM support.  This test
 282          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 283          * been triggered by then.
 284          */
 285         if (!device_can_wakeup(&pdev->dev)) {
 286                 u16     port_wake;
 287
 288                 pci_read_config_word(pdev, 0x62, &port_wake);
 289                 if (port_wake & 0x0001) {
 290                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 291                         device_set_wakeup_capable(&pdev->dev, 1);
 292                 }
 293         }
 294
 295 #ifdef  CONFIG_USB_SUSPEND
 296         /* REVISIT: the controller works fine for wakeup iff the root hub
 297          * itself is "globally" suspended, but usbcore currently doesn't
 298          * understand such things.
 299          *
 300          * System suspend currently expects to be able to suspend the entire
 301          * device tree, device-at-a-time.  If we failed selective suspend
 302          * reports, system suspend would fail; so the root hub code must claim
 303          * success.  That's lying to usbcore, and it matters for runtime
 304          * PM scenarios with selective suspend and remote wakeup...
 305          */
 306         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 307                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 308 #endif
 309
 310         retval = ehci_pci_reinit(ehci, pdev);
 311 done:
 312         return retval;
 313 }
 314
 315 /*-------------------------------------------------------------------------*/
 316
 317 #ifdef  CONFIG_PM
 318
 319 /* suspend/resume, section 4.3 */
 320
 321 /* These routines rely on the PCI bus glue
 322  * to handle powerdown and wakeup, and currently also on
 323  * transceivers that don't need any software attention to set up
 324  * the right sort of wakeup.
 325  * Also they depend on separate root hub suspend/resume.
 326  */
 327
 328 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
 329 {
 330         return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
 331                 pdev->vendor == PCI_VENDOR_ID_INTEL &&
 332                 (pdev->device == 0x1E26 ||
 333                  pdev->device == 0x8C2D ||
 334                  pdev->device == 0x8C26 ||
 335                  pdev->device == 0x9C26);
 336 }
 337
 338 static void ehci_enable_xhci_companion(void)
 339 {
 340         struct pci_dev          *companion = NULL;
 341
 342         /* The xHCI and EHCI controllers are not on the same PCI slot */
 343         for_each_pci_dev(companion) {
 344                 if (!usb_is_intel_switchable_xhci(companion))
 345                         continue;
 346                 usb_enable_xhci_ports(companion);
 347                 return;
 348         }
 349 }
 350
 351 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 352 {
 353         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 354         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 355
 356         /* The BIOS on systems with the Intel Panther Point chipset may or may
 357          * not support xHCI natively.  That means that during system resume, it
 358          * may switch the ports back to EHCI so that users can use their
 359          * keyboard to select a kernel from GRUB after resume from hibernate.
 360          *
 361          * The BIOS is supposed to remember whether the OS had xHCI ports
 362          * enabled before resume, and switch the ports back to xHCI when the
 363          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 364          * writers.
 365          *
 366          * Unconditionally switch the ports back to xHCI after a system resume.
 367          * We can't tell whether the EHCI or xHCI controller will be resumed
 368          * first, so we have to do the port switchover in both drivers.  Writing
 369          * a '1' to the port switchover registers should have no effect if the
 370          * port was already switched over.
 371          */
 372         if (usb_is_intel_switchable_ehci(pdev))
 373                 ehci_enable_xhci_companion();
 374
 375         if (ehci_resume(hcd, hibernated) != 0)
 376                 (void) ehci_pci_reinit(ehci, pdev);
 377         return 0;
 378 }
 379
 380 #else
 381
 382 #define ehci_suspend            NULL
 383 #define ehci_pci_resume         NULL
 384 #endif  /* CONFIG_PM */
 385
 386 static struct hc_driver __read_mostly ehci_pci_hc_driver;
 387
 388 static const struct ehci_driver_overrides pci_overrides __initdata = {
 389         .reset =                ehci_pci_setup,
 390 };
 391
 392 /*-------------------------------------------------------------------------*/
 393
 394 /* PCI driver selection metadata; PCI hotplugging uses this */
 395 static const struct pci_device_id pci_ids [] = { {
 396         /* handle any USB 2.0 EHCI controller */
 397         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 398         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 399         }, {
 400         PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 401         .driver_data = (unsigned long) &ehci_pci_hc_driver,
 402         },
 403         { /* end: all zeroes */ }
 404 };
 405 MODULE_DEVICE_TABLE(pci, pci_ids);
 406
 407 /* pci driver glue; this is a "new style" PCI driver module */
 408 static struct pci_driver ehci_pci_driver = {
 409         .name =         (char *) hcd_name,
 410         .id_table =     pci_ids,
 411
 412         .probe =        usb_hcd_pci_probe,
 413         .remove =       usb_hcd_pci_remove,
 414         .shutdown =     usb_hcd_pci_shutdown,
 415
 416 #ifdef CONFIG_PM_SLEEP
 417         .driver =       {
 418                 .pm =   &usb_hcd_pci_pm_ops
 419         },
 420 #endif
 421 };
 422
 423 static int __init ehci_pci_init(void)
 424 {
 425         if (usb_disabled())
 426                 return -ENODEV;
 427
 428         pr_info("%s: " DRIVER_DESC "\n", hcd_name);
 429
 430         ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
 431
 432         /* Entries for the PCI suspend/resume callbacks are special */
 433         ehci_pci_hc_driver.pci_suspend = ehci_suspend;
 434         ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
 435
 436         return pci_register_driver(&ehci_pci_driver);
 437 }
 438 module_init(ehci_pci_init);
 439
 440 static void __exit ehci_pci_cleanup(void)
 441 {
 442         pci_unregister_driver(&ehci_pci_driver);
 443 }
 444 module_exit(ehci_pci_cleanup);
 445
 446 MODULE_DESCRIPTION(DRIVER_DESC);
 447 MODULE_AUTHOR("David Brownell");
 448 MODULE_AUTHOR("Alan Stern");
 449 MODULE_LICENSE("GPL");