2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/hrtimer.h>
34 #include <linux/list.h>
35 #include <linux/interrupt.h>
36 #include <linux/usb.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/moduleparam.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/debugfs.h>
41 #include <linux/slab.h>
43 #include <asm/byteorder.h>
46 #include <asm/unaligned.h>
48 #if defined(CONFIG_PPC_PS3)
49 #include <asm/firmware.h>
52 /*-------------------------------------------------------------------------*/
55 * EHCI hc_driver implementation ... experimental, incomplete.
56 * Based on the final 1.0 register interface specification.
58 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
59 * First was PCMCIA, like ISA; then CardBus, which is PCI.
60 * Next comes "CardBay", using USB 2.0 signals.
62 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
63 * Special thanks to Intel and VIA for providing host controllers to
64 * test this driver on, and Cypress (including In-System Design) for
65 * providing early devices for those host controllers to talk to!
68 #define DRIVER_AUTHOR "David Brownell"
69 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
71 static const char hcd_name
[] = "ehci_hcd";
81 /* magic numbers that can affect system performance */
82 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
83 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
84 #define EHCI_TUNE_RL_TT 0
85 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
86 #define EHCI_TUNE_MULT_TT 1
88 * Some drivers think it's safe to schedule isochronous transfers more than
89 * 256 ms into the future (partly as a result of an old bug in the scheduling
90 * code). In an attempt to avoid trouble, we will use a minimum scheduling
91 * length of 512 frames instead of 256.
93 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
95 /* Initial IRQ latency: faster than hw default */
96 static int log2_irq_thresh
= 0; // 0 to 6
97 module_param (log2_irq_thresh
, int, S_IRUGO
);
98 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
100 /* initial park setting: slower than hw default */
101 static unsigned park
= 0;
102 module_param (park
, uint
, S_IRUGO
);
103 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
105 /* for flakey hardware, ignore overcurrent indicators */
106 static bool ignore_oc
= 0;
107 module_param (ignore_oc
, bool, S_IRUGO
);
108 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
110 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
112 /*-------------------------------------------------------------------------*/
115 #include "pci-quirks.h"
118 * The MosChip MCS9990 controller updates its microframe counter
119 * a little before the frame counter, and occasionally we will read
120 * the invalid intermediate value. Avoid problems by checking the
121 * microframe number (the low-order 3 bits); if they are 0 then
122 * re-read the register to get the correct value.
124 static unsigned ehci_moschip_read_frame_index(struct ehci_hcd
*ehci
)
128 uf
= ehci_readl(ehci
, &ehci
->regs
->frame_index
);
129 if (unlikely((uf
& 7) == 0))
130 uf
= ehci_readl(ehci
, &ehci
->regs
->frame_index
);
134 static inline unsigned ehci_read_frame_index(struct ehci_hcd
*ehci
)
136 if (ehci
->frame_index_bug
)
137 return ehci_moschip_read_frame_index(ehci
);
138 return ehci_readl(ehci
, &ehci
->regs
->frame_index
);
141 #include "ehci-dbg.c"
143 /*-------------------------------------------------------------------------*/
146 * handshake - spin reading hc until handshake completes or fails
147 * @ptr: address of hc register to be read
148 * @mask: bits to look at in result of read
149 * @done: value of those bits when handshake succeeds
150 * @usec: timeout in microseconds
152 * Returns negative errno, or zero on success
154 * Success happens when the "mask" bits have the specified value (hardware
155 * handshake done). There are two failure modes: "usec" have passed (major
156 * hardware flakeout), or the register reads as all-ones (hardware removed).
158 * That last failure should_only happen in cases like physical cardbus eject
159 * before driver shutdown. But it also seems to be caused by bugs in cardbus
160 * bridge shutdown: shutting down the bridge before the devices using it.
162 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
163 u32 mask
, u32 done
, int usec
)
168 result
= ehci_readl(ehci
, ptr
);
169 if (result
== ~(u32
)0) /* card removed */
180 /* check TDI/ARC silicon is in host mode */
181 static int tdi_in_host_mode (struct ehci_hcd
*ehci
)
185 tmp
= ehci_readl(ehci
, &ehci
->regs
->usbmode
);
186 return (tmp
& 3) == USBMODE_CM_HC
;
190 * Force HC to halt state from unknown (EHCI spec section 2.3).
191 * Must be called with interrupts enabled and the lock not held.
193 static int ehci_halt (struct ehci_hcd
*ehci
)
197 spin_lock_irq(&ehci
->lock
);
199 /* disable any irqs left enabled by previous code */
200 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
202 if (ehci_is_TDI(ehci
) && !tdi_in_host_mode(ehci
)) {
203 spin_unlock_irq(&ehci
->lock
);
208 * This routine gets called during probe before ehci->command
209 * has been initialized, so we can't rely on its value.
211 ehci
->command
&= ~CMD_RUN
;
212 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
213 temp
&= ~(CMD_RUN
| CMD_IAAD
);
214 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
216 spin_unlock_irq(&ehci
->lock
);
217 synchronize_irq(ehci_to_hcd(ehci
)->irq
);
219 return handshake(ehci
, &ehci
->regs
->status
,
220 STS_HALT
, STS_HALT
, 16 * 125);
223 /* put TDI/ARC silicon into EHCI mode */
224 static void tdi_reset (struct ehci_hcd
*ehci
)
228 tmp
= ehci_readl(ehci
, &ehci
->regs
->usbmode
);
229 tmp
|= USBMODE_CM_HC
;
230 /* The default byte access to MMR space is LE after
231 * controller reset. Set the required endian mode
232 * for transfer buffers to match the host microprocessor
234 if (ehci_big_endian_mmio(ehci
))
236 ehci_writel(ehci
, tmp
, &ehci
->regs
->usbmode
);
240 * Reset a non-running (STS_HALT == 1) controller.
241 * Must be called with interrupts enabled and the lock not held.
243 static int ehci_reset (struct ehci_hcd
*ehci
)
246 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
248 /* If the EHCI debug controller is active, special care must be
249 * taken before and after a host controller reset */
250 if (ehci
->debug
&& !dbgp_reset_prep(ehci_to_hcd(ehci
)))
253 command
|= CMD_RESET
;
254 dbg_cmd (ehci
, "reset", command
);
255 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
256 ehci
->rh_state
= EHCI_RH_HALTED
;
257 ehci
->next_statechange
= jiffies
;
258 retval
= handshake (ehci
, &ehci
->regs
->command
,
259 CMD_RESET
, 0, 250 * 1000);
261 if (ehci
->has_hostpc
) {
262 ehci_writel(ehci
, USBMODE_EX_HC
| USBMODE_EX_VBPS
,
263 &ehci
->regs
->usbmode_ex
);
264 ehci_writel(ehci
, TXFIFO_DEFAULT
, &ehci
->regs
->txfill_tuning
);
269 if (ehci_is_TDI(ehci
))
273 dbgp_external_startup(ehci_to_hcd(ehci
));
275 ehci
->port_c_suspend
= ehci
->suspended_ports
=
276 ehci
->resuming_ports
= 0;
281 * Idle the controller (turn off the schedules).
282 * Must be called with interrupts enabled and the lock not held.
284 static void ehci_quiesce (struct ehci_hcd
*ehci
)
288 if (ehci
->rh_state
!= EHCI_RH_RUNNING
)
291 /* wait for any schedule enables/disables to take effect */
292 temp
= (ehci
->command
<< 10) & (STS_ASS
| STS_PSS
);
293 handshake(ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
, temp
, 16 * 125);
295 /* then disable anything that's still active */
296 spin_lock_irq(&ehci
->lock
);
297 ehci
->command
&= ~(CMD_ASE
| CMD_PSE
);
298 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
299 spin_unlock_irq(&ehci
->lock
);
301 /* hardware can take 16 microframes to turn off ... */
302 handshake(ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
, 0, 16 * 125);
305 /*-------------------------------------------------------------------------*/
307 static void end_unlink_async(struct ehci_hcd
*ehci
);
308 static void unlink_empty_async(struct ehci_hcd
*ehci
);
309 static void ehci_work(struct ehci_hcd
*ehci
);
310 static void start_unlink_intr(struct ehci_hcd
*ehci
, struct ehci_qh
*qh
);
311 static void end_unlink_intr(struct ehci_hcd
*ehci
, struct ehci_qh
*qh
);
313 #include "ehci-timer.c"
314 #include "ehci-hub.c"
315 #include "ehci-mem.c"
317 #include "ehci-sched.c"
318 #include "ehci-sysfs.c"
320 /*-------------------------------------------------------------------------*/
322 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
323 * The firmware seems to think that powering off is a wakeup event!
324 * This routine turns off remote wakeup and everything else, on all ports.
326 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
328 int port
= HCS_N_PORTS(ehci
->hcs_params
);
331 ehci_writel(ehci
, PORT_RWC_BITS
,
332 &ehci
->regs
->port_status
[port
]);
336 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
337 * Must be called with interrupts enabled and the lock not held.
339 static void ehci_silence_controller(struct ehci_hcd
*ehci
)
343 spin_lock_irq(&ehci
->lock
);
344 ehci
->rh_state
= EHCI_RH_HALTED
;
345 ehci_turn_off_all_ports(ehci
);
347 /* make BIOS/etc use companion controller during reboot */
348 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
350 /* unblock posted writes */
351 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
352 spin_unlock_irq(&ehci
->lock
);
355 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
356 * This forcibly disables dma and IRQs, helping kexec and other cases
357 * where the next system software may expect clean state.
359 static void ehci_shutdown(struct usb_hcd
*hcd
)
361 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
363 spin_lock_irq(&ehci
->lock
);
364 ehci
->shutdown
= true;
365 ehci
->rh_state
= EHCI_RH_STOPPING
;
366 ehci
->enabled_hrtimer_events
= 0;
367 spin_unlock_irq(&ehci
->lock
);
369 ehci_silence_controller(ehci
);
371 hrtimer_cancel(&ehci
->hrtimer
);
374 /*-------------------------------------------------------------------------*/
377 * ehci_work is called from some interrupts, timers, and so on.
378 * it calls driver completion functions, after dropping ehci->lock.
380 static void ehci_work (struct ehci_hcd
*ehci
)
382 /* another CPU may drop ehci->lock during a schedule scan while
383 * it reports urb completions. this flag guards against bogus
384 * attempts at re-entrant schedule scanning.
386 if (ehci
->scanning
) {
387 ehci
->need_rescan
= true;
390 ehci
->scanning
= true;
393 ehci
->need_rescan
= false;
394 if (ehci
->async_count
)
396 if (ehci
->intr_count
> 0)
398 if (ehci
->isoc_count
> 0)
400 if (ehci
->need_rescan
)
402 ehci
->scanning
= false;
404 /* the IO watchdog guards against hardware or driver bugs that
405 * misplace IRQs, and should let us run completely without IRQs.
406 * such lossage has been observed on both VT6202 and VT8235.
408 turn_on_io_watchdog(ehci
);
412 * Called when the ehci_hcd module is removed.
414 static void ehci_stop (struct usb_hcd
*hcd
)
416 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
418 ehci_dbg (ehci
, "stop\n");
420 /* no more interrupts ... */
422 spin_lock_irq(&ehci
->lock
);
423 ehci
->enabled_hrtimer_events
= 0;
424 spin_unlock_irq(&ehci
->lock
);
427 ehci_silence_controller(ehci
);
430 hrtimer_cancel(&ehci
->hrtimer
);
431 remove_sysfs_files(ehci
);
432 remove_debug_files (ehci
);
434 /* root hub is shut down separately (first, when possible) */
435 spin_lock_irq (&ehci
->lock
);
437 spin_unlock_irq (&ehci
->lock
);
438 ehci_mem_cleanup (ehci
);
440 if (ehci
->amd_pll_fix
== 1)
444 ehci_dbg(ehci
, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
445 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.iaa
,
446 ehci
->stats
.lost_iaa
);
447 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
448 ehci
->stats
.complete
, ehci
->stats
.unlink
);
451 dbg_status (ehci
, "ehci_stop completed",
452 ehci_readl(ehci
, &ehci
->regs
->status
));
455 /* one-time init, only for memory state */
456 static int ehci_init(struct usb_hcd
*hcd
)
458 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
462 struct ehci_qh_hw
*hw
;
464 spin_lock_init(&ehci
->lock
);
467 * keep io watchdog by default, those good HCDs could turn off it later
469 ehci
->need_io_watchdog
= 1;
471 hrtimer_init(&ehci
->hrtimer
, CLOCK_MONOTONIC
, HRTIMER_MODE_ABS
);
472 ehci
->hrtimer
.function
= ehci_hrtimer_func
;
473 ehci
->next_hrtimer_event
= EHCI_HRTIMER_NO_EVENT
;
475 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
478 * by default set standard 80% (== 100 usec/uframe) max periodic
479 * bandwidth as required by USB 2.0
481 ehci
->uframe_periodic_max
= 100;
484 * hw default: 1K periodic list heads, one per frame.
485 * periodic_size can shrink by USBCMD update if hcc_params allows.
487 ehci
->periodic_size
= DEFAULT_I_TDPS
;
488 INIT_LIST_HEAD(&ehci
->intr_qh_list
);
489 INIT_LIST_HEAD(&ehci
->cached_itd_list
);
490 INIT_LIST_HEAD(&ehci
->cached_sitd_list
);
492 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
493 /* periodic schedule size can be smaller than default */
494 switch (EHCI_TUNE_FLS
) {
495 case 0: ehci
->periodic_size
= 1024; break;
496 case 1: ehci
->periodic_size
= 512; break;
497 case 2: ehci
->periodic_size
= 256; break;
501 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
504 /* controllers may cache some of the periodic schedule ... */
505 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
507 else // N microframes cached
508 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
511 * dedicate a qh for the async ring head, since we couldn't unlink
512 * a 'real' qh without stopping the async schedule [4.8]. use it
513 * as the 'reclamation list head' too.
514 * its dummy is used in hw_alt_next of many tds, to prevent the qh
515 * from automatically advancing to the next td after short reads.
517 ehci
->async
->qh_next
.qh
= NULL
;
518 hw
= ehci
->async
->hw
;
519 hw
->hw_next
= QH_NEXT(ehci
, ehci
->async
->qh_dma
);
520 hw
->hw_info1
= cpu_to_hc32(ehci
, QH_HEAD
);
521 #if defined(CONFIG_PPC_PS3)
522 hw
->hw_info1
|= cpu_to_hc32(ehci
, QH_INACTIVATE
);
524 hw
->hw_token
= cpu_to_hc32(ehci
, QTD_STS_HALT
);
525 hw
->hw_qtd_next
= EHCI_LIST_END(ehci
);
526 ehci
->async
->qh_state
= QH_STATE_LINKED
;
527 hw
->hw_alt_next
= QTD_NEXT(ehci
, ehci
->async
->dummy
->qtd_dma
);
529 /* clear interrupt enables, set irq latency */
530 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
532 temp
= 1 << (16 + log2_irq_thresh
);
533 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params
)) {
535 ehci_dbg(ehci
, "enable per-port change event\n");
538 if (HCC_CANPARK(hcc_params
)) {
539 /* HW default park == 3, on hardware that supports it (like
540 * NVidia and ALI silicon), maximizes throughput on the async
541 * schedule by avoiding QH fetches between transfers.
543 * With fast usb storage devices and NForce2, "park" seems to
544 * make problems: throughput reduction (!), data errors...
547 park
= min(park
, (unsigned) 3);
551 ehci_dbg(ehci
, "park %d\n", park
);
553 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
554 /* periodic schedule size can be smaller than default */
556 temp
|= (EHCI_TUNE_FLS
<< 2);
558 ehci
->command
= temp
;
560 /* Accept arbitrarily long scatter-gather lists */
561 if (!(hcd
->driver
->flags
& HCD_LOCAL_MEM
))
562 hcd
->self
.sg_tablesize
= ~0;
566 /* start HC running; it's halted, ehci_init() has been run (once) */
567 static int ehci_run (struct usb_hcd
*hcd
)
569 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
573 hcd
->uses_new_polling
= 1;
575 /* EHCI spec section 4.1 */
577 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
578 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
581 * hcc_params controls whether ehci->regs->segment must (!!!)
582 * be used; it constrains QH/ITD/SITD and QTD locations.
583 * pci_pool consistent memory always uses segment zero.
584 * streaming mappings for I/O buffers, like pci_map_single(),
585 * can return segments above 4GB, if the device allows.
587 * NOTE: the dma mask is visible through dma_supported(), so
588 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
589 * Scsi_Host.highmem_io, and so forth. It's readonly to all
590 * host side drivers though.
592 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
593 if (HCC_64BIT_ADDR(hcc_params
)) {
594 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
596 // this is deeply broken on almost all architectures
597 if (!dma_set_mask(hcd
->self
.controller
, DMA_BIT_MASK(64)))
598 ehci_info(ehci
, "enabled 64bit DMA\n");
603 // Philips, Intel, and maybe others need CMD_RUN before the
604 // root hub will detect new devices (why?); NEC doesn't
605 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
606 ehci
->command
|= CMD_RUN
;
607 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
608 dbg_cmd (ehci
, "init", ehci
->command
);
611 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
612 * are explicitly handed to companion controller(s), so no TT is
613 * involved with the root hub. (Except where one is integrated,
614 * and there's no companion controller unless maybe for USB OTG.)
616 * Turning on the CF flag will transfer ownership of all ports
617 * from the companions to the EHCI controller. If any of the
618 * companions are in the middle of a port reset at the time, it
619 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
620 * guarantees that no resets are in progress. After we set CF,
621 * a short delay lets the hardware catch up; new resets shouldn't
622 * be started before the port switching actions could complete.
624 down_write(&ehci_cf_port_reset_rwsem
);
625 ehci
->rh_state
= EHCI_RH_RUNNING
;
626 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
627 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
629 up_write(&ehci_cf_port_reset_rwsem
);
630 ehci
->last_periodic_enable
= ktime_get_real();
632 temp
= HC_VERSION(ehci
, ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
634 "USB %x.%x started, EHCI %x.%02x%s\n",
635 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
636 temp
>> 8, temp
& 0xff,
637 ignore_oc
? ", overcurrent ignored" : "");
639 ehci_writel(ehci
, INTR_MASK
,
640 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
642 /* GRR this is run-once init(), being done every time the HC starts.
643 * So long as they're part of class devices, we can't do it init()
644 * since the class device isn't created that early.
646 create_debug_files(ehci
);
647 create_sysfs_files(ehci
);
652 int ehci_setup(struct usb_hcd
*hcd
)
654 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
657 ehci
->regs
= (void __iomem
*)ehci
->caps
+
658 HC_LENGTH(ehci
, ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
659 dbg_hcs_params(ehci
, "reset");
660 dbg_hcc_params(ehci
, "reset");
662 /* cache this readonly data; minimize chip reads */
663 ehci
->hcs_params
= ehci_readl(ehci
, &ehci
->caps
->hcs_params
);
665 ehci
->sbrn
= HCD_USB2
;
667 /* data structure init */
668 retval
= ehci_init(hcd
);
672 retval
= ehci_halt(ehci
);
676 if (ehci_is_TDI(ehci
))
683 EXPORT_SYMBOL_GPL(ehci_setup
);
685 /*-------------------------------------------------------------------------*/
687 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
689 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
690 u32 status
, masked_status
, pcd_status
= 0, cmd
;
693 spin_lock (&ehci
->lock
);
695 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
697 /* e.g. cardbus physical eject */
698 if (status
== ~(u32
) 0) {
699 ehci_dbg (ehci
, "device removed\n");
704 * We don't use STS_FLR, but some controllers don't like it to
705 * remain on, so mask it out along with the other status bits.
707 masked_status
= status
& (INTR_MASK
| STS_FLR
);
710 if (!masked_status
|| unlikely(ehci
->rh_state
== EHCI_RH_HALTED
)) {
711 spin_unlock(&ehci
->lock
);
715 /* clear (just) interrupts */
716 ehci_writel(ehci
, masked_status
, &ehci
->regs
->status
);
717 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
);
721 /* unrequested/ignored: Frame List Rollover */
722 dbg_status (ehci
, "irq", status
);
725 /* INT, ERR, and IAA interrupt rates can be throttled */
727 /* normal [4.15.1.2] or error [4.15.1.1] completion */
728 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
729 if (likely ((status
& STS_ERR
) == 0))
730 COUNT (ehci
->stats
.normal
);
732 COUNT (ehci
->stats
.error
);
736 /* complete the unlinking of some qh [4.15.2.3] */
737 if (status
& STS_IAA
) {
739 /* Turn off the IAA watchdog */
740 ehci
->enabled_hrtimer_events
&= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG
);
743 * Mild optimization: Allow another IAAD to reset the
744 * hrtimer, if one occurs before the next expiration.
745 * In theory we could always cancel the hrtimer, but
746 * tests show that about half the time it will be reset
747 * for some other event anyway.
749 if (ehci
->next_hrtimer_event
== EHCI_HRTIMER_IAA_WATCHDOG
)
750 ++ehci
->next_hrtimer_event
;
752 /* guard against (alleged) silicon errata */
754 ehci_dbg(ehci
, "IAA with IAAD still set?\n");
755 if (ehci
->async_iaa
) {
756 COUNT(ehci
->stats
.iaa
);
757 end_unlink_async(ehci
);
759 ehci_dbg(ehci
, "IAA with nothing unlinked?\n");
762 /* remote wakeup [4.3.1] */
763 if (status
& STS_PCD
) {
764 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
767 /* kick root hub later */
770 /* resume root hub? */
771 if (ehci
->rh_state
== EHCI_RH_SUSPENDED
)
772 usb_hcd_resume_root_hub(hcd
);
774 /* get per-port change detect bits */
781 /* leverage per-port change bits feature */
782 if (ehci
->has_ppcd
&& !(ppcd
& (1 << i
)))
784 pstatus
= ehci_readl(ehci
,
785 &ehci
->regs
->port_status
[i
]);
787 if (pstatus
& PORT_OWNER
)
789 if (!(test_bit(i
, &ehci
->suspended_ports
) &&
790 ((pstatus
& PORT_RESUME
) ||
791 !(pstatus
& PORT_SUSPEND
)) &&
792 (pstatus
& PORT_PE
) &&
793 ehci
->reset_done
[i
] == 0))
796 /* start 20 msec resume signaling from this port,
797 * and make khubd collect PORT_STAT_C_SUSPEND to
798 * stop that signaling. Use 5 ms extra for safety,
799 * like usb_port_resume() does.
801 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies(25);
802 set_bit(i
, &ehci
->resuming_ports
);
803 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
804 mod_timer(&hcd
->rh_timer
, ehci
->reset_done
[i
]);
808 /* PCI errors [4.15.2.4] */
809 if (unlikely ((status
& STS_FATAL
) != 0)) {
810 ehci_err(ehci
, "fatal error\n");
811 dbg_cmd(ehci
, "fatal", cmd
);
812 dbg_status(ehci
, "fatal", status
);
816 /* Don't let the controller do anything more */
817 ehci
->shutdown
= true;
818 ehci
->rh_state
= EHCI_RH_STOPPING
;
819 ehci
->command
&= ~(CMD_RUN
| CMD_ASE
| CMD_PSE
);
820 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
821 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
822 ehci_handle_controller_death(ehci
);
824 /* Handle completions when the controller stops */
830 spin_unlock (&ehci
->lock
);
832 usb_hcd_poll_rh_status(hcd
);
836 /*-------------------------------------------------------------------------*/
839 * non-error returns are a promise to giveback() the urb later
840 * we drop ownership so next owner (or urb unlink) can get it
842 * urb + dev is in hcd.self.controller.urb_list
843 * we're queueing TDs onto software and hardware lists
845 * hcd-specific init for hcpriv hasn't been done yet
847 * NOTE: control, bulk, and interrupt share the same code to append TDs
848 * to a (possibly active) QH, and the same QH scanning code.
850 static int ehci_urb_enqueue (
855 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
856 struct list_head qtd_list
;
858 INIT_LIST_HEAD (&qtd_list
);
860 switch (usb_pipetype (urb
->pipe
)) {
862 /* qh_completions() code doesn't handle all the fault cases
863 * in multi-TD control transfers. Even 1KB is rare anyway.
865 if (urb
->transfer_buffer_length
> (16 * 1024))
868 /* case PIPE_BULK: */
870 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
872 return submit_async(ehci
, urb
, &qtd_list
, mem_flags
);
875 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
877 return intr_submit(ehci
, urb
, &qtd_list
, mem_flags
);
879 case PIPE_ISOCHRONOUS
:
880 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
881 return itd_submit (ehci
, urb
, mem_flags
);
883 return sitd_submit (ehci
, urb
, mem_flags
);
887 /* remove from hardware lists
888 * completions normally happen asynchronously
891 static int ehci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
893 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
898 spin_lock_irqsave (&ehci
->lock
, flags
);
899 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
903 switch (usb_pipetype (urb
->pipe
)) {
904 // case PIPE_CONTROL:
907 qh
= (struct ehci_qh
*) urb
->hcpriv
;
910 switch (qh
->qh_state
) {
911 case QH_STATE_LINKED
:
912 case QH_STATE_COMPLETING
:
913 start_unlink_async(ehci
, qh
);
915 case QH_STATE_UNLINK
:
916 case QH_STATE_UNLINK_WAIT
:
917 /* already started */
920 /* QH might be waiting for a Clear-TT-Buffer */
921 qh_completions(ehci
, qh
);
927 qh
= (struct ehci_qh
*) urb
->hcpriv
;
930 switch (qh
->qh_state
) {
931 case QH_STATE_LINKED
:
932 case QH_STATE_COMPLETING
:
933 start_unlink_intr(ehci
, qh
);
936 qh_completions (ehci
, qh
);
939 ehci_dbg (ehci
, "bogus qh %p state %d\n",
945 case PIPE_ISOCHRONOUS
:
948 // wait till next completion, do it then.
949 // completion irqs can wait up to 1024 msec,
953 spin_unlock_irqrestore (&ehci
->lock
, flags
);
957 /*-------------------------------------------------------------------------*/
959 // bulk qh holds the data toggle
962 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
964 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
966 struct ehci_qh
*qh
, *tmp
;
968 /* ASSERT: any requests/urbs are being unlinked */
969 /* ASSERT: nobody can be submitting urbs for this any more */
972 spin_lock_irqsave (&ehci
->lock
, flags
);
977 /* endpoints can be iso streams. for now, we don't
978 * accelerate iso completions ... so spin a while.
980 if (qh
->hw
== NULL
) {
981 struct ehci_iso_stream
*stream
= ep
->hcpriv
;
983 if (!list_empty(&stream
->td_list
))
986 /* BUG_ON(!list_empty(&stream->free_list)); */
991 if (ehci
->rh_state
< EHCI_RH_RUNNING
)
992 qh
->qh_state
= QH_STATE_IDLE
;
993 switch (qh
->qh_state
) {
994 case QH_STATE_LINKED
:
995 case QH_STATE_COMPLETING
:
996 for (tmp
= ehci
->async
->qh_next
.qh
;
998 tmp
= tmp
->qh_next
.qh
)
1000 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1001 * may already be unlinked.
1004 start_unlink_async(ehci
, qh
);
1006 case QH_STATE_UNLINK
: /* wait for hw to finish? */
1007 case QH_STATE_UNLINK_WAIT
:
1009 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1010 schedule_timeout_uninterruptible(1);
1012 case QH_STATE_IDLE
: /* fully unlinked */
1013 if (qh
->clearing_tt
)
1015 if (list_empty (&qh
->qtd_list
)) {
1016 qh_destroy(ehci
, qh
);
1019 /* else FALL THROUGH */
1021 /* caller was supposed to have unlinked any requests;
1022 * that's not our job. just leak this memory.
1024 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
1025 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
1026 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
1031 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1035 ehci_endpoint_reset(struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
1037 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
1039 int eptype
= usb_endpoint_type(&ep
->desc
);
1040 int epnum
= usb_endpoint_num(&ep
->desc
);
1041 int is_out
= usb_endpoint_dir_out(&ep
->desc
);
1042 unsigned long flags
;
1044 if (eptype
!= USB_ENDPOINT_XFER_BULK
&& eptype
!= USB_ENDPOINT_XFER_INT
)
1047 spin_lock_irqsave(&ehci
->lock
, flags
);
1050 /* For Bulk and Interrupt endpoints we maintain the toggle state
1051 * in the hardware; the toggle bits in udev aren't used at all.
1052 * When an endpoint is reset by usb_clear_halt() we must reset
1053 * the toggle bit in the QH.
1056 usb_settoggle(qh
->dev
, epnum
, is_out
, 0);
1057 if (!list_empty(&qh
->qtd_list
)) {
1058 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1059 } else if (qh
->qh_state
== QH_STATE_LINKED
||
1060 qh
->qh_state
== QH_STATE_COMPLETING
) {
1062 /* The toggle value in the QH can't be updated
1063 * while the QH is active. Unlink it now;
1064 * re-linking will call qh_refresh().
1066 if (eptype
== USB_ENDPOINT_XFER_BULK
)
1067 start_unlink_async(ehci
, qh
);
1069 start_unlink_intr(ehci
, qh
);
1072 spin_unlock_irqrestore(&ehci
->lock
, flags
);
1075 static int ehci_get_frame (struct usb_hcd
*hcd
)
1077 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
1078 return (ehci_read_frame_index(ehci
) >> 3) % ehci
->periodic_size
;
1081 /*-------------------------------------------------------------------------*/
1085 /* suspend/resume, section 4.3 */
1087 /* These routines handle the generic parts of controller suspend/resume */
1089 int ehci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1091 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
1093 if (time_before(jiffies
, ehci
->next_statechange
))
1097 * Root hub was already suspended. Disable IRQ emission and
1098 * mark HW unaccessible. The PM and USB cores make sure that
1099 * the root hub is either suspended or stopped.
1101 ehci_prepare_ports_for_controller_suspend(ehci
, do_wakeup
);
1103 spin_lock_irq(&ehci
->lock
);
1104 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
1105 (void) ehci_readl(ehci
, &ehci
->regs
->intr_enable
);
1107 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1108 spin_unlock_irq(&ehci
->lock
);
1112 EXPORT_SYMBOL_GPL(ehci_suspend
);
1114 /* Returns 0 if power was preserved, 1 if power was lost */
1115 int ehci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1117 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
1119 if (time_before(jiffies
, ehci
->next_statechange
))
1122 /* Mark hardware accessible again as we are back to full power by now */
1123 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1126 return 0; /* Controller is dead */
1129 * If CF is still set and we aren't resuming from hibernation
1130 * then we maintained suspend power.
1131 * Just undo the effect of ehci_suspend().
1133 if (ehci_readl(ehci
, &ehci
->regs
->configured_flag
) == FLAG_CF
&&
1135 int mask
= INTR_MASK
;
1137 ehci_prepare_ports_for_controller_resume(ehci
);
1139 spin_lock_irq(&ehci
->lock
);
1143 if (!hcd
->self
.root_hub
->do_remote_wakeup
)
1145 ehci_writel(ehci
, mask
, &ehci
->regs
->intr_enable
);
1146 ehci_readl(ehci
, &ehci
->regs
->intr_enable
);
1148 spin_unlock_irq(&ehci
->lock
);
1153 * Else reset, to cope with power loss or resume from hibernation
1154 * having let the firmware kick in during reboot.
1156 usb_root_hub_lost_power(hcd
->self
.root_hub
);
1157 (void) ehci_halt(ehci
);
1158 (void) ehci_reset(ehci
);
1160 spin_lock_irq(&ehci
->lock
);
1164 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
1165 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
1166 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
1168 ehci
->rh_state
= EHCI_RH_SUSPENDED
;
1169 spin_unlock_irq(&ehci
->lock
);
1173 EXPORT_SYMBOL_GPL(ehci_resume
);
1177 /*-------------------------------------------------------------------------*/
1180 * Generic structure: This gets copied for platform drivers so that
1181 * individual entries can be overridden as needed.
1184 static const struct hc_driver ehci_hc_driver
= {
1185 .description
= hcd_name
,
1186 .product_desc
= "EHCI Host Controller",
1187 .hcd_priv_size
= sizeof(struct ehci_hcd
),
1190 * generic hardware linkage
1193 .flags
= HCD_MEMORY
| HCD_USB2
,
1196 * basic lifecycle operations
1198 .reset
= ehci_setup
,
1201 .shutdown
= ehci_shutdown
,
1204 * managing i/o requests and associated device resources
1206 .urb_enqueue
= ehci_urb_enqueue
,
1207 .urb_dequeue
= ehci_urb_dequeue
,
1208 .endpoint_disable
= ehci_endpoint_disable
,
1209 .endpoint_reset
= ehci_endpoint_reset
,
1210 .clear_tt_buffer_complete
= ehci_clear_tt_buffer_complete
,
1213 * scheduling support
1215 .get_frame_number
= ehci_get_frame
,
1220 .hub_status_data
= ehci_hub_status_data
,
1221 .hub_control
= ehci_hub_control
,
1222 .bus_suspend
= ehci_bus_suspend
,
1223 .bus_resume
= ehci_bus_resume
,
1224 .relinquish_port
= ehci_relinquish_port
,
1225 .port_handed_over
= ehci_port_handed_over
,
1228 void ehci_init_driver(struct hc_driver
*drv
,
1229 const struct ehci_driver_overrides
*over
)
1231 /* Copy the generic table to drv and then apply the overrides */
1232 *drv
= ehci_hc_driver
;
1235 drv
->hcd_priv_size
+= over
->extra_priv_size
;
1237 drv
->reset
= over
->reset
;
1240 EXPORT_SYMBOL_GPL(ehci_init_driver
);
1242 /*-------------------------------------------------------------------------*/
1244 MODULE_DESCRIPTION(DRIVER_DESC
);
1245 MODULE_AUTHOR (DRIVER_AUTHOR
);
1246 MODULE_LICENSE ("GPL");
1248 #ifdef CONFIG_USB_EHCI_FSL
1249 #include "ehci-fsl.c"
1250 #define PLATFORM_DRIVER ehci_fsl_driver
1253 #ifdef CONFIG_USB_EHCI_MXC
1254 #include "ehci-mxc.c"
1255 #define PLATFORM_DRIVER ehci_mxc_driver
1258 #ifdef CONFIG_USB_EHCI_SH
1259 #include "ehci-sh.c"
1260 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1263 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1264 #include "ehci-omap.c"
1265 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1268 #ifdef CONFIG_PPC_PS3
1269 #include "ehci-ps3.c"
1270 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1273 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1274 #include "ehci-ppc-of.c"
1275 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1278 #ifdef CONFIG_XPS_USB_HCD_XILINX
1279 #include "ehci-xilinx-of.c"
1280 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1283 #ifdef CONFIG_PLAT_ORION
1284 #include "ehci-orion.c"
1285 #define PLATFORM_DRIVER ehci_orion_driver
1288 #ifdef CONFIG_USB_W90X900_EHCI
1289 #include "ehci-w90x900.c"
1290 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1293 #ifdef CONFIG_ARCH_AT91
1294 #include "ehci-atmel.c"
1295 #define PLATFORM_DRIVER ehci_atmel_driver
1298 #ifdef CONFIG_USB_OCTEON_EHCI
1299 #include "ehci-octeon.c"
1300 #define PLATFORM_DRIVER ehci_octeon_driver
1303 #ifdef CONFIG_ARCH_VT8500
1304 #include "ehci-vt8500.c"
1305 #define PLATFORM_DRIVER vt8500_ehci_driver
1308 #ifdef CONFIG_PLAT_SPEAR
1309 #include "ehci-spear.c"
1310 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1313 #ifdef CONFIG_USB_EHCI_MSM
1314 #include "ehci-msm.c"
1315 #define PLATFORM_DRIVER ehci_msm_driver
1318 #ifdef CONFIG_TILE_USB
1319 #include "ehci-tilegx.c"
1320 #define PLATFORM_DRIVER ehci_hcd_tilegx_driver
1323 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1324 #include "ehci-pmcmsp.c"
1325 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1328 #ifdef CONFIG_USB_EHCI_TEGRA
1329 #include "ehci-tegra.c"
1330 #define PLATFORM_DRIVER tegra_ehci_driver
1333 #ifdef CONFIG_USB_EHCI_S5P
1334 #include "ehci-s5p.c"
1335 #define PLATFORM_DRIVER s5p_ehci_driver
1338 #ifdef CONFIG_SPARC_LEON
1339 #include "ehci-grlib.c"
1340 #define PLATFORM_DRIVER ehci_grlib_driver
1343 #ifdef CONFIG_USB_EHCI_MV
1344 #include "ehci-mv.c"
1345 #define PLATFORM_DRIVER ehci_mv_driver
1348 #ifdef CONFIG_MIPS_SEAD3
1349 #include "ehci-sead3.c"
1350 #define PLATFORM_DRIVER ehci_hcd_sead3_driver
1353 #if !IS_ENABLED(CONFIG_USB_EHCI_PCI) && \
1354 !IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) && \
1355 !defined(CONFIG_USB_CHIPIDEA_HOST) && \
1356 !defined(PLATFORM_DRIVER) && \
1357 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1358 !defined(OF_PLATFORM_DRIVER) && \
1359 !defined(XILINX_OF_PLATFORM_DRIVER)
1360 #error "missing bus glue for ehci-hcd"
1363 static int __init
ehci_hcd_init(void)
1370 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1371 set_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1372 if (test_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
) ||
1373 test_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
))
1374 printk(KERN_WARNING
"Warning! ehci_hcd should always be loaded"
1375 " before uhci_hcd and ohci_hcd, not after\n");
1377 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1379 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
1380 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
1383 ehci_debug_root
= debugfs_create_dir("ehci", usb_debug_root
);
1384 if (!ehci_debug_root
) {
1390 #ifdef PLATFORM_DRIVER
1391 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1396 #ifdef PS3_SYSTEM_BUS_DRIVER
1397 retval
= ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1402 #ifdef OF_PLATFORM_DRIVER
1403 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1408 #ifdef XILINX_OF_PLATFORM_DRIVER
1409 retval
= platform_driver_register(&XILINX_OF_PLATFORM_DRIVER
);
1415 #ifdef XILINX_OF_PLATFORM_DRIVER
1416 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1419 #ifdef OF_PLATFORM_DRIVER
1420 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1423 #ifdef PS3_SYSTEM_BUS_DRIVER
1424 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1427 #ifdef PLATFORM_DRIVER
1428 platform_driver_unregister(&PLATFORM_DRIVER
);
1432 debugfs_remove(ehci_debug_root
);
1433 ehci_debug_root
= NULL
;
1436 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1439 module_init(ehci_hcd_init
);
1441 static void __exit
ehci_hcd_cleanup(void)
1443 #ifdef XILINX_OF_PLATFORM_DRIVER
1444 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER
);
1446 #ifdef OF_PLATFORM_DRIVER
1447 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1449 #ifdef PLATFORM_DRIVER
1450 platform_driver_unregister(&PLATFORM_DRIVER
);
1452 #ifdef PS3_SYSTEM_BUS_DRIVER
1453 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1456 debugfs_remove(ehci_debug_root
);
1458 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1460 module_exit(ehci_hcd_cleanup
);