2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
40 #include "s3c-hsotg.h"
42 static const char * const s3c_hsotg_supply_names
[] = {
43 "vusb_d", /* digital USB supply, 1.2V */
44 "vusb_a", /* analog USB supply, 1.1V */
50 * Unfortunately there seems to be a limit of the amount of data that can
51 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
52 * packets (which practically means 1 packet and 63 bytes of data) when the
55 * This means if we are wanting to move >127 bytes of data, we need to
56 * split the transactions up, but just doing one packet at a time does
57 * not work (this may be an implicit DATA0 PID on first packet of the
58 * transaction) and doing 2 packets is outside the controller's limits.
60 * If we try to lower the MPS size for EP0, then no transfers work properly
61 * for EP0, and the system will fail basic enumeration. As no cause for this
62 * has currently been found, we cannot support any large IN transfers for
65 #define EP0_MPS_LIMIT 64
71 * struct s3c_hsotg_ep - driver endpoint definition.
72 * @ep: The gadget layer representation of the endpoint.
73 * @name: The driver generated name for the endpoint.
74 * @queue: Queue of requests for this endpoint.
75 * @parent: Reference back to the parent device structure.
76 * @req: The current request that the endpoint is processing. This is
77 * used to indicate an request has been loaded onto the endpoint
78 * and has yet to be completed (maybe due to data move, or simply
79 * awaiting an ack from the core all the data has been completed).
80 * @debugfs: File entry for debugfs file for this endpoint.
81 * @lock: State lock to protect contents of endpoint.
82 * @dir_in: Set to true if this endpoint is of the IN direction, which
83 * means that it is sending data to the Host.
84 * @index: The index for the endpoint registers.
85 * @name: The name array passed to the USB core.
86 * @halted: Set if the endpoint has been halted.
87 * @periodic: Set if this is a periodic ep, such as Interrupt
88 * @sent_zlp: Set if we've sent a zero-length packet.
89 * @total_data: The total number of data bytes done.
90 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
91 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
92 * @last_load: The offset of data for the last start of request.
93 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
95 * This is the driver's state for each registered enpoint, allowing it
96 * to keep track of transactions that need doing. Each endpoint has a
97 * lock to protect the state, to try and avoid using an overall lock
98 * for the host controller as much as possible.
100 * For periodic IN endpoints, we have fifo_size and fifo_load to try
101 * and keep track of the amount of data in the periodic FIFO for each
102 * of these as we don't have a status register that tells us how much
103 * is in each of them. (note, this may actually be useless information
104 * as in shared-fifo mode periodic in acts like a single-frame packet
105 * buffer than a fifo)
107 struct s3c_hsotg_ep
{
109 struct list_head queue
;
110 struct s3c_hsotg
*parent
;
111 struct s3c_hsotg_req
*req
;
112 struct dentry
*debugfs
;
115 unsigned long total_data
;
116 unsigned int size_loaded
;
117 unsigned int last_load
;
118 unsigned int fifo_load
;
119 unsigned short fifo_size
;
121 unsigned char dir_in
;
124 unsigned int halted
:1;
125 unsigned int periodic
:1;
126 unsigned int sent_zlp
:1;
132 * struct s3c_hsotg - driver state.
133 * @dev: The parent device supplied to the probe function
134 * @driver: USB gadget driver
135 * @phy: The otg phy transceiver structure for phy control.
136 * @plat: The platform specific configuration data. This can be removed once
137 * all SoCs support usb transceiver.
138 * @regs: The memory area mapped for accessing registers.
139 * @irq: The IRQ number we are using
140 * @supplies: Definition of USB power supplies
141 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
142 * @num_of_eps: Number of available EPs (excluding EP0)
143 * @debug_root: root directrory for debugfs.
144 * @debug_file: main status file for debugfs.
145 * @debug_fifo: FIFO status file for debugfs.
146 * @ep0_reply: Request used for ep0 reply.
147 * @ep0_buff: Buffer for EP0 reply data, if needed.
148 * @ctrl_buff: Buffer for EP0 control requests.
149 * @ctrl_req: Request for EP0 control packets.
150 * @setup: NAK management for EP0 SETUP
151 * @last_rst: Time of last reset
152 * @eps: The endpoints being supplied to the gadget framework
156 struct usb_gadget_driver
*driver
;
158 struct s3c_hsotg_plat
*plat
;
166 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
168 unsigned int dedicated_fifos
:1;
169 unsigned char num_of_eps
;
171 struct dentry
*debug_root
;
172 struct dentry
*debug_file
;
173 struct dentry
*debug_fifo
;
175 struct usb_request
*ep0_reply
;
176 struct usb_request
*ctrl_req
;
180 struct usb_gadget gadget
;
182 unsigned long last_rst
;
183 struct s3c_hsotg_ep
*eps
;
187 * struct s3c_hsotg_req - data transfer request
188 * @req: The USB gadget request
189 * @queue: The list of requests for the endpoint this is queued for.
190 * @in_progress: Has already had size/packets written to core
191 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
193 struct s3c_hsotg_req
{
194 struct usb_request req
;
195 struct list_head queue
;
196 unsigned char in_progress
;
197 unsigned char mapped
;
200 /* conversion functions */
201 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
203 return container_of(req
, struct s3c_hsotg_req
, req
);
206 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
208 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
211 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
213 return container_of(gadget
, struct s3c_hsotg
, gadget
);
216 static inline void __orr32(void __iomem
*ptr
, u32 val
)
218 writel(readl(ptr
) | val
, ptr
);
221 static inline void __bic32(void __iomem
*ptr
, u32 val
)
223 writel(readl(ptr
) & ~val
, ptr
);
226 /* forward decleration of functions */
227 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
230 * using_dma - return the DMA status of the driver.
231 * @hsotg: The driver state.
233 * Return true if we're using DMA.
235 * Currently, we have the DMA support code worked into everywhere
236 * that needs it, but the AMBA DMA implementation in the hardware can
237 * only DMA from 32bit aligned addresses. This means that gadgets such
238 * as the CDC Ethernet cannot work as they often pass packets which are
241 * Unfortunately the choice to use DMA or not is global to the controller
242 * and seems to be only settable when the controller is being put through
243 * a core reset. This means we either need to fix the gadgets to take
244 * account of DMA alignment, or add bounce buffers (yuerk).
246 * Until this issue is sorted out, we always return 'false'.
248 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
250 return false; /* support is not complete */
254 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
255 * @hsotg: The device state
256 * @ints: A bitmask of the interrupts to enable
258 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
260 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
263 new_gsintmsk
= gsintmsk
| ints
;
265 if (new_gsintmsk
!= gsintmsk
) {
266 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
267 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
272 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
273 * @hsotg: The device state
274 * @ints: A bitmask of the interrupts to enable
276 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
278 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
281 new_gsintmsk
= gsintmsk
& ~ints
;
283 if (new_gsintmsk
!= gsintmsk
)
284 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
288 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
289 * @hsotg: The device state
290 * @ep: The endpoint index
291 * @dir_in: True if direction is in.
292 * @en: The enable value, true to enable
294 * Set or clear the mask for an individual endpoint's interrupt
297 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
298 unsigned int ep
, unsigned int dir_in
,
308 local_irq_save(flags
);
309 daint
= readl(hsotg
->regs
+ DAINTMSK
);
314 writel(daint
, hsotg
->regs
+ DAINTMSK
);
315 local_irq_restore(flags
);
319 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
320 * @hsotg: The device instance.
322 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
330 /* set FIFO sizes to 2048/1024 */
332 writel(2048, hsotg
->regs
+ GRXFSIZ
);
333 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
334 GNPTXFSIZ_NPTxFDep(1024),
335 hsotg
->regs
+ GNPTXFSIZ
);
338 * arange all the rest of the TX FIFOs, as some versions of this
339 * block have overlapping default addresses. This also ensures
340 * that if the settings have been changed, then they are set to
344 /* start at the end of the GNPTXFSIZ, rounded up */
349 * currently we allocate TX FIFOs for all possible endpoints,
350 * and assume that they are all the same size.
353 for (ep
= 1; ep
<= 15; ep
++) {
355 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
358 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
362 * according to p428 of the design guide, we need to ensure that
363 * all fifos are flushed before continuing
366 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
367 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
369 /* wait until the fifos are both flushed */
372 val
= readl(hsotg
->regs
+ GRSTCTL
);
374 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
377 if (--timeout
== 0) {
379 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
386 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
390 * @ep: USB endpoint to allocate request for.
391 * @flags: Allocation flags
393 * Allocate a new USB request structure appropriate for the specified endpoint
395 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
398 struct s3c_hsotg_req
*req
;
400 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
404 INIT_LIST_HEAD(&req
->queue
);
410 * is_ep_periodic - return true if the endpoint is in periodic mode.
411 * @hs_ep: The endpoint to query.
413 * Returns true if the endpoint is in periodic mode, meaning it is being
414 * used for an Interrupt or ISO transfer.
416 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
418 return hs_ep
->periodic
;
422 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
423 * @hsotg: The device state.
424 * @hs_ep: The endpoint for the request
425 * @hs_req: The request being processed.
427 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
428 * of a request to ensure the buffer is ready for access by the caller.
430 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
431 struct s3c_hsotg_ep
*hs_ep
,
432 struct s3c_hsotg_req
*hs_req
)
434 struct usb_request
*req
= &hs_req
->req
;
436 /* ignore this if we're not moving any data */
437 if (hs_req
->req
.length
== 0)
440 usb_gadget_unmap_request(&hsotg
->gadget
, hs_req
, hs_ep
->dir_in
);
444 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
445 * @hsotg: The controller state.
446 * @hs_ep: The endpoint we're going to write for.
447 * @hs_req: The request to write data for.
449 * This is called when the TxFIFO has some space in it to hold a new
450 * transmission and we have something to give it. The actual setup of
451 * the data size is done elsewhere, so all we have to do is to actually
454 * The return value is zero if there is more space (or nothing was done)
455 * otherwise -ENOSPC is returned if the FIFO space was used up.
457 * This routine is only needed for PIO
459 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
460 struct s3c_hsotg_ep
*hs_ep
,
461 struct s3c_hsotg_req
*hs_req
)
463 bool periodic
= is_ep_periodic(hs_ep
);
464 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
465 int buf_pos
= hs_req
->req
.actual
;
466 int to_write
= hs_ep
->size_loaded
;
471 to_write
-= (buf_pos
- hs_ep
->last_load
);
473 /* if there's nothing to write, get out early */
477 if (periodic
&& !hsotg
->dedicated_fifos
) {
478 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
483 * work out how much data was loaded so we can calculate
484 * how much data is left in the fifo.
487 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
490 * if shared fifo, we cannot write anything until the
491 * previous data has been completely sent.
493 if (hs_ep
->fifo_load
!= 0) {
494 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
498 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
500 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
502 /* how much of the data has moved */
503 size_done
= hs_ep
->size_loaded
- size_left
;
505 /* how much data is left in the fifo */
506 can_write
= hs_ep
->fifo_load
- size_done
;
507 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
508 __func__
, can_write
);
510 can_write
= hs_ep
->fifo_size
- can_write
;
511 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
512 __func__
, can_write
);
514 if (can_write
<= 0) {
515 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
518 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
519 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
524 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
526 "%s: no queue slots available (0x%08x)\n",
529 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
533 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
534 can_write
*= 4; /* fifo size is in 32bit quantities. */
537 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
538 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
541 * limit to 512 bytes of data, it seems at least on the non-periodic
542 * FIFO, requests of >512 cause the endpoint to get stuck with a
543 * fragment of the end of the transfer in it.
549 * limit the write to one max-packet size worth of data, but allow
550 * the transfer to return that it did not run out of fifo space
553 if (to_write
> hs_ep
->ep
.maxpacket
) {
554 to_write
= hs_ep
->ep
.maxpacket
;
556 s3c_hsotg_en_gsint(hsotg
,
557 periodic
? GINTSTS_PTxFEmp
:
561 /* see if we can write data */
563 if (to_write
> can_write
) {
564 to_write
= can_write
;
565 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
568 * Round the write down to an
569 * exact number of packets.
571 * Note, we do not currently check to see if we can ever
572 * write a full packet or not to the FIFO.
576 to_write
-= pkt_round
;
579 * enable correct FIFO interrupt to alert us when there
583 s3c_hsotg_en_gsint(hsotg
,
584 periodic
? GINTSTS_PTxFEmp
:
588 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
589 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
594 hs_req
->req
.actual
= buf_pos
+ to_write
;
595 hs_ep
->total_data
+= to_write
;
598 hs_ep
->fifo_load
+= to_write
;
600 to_write
= DIV_ROUND_UP(to_write
, 4);
601 data
= hs_req
->req
.buf
+ buf_pos
;
603 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
605 return (to_write
>= can_write
) ? -ENOSPC
: 0;
609 * get_ep_limit - get the maximum data legnth for this endpoint
610 * @hs_ep: The endpoint
612 * Return the maximum data that can be queued in one go on a given endpoint
613 * so that transfers that are too long can be split.
615 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
617 int index
= hs_ep
->index
;
622 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
623 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
627 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
632 /* we made the constant loading easier above by using +1 */
637 * constrain by packet count if maxpkts*pktsize is greater
638 * than the length register size.
641 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
642 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
648 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
649 * @hsotg: The controller state.
650 * @hs_ep: The endpoint to process a request for
651 * @hs_req: The request to start.
652 * @continuing: True if we are doing more for the current request.
654 * Start the given request running by setting the endpoint registers
655 * appropriately, and writing any data to the FIFOs.
657 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
658 struct s3c_hsotg_ep
*hs_ep
,
659 struct s3c_hsotg_req
*hs_req
,
662 struct usb_request
*ureq
= &hs_req
->req
;
663 int index
= hs_ep
->index
;
664 int dir_in
= hs_ep
->dir_in
;
674 if (hs_ep
->req
&& !continuing
) {
675 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
678 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
680 "%s: continue different req\n", __func__
);
686 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
687 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
689 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
690 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
691 hs_ep
->dir_in
? "in" : "out");
693 /* If endpoint is stalled, we will restart request later */
694 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
696 if (ctrl
& DxEPCTL_Stall
) {
697 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
701 length
= ureq
->length
- ureq
->actual
;
702 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
703 ureq
->length
, ureq
->actual
);
706 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
707 ureq
->buf
, length
, ureq
->dma
,
708 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
710 maxreq
= get_ep_limit(hs_ep
);
711 if (length
> maxreq
) {
712 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
714 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
715 __func__
, length
, maxreq
, round
);
717 /* round down to multiple of packets */
725 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
727 packets
= 1; /* send one packet if length is zero. */
729 if (dir_in
&& index
!= 0)
730 epsize
= DxEPTSIZ_MC(1);
734 if (index
!= 0 && ureq
->zero
) {
736 * test for the packets being exactly right for the
740 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
744 epsize
|= DxEPTSIZ_PktCnt(packets
);
745 epsize
|= DxEPTSIZ_XferSize(length
);
747 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
748 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
750 /* store the request as the current one we're doing */
753 /* write size / packets */
754 writel(epsize
, hsotg
->regs
+ epsize_reg
);
756 if (using_dma(hsotg
) && !continuing
) {
757 unsigned int dma_reg
;
760 * write DMA address to control register, buffer already
761 * synced by s3c_hsotg_ep_queue().
764 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
765 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
767 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
768 __func__
, ureq
->dma
, dma_reg
);
771 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
772 ctrl
|= DxEPCTL_USBActEp
;
774 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
776 /* For Setup request do not clear NAK */
777 if (hsotg
->setup
&& index
== 0)
780 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
783 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
784 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
787 * set these, it seems that DMA support increments past the end
788 * of the packet buffer so we need to calculate the length from
791 hs_ep
->size_loaded
= length
;
792 hs_ep
->last_load
= ureq
->actual
;
794 if (dir_in
&& !using_dma(hsotg
)) {
795 /* set these anyway, we may need them for non-periodic in */
796 hs_ep
->fifo_load
= 0;
798 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
802 * clear the INTknTXFEmpMsk when we start request, more as a aide
803 * to debugging to see what is going on.
806 writel(DIEPMSK_INTknTXFEmpMsk
,
807 hsotg
->regs
+ DIEPINT(index
));
810 * Note, trying to clear the NAK here causes problems with transmit
811 * on the S3C6400 ending up with the TXFIFO becoming full.
814 /* check ep is enabled */
815 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
817 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
818 index
, readl(hsotg
->regs
+ epctrl_reg
));
820 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
821 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
825 * s3c_hsotg_map_dma - map the DMA memory being used for the request
826 * @hsotg: The device state.
827 * @hs_ep: The endpoint the request is on.
828 * @req: The request being processed.
830 * We've been asked to queue a request, so ensure that the memory buffer
831 * is correctly setup for DMA. If we've been passed an extant DMA address
832 * then ensure the buffer has been synced to memory. If our buffer has no
833 * DMA memory, then we map the memory and mark our request to allow us to
834 * cleanup on completion.
836 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
837 struct s3c_hsotg_ep
*hs_ep
,
838 struct usb_request
*req
)
840 struct s3c_hsotg_req
*hs_req
= our_req(req
);
843 /* if the length is zero, ignore the DMA data */
844 if (hs_req
->req
.length
== 0)
847 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
854 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
855 __func__
, req
->buf
, req
->length
);
860 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
863 struct s3c_hsotg_req
*hs_req
= our_req(req
);
864 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
865 struct s3c_hsotg
*hs
= hs_ep
->parent
;
868 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
869 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
870 req
->zero
, req
->short_not_ok
);
872 /* initialise status of the request */
873 INIT_LIST_HEAD(&hs_req
->queue
);
875 req
->status
= -EINPROGRESS
;
877 /* if we're using DMA, sync the buffers as necessary */
879 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
884 first
= list_empty(&hs_ep
->queue
);
885 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
888 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
893 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
896 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
897 struct s3c_hsotg
*hs
= hs_ep
->parent
;
898 unsigned long flags
= 0;
901 spin_lock_irqsave(&hs
->lock
, flags
);
902 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
903 spin_unlock_irqrestore(&hs
->lock
, flags
);
908 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
909 struct usb_request
*req
)
911 struct s3c_hsotg_req
*hs_req
= our_req(req
);
917 * s3c_hsotg_complete_oursetup - setup completion callback
918 * @ep: The endpoint the request was on.
919 * @req: The request completed.
921 * Called on completion of any requests the driver itself
922 * submitted that need cleaning up.
924 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
925 struct usb_request
*req
)
927 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
928 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
930 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
932 s3c_hsotg_ep_free_request(ep
, req
);
936 * ep_from_windex - convert control wIndex value to endpoint
937 * @hsotg: The driver state.
938 * @windex: The control request wIndex field (in host order).
940 * Convert the given wIndex into a pointer to an driver endpoint
941 * structure, or return NULL if it is not a valid endpoint.
943 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
946 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
947 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
948 int idx
= windex
& 0x7F;
953 if (idx
> hsotg
->num_of_eps
)
956 if (idx
&& ep
->dir_in
!= dir
)
963 * s3c_hsotg_send_reply - send reply to control request
964 * @hsotg: The device state
966 * @buff: Buffer for request
967 * @length: Length of reply.
969 * Create a request and queue it on the given endpoint. This is useful as
970 * an internal method of sending replies to certain control requests, etc.
972 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
973 struct s3c_hsotg_ep
*ep
,
977 struct usb_request
*req
;
980 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
982 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
983 hsotg
->ep0_reply
= req
;
985 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
989 req
->buf
= hsotg
->ep0_buff
;
990 req
->length
= length
;
991 req
->zero
= 1; /* always do zero-length final transfer */
992 req
->complete
= s3c_hsotg_complete_oursetup
;
995 memcpy(req
->buf
, buff
, length
);
999 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1001 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1009 * s3c_hsotg_process_req_status - process request GET_STATUS
1010 * @hsotg: The device state
1011 * @ctrl: USB control request
1013 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1014 struct usb_ctrlrequest
*ctrl
)
1016 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1017 struct s3c_hsotg_ep
*ep
;
1021 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1024 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1028 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1029 case USB_RECIP_DEVICE
:
1030 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1031 * bit 1 => remote wakeup */
1034 case USB_RECIP_INTERFACE
:
1035 /* currently, the data result should be zero */
1036 reply
= cpu_to_le16(0);
1039 case USB_RECIP_ENDPOINT
:
1040 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1044 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1051 if (le16_to_cpu(ctrl
->wLength
) != 2)
1054 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1056 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1063 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1066 * get_ep_head - return the first request on the endpoint
1067 * @hs_ep: The controller endpoint to get
1069 * Get the first request on the endpoint.
1071 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1073 if (list_empty(&hs_ep
->queue
))
1076 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1080 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1081 * @hsotg: The device state
1082 * @ctrl: USB control request
1084 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1085 struct usb_ctrlrequest
*ctrl
)
1087 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1088 struct s3c_hsotg_req
*hs_req
;
1090 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1091 struct s3c_hsotg_ep
*ep
;
1094 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1095 __func__
, set
? "SET" : "CLEAR");
1097 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1098 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1100 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1101 __func__
, le16_to_cpu(ctrl
->wIndex
));
1105 switch (le16_to_cpu(ctrl
->wValue
)) {
1106 case USB_ENDPOINT_HALT
:
1107 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1109 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1112 "%s: failed to send reply\n", __func__
);
1118 * If we have request in progress,
1124 list_del_init(&hs_req
->queue
);
1125 hs_req
->req
.complete(&ep
->ep
,
1129 /* If we have pending request, then start it */
1130 restart
= !list_empty(&ep
->queue
);
1132 hs_req
= get_ep_head(ep
);
1133 s3c_hsotg_start_req(hsotg
, ep
,
1144 return -ENOENT
; /* currently only deal with endpoint */
1150 * s3c_hsotg_process_control - process a control request
1151 * @hsotg: The device state
1152 * @ctrl: The control request received
1154 * The controller has received the SETUP phase of a control request, and
1155 * needs to work out what to do next (and whether to pass it on to the
1158 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1159 struct usb_ctrlrequest
*ctrl
)
1161 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1167 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1168 ctrl
->bRequest
, ctrl
->bRequestType
,
1169 ctrl
->wValue
, ctrl
->wLength
);
1172 * record the direction of the request, for later use when enquing
1176 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1177 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1180 * if we've no data with this request, then the last part of the
1181 * transaction is going to implicitly be IN.
1183 if (ctrl
->wLength
== 0)
1186 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1187 switch (ctrl
->bRequest
) {
1188 case USB_REQ_SET_ADDRESS
:
1189 dcfg
= readl(hsotg
->regs
+ DCFG
);
1190 dcfg
&= ~DCFG_DevAddr_MASK
;
1191 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1192 writel(dcfg
, hsotg
->regs
+ DCFG
);
1194 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1196 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1199 case USB_REQ_GET_STATUS
:
1200 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1203 case USB_REQ_CLEAR_FEATURE
:
1204 case USB_REQ_SET_FEATURE
:
1205 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1210 /* as a fallback, try delivering it to the driver to deal with */
1212 if (ret
== 0 && hsotg
->driver
) {
1213 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1215 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1219 * the request is either unhandlable, or is not formatted correctly
1220 * so respond with a STALL for the status stage to indicate failure.
1227 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1228 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1231 * DxEPCTL_Stall will be cleared by EP once it has
1232 * taken effect, so no need to clear later.
1235 ctrl
= readl(hsotg
->regs
+ reg
);
1236 ctrl
|= DxEPCTL_Stall
;
1237 ctrl
|= DxEPCTL_CNAK
;
1238 writel(ctrl
, hsotg
->regs
+ reg
);
1241 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1242 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1245 * don't believe we need to anything more to get the EP
1246 * to reply with a STALL packet
1251 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1254 * s3c_hsotg_complete_setup - completion of a setup transfer
1255 * @ep: The endpoint the request was on.
1256 * @req: The request completed.
1258 * Called on completion of any requests the driver itself submitted for
1261 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1262 struct usb_request
*req
)
1264 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1265 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1267 if (req
->status
< 0) {
1268 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1272 if (req
->actual
== 0)
1273 s3c_hsotg_enqueue_setup(hsotg
);
1275 s3c_hsotg_process_control(hsotg
, req
->buf
);
1279 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1280 * @hsotg: The device state.
1282 * Enqueue a request on EP0 if necessary to received any SETUP packets
1283 * received from the host.
1285 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1287 struct usb_request
*req
= hsotg
->ctrl_req
;
1288 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1291 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1295 req
->buf
= hsotg
->ctrl_buff
;
1296 req
->complete
= s3c_hsotg_complete_setup
;
1298 if (!list_empty(&hs_req
->queue
)) {
1299 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1303 hsotg
->eps
[0].dir_in
= 0;
1305 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1307 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1309 * Don't think there's much we can do other than watch the
1316 * s3c_hsotg_complete_request - complete a request given to us
1317 * @hsotg: The device state.
1318 * @hs_ep: The endpoint the request was on.
1319 * @hs_req: The request to complete.
1320 * @result: The result code (0 => Ok, otherwise errno)
1322 * The given request has finished, so call the necessary completion
1323 * if it has one and then look to see if we can start a new request
1326 * Note, expects the ep to already be locked as appropriate.
1328 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1329 struct s3c_hsotg_ep
*hs_ep
,
1330 struct s3c_hsotg_req
*hs_req
,
1336 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1340 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1341 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1344 * only replace the status if we've not already set an error
1345 * from a previous transaction
1348 if (hs_req
->req
.status
== -EINPROGRESS
)
1349 hs_req
->req
.status
= result
;
1352 list_del_init(&hs_req
->queue
);
1354 if (using_dma(hsotg
))
1355 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1358 * call the complete request with the locks off, just in case the
1359 * request tries to queue more work for this endpoint.
1362 if (hs_req
->req
.complete
) {
1363 spin_unlock(&hsotg
->lock
);
1364 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1365 spin_lock(&hsotg
->lock
);
1369 * Look to see if there is anything else to do. Note, the completion
1370 * of the previous request may have caused a new request to be started
1371 * so be careful when doing this.
1374 if (!hs_ep
->req
&& result
>= 0) {
1375 restart
= !list_empty(&hs_ep
->queue
);
1377 hs_req
= get_ep_head(hs_ep
);
1378 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1384 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1385 * @hsotg: The device state.
1386 * @ep_idx: The endpoint index for the data
1387 * @size: The size of data in the fifo, in bytes
1389 * The FIFO status shows there is data to read from the FIFO for a given
1390 * endpoint, so sort out whether we need to read the data into a request
1391 * that has been made for that endpoint.
1393 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1395 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1396 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1397 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1404 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1407 dev_warn(hsotg
->dev
,
1408 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1409 __func__
, size
, ep_idx
, epctl
);
1411 /* dump the data from the FIFO, we've nothing we can do */
1412 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1419 read_ptr
= hs_req
->req
.actual
;
1420 max_req
= hs_req
->req
.length
- read_ptr
;
1422 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1423 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1425 if (to_read
> max_req
) {
1427 * more data appeared than we where willing
1428 * to deal with in this request.
1431 /* currently we don't deal this */
1435 hs_ep
->total_data
+= to_read
;
1436 hs_req
->req
.actual
+= to_read
;
1437 to_read
= DIV_ROUND_UP(to_read
, 4);
1440 * note, we might over-write the buffer end by 3 bytes depending on
1441 * alignment of the data.
1443 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1447 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1448 * @hsotg: The device instance
1449 * @req: The request currently on this endpoint
1451 * Generate a zero-length IN packet request for terminating a SETUP
1454 * Note, since we don't write any data to the TxFIFO, then it is
1455 * currently believed that we do not need to wait for any space in
1458 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1459 struct s3c_hsotg_req
*req
)
1464 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1468 if (req
->req
.length
== 0) {
1469 hsotg
->eps
[0].sent_zlp
= 1;
1470 s3c_hsotg_enqueue_setup(hsotg
);
1474 hsotg
->eps
[0].dir_in
= 1;
1475 hsotg
->eps
[0].sent_zlp
= 1;
1477 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1479 /* issue a zero-sized packet to terminate this */
1480 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1481 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1483 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1484 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1485 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1486 ctrl
|= DxEPCTL_USBActEp
;
1487 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1491 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1492 * @hsotg: The device instance
1493 * @epnum: The endpoint received from
1494 * @was_setup: Set if processing a SetupDone event.
1496 * The RXFIFO has delivered an OutDone event, which means that the data
1497 * transfer for an OUT endpoint has been completed, either by a short
1498 * packet or by the finish of a transfer.
1500 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1501 int epnum
, bool was_setup
)
1503 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1504 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1505 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1506 struct usb_request
*req
= &hs_req
->req
;
1507 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1511 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1515 if (using_dma(hsotg
)) {
1519 * Calculate the size of the transfer by checking how much
1520 * is left in the endpoint size register and then working it
1521 * out from the amount we loaded for the transfer.
1523 * We need to do this as DMA pointers are always 32bit aligned
1524 * so may overshoot/undershoot the transfer.
1527 size_done
= hs_ep
->size_loaded
- size_left
;
1528 size_done
+= hs_ep
->last_load
;
1530 req
->actual
= size_done
;
1533 /* if there is more request to do, schedule new transfer */
1534 if (req
->actual
< req
->length
&& size_left
== 0) {
1535 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1537 } else if (epnum
== 0) {
1539 * After was_setup = 1 =>
1540 * set CNAK for non Setup requests
1542 hsotg
->setup
= was_setup
? 0 : 1;
1545 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1546 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1547 __func__
, req
->actual
, req
->length
);
1550 * todo - what should we return here? there's no one else
1551 * even bothering to check the status.
1557 * Condition req->complete != s3c_hsotg_complete_setup says:
1558 * send ZLP when we have an asynchronous request from gadget
1560 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1561 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1564 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1568 * s3c_hsotg_read_frameno - read current frame number
1569 * @hsotg: The device instance
1571 * Return the current frame number
1573 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1577 dsts
= readl(hsotg
->regs
+ DSTS
);
1578 dsts
&= DSTS_SOFFN_MASK
;
1579 dsts
>>= DSTS_SOFFN_SHIFT
;
1585 * s3c_hsotg_handle_rx - RX FIFO has data
1586 * @hsotg: The device instance
1588 * The IRQ handler has detected that the RX FIFO has some data in it
1589 * that requires processing, so find out what is in there and do the
1592 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1593 * chunks, so if you have x packets received on an endpoint you'll get x
1594 * FIFO events delivered, each with a packet's worth of data in it.
1596 * When using DMA, we should not be processing events from the RXFIFO
1597 * as the actual data should be sent to the memory directly and we turn
1598 * on the completion interrupts to get notifications of transfer completion.
1600 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1602 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1603 u32 epnum
, status
, size
;
1605 WARN_ON(using_dma(hsotg
));
1607 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1608 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1610 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1611 size
>>= GRXSTS_ByteCnt_SHIFT
;
1614 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1615 __func__
, grxstsr
, size
, epnum
);
1617 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1619 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1620 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1621 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1624 case __status(GRXSTS_PktSts_OutDone
):
1625 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1626 s3c_hsotg_read_frameno(hsotg
));
1628 if (!using_dma(hsotg
))
1629 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1632 case __status(GRXSTS_PktSts_SetupDone
):
1634 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1635 s3c_hsotg_read_frameno(hsotg
),
1636 readl(hsotg
->regs
+ DOEPCTL(0)));
1638 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1641 case __status(GRXSTS_PktSts_OutRX
):
1642 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1645 case __status(GRXSTS_PktSts_SetupRX
):
1647 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1648 s3c_hsotg_read_frameno(hsotg
),
1649 readl(hsotg
->regs
+ DOEPCTL(0)));
1651 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1655 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1658 s3c_hsotg_dump(hsotg
);
1664 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1665 * @mps: The maximum packet size in bytes.
1667 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1671 return D0EPCTL_MPS_64
;
1673 return D0EPCTL_MPS_32
;
1675 return D0EPCTL_MPS_16
;
1677 return D0EPCTL_MPS_8
;
1680 /* bad max packet size, warn and return invalid result */
1686 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1687 * @hsotg: The driver state.
1688 * @ep: The index number of the endpoint
1689 * @mps: The maximum packet size in bytes
1691 * Configure the maximum packet size for the given endpoint, updating
1692 * the hardware control registers to reflect this.
1694 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1695 unsigned int ep
, unsigned int mps
)
1697 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1698 void __iomem
*regs
= hsotg
->regs
;
1703 /* EP0 is a special case */
1704 mpsval
= s3c_hsotg_ep0_mps(mps
);
1708 if (mps
>= DxEPCTL_MPS_LIMIT
+1)
1714 hs_ep
->ep
.maxpacket
= mps
;
1717 * update both the in and out endpoint controldir_ registers, even
1718 * if one of the directions may not be in use.
1721 reg
= readl(regs
+ DIEPCTL(ep
));
1722 reg
&= ~DxEPCTL_MPS_MASK
;
1724 writel(reg
, regs
+ DIEPCTL(ep
));
1727 reg
= readl(regs
+ DOEPCTL(ep
));
1728 reg
&= ~DxEPCTL_MPS_MASK
;
1730 writel(reg
, regs
+ DOEPCTL(ep
));
1736 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1740 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1741 * @hsotg: The driver state
1742 * @idx: The index for the endpoint (0..15)
1744 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1749 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1750 hsotg
->regs
+ GRSTCTL
);
1752 /* wait until the fifo is flushed */
1756 val
= readl(hsotg
->regs
+ GRSTCTL
);
1758 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1761 if (--timeout
== 0) {
1763 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1772 * s3c_hsotg_trytx - check to see if anything needs transmitting
1773 * @hsotg: The driver state
1774 * @hs_ep: The driver endpoint to check.
1776 * Check to see if there is a request that has data to send, and if so
1777 * make an attempt to write data into the FIFO.
1779 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1780 struct s3c_hsotg_ep
*hs_ep
)
1782 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1784 if (!hs_ep
->dir_in
|| !hs_req
)
1787 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1788 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1790 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1797 * s3c_hsotg_complete_in - complete IN transfer
1798 * @hsotg: The device state.
1799 * @hs_ep: The endpoint that has just completed.
1801 * An IN transfer has been completed, update the transfer's state and then
1802 * call the relevant completion routines.
1804 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1805 struct s3c_hsotg_ep
*hs_ep
)
1807 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1808 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1809 int size_left
, size_done
;
1812 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1816 /* Finish ZLP handling for IN EP0 transactions */
1817 if (hsotg
->eps
[0].sent_zlp
) {
1818 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1819 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1824 * Calculate the size of the transfer by checking how much is left
1825 * in the endpoint size register and then working it out from
1826 * the amount we loaded for the transfer.
1828 * We do this even for DMA, as the transfer may have incremented
1829 * past the end of the buffer (DMA transfers are always 32bit
1833 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1835 size_done
= hs_ep
->size_loaded
- size_left
;
1836 size_done
+= hs_ep
->last_load
;
1838 if (hs_req
->req
.actual
!= size_done
)
1839 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1840 __func__
, hs_req
->req
.actual
, size_done
);
1842 hs_req
->req
.actual
= size_done
;
1843 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1844 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1847 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1848 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1849 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1850 * inform the host that no more data is available.
1851 * The state of req.zero member is checked to be sure that the value to
1852 * send is smaller than wValue expected from host.
1853 * Check req.length to NOT send another ZLP when the current one is
1854 * under completion (the one for which this completion has been called).
1856 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1857 hs_req
->req
.length
== hs_req
->req
.actual
&&
1858 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1860 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1861 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1866 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1867 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1868 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1870 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1874 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1875 * @hsotg: The driver state
1876 * @idx: The index for the endpoint (0..15)
1877 * @dir_in: Set if this is an IN endpoint
1879 * Process and clear any interrupt pending for an individual endpoint
1881 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1884 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1885 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1886 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1887 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1890 ints
= readl(hsotg
->regs
+ epint_reg
);
1892 /* Clear endpoint interrupts */
1893 writel(ints
, hsotg
->regs
+ epint_reg
);
1895 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1896 __func__
, idx
, dir_in
? "in" : "out", ints
);
1898 if (ints
& DxEPINT_XferCompl
) {
1900 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1901 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1902 readl(hsotg
->regs
+ epsiz_reg
));
1905 * we get OutDone from the FIFO, so we only need to look
1906 * at completing IN requests here
1909 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1911 if (idx
== 0 && !hs_ep
->req
)
1912 s3c_hsotg_enqueue_setup(hsotg
);
1913 } else if (using_dma(hsotg
)) {
1915 * We're using DMA, we need to fire an OutDone here
1916 * as we ignore the RXFIFO.
1919 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1923 if (ints
& DxEPINT_EPDisbld
) {
1924 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1927 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1929 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1931 if ((epctl
& DxEPCTL_Stall
) &&
1932 (epctl
& DxEPCTL_EPType_Bulk
)) {
1933 int dctl
= readl(hsotg
->regs
+ DCTL
);
1935 dctl
|= DCTL_CGNPInNAK
;
1936 writel(dctl
, hsotg
->regs
+ DCTL
);
1941 if (ints
& DxEPINT_AHBErr
)
1942 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1944 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1945 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1947 if (using_dma(hsotg
) && idx
== 0) {
1949 * this is the notification we've received a
1950 * setup packet. In non-DMA mode we'd get this
1951 * from the RXFIFO, instead we need to process
1958 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1962 if (ints
& DxEPINT_Back2BackSetup
)
1963 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1966 /* not sure if this is important, but we'll clear it anyway */
1967 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
1968 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
1972 /* this probably means something bad is happening */
1973 if (ints
& DIEPMSK_INTknEPMisMsk
) {
1974 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
1978 /* FIFO has space or is empty (see GAHBCFG) */
1979 if (hsotg
->dedicated_fifos
&&
1980 ints
& DIEPMSK_TxFIFOEmpty
) {
1981 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
1983 if (!using_dma(hsotg
))
1984 s3c_hsotg_trytx(hsotg
, hs_ep
);
1990 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1991 * @hsotg: The device state.
1993 * Handle updating the device settings after the enumeration phase has
1996 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
1998 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
1999 int ep0_mps
= 0, ep_mps
;
2002 * This should signal the finish of the enumeration phase
2003 * of the USB handshaking, so we should now know what rate
2007 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2010 * note, since we're limited by the size of transfer on EP0, and
2011 * it seems IN transfers must be a even number of packets we do
2012 * not advertise a 64byte MPS on EP0.
2015 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2016 switch (dsts
& DSTS_EnumSpd_MASK
) {
2017 case DSTS_EnumSpd_FS
:
2018 case DSTS_EnumSpd_FS48
:
2019 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2020 ep0_mps
= EP0_MPS_LIMIT
;
2024 case DSTS_EnumSpd_HS
:
2025 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2026 ep0_mps
= EP0_MPS_LIMIT
;
2030 case DSTS_EnumSpd_LS
:
2031 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2033 * note, we don't actually support LS in this driver at the
2034 * moment, and the documentation seems to imply that it isn't
2035 * supported by the PHYs on some of the devices.
2039 dev_info(hsotg
->dev
, "new device is %s\n",
2040 usb_speed_string(hsotg
->gadget
.speed
));
2043 * we should now know the maximum packet size for an
2044 * endpoint, so set the endpoints to a default value.
2049 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2050 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2051 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2054 /* ensure after enumeration our EP0 is active */
2056 s3c_hsotg_enqueue_setup(hsotg
);
2058 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2059 readl(hsotg
->regs
+ DIEPCTL0
),
2060 readl(hsotg
->regs
+ DOEPCTL0
));
2064 * kill_all_requests - remove all requests from the endpoint's queue
2065 * @hsotg: The device state.
2066 * @ep: The endpoint the requests may be on.
2067 * @result: The result code to use.
2068 * @force: Force removal of any current requests
2070 * Go through the requests on the given endpoint and mark them
2071 * completed with the given result code.
2073 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2074 struct s3c_hsotg_ep
*ep
,
2075 int result
, bool force
)
2077 struct s3c_hsotg_req
*req
, *treq
;
2079 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2081 * currently, we can't do much about an already
2082 * running request on an in endpoint
2085 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2088 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2093 #define call_gadget(_hs, _entry) \
2094 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2095 (_hs)->driver && (_hs)->driver->_entry) { \
2096 spin_unlock(&_hs->lock); \
2097 (_hs)->driver->_entry(&(_hs)->gadget); \
2098 spin_lock(&_hs->lock); \
2102 * s3c_hsotg_disconnect - disconnect service
2103 * @hsotg: The device state.
2105 * The device has been disconnected. Remove all current
2106 * transactions and signal the gadget driver that this
2109 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2113 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2114 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2116 call_gadget(hsotg
, disconnect
);
2120 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2121 * @hsotg: The device state:
2122 * @periodic: True if this is a periodic FIFO interrupt
2124 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2126 struct s3c_hsotg_ep
*ep
;
2129 /* look through for any more data to transmit */
2131 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2132 ep
= &hsotg
->eps
[epno
];
2137 if ((periodic
&& !ep
->periodic
) ||
2138 (!periodic
&& ep
->periodic
))
2141 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2147 /* IRQ flags which will trigger a retry around the IRQ loop */
2148 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2153 * s3c_hsotg_corereset - issue softreset to the core
2154 * @hsotg: The device state
2156 * Issue a soft reset to the core, and await the core finishing it.
2158 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2163 dev_dbg(hsotg
->dev
, "resetting core\n");
2165 /* issue soft reset */
2166 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2170 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2171 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2173 if (grstctl
& GRSTCTL_CSftRst
) {
2174 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2181 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2183 if (timeout
-- < 0) {
2184 dev_info(hsotg
->dev
,
2185 "%s: reset failed, GRSTCTL=%08x\n",
2190 if (!(grstctl
& GRSTCTL_AHBIdle
))
2193 break; /* reset done */
2196 dev_dbg(hsotg
->dev
, "reset successful\n");
2201 * s3c_hsotg_core_init - issue softreset to the core
2202 * @hsotg: The device state
2204 * Issue a soft reset to the core, and await the core finishing it.
2206 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2208 s3c_hsotg_corereset(hsotg
);
2211 * we must now enable ep0 ready for host detection and then
2212 * set configuration.
2215 /* set the PLL on, remove the HNP/SRP and set the PHY */
2216 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2217 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2219 s3c_hsotg_init_fifo(hsotg
);
2221 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2223 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2225 /* Clear any pending OTG interrupts */
2226 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2228 /* Clear any pending interrupts */
2229 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2231 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2232 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2233 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2234 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2235 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2236 hsotg
->regs
+ GINTMSK
);
2238 if (using_dma(hsotg
))
2239 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2240 GAHBCFG_HBstLen_Incr4
,
2241 hsotg
->regs
+ GAHBCFG
);
2243 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2246 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2247 * up being flooded with interrupts if the host is polling the
2248 * endpoint to try and read data.
2251 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2252 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2253 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2254 DIEPMSK_INTknEPMisMsk
,
2255 hsotg
->regs
+ DIEPMSK
);
2258 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2259 * DMA mode we may need this.
2261 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2262 DIEPMSK_TimeOUTMsk
) : 0) |
2263 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2265 hsotg
->regs
+ DOEPMSK
);
2267 writel(0, hsotg
->regs
+ DAINTMSK
);
2269 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2270 readl(hsotg
->regs
+ DIEPCTL0
),
2271 readl(hsotg
->regs
+ DOEPCTL0
));
2273 /* enable in and out endpoint interrupts */
2274 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2277 * Enable the RXFIFO when in slave mode, as this is how we collect
2278 * the data. In DMA mode, we get events from the FIFO but also
2279 * things we cannot process, so do not use it.
2281 if (!using_dma(hsotg
))
2282 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2284 /* Enable interrupts for EP0 in and out */
2285 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2286 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2288 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2289 udelay(10); /* see openiboot */
2290 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2292 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2295 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2296 * writing to the EPCTL register..
2299 /* set to read 1 8byte packet */
2300 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2301 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2303 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2304 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2306 hsotg
->regs
+ DOEPCTL0
);
2308 /* enable, but don't activate EP0in */
2309 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2310 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2312 s3c_hsotg_enqueue_setup(hsotg
);
2314 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2315 readl(hsotg
->regs
+ DIEPCTL0
),
2316 readl(hsotg
->regs
+ DOEPCTL0
));
2318 /* clear global NAKs */
2319 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2320 hsotg
->regs
+ DCTL
);
2322 /* must be at-least 3ms to allow bus to see disconnect */
2325 /* remove the soft-disconnect and let's go */
2326 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2330 * s3c_hsotg_irq - handle device interrupt
2331 * @irq: The IRQ number triggered
2332 * @pw: The pw value when registered the handler.
2334 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2336 struct s3c_hsotg
*hsotg
= pw
;
2337 int retry_count
= 8;
2341 spin_lock(&hsotg
->lock
);
2343 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2344 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2346 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2347 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2351 if (gintsts
& GINTSTS_OTGInt
) {
2352 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2354 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2356 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2359 if (gintsts
& GINTSTS_SessReqInt
) {
2360 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2361 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2364 if (gintsts
& GINTSTS_EnumDone
) {
2365 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2367 s3c_hsotg_irq_enumdone(hsotg
);
2370 if (gintsts
& GINTSTS_ConIDStsChng
) {
2371 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2372 readl(hsotg
->regs
+ DSTS
),
2373 readl(hsotg
->regs
+ GOTGCTL
));
2375 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2378 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2379 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2380 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2381 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2384 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2386 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2388 s3c_hsotg_epint(hsotg
, ep
, 0);
2391 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2393 s3c_hsotg_epint(hsotg
, ep
, 1);
2397 if (gintsts
& GINTSTS_USBRst
) {
2399 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2401 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2402 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2403 readl(hsotg
->regs
+ GNPTXSTS
));
2405 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2407 if (usb_status
& GOTGCTL_BSESVLD
) {
2408 if (time_after(jiffies
, hsotg
->last_rst
+
2409 msecs_to_jiffies(200))) {
2411 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2414 s3c_hsotg_core_init(hsotg
);
2415 hsotg
->last_rst
= jiffies
;
2420 /* check both FIFOs */
2422 if (gintsts
& GINTSTS_NPTxFEmp
) {
2423 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2426 * Disable the interrupt to stop it happening again
2427 * unless one of these endpoint routines decides that
2428 * it needs re-enabling
2431 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2432 s3c_hsotg_irq_fifoempty(hsotg
, false);
2435 if (gintsts
& GINTSTS_PTxFEmp
) {
2436 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2438 /* See note in GINTSTS_NPTxFEmp */
2440 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2441 s3c_hsotg_irq_fifoempty(hsotg
, true);
2444 if (gintsts
& GINTSTS_RxFLvl
) {
2446 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2447 * we need to retry s3c_hsotg_handle_rx if this is still
2451 s3c_hsotg_handle_rx(hsotg
);
2454 if (gintsts
& GINTSTS_ModeMis
) {
2455 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2456 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2459 if (gintsts
& GINTSTS_USBSusp
) {
2460 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2461 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2463 call_gadget(hsotg
, suspend
);
2464 s3c_hsotg_disconnect(hsotg
);
2467 if (gintsts
& GINTSTS_WkUpInt
) {
2468 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2469 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2471 call_gadget(hsotg
, resume
);
2474 if (gintsts
& GINTSTS_ErlySusp
) {
2475 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2476 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2478 s3c_hsotg_disconnect(hsotg
);
2482 * these next two seem to crop-up occasionally causing the core
2483 * to shutdown the USB transfer, so try clearing them and logging
2487 if (gintsts
& GINTSTS_GOUTNakEff
) {
2488 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2490 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2492 s3c_hsotg_dump(hsotg
);
2495 if (gintsts
& GINTSTS_GINNakEff
) {
2496 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2498 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2500 s3c_hsotg_dump(hsotg
);
2504 * if we've had fifo events, we should try and go around the
2505 * loop again to see if there's any point in returning yet.
2508 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2511 spin_unlock(&hsotg
->lock
);
2517 * s3c_hsotg_ep_enable - enable the given endpoint
2518 * @ep: The USB endpint to configure
2519 * @desc: The USB endpoint descriptor to configure with.
2521 * This is called from the USB gadget code's usb_ep_enable().
2523 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2524 const struct usb_endpoint_descriptor
*desc
)
2526 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2527 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2528 unsigned long flags
;
2529 int index
= hs_ep
->index
;
2537 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2538 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2539 desc
->wMaxPacketSize
, desc
->bInterval
);
2541 /* not to be called for EP0 */
2542 WARN_ON(index
== 0);
2544 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2545 if (dir_in
!= hs_ep
->dir_in
) {
2546 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2550 mps
= usb_endpoint_maxp(desc
);
2552 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2554 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2555 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2557 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2558 __func__
, epctrl
, epctrl_reg
);
2560 spin_lock_irqsave(&hsotg
->lock
, flags
);
2562 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2563 epctrl
|= DxEPCTL_MPS(mps
);
2566 * mark the endpoint as active, otherwise the core may ignore
2567 * transactions entirely for this endpoint
2569 epctrl
|= DxEPCTL_USBActEp
;
2572 * set the NAK status on the endpoint, otherwise we might try and
2573 * do something with data that we've yet got a request to process
2574 * since the RXFIFO will take data for an endpoint even if the
2575 * size register hasn't been set.
2578 epctrl
|= DxEPCTL_SNAK
;
2580 /* update the endpoint state */
2581 hs_ep
->ep
.maxpacket
= mps
;
2583 /* default, set to non-periodic */
2584 hs_ep
->periodic
= 0;
2586 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2587 case USB_ENDPOINT_XFER_ISOC
:
2588 dev_err(hsotg
->dev
, "no current ISOC support\n");
2592 case USB_ENDPOINT_XFER_BULK
:
2593 epctrl
|= DxEPCTL_EPType_Bulk
;
2596 case USB_ENDPOINT_XFER_INT
:
2599 * Allocate our TxFNum by simply using the index
2600 * of the endpoint for the moment. We could do
2601 * something better if the host indicates how
2602 * many FIFOs we are expecting to use.
2605 hs_ep
->periodic
= 1;
2606 epctrl
|= DxEPCTL_TxFNum(index
);
2609 epctrl
|= DxEPCTL_EPType_Intterupt
;
2612 case USB_ENDPOINT_XFER_CONTROL
:
2613 epctrl
|= DxEPCTL_EPType_Control
;
2618 * if the hardware has dedicated fifos, we must give each IN EP
2619 * a unique tx-fifo even if it is non-periodic.
2621 if (dir_in
&& hsotg
->dedicated_fifos
)
2622 epctrl
|= DxEPCTL_TxFNum(index
);
2624 /* for non control endpoints, set PID to D0 */
2626 epctrl
|= DxEPCTL_SetD0PID
;
2628 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2631 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2632 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2633 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2635 /* enable the endpoint interrupt */
2636 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2639 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2644 * s3c_hsotg_ep_disable - disable given endpoint
2645 * @ep: The endpoint to disable.
2647 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2649 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2650 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2651 int dir_in
= hs_ep
->dir_in
;
2652 int index
= hs_ep
->index
;
2653 unsigned long flags
;
2657 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2659 if (ep
== &hsotg
->eps
[0].ep
) {
2660 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2664 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2666 spin_lock_irqsave(&hsotg
->lock
, flags
);
2667 /* terminate all requests with shutdown */
2668 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2671 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2672 ctrl
&= ~DxEPCTL_EPEna
;
2673 ctrl
&= ~DxEPCTL_USBActEp
;
2674 ctrl
|= DxEPCTL_SNAK
;
2676 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2677 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2679 /* disable endpoint interrupts */
2680 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2682 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2687 * on_list - check request is on the given endpoint
2688 * @ep: The endpoint to check.
2689 * @test: The request to test if it is on the endpoint.
2691 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2693 struct s3c_hsotg_req
*req
, *treq
;
2695 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2704 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2705 * @ep: The endpoint to dequeue.
2706 * @req: The request to be removed from a queue.
2708 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2710 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2711 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2712 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2713 unsigned long flags
;
2715 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2717 spin_lock_irqsave(&hs
->lock
, flags
);
2719 if (!on_list(hs_ep
, hs_req
)) {
2720 spin_unlock_irqrestore(&hs
->lock
, flags
);
2724 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2725 spin_unlock_irqrestore(&hs
->lock
, flags
);
2731 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2732 * @ep: The endpoint to set halt.
2733 * @value: Set or unset the halt.
2735 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2737 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2738 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2739 int index
= hs_ep
->index
;
2744 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2746 /* write both IN and OUT control registers */
2748 epreg
= DIEPCTL(index
);
2749 epctl
= readl(hs
->regs
+ epreg
);
2752 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2753 if (epctl
& DxEPCTL_EPEna
)
2754 epctl
|= DxEPCTL_EPDis
;
2756 epctl
&= ~DxEPCTL_Stall
;
2757 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2758 if (xfertype
== DxEPCTL_EPType_Bulk
||
2759 xfertype
== DxEPCTL_EPType_Intterupt
)
2760 epctl
|= DxEPCTL_SetD0PID
;
2763 writel(epctl
, hs
->regs
+ epreg
);
2765 epreg
= DOEPCTL(index
);
2766 epctl
= readl(hs
->regs
+ epreg
);
2769 epctl
|= DxEPCTL_Stall
;
2771 epctl
&= ~DxEPCTL_Stall
;
2772 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2773 if (xfertype
== DxEPCTL_EPType_Bulk
||
2774 xfertype
== DxEPCTL_EPType_Intterupt
)
2775 epctl
|= DxEPCTL_SetD0PID
;
2778 writel(epctl
, hs
->regs
+ epreg
);
2784 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2785 * @ep: The endpoint to set halt.
2786 * @value: Set or unset the halt.
2788 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2790 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2791 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2792 unsigned long flags
= 0;
2795 spin_lock_irqsave(&hs
->lock
, flags
);
2796 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2797 spin_unlock_irqrestore(&hs
->lock
, flags
);
2802 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2803 .enable
= s3c_hsotg_ep_enable
,
2804 .disable
= s3c_hsotg_ep_disable
,
2805 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2806 .free_request
= s3c_hsotg_ep_free_request
,
2807 .queue
= s3c_hsotg_ep_queue_lock
,
2808 .dequeue
= s3c_hsotg_ep_dequeue
,
2809 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2810 /* note, don't believe we have any call for the fifo routines */
2814 * s3c_hsotg_phy_enable - enable platform phy dev
2815 * @hsotg: The driver state
2817 * A wrapper for platform code responsible for controlling
2818 * low-level USB code
2820 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2822 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2824 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2827 usb_phy_init(hsotg
->phy
);
2828 else if (hsotg
->plat
->phy_init
)
2829 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2833 * s3c_hsotg_phy_disable - disable platform phy dev
2834 * @hsotg: The driver state
2836 * A wrapper for platform code responsible for controlling
2837 * low-level USB code
2839 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2841 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2844 usb_phy_shutdown(hsotg
->phy
);
2845 else if (hsotg
->plat
->phy_exit
)
2846 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2850 * s3c_hsotg_init - initalize the usb core
2851 * @hsotg: The driver state
2853 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2855 /* unmask subset of endpoint interrupts */
2857 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2858 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2859 hsotg
->regs
+ DIEPMSK
);
2861 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2862 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2863 hsotg
->regs
+ DOEPMSK
);
2865 writel(0, hsotg
->regs
+ DAINTMSK
);
2867 /* Be in disconnected state until gadget is registered */
2868 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2871 /* post global nak until we're ready */
2872 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2873 hsotg
->regs
+ DCTL
);
2878 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2879 readl(hsotg
->regs
+ GRXFSIZ
),
2880 readl(hsotg
->regs
+ GNPTXFSIZ
));
2882 s3c_hsotg_init_fifo(hsotg
);
2884 /* set the PLL on, remove the HNP/SRP and set the PHY */
2885 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2886 hsotg
->regs
+ GUSBCFG
);
2888 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2889 hsotg
->regs
+ GAHBCFG
);
2893 * s3c_hsotg_udc_start - prepare the udc for work
2894 * @gadget: The usb gadget state
2895 * @driver: The usb gadget driver
2897 * Perform initialization to prepare udc device and driver
2900 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2901 struct usb_gadget_driver
*driver
)
2903 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2907 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2912 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2916 if (driver
->max_speed
< USB_SPEED_FULL
)
2917 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2919 if (!driver
->setup
) {
2920 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2924 WARN_ON(hsotg
->driver
);
2926 driver
->driver
.bus
= NULL
;
2927 hsotg
->driver
= driver
;
2928 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2929 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2931 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2934 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2938 hsotg
->last_rst
= jiffies
;
2939 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2943 hsotg
->driver
= NULL
;
2948 * s3c_hsotg_udc_stop - stop the udc
2949 * @gadget: The usb gadget state
2950 * @driver: The usb gadget driver
2952 * Stop udc hw block and stay tunned for future transmissions
2954 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
2955 struct usb_gadget_driver
*driver
)
2957 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2958 unsigned long flags
= 0;
2964 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2967 /* all endpoints should be shutdown */
2968 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2969 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
2971 spin_lock_irqsave(&hsotg
->lock
, flags
);
2973 s3c_hsotg_phy_disable(hsotg
);
2974 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
2976 hsotg
->driver
= NULL
;
2977 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2979 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2981 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
2982 driver
->driver
.name
);
2988 * s3c_hsotg_gadget_getframe - read the frame number
2989 * @gadget: The usb gadget state
2991 * Read the {micro} frame number
2993 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
2995 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
2999 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3000 * @gadget: The usb gadget state
3001 * @is_on: Current state of the USB PHY
3003 * Connect/Disconnect the USB PHY pullup
3005 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3007 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3008 unsigned long flags
= 0;
3010 dev_dbg(hsotg
->dev
, "%s: is_in: %d\n", __func__
, is_on
);
3012 spin_lock_irqsave(&hsotg
->lock
, flags
);
3014 s3c_hsotg_phy_enable(hsotg
);
3015 s3c_hsotg_core_init(hsotg
);
3017 s3c_hsotg_disconnect(hsotg
);
3018 s3c_hsotg_phy_disable(hsotg
);
3021 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3022 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3027 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3028 .get_frame
= s3c_hsotg_gadget_getframe
,
3029 .udc_start
= s3c_hsotg_udc_start
,
3030 .udc_stop
= s3c_hsotg_udc_stop
,
3031 .pullup
= s3c_hsotg_pullup
,
3035 * s3c_hsotg_initep - initialise a single endpoint
3036 * @hsotg: The device state.
3037 * @hs_ep: The endpoint to be initialised.
3038 * @epnum: The endpoint number
3040 * Initialise the given endpoint (as part of the probe and device state
3041 * creation) to give to the gadget driver. Setup the endpoint name, any
3042 * direction information and other state that may be required.
3044 static void s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3045 struct s3c_hsotg_ep
*hs_ep
,
3053 else if ((epnum
% 2) == 0) {
3060 hs_ep
->index
= epnum
;
3062 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3064 INIT_LIST_HEAD(&hs_ep
->queue
);
3065 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3067 /* add to the list of endpoints known by the gadget driver */
3069 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3071 hs_ep
->parent
= hsotg
;
3072 hs_ep
->ep
.name
= hs_ep
->name
;
3073 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
3074 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3077 * Read the FIFO size for the Periodic TX FIFO, even if we're
3078 * an OUT endpoint, we may as well do this if in future the
3079 * code is changed to make each endpoint's direction changeable.
3082 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3083 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3086 * if we're using dma, we need to set the next-endpoint pointer
3087 * to be something valid.
3090 if (using_dma(hsotg
)) {
3091 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3092 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3093 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3098 * s3c_hsotg_hw_cfg - read HW configuration registers
3099 * @param: The device state
3101 * Read the USB core HW configuration registers
3103 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3106 /* check hardware configuration */
3108 cfg2
= readl(hsotg
->regs
+ 0x48);
3109 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3111 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3113 cfg4
= readl(hsotg
->regs
+ 0x50);
3114 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3116 dev_info(hsotg
->dev
, "%s fifos\n",
3117 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3121 * s3c_hsotg_dump - dump state of the udc
3122 * @param: The device state
3124 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3127 struct device
*dev
= hsotg
->dev
;
3128 void __iomem
*regs
= hsotg
->regs
;
3132 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3133 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3134 readl(regs
+ DIEPMSK
));
3136 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3137 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3139 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3140 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3142 /* show periodic fifo settings */
3144 for (idx
= 1; idx
<= 15; idx
++) {
3145 val
= readl(regs
+ DPTXFSIZn(idx
));
3146 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3147 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3148 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3151 for (idx
= 0; idx
< 15; idx
++) {
3153 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3154 readl(regs
+ DIEPCTL(idx
)),
3155 readl(regs
+ DIEPTSIZ(idx
)),
3156 readl(regs
+ DIEPDMA(idx
)));
3158 val
= readl(regs
+ DOEPCTL(idx
));
3160 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3161 idx
, readl(regs
+ DOEPCTL(idx
)),
3162 readl(regs
+ DOEPTSIZ(idx
)),
3163 readl(regs
+ DOEPDMA(idx
)));
3167 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3168 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3173 * state_show - debugfs: show overall driver and device state.
3174 * @seq: The seq file to write to.
3175 * @v: Unused parameter.
3177 * This debugfs entry shows the overall state of the hardware and
3178 * some general information about each of the endpoints available
3181 static int state_show(struct seq_file
*seq
, void *v
)
3183 struct s3c_hsotg
*hsotg
= seq
->private;
3184 void __iomem
*regs
= hsotg
->regs
;
3187 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3190 readl(regs
+ DSTS
));
3192 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3193 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3195 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3196 readl(regs
+ GINTMSK
),
3197 readl(regs
+ GINTSTS
));
3199 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3200 readl(regs
+ DAINTMSK
),
3201 readl(regs
+ DAINT
));
3203 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3204 readl(regs
+ GNPTXSTS
),
3205 readl(regs
+ GRXSTSR
));
3207 seq_printf(seq
, "\nEndpoint status:\n");
3209 for (idx
= 0; idx
< 15; idx
++) {
3212 in
= readl(regs
+ DIEPCTL(idx
));
3213 out
= readl(regs
+ DOEPCTL(idx
));
3215 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3218 in
= readl(regs
+ DIEPTSIZ(idx
));
3219 out
= readl(regs
+ DOEPTSIZ(idx
));
3221 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3224 seq_printf(seq
, "\n");
3230 static int state_open(struct inode
*inode
, struct file
*file
)
3232 return single_open(file
, state_show
, inode
->i_private
);
3235 static const struct file_operations state_fops
= {
3236 .owner
= THIS_MODULE
,
3239 .llseek
= seq_lseek
,
3240 .release
= single_release
,
3244 * fifo_show - debugfs: show the fifo information
3245 * @seq: The seq_file to write data to.
3246 * @v: Unused parameter.
3248 * Show the FIFO information for the overall fifo and all the
3249 * periodic transmission FIFOs.
3251 static int fifo_show(struct seq_file
*seq
, void *v
)
3253 struct s3c_hsotg
*hsotg
= seq
->private;
3254 void __iomem
*regs
= hsotg
->regs
;
3258 seq_printf(seq
, "Non-periodic FIFOs:\n");
3259 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3261 val
= readl(regs
+ GNPTXFSIZ
);
3262 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3263 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3264 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3266 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3268 for (idx
= 1; idx
<= 15; idx
++) {
3269 val
= readl(regs
+ DPTXFSIZn(idx
));
3271 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3272 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3273 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3279 static int fifo_open(struct inode
*inode
, struct file
*file
)
3281 return single_open(file
, fifo_show
, inode
->i_private
);
3284 static const struct file_operations fifo_fops
= {
3285 .owner
= THIS_MODULE
,
3288 .llseek
= seq_lseek
,
3289 .release
= single_release
,
3293 static const char *decode_direction(int is_in
)
3295 return is_in
? "in" : "out";
3299 * ep_show - debugfs: show the state of an endpoint.
3300 * @seq: The seq_file to write data to.
3301 * @v: Unused parameter.
3303 * This debugfs entry shows the state of the given endpoint (one is
3304 * registered for each available).
3306 static int ep_show(struct seq_file
*seq
, void *v
)
3308 struct s3c_hsotg_ep
*ep
= seq
->private;
3309 struct s3c_hsotg
*hsotg
= ep
->parent
;
3310 struct s3c_hsotg_req
*req
;
3311 void __iomem
*regs
= hsotg
->regs
;
3312 int index
= ep
->index
;
3313 int show_limit
= 15;
3314 unsigned long flags
;
3316 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3317 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3319 /* first show the register state */
3321 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3322 readl(regs
+ DIEPCTL(index
)),
3323 readl(regs
+ DOEPCTL(index
)));
3325 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3326 readl(regs
+ DIEPDMA(index
)),
3327 readl(regs
+ DOEPDMA(index
)));
3329 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3330 readl(regs
+ DIEPINT(index
)),
3331 readl(regs
+ DOEPINT(index
)));
3333 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3334 readl(regs
+ DIEPTSIZ(index
)),
3335 readl(regs
+ DOEPTSIZ(index
)));
3337 seq_printf(seq
, "\n");
3338 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3339 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3341 seq_printf(seq
, "request list (%p,%p):\n",
3342 ep
->queue
.next
, ep
->queue
.prev
);
3344 spin_lock_irqsave(&hsotg
->lock
, flags
);
3346 list_for_each_entry(req
, &ep
->queue
, queue
) {
3347 if (--show_limit
< 0) {
3348 seq_printf(seq
, "not showing more requests...\n");
3352 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3353 req
== ep
->req
? '*' : ' ',
3354 req
, req
->req
.length
, req
->req
.buf
);
3355 seq_printf(seq
, "%d done, res %d\n",
3356 req
->req
.actual
, req
->req
.status
);
3359 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3364 static int ep_open(struct inode
*inode
, struct file
*file
)
3366 return single_open(file
, ep_show
, inode
->i_private
);
3369 static const struct file_operations ep_fops
= {
3370 .owner
= THIS_MODULE
,
3373 .llseek
= seq_lseek
,
3374 .release
= single_release
,
3378 * s3c_hsotg_create_debug - create debugfs directory and files
3379 * @hsotg: The driver state
3381 * Create the debugfs files to allow the user to get information
3382 * about the state of the system. The directory name is created
3383 * with the same name as the device itself, in case we end up
3384 * with multiple blocks in future systems.
3386 static void s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3388 struct dentry
*root
;
3391 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3392 hsotg
->debug_root
= root
;
3394 dev_err(hsotg
->dev
, "cannot create debug root\n");
3398 /* create general state file */
3400 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3401 hsotg
, &state_fops
);
3403 if (IS_ERR(hsotg
->debug_file
))
3404 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3406 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3409 if (IS_ERR(hsotg
->debug_fifo
))
3410 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3412 /* create one file for each endpoint */
3414 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3415 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3417 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3418 root
, ep
, &ep_fops
);
3420 if (IS_ERR(ep
->debugfs
))
3421 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3427 * s3c_hsotg_delete_debug - cleanup debugfs entries
3428 * @hsotg: The driver state
3430 * Cleanup (remove) the debugfs files for use on module exit.
3432 static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3436 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3437 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3438 debugfs_remove(ep
->debugfs
);
3441 debugfs_remove(hsotg
->debug_file
);
3442 debugfs_remove(hsotg
->debug_fifo
);
3443 debugfs_remove(hsotg
->debug_root
);
3447 * s3c_hsotg_probe - probe function for hsotg driver
3448 * @pdev: The platform information for the driver
3451 static int s3c_hsotg_probe(struct platform_device
*pdev
)
3453 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3454 struct usb_phy
*phy
;
3455 struct device
*dev
= &pdev
->dev
;
3456 struct s3c_hsotg_ep
*eps
;
3457 struct s3c_hsotg
*hsotg
;
3458 struct resource
*res
;
3463 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3465 dev_err(dev
, "cannot get memory\n");
3469 phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
3471 /* Fallback for pdata */
3472 plat
= pdev
->dev
.platform_data
;
3474 dev_err(&pdev
->dev
, "no platform data or transceiver defined\n");
3475 return -EPROBE_DEFER
;
3485 hsotg
->clk
= devm_clk_get(&pdev
->dev
, "otg");
3486 if (IS_ERR(hsotg
->clk
)) {
3487 dev_err(dev
, "cannot get otg clock\n");
3488 return PTR_ERR(hsotg
->clk
);
3491 platform_set_drvdata(pdev
, hsotg
);
3493 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3495 hsotg
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
3496 if (IS_ERR(hsotg
->regs
)) {
3497 ret
= PTR_ERR(hsotg
->regs
);
3501 ret
= platform_get_irq(pdev
, 0);
3503 dev_err(dev
, "cannot find IRQ\n");
3507 spin_lock_init(&hsotg
->lock
);
3511 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3512 dev_name(dev
), hsotg
);
3514 dev_err(dev
, "cannot claim IRQ\n");
3518 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3520 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3521 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3522 hsotg
->gadget
.name
= dev_name(dev
);
3524 /* reset the system */
3526 clk_prepare_enable(hsotg
->clk
);
3530 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3531 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3533 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3536 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3540 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3544 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3548 /* usb phy enable */
3549 s3c_hsotg_phy_enable(hsotg
);
3551 s3c_hsotg_corereset(hsotg
);
3552 s3c_hsotg_init(hsotg
);
3553 s3c_hsotg_hw_cfg(hsotg
);
3555 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3557 if (hsotg
->num_of_eps
== 0) {
3558 dev_err(dev
, "wrong number of EPs (zero)\n");
3563 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3566 dev_err(dev
, "cannot get memory\n");
3573 /* setup endpoint information */
3575 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3576 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3578 /* allocate EP0 request */
3580 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3582 if (!hsotg
->ctrl_req
) {
3583 dev_err(dev
, "failed to allocate ctrl req\n");
3588 /* initialise the endpoints now the core has been initialised */
3589 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3590 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3592 /* disable power and clock */
3594 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3597 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3601 s3c_hsotg_phy_disable(hsotg
);
3603 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3607 s3c_hsotg_create_debug(hsotg
);
3609 s3c_hsotg_dump(hsotg
);
3616 s3c_hsotg_phy_disable(hsotg
);
3618 clk_disable_unprepare(hsotg
->clk
);
3624 * s3c_hsotg_remove - remove function for hsotg driver
3625 * @pdev: The platform information for the driver
3627 static int s3c_hsotg_remove(struct platform_device
*pdev
)
3629 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3631 usb_del_gadget_udc(&hsotg
->gadget
);
3633 s3c_hsotg_delete_debug(hsotg
);
3635 if (hsotg
->driver
) {
3636 /* should have been done already by driver model core */
3637 usb_gadget_unregister_driver(hsotg
->driver
);
3640 s3c_hsotg_phy_disable(hsotg
);
3641 clk_disable_unprepare(hsotg
->clk
);
3647 #define s3c_hsotg_suspend NULL
3648 #define s3c_hsotg_resume NULL
3651 static struct platform_driver s3c_hsotg_driver
= {
3653 .name
= "s3c-hsotg",
3654 .owner
= THIS_MODULE
,
3656 .probe
= s3c_hsotg_probe
,
3657 .remove
= s3c_hsotg_remove
,
3658 .suspend
= s3c_hsotg_suspend
,
3659 .resume
= s3c_hsotg_resume
,
3662 module_platform_driver(s3c_hsotg_driver
);
3664 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3665 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3666 MODULE_LICENSE("GPL");
3667 MODULE_ALIAS("platform:s3c-hsotg");