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[DRIVER MODEL] Convert platform drivers to use struct platform_driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / omap_udc.c
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #undef DEBUG
23 #undef VERBOSE
24
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/types.h>
30 #include <linux/errno.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/timer.h>
36 #include <linux/list.h>
37 #include <linux/interrupt.h>
38 #include <linux/proc_fs.h>
39 #include <linux/mm.h>
40 #include <linux/moduleparam.h>
41 #include <linux/platform_device.h>
42 #include <linux/usb_ch9.h>
43 #include <linux/usb_gadget.h>
44 #include <linux/usb_otg.h>
45 #include <linux/dma-mapping.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/system.h>
51 #include <asm/unaligned.h>
52 #include <asm/mach-types.h>
53
54 #include <asm/arch/dma.h>
55 #include <asm/arch/usb.h>
56
57 #include "omap_udc.h"
58
59 #undef USB_TRACE
60
61 /* bulk DMA seems to be behaving for both IN and OUT */
62 #define USE_DMA
63
64 /* ISO too */
65 #define USE_ISO
66
67 #define DRIVER_DESC "OMAP UDC driver"
68 #define DRIVER_VERSION "4 October 2004"
69
70 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
71
72
73 /*
74 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
75 * D+ pullup to allow enumeration. That's too early for the gadget
76 * framework to use from usb_endpoint_enable(), which happens after
77 * enumeration as part of activating an interface. (But if we add an
78 * optional new "UDC not yet running" state to the gadget driver model,
79 * even just during driver binding, the endpoint autoconfig logic is the
80 * natural spot to manufacture new endpoints.)
81 *
82 * So instead of using endpoint enable calls to control the hardware setup,
83 * this driver defines a "fifo mode" parameter. It's used during driver
84 * initialization to choose among a set of pre-defined endpoint configs.
85 * See omap_udc_setup() for available modes, or to add others. That code
86 * lives in an init section, so use this driver as a module if you need
87 * to change the fifo mode after the kernel boots.
88 *
89 * Gadget drivers normally ignore endpoints they don't care about, and
90 * won't include them in configuration descriptors. That means only
91 * misbehaving hosts would even notice they exist.
92 */
93 #ifdef USE_ISO
94 static unsigned fifo_mode = 3;
95 #else
96 static unsigned fifo_mode = 0;
97 #endif
98
99 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
100 * boot parameter "omap_udc:fifo_mode=42"
101 */
102 module_param (fifo_mode, uint, 0);
103 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
104
105 #ifdef USE_DMA
106 static unsigned use_dma = 1;
107
108 /* "modprobe omap_udc use_dma=y", or else as a kernel
109 * boot parameter "omap_udc:use_dma=y"
110 */
111 module_param (use_dma, bool, 0);
112 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
113 #else /* !USE_DMA */
114
115 /* save a bit of code */
116 #define use_dma 0
117 #endif /* !USE_DMA */
118
119
120 static const char driver_name [] = "omap_udc";
121 static const char driver_desc [] = DRIVER_DESC;
122
123 /*-------------------------------------------------------------------------*/
124
125 /* there's a notion of "current endpoint" for modifying endpoint
126 * state, and PIO access to its FIFO.
127 */
128
129 static void use_ep(struct omap_ep *ep, u16 select)
130 {
131 u16 num = ep->bEndpointAddress & 0x0f;
132
133 if (ep->bEndpointAddress & USB_DIR_IN)
134 num |= UDC_EP_DIR;
135 UDC_EP_NUM_REG = num | select;
136 /* when select, MUST deselect later !! */
137 }
138
139 static inline void deselect_ep(void)
140 {
141 UDC_EP_NUM_REG &= ~UDC_EP_SEL;
142 /* 6 wait states before TX will happen */
143 }
144
145 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
146
147 /*-------------------------------------------------------------------------*/
148
149 static int omap_ep_enable(struct usb_ep *_ep,
150 const struct usb_endpoint_descriptor *desc)
151 {
152 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
153 struct omap_udc *udc;
154 unsigned long flags;
155 u16 maxp;
156
157 /* catch various bogus parameters */
158 if (!_ep || !desc || ep->desc
159 || desc->bDescriptorType != USB_DT_ENDPOINT
160 || ep->bEndpointAddress != desc->bEndpointAddress
161 || ep->maxpacket < le16_to_cpu
162 (desc->wMaxPacketSize)) {
163 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
164 return -EINVAL;
165 }
166 maxp = le16_to_cpu (desc->wMaxPacketSize);
167 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
168 && maxp != ep->maxpacket)
169 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
170 || !desc->wMaxPacketSize) {
171 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
172 return -ERANGE;
173 }
174
175 #ifdef USE_ISO
176 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
177 && desc->bInterval != 1)) {
178 /* hardware wants period = 1; USB allows 2^(Interval-1) */
179 DBG("%s, unsupported ISO period %dms\n", _ep->name,
180 1 << (desc->bInterval - 1));
181 return -EDOM;
182 }
183 #else
184 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
185 DBG("%s, ISO nyet\n", _ep->name);
186 return -EDOM;
187 }
188 #endif
189
190 /* xfer types must match, except that interrupt ~= bulk */
191 if (ep->bmAttributes != desc->bmAttributes
192 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
193 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
194 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
195 return -EINVAL;
196 }
197
198 udc = ep->udc;
199 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
200 DBG("%s, bogus device state\n", __FUNCTION__);
201 return -ESHUTDOWN;
202 }
203
204 spin_lock_irqsave(&udc->lock, flags);
205
206 ep->desc = desc;
207 ep->irqs = 0;
208 ep->stopped = 0;
209 ep->ep.maxpacket = maxp;
210
211 /* set endpoint to initial state */
212 ep->dma_channel = 0;
213 ep->has_dma = 0;
214 ep->lch = -1;
215 use_ep(ep, UDC_EP_SEL);
216 UDC_CTRL_REG = udc->clr_halt;
217 ep->ackwait = 0;
218 deselect_ep();
219
220 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
221 list_add(&ep->iso, &udc->iso);
222
223 /* maybe assign a DMA channel to this endpoint */
224 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
225 /* FIXME ISO can dma, but prefers first channel */
226 dma_channel_claim(ep, 0);
227
228 /* PIO OUT may RX packets */
229 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
230 && !ep->has_dma
231 && !(ep->bEndpointAddress & USB_DIR_IN)) {
232 UDC_CTRL_REG = UDC_SET_FIFO_EN;
233 ep->ackwait = 1 + ep->double_buf;
234 }
235
236 spin_unlock_irqrestore(&udc->lock, flags);
237 VDBG("%s enabled\n", _ep->name);
238 return 0;
239 }
240
241 static void nuke(struct omap_ep *, int status);
242
243 static int omap_ep_disable(struct usb_ep *_ep)
244 {
245 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
246 unsigned long flags;
247
248 if (!_ep || !ep->desc) {
249 DBG("%s, %s not enabled\n", __FUNCTION__,
250 _ep ? ep->ep.name : NULL);
251 return -EINVAL;
252 }
253
254 spin_lock_irqsave(&ep->udc->lock, flags);
255 ep->desc = NULL;
256 nuke (ep, -ESHUTDOWN);
257 ep->ep.maxpacket = ep->maxpacket;
258 ep->has_dma = 0;
259 UDC_CTRL_REG = UDC_SET_HALT;
260 list_del_init(&ep->iso);
261 del_timer(&ep->timer);
262
263 spin_unlock_irqrestore(&ep->udc->lock, flags);
264
265 VDBG("%s disabled\n", _ep->name);
266 return 0;
267 }
268
269 /*-------------------------------------------------------------------------*/
270
271 static struct usb_request *
272 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
273 {
274 struct omap_req *req;
275
276 req = kmalloc(sizeof *req, gfp_flags);
277 if (req) {
278 memset (req, 0, sizeof *req);
279 req->req.dma = DMA_ADDR_INVALID;
280 INIT_LIST_HEAD (&req->queue);
281 }
282 return &req->req;
283 }
284
285 static void
286 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
287 {
288 struct omap_req *req = container_of(_req, struct omap_req, req);
289
290 if (_req)
291 kfree (req);
292 }
293
294 /*-------------------------------------------------------------------------*/
295
296 static void *
297 omap_alloc_buffer(
298 struct usb_ep *_ep,
299 unsigned bytes,
300 dma_addr_t *dma,
301 gfp_t gfp_flags
302 )
303 {
304 void *retval;
305 struct omap_ep *ep;
306
307 ep = container_of(_ep, struct omap_ep, ep);
308 if (use_dma && ep->has_dma) {
309 static int warned;
310 if (!warned && bytes < PAGE_SIZE) {
311 dev_warn(ep->udc->gadget.dev.parent,
312 "using dma_alloc_coherent for "
313 "small allocations wastes memory\n");
314 warned++;
315 }
316 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
317 bytes, dma, gfp_flags);
318 }
319
320 retval = kmalloc(bytes, gfp_flags);
321 if (retval)
322 *dma = virt_to_phys(retval);
323 return retval;
324 }
325
326 static void omap_free_buffer(
327 struct usb_ep *_ep,
328 void *buf,
329 dma_addr_t dma,
330 unsigned bytes
331 )
332 {
333 struct omap_ep *ep;
334
335 ep = container_of(_ep, struct omap_ep, ep);
336 if (use_dma && _ep && ep->has_dma)
337 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
338 else
339 kfree (buf);
340 }
341
342 /*-------------------------------------------------------------------------*/
343
344 static void
345 done(struct omap_ep *ep, struct omap_req *req, int status)
346 {
347 unsigned stopped = ep->stopped;
348
349 list_del_init(&req->queue);
350
351 if (req->req.status == -EINPROGRESS)
352 req->req.status = status;
353 else
354 status = req->req.status;
355
356 if (use_dma && ep->has_dma) {
357 if (req->mapped) {
358 dma_unmap_single(ep->udc->gadget.dev.parent,
359 req->req.dma, req->req.length,
360 (ep->bEndpointAddress & USB_DIR_IN)
361 ? DMA_TO_DEVICE
362 : DMA_FROM_DEVICE);
363 req->req.dma = DMA_ADDR_INVALID;
364 req->mapped = 0;
365 } else
366 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
367 req->req.dma, req->req.length,
368 (ep->bEndpointAddress & USB_DIR_IN)
369 ? DMA_TO_DEVICE
370 : DMA_FROM_DEVICE);
371 }
372
373 #ifndef USB_TRACE
374 if (status && status != -ESHUTDOWN)
375 #endif
376 VDBG("complete %s req %p stat %d len %u/%u\n",
377 ep->ep.name, &req->req, status,
378 req->req.actual, req->req.length);
379
380 /* don't modify queue heads during completion callback */
381 ep->stopped = 1;
382 spin_unlock(&ep->udc->lock);
383 req->req.complete(&ep->ep, &req->req);
384 spin_lock(&ep->udc->lock);
385 ep->stopped = stopped;
386 }
387
388 /*-------------------------------------------------------------------------*/
389
390 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
391 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
392
393 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
394 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
395
396 static inline int
397 write_packet(u8 *buf, struct omap_req *req, unsigned max)
398 {
399 unsigned len;
400 u16 *wp;
401
402 len = min(req->req.length - req->req.actual, max);
403 req->req.actual += len;
404
405 max = len;
406 if (likely((((int)buf) & 1) == 0)) {
407 wp = (u16 *)buf;
408 while (max >= 2) {
409 UDC_DATA_REG = *wp++;
410 max -= 2;
411 }
412 buf = (u8 *)wp;
413 }
414 while (max--)
415 *(volatile u8 *)&UDC_DATA_REG = *buf++;
416 return len;
417 }
418
419 // FIXME change r/w fifo calling convention
420
421
422 // return: 0 = still running, 1 = completed, negative = errno
423 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
424 {
425 u8 *buf;
426 unsigned count;
427 int is_last;
428 u16 ep_stat;
429
430 buf = req->req.buf + req->req.actual;
431 prefetch(buf);
432
433 /* PIO-IN isn't double buffered except for iso */
434 ep_stat = UDC_STAT_FLG_REG;
435 if (ep_stat & UDC_FIFO_UNWRITABLE)
436 return 0;
437
438 count = ep->ep.maxpacket;
439 count = write_packet(buf, req, count);
440 UDC_CTRL_REG = UDC_SET_FIFO_EN;
441 ep->ackwait = 1;
442
443 /* last packet is often short (sometimes a zlp) */
444 if (count != ep->ep.maxpacket)
445 is_last = 1;
446 else if (req->req.length == req->req.actual
447 && !req->req.zero)
448 is_last = 1;
449 else
450 is_last = 0;
451
452 /* NOTE: requests complete when all IN data is in a
453 * FIFO (or sometimes later, if a zlp was needed).
454 * Use usb_ep_fifo_status() where needed.
455 */
456 if (is_last)
457 done(ep, req, 0);
458 return is_last;
459 }
460
461 static inline int
462 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
463 {
464 unsigned len;
465 u16 *wp;
466
467 len = min(req->req.length - req->req.actual, avail);
468 req->req.actual += len;
469 avail = len;
470
471 if (likely((((int)buf) & 1) == 0)) {
472 wp = (u16 *)buf;
473 while (avail >= 2) {
474 *wp++ = UDC_DATA_REG;
475 avail -= 2;
476 }
477 buf = (u8 *)wp;
478 }
479 while (avail--)
480 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
481 return len;
482 }
483
484 // return: 0 = still running, 1 = queue empty, negative = errno
485 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
486 {
487 u8 *buf;
488 unsigned count, avail;
489 int is_last;
490
491 buf = req->req.buf + req->req.actual;
492 prefetchw(buf);
493
494 for (;;) {
495 u16 ep_stat = UDC_STAT_FLG_REG;
496
497 is_last = 0;
498 if (ep_stat & FIFO_EMPTY) {
499 if (!ep->double_buf)
500 break;
501 ep->fnf = 1;
502 }
503 if (ep_stat & UDC_EP_HALTED)
504 break;
505
506 if (ep_stat & UDC_FIFO_FULL)
507 avail = ep->ep.maxpacket;
508 else {
509 avail = UDC_RXFSTAT_REG;
510 ep->fnf = ep->double_buf;
511 }
512 count = read_packet(buf, req, avail);
513
514 /* partial packet reads may not be errors */
515 if (count < ep->ep.maxpacket) {
516 is_last = 1;
517 /* overflowed this request? flush extra data */
518 if (count != avail) {
519 req->req.status = -EOVERFLOW;
520 avail -= count;
521 while (avail--)
522 (void) *(volatile u8 *)&UDC_DATA_REG;
523 }
524 } else if (req->req.length == req->req.actual)
525 is_last = 1;
526 else
527 is_last = 0;
528
529 if (!ep->bEndpointAddress)
530 break;
531 if (is_last)
532 done(ep, req, 0);
533 break;
534 }
535 return is_last;
536 }
537
538 /*-------------------------------------------------------------------------*/
539
540 static inline dma_addr_t dma_csac(unsigned lch)
541 {
542 dma_addr_t csac;
543
544 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
545 * read before the DMA controller finished disabling the channel.
546 */
547 csac = omap_readw(OMAP_DMA_CSAC(lch));
548 if (csac == 0)
549 csac = omap_readw(OMAP_DMA_CSAC(lch));
550 return csac;
551 }
552
553 static inline dma_addr_t dma_cdac(unsigned lch)
554 {
555 dma_addr_t cdac;
556
557 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
558 * read before the DMA controller finished disabling the channel.
559 */
560 cdac = omap_readw(OMAP_DMA_CDAC(lch));
561 if (cdac == 0)
562 cdac = omap_readw(OMAP_DMA_CDAC(lch));
563 return cdac;
564 }
565
566 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
567 {
568 dma_addr_t end;
569
570 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
571 * the last transfer's bytecount by more than a FIFO's worth.
572 */
573 if (cpu_is_omap15xx())
574 return 0;
575
576 end = dma_csac(ep->lch);
577 if (end == ep->dma_counter)
578 return 0;
579
580 end |= start & (0xffff << 16);
581 if (end < start)
582 end += 0x10000;
583 return end - start;
584 }
585
586 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
587 ? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \
588 : dma_cdac(x))
589
590 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
591 {
592 dma_addr_t end;
593
594 end = DMA_DEST_LAST(ep->lch);
595 if (end == ep->dma_counter)
596 return 0;
597
598 end |= start & (0xffff << 16);
599 if (cpu_is_omap15xx())
600 end++;
601 if (end < start)
602 end += 0x10000;
603 return end - start;
604 }
605
606
607 /* Each USB transfer request using DMA maps to one or more DMA transfers.
608 * When DMA completion isn't request completion, the UDC continues with
609 * the next DMA transfer for that USB transfer.
610 */
611
612 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
613 {
614 u16 txdma_ctrl;
615 unsigned length = req->req.length - req->req.actual;
616 const int sync_mode = cpu_is_omap15xx()
617 ? OMAP_DMA_SYNC_FRAME
618 : OMAP_DMA_SYNC_ELEMENT;
619
620 /* measure length in either bytes or packets */
621 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
622 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
623 txdma_ctrl = UDC_TXN_EOT | length;
624 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
625 length, 1, sync_mode);
626 } else {
627 length = min(length / ep->maxpacket,
628 (unsigned) UDC_TXN_TSC + 1);
629 txdma_ctrl = length;
630 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
631 ep->ep.maxpacket >> 1, length, sync_mode);
632 length *= ep->maxpacket;
633 }
634 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
635 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
636
637 omap_start_dma(ep->lch);
638 ep->dma_counter = dma_csac(ep->lch);
639 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
640 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
641 req->dma_bytes = length;
642 }
643
644 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
645 {
646 if (status == 0) {
647 req->req.actual += req->dma_bytes;
648
649 /* return if this request needs to send data or zlp */
650 if (req->req.actual < req->req.length)
651 return;
652 if (req->req.zero
653 && req->dma_bytes != 0
654 && (req->req.actual % ep->maxpacket) == 0)
655 return;
656 } else
657 req->req.actual += dma_src_len(ep, req->req.dma
658 + req->req.actual);
659
660 /* tx completion */
661 omap_stop_dma(ep->lch);
662 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
663 done(ep, req, status);
664 }
665
666 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
667 {
668 unsigned packets;
669
670 /* NOTE: we filtered out "short reads" before, so we know
671 * the buffer has only whole numbers of packets.
672 */
673
674 /* set up this DMA transfer, enable the fifo, start */
675 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
676 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
677 req->dma_bytes = packets * ep->ep.maxpacket;
678 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
679 ep->ep.maxpacket >> 1, packets,
680 OMAP_DMA_SYNC_ELEMENT);
681 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
682 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
683 ep->dma_counter = DMA_DEST_LAST(ep->lch);
684
685 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
686 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
687 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
688 UDC_CTRL_REG = UDC_SET_FIFO_EN;
689
690 omap_start_dma(ep->lch);
691 }
692
693 static void
694 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
695 {
696 u16 count;
697
698 if (status == 0)
699 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
700 count = dma_dest_len(ep, req->req.dma + req->req.actual);
701 count += req->req.actual;
702 if (one)
703 count--;
704 if (count <= req->req.length)
705 req->req.actual = count;
706
707 if (count != req->dma_bytes || status)
708 omap_stop_dma(ep->lch);
709
710 /* if this wasn't short, request may need another transfer */
711 else if (req->req.actual < req->req.length)
712 return;
713
714 /* rx completion */
715 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
716 done(ep, req, status);
717 }
718
719 static void dma_irq(struct omap_udc *udc, u16 irq_src)
720 {
721 u16 dman_stat = UDC_DMAN_STAT_REG;
722 struct omap_ep *ep;
723 struct omap_req *req;
724
725 /* IN dma: tx to host */
726 if (irq_src & UDC_TXN_DONE) {
727 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
728 ep->irqs++;
729 /* can see TXN_DONE after dma abort */
730 if (!list_empty(&ep->queue)) {
731 req = container_of(ep->queue.next,
732 struct omap_req, queue);
733 finish_in_dma(ep, req, 0);
734 }
735 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
736
737 if (!list_empty (&ep->queue)) {
738 req = container_of(ep->queue.next,
739 struct omap_req, queue);
740 next_in_dma(ep, req);
741 }
742 }
743
744 /* OUT dma: rx from host */
745 if (irq_src & UDC_RXN_EOT) {
746 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
747 ep->irqs++;
748 /* can see RXN_EOT after dma abort */
749 if (!list_empty(&ep->queue)) {
750 req = container_of(ep->queue.next,
751 struct omap_req, queue);
752 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
753 }
754 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
755
756 if (!list_empty (&ep->queue)) {
757 req = container_of(ep->queue.next,
758 struct omap_req, queue);
759 next_out_dma(ep, req);
760 }
761 }
762
763 if (irq_src & UDC_RXN_CNT) {
764 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
765 ep->irqs++;
766 /* omap15xx does this unasked... */
767 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
768 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
769 }
770 }
771
772 static void dma_error(int lch, u16 ch_status, void *data)
773 {
774 struct omap_ep *ep = data;
775
776 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
777 /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
778 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
779
780 /* complete current transfer ... */
781 }
782
783 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
784 {
785 u16 reg;
786 int status, restart, is_in;
787
788 is_in = ep->bEndpointAddress & USB_DIR_IN;
789 if (is_in)
790 reg = UDC_TXDMA_CFG_REG;
791 else
792 reg = UDC_RXDMA_CFG_REG;
793 reg |= UDC_DMA_REQ; /* "pulse" activated */
794
795 ep->dma_channel = 0;
796 ep->lch = -1;
797 if (channel == 0 || channel > 3) {
798 if ((reg & 0x0f00) == 0)
799 channel = 3;
800 else if ((reg & 0x00f0) == 0)
801 channel = 2;
802 else if ((reg & 0x000f) == 0) /* preferred for ISO */
803 channel = 1;
804 else {
805 status = -EMLINK;
806 goto just_restart;
807 }
808 }
809 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
810 ep->dma_channel = channel;
811
812 if (is_in) {
813 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
814 ep->ep.name, dma_error, ep, &ep->lch);
815 if (status == 0) {
816 UDC_TXDMA_CFG_REG = reg;
817 /* EMIFF */
818 omap_set_dma_src_burst_mode(ep->lch,
819 OMAP_DMA_DATA_BURST_4);
820 omap_set_dma_src_data_pack(ep->lch, 1);
821 /* TIPB */
822 omap_set_dma_dest_params(ep->lch,
823 OMAP_DMA_PORT_TIPB,
824 OMAP_DMA_AMODE_CONSTANT,
825 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
826 }
827 } else {
828 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
829 ep->ep.name, dma_error, ep, &ep->lch);
830 if (status == 0) {
831 UDC_RXDMA_CFG_REG = reg;
832 /* TIPB */
833 omap_set_dma_src_params(ep->lch,
834 OMAP_DMA_PORT_TIPB,
835 OMAP_DMA_AMODE_CONSTANT,
836 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
837 /* EMIFF */
838 omap_set_dma_dest_burst_mode(ep->lch,
839 OMAP_DMA_DATA_BURST_4);
840 omap_set_dma_dest_data_pack(ep->lch, 1);
841 }
842 }
843 if (status)
844 ep->dma_channel = 0;
845 else {
846 ep->has_dma = 1;
847 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
848
849 /* channel type P: hw synch (fifo) */
850 if (!cpu_is_omap15xx())
851 omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch));
852 }
853
854 just_restart:
855 /* restart any queue, even if the claim failed */
856 restart = !ep->stopped && !list_empty(&ep->queue);
857
858 if (status)
859 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
860 restart ? " (restart)" : "");
861 else
862 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
863 is_in ? 't' : 'r',
864 ep->dma_channel - 1, ep->lch,
865 restart ? " (restart)" : "");
866
867 if (restart) {
868 struct omap_req *req;
869 req = container_of(ep->queue.next, struct omap_req, queue);
870 if (ep->has_dma)
871 (is_in ? next_in_dma : next_out_dma)(ep, req);
872 else {
873 use_ep(ep, UDC_EP_SEL);
874 (is_in ? write_fifo : read_fifo)(ep, req);
875 deselect_ep();
876 if (!is_in) {
877 UDC_CTRL_REG = UDC_SET_FIFO_EN;
878 ep->ackwait = 1 + ep->double_buf;
879 }
880 /* IN: 6 wait states before it'll tx */
881 }
882 }
883 }
884
885 static void dma_channel_release(struct omap_ep *ep)
886 {
887 int shift = 4 * (ep->dma_channel - 1);
888 u16 mask = 0x0f << shift;
889 struct omap_req *req;
890 int active;
891
892 /* abort any active usb transfer request */
893 if (!list_empty(&ep->queue))
894 req = container_of(ep->queue.next, struct omap_req, queue);
895 else
896 req = NULL;
897
898 active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
899
900 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
901 active ? "active" : "idle",
902 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
903 ep->dma_channel - 1, req);
904
905 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
906 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
907 */
908
909 /* wait till current packet DMA finishes, and fifo empties */
910 if (ep->bEndpointAddress & USB_DIR_IN) {
911 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
912
913 if (req) {
914 finish_in_dma(ep, req, -ECONNRESET);
915
916 /* clear FIFO; hosts probably won't empty it */
917 use_ep(ep, UDC_EP_SEL);
918 UDC_CTRL_REG = UDC_CLR_EP;
919 deselect_ep();
920 }
921 while (UDC_TXDMA_CFG_REG & mask)
922 udelay(10);
923 } else {
924 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
925
926 /* dma empties the fifo */
927 while (UDC_RXDMA_CFG_REG & mask)
928 udelay(10);
929 if (req)
930 finish_out_dma(ep, req, -ECONNRESET, 0);
931 }
932 omap_free_dma(ep->lch);
933 ep->dma_channel = 0;
934 ep->lch = -1;
935 /* has_dma still set, till endpoint is fully quiesced */
936 }
937
938
939 /*-------------------------------------------------------------------------*/
940
941 static int
942 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
943 {
944 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
945 struct omap_req *req = container_of(_req, struct omap_req, req);
946 struct omap_udc *udc;
947 unsigned long flags;
948 int is_iso = 0;
949
950 /* catch various bogus parameters */
951 if (!_req || !req->req.complete || !req->req.buf
952 || !list_empty(&req->queue)) {
953 DBG("%s, bad params\n", __FUNCTION__);
954 return -EINVAL;
955 }
956 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
957 DBG("%s, bad ep\n", __FUNCTION__);
958 return -EINVAL;
959 }
960 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
961 if (req->req.length > ep->ep.maxpacket)
962 return -EMSGSIZE;
963 is_iso = 1;
964 }
965
966 /* this isn't bogus, but OMAP DMA isn't the only hardware to
967 * have a hard time with partial packet reads... reject it.
968 */
969 if (use_dma
970 && ep->has_dma
971 && ep->bEndpointAddress != 0
972 && (ep->bEndpointAddress & USB_DIR_IN) == 0
973 && (req->req.length % ep->ep.maxpacket) != 0) {
974 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
975 return -EMSGSIZE;
976 }
977
978 udc = ep->udc;
979 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
980 return -ESHUTDOWN;
981
982 if (use_dma && ep->has_dma) {
983 if (req->req.dma == DMA_ADDR_INVALID) {
984 req->req.dma = dma_map_single(
985 ep->udc->gadget.dev.parent,
986 req->req.buf,
987 req->req.length,
988 (ep->bEndpointAddress & USB_DIR_IN)
989 ? DMA_TO_DEVICE
990 : DMA_FROM_DEVICE);
991 req->mapped = 1;
992 } else {
993 dma_sync_single_for_device(
994 ep->udc->gadget.dev.parent,
995 req->req.dma, req->req.length,
996 (ep->bEndpointAddress & USB_DIR_IN)
997 ? DMA_TO_DEVICE
998 : DMA_FROM_DEVICE);
999 req->mapped = 0;
1000 }
1001 }
1002
1003 VDBG("%s queue req %p, len %d buf %p\n",
1004 ep->ep.name, _req, _req->length, _req->buf);
1005
1006 spin_lock_irqsave(&udc->lock, flags);
1007
1008 req->req.status = -EINPROGRESS;
1009 req->req.actual = 0;
1010
1011 /* maybe kickstart non-iso i/o queues */
1012 if (is_iso)
1013 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1014 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1015 int is_in;
1016
1017 if (ep->bEndpointAddress == 0) {
1018 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1019 spin_unlock_irqrestore(&udc->lock, flags);
1020 return -EL2HLT;
1021 }
1022
1023 /* empty DATA stage? */
1024 is_in = udc->ep0_in;
1025 if (!req->req.length) {
1026
1027 /* chip became CONFIGURED or ADDRESSED
1028 * earlier; drivers may already have queued
1029 * requests to non-control endpoints
1030 */
1031 if (udc->ep0_set_config) {
1032 u16 irq_en = UDC_IRQ_EN_REG;
1033
1034 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1035 if (!udc->ep0_reset_config)
1036 irq_en |= UDC_EPN_RX_IE
1037 | UDC_EPN_TX_IE;
1038 UDC_IRQ_EN_REG = irq_en;
1039 }
1040
1041 /* STATUS for zero length DATA stages is
1042 * always an IN ... even for IN transfers,
1043 * a wierd case which seem to stall OMAP.
1044 */
1045 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1046 UDC_CTRL_REG = UDC_CLR_EP;
1047 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1048 UDC_EP_NUM_REG = UDC_EP_DIR;
1049
1050 /* cleanup */
1051 udc->ep0_pending = 0;
1052 done(ep, req, 0);
1053 req = NULL;
1054
1055 /* non-empty DATA stage */
1056 } else if (is_in) {
1057 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1058 } else {
1059 if (udc->ep0_setup)
1060 goto irq_wait;
1061 UDC_EP_NUM_REG = UDC_EP_SEL;
1062 }
1063 } else {
1064 is_in = ep->bEndpointAddress & USB_DIR_IN;
1065 if (!ep->has_dma)
1066 use_ep(ep, UDC_EP_SEL);
1067 /* if ISO: SOF IRQs must be enabled/disabled! */
1068 }
1069
1070 if (ep->has_dma)
1071 (is_in ? next_in_dma : next_out_dma)(ep, req);
1072 else if (req) {
1073 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1074 req = NULL;
1075 deselect_ep();
1076 if (!is_in) {
1077 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1078 ep->ackwait = 1 + ep->double_buf;
1079 }
1080 /* IN: 6 wait states before it'll tx */
1081 }
1082 }
1083
1084 irq_wait:
1085 /* irq handler advances the queue */
1086 if (req != NULL)
1087 list_add_tail(&req->queue, &ep->queue);
1088 spin_unlock_irqrestore(&udc->lock, flags);
1089
1090 return 0;
1091 }
1092
1093 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1094 {
1095 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1096 struct omap_req *req;
1097 unsigned long flags;
1098
1099 if (!_ep || !_req)
1100 return -EINVAL;
1101
1102 spin_lock_irqsave(&ep->udc->lock, flags);
1103
1104 /* make sure it's actually queued on this endpoint */
1105 list_for_each_entry (req, &ep->queue, queue) {
1106 if (&req->req == _req)
1107 break;
1108 }
1109 if (&req->req != _req) {
1110 spin_unlock_irqrestore(&ep->udc->lock, flags);
1111 return -EINVAL;
1112 }
1113
1114 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1115 int channel = ep->dma_channel;
1116
1117 /* releasing the channel cancels the request,
1118 * reclaiming the channel restarts the queue
1119 */
1120 dma_channel_release(ep);
1121 dma_channel_claim(ep, channel);
1122 } else
1123 done(ep, req, -ECONNRESET);
1124 spin_unlock_irqrestore(&ep->udc->lock, flags);
1125 return 0;
1126 }
1127
1128 /*-------------------------------------------------------------------------*/
1129
1130 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1131 {
1132 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1133 unsigned long flags;
1134 int status = -EOPNOTSUPP;
1135
1136 spin_lock_irqsave(&ep->udc->lock, flags);
1137
1138 /* just use protocol stalls for ep0; real halts are annoying */
1139 if (ep->bEndpointAddress == 0) {
1140 if (!ep->udc->ep0_pending)
1141 status = -EINVAL;
1142 else if (value) {
1143 if (ep->udc->ep0_set_config) {
1144 WARN("error changing config?\n");
1145 UDC_SYSCON2_REG = UDC_CLR_CFG;
1146 }
1147 UDC_SYSCON2_REG = UDC_STALL_CMD;
1148 ep->udc->ep0_pending = 0;
1149 status = 0;
1150 } else /* NOP */
1151 status = 0;
1152
1153 /* otherwise, all active non-ISO endpoints can halt */
1154 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1155
1156 /* IN endpoints must already be idle */
1157 if ((ep->bEndpointAddress & USB_DIR_IN)
1158 && !list_empty(&ep->queue)) {
1159 status = -EAGAIN;
1160 goto done;
1161 }
1162
1163 if (value) {
1164 int channel;
1165
1166 if (use_dma && ep->dma_channel
1167 && !list_empty(&ep->queue)) {
1168 channel = ep->dma_channel;
1169 dma_channel_release(ep);
1170 } else
1171 channel = 0;
1172
1173 use_ep(ep, UDC_EP_SEL);
1174 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1175 UDC_CTRL_REG = UDC_SET_HALT;
1176 status = 0;
1177 } else
1178 status = -EAGAIN;
1179 deselect_ep();
1180
1181 if (channel)
1182 dma_channel_claim(ep, channel);
1183 } else {
1184 use_ep(ep, 0);
1185 UDC_CTRL_REG = ep->udc->clr_halt;
1186 ep->ackwait = 0;
1187 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1188 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1189 ep->ackwait = 1 + ep->double_buf;
1190 }
1191 }
1192 }
1193 done:
1194 VDBG("%s %s halt stat %d\n", ep->ep.name,
1195 value ? "set" : "clear", status);
1196
1197 spin_unlock_irqrestore(&ep->udc->lock, flags);
1198 return status;
1199 }
1200
1201 static struct usb_ep_ops omap_ep_ops = {
1202 .enable = omap_ep_enable,
1203 .disable = omap_ep_disable,
1204
1205 .alloc_request = omap_alloc_request,
1206 .free_request = omap_free_request,
1207
1208 .alloc_buffer = omap_alloc_buffer,
1209 .free_buffer = omap_free_buffer,
1210
1211 .queue = omap_ep_queue,
1212 .dequeue = omap_ep_dequeue,
1213
1214 .set_halt = omap_ep_set_halt,
1215 // fifo_status ... report bytes in fifo
1216 // fifo_flush ... flush fifo
1217 };
1218
1219 /*-------------------------------------------------------------------------*/
1220
1221 static int omap_get_frame(struct usb_gadget *gadget)
1222 {
1223 u16 sof = UDC_SOF_REG;
1224 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1225 }
1226
1227 static int omap_wakeup(struct usb_gadget *gadget)
1228 {
1229 struct omap_udc *udc;
1230 unsigned long flags;
1231 int retval = -EHOSTUNREACH;
1232
1233 udc = container_of(gadget, struct omap_udc, gadget);
1234
1235 spin_lock_irqsave(&udc->lock, flags);
1236 if (udc->devstat & UDC_SUS) {
1237 /* NOTE: OTG spec erratum says that OTG devices may
1238 * issue wakeups without host enable.
1239 */
1240 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1241 DBG("remote wakeup...\n");
1242 UDC_SYSCON2_REG = UDC_RMT_WKP;
1243 retval = 0;
1244 }
1245
1246 /* NOTE: non-OTG systems may use SRP TOO... */
1247 } else if (!(udc->devstat & UDC_ATT)) {
1248 if (udc->transceiver)
1249 retval = otg_start_srp(udc->transceiver);
1250 }
1251 spin_unlock_irqrestore(&udc->lock, flags);
1252
1253 return retval;
1254 }
1255
1256 static int
1257 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1258 {
1259 struct omap_udc *udc;
1260 unsigned long flags;
1261 u16 syscon1;
1262
1263 udc = container_of(gadget, struct omap_udc, gadget);
1264 spin_lock_irqsave(&udc->lock, flags);
1265 syscon1 = UDC_SYSCON1_REG;
1266 if (is_selfpowered)
1267 syscon1 |= UDC_SELF_PWR;
1268 else
1269 syscon1 &= ~UDC_SELF_PWR;
1270 UDC_SYSCON1_REG = syscon1;
1271 spin_unlock_irqrestore(&udc->lock, flags);
1272
1273 return 0;
1274 }
1275
1276 static int can_pullup(struct omap_udc *udc)
1277 {
1278 return udc->driver && udc->softconnect && udc->vbus_active;
1279 }
1280
1281 static void pullup_enable(struct omap_udc *udc)
1282 {
1283 udc->gadget.dev.parent->power.power_state = PMSG_ON;
1284 udc->gadget.dev.power.power_state = PMSG_ON;
1285 UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1286 #ifndef CONFIG_USB_OTG
1287 if (!cpu_is_omap15xx())
1288 OTG_CTRL_REG |= OTG_BSESSVLD;
1289 #endif
1290 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1291 }
1292
1293 static void pullup_disable(struct omap_udc *udc)
1294 {
1295 #ifndef CONFIG_USB_OTG
1296 if (!cpu_is_omap15xx())
1297 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1298 #endif
1299 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1300 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1301 }
1302
1303 /*
1304 * Called by whatever detects VBUS sessions: external transceiver
1305 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1306 */
1307 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1308 {
1309 struct omap_udc *udc;
1310 unsigned long flags;
1311
1312 udc = container_of(gadget, struct omap_udc, gadget);
1313 spin_lock_irqsave(&udc->lock, flags);
1314 VDBG("VBUS %s\n", is_active ? "on" : "off");
1315 udc->vbus_active = (is_active != 0);
1316 if (cpu_is_omap15xx()) {
1317 /* "software" detect, ignored if !VBUS_MODE_1510 */
1318 if (is_active)
1319 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1320 else
1321 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1322 }
1323 if (can_pullup(udc))
1324 pullup_enable(udc);
1325 else
1326 pullup_disable(udc);
1327 spin_unlock_irqrestore(&udc->lock, flags);
1328 return 0;
1329 }
1330
1331 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1332 {
1333 struct omap_udc *udc;
1334
1335 udc = container_of(gadget, struct omap_udc, gadget);
1336 if (udc->transceiver)
1337 return otg_set_power(udc->transceiver, mA);
1338 return -EOPNOTSUPP;
1339 }
1340
1341 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1342 {
1343 struct omap_udc *udc;
1344 unsigned long flags;
1345
1346 udc = container_of(gadget, struct omap_udc, gadget);
1347 spin_lock_irqsave(&udc->lock, flags);
1348 udc->softconnect = (is_on != 0);
1349 if (can_pullup(udc))
1350 pullup_enable(udc);
1351 else
1352 pullup_disable(udc);
1353 spin_unlock_irqrestore(&udc->lock, flags);
1354 return 0;
1355 }
1356
1357 static struct usb_gadget_ops omap_gadget_ops = {
1358 .get_frame = omap_get_frame,
1359 .wakeup = omap_wakeup,
1360 .set_selfpowered = omap_set_selfpowered,
1361 .vbus_session = omap_vbus_session,
1362 .vbus_draw = omap_vbus_draw,
1363 .pullup = omap_pullup,
1364 };
1365
1366 /*-------------------------------------------------------------------------*/
1367
1368 /* dequeue ALL requests; caller holds udc->lock */
1369 static void nuke(struct omap_ep *ep, int status)
1370 {
1371 struct omap_req *req;
1372
1373 ep->stopped = 1;
1374
1375 if (use_dma && ep->dma_channel)
1376 dma_channel_release(ep);
1377
1378 use_ep(ep, 0);
1379 UDC_CTRL_REG = UDC_CLR_EP;
1380 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1381 UDC_CTRL_REG = UDC_SET_HALT;
1382
1383 while (!list_empty(&ep->queue)) {
1384 req = list_entry(ep->queue.next, struct omap_req, queue);
1385 done(ep, req, status);
1386 }
1387 }
1388
1389 /* caller holds udc->lock */
1390 static void udc_quiesce(struct omap_udc *udc)
1391 {
1392 struct omap_ep *ep;
1393
1394 udc->gadget.speed = USB_SPEED_UNKNOWN;
1395 nuke(&udc->ep[0], -ESHUTDOWN);
1396 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1397 nuke(ep, -ESHUTDOWN);
1398 }
1399
1400 /*-------------------------------------------------------------------------*/
1401
1402 static void update_otg(struct omap_udc *udc)
1403 {
1404 u16 devstat;
1405
1406 if (!udc->gadget.is_otg)
1407 return;
1408
1409 if (OTG_CTRL_REG & OTG_ID)
1410 devstat = UDC_DEVSTAT_REG;
1411 else
1412 devstat = 0;
1413
1414 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1415 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1416 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1417
1418 /* Enable HNP early, avoiding races on suspend irq path.
1419 * ASSUMES OTG state machine B_BUS_REQ input is true.
1420 */
1421 if (udc->gadget.b_hnp_enable)
1422 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1423 & ~OTG_PULLUP;
1424 }
1425
1426 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1427 {
1428 struct omap_ep *ep0 = &udc->ep[0];
1429 struct omap_req *req = NULL;
1430
1431 ep0->irqs++;
1432
1433 /* Clear any pending requests and then scrub any rx/tx state
1434 * before starting to handle the SETUP request.
1435 */
1436 if (irq_src & UDC_SETUP) {
1437 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1438
1439 nuke(ep0, 0);
1440 if (ack) {
1441 UDC_IRQ_SRC_REG = ack;
1442 irq_src = UDC_SETUP;
1443 }
1444 }
1445
1446 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1447 * This driver uses only uses protocol stalls (ep0 never halts),
1448 * and if we got this far the gadget driver already had a
1449 * chance to stall. Tries to be forgiving of host oddities.
1450 *
1451 * NOTE: the last chance gadget drivers have to stall control
1452 * requests is during their request completion callback.
1453 */
1454 if (!list_empty(&ep0->queue))
1455 req = container_of(ep0->queue.next, struct omap_req, queue);
1456
1457 /* IN == TX to host */
1458 if (irq_src & UDC_EP0_TX) {
1459 int stat;
1460
1461 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1462 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1463 stat = UDC_STAT_FLG_REG;
1464 if (stat & UDC_ACK) {
1465 if (udc->ep0_in) {
1466 /* write next IN packet from response,
1467 * or set up the status stage.
1468 */
1469 if (req)
1470 stat = write_fifo(ep0, req);
1471 UDC_EP_NUM_REG = UDC_EP_DIR;
1472 if (!req && udc->ep0_pending) {
1473 UDC_EP_NUM_REG = UDC_EP_SEL;
1474 UDC_CTRL_REG = UDC_CLR_EP;
1475 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1476 UDC_EP_NUM_REG = 0;
1477 udc->ep0_pending = 0;
1478 } /* else: 6 wait states before it'll tx */
1479 } else {
1480 /* ack status stage of OUT transfer */
1481 UDC_EP_NUM_REG = UDC_EP_DIR;
1482 if (req)
1483 done(ep0, req, 0);
1484 }
1485 req = NULL;
1486 } else if (stat & UDC_STALL) {
1487 UDC_CTRL_REG = UDC_CLR_HALT;
1488 UDC_EP_NUM_REG = UDC_EP_DIR;
1489 } else {
1490 UDC_EP_NUM_REG = UDC_EP_DIR;
1491 }
1492 }
1493
1494 /* OUT == RX from host */
1495 if (irq_src & UDC_EP0_RX) {
1496 int stat;
1497
1498 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1499 UDC_EP_NUM_REG = UDC_EP_SEL;
1500 stat = UDC_STAT_FLG_REG;
1501 if (stat & UDC_ACK) {
1502 if (!udc->ep0_in) {
1503 stat = 0;
1504 /* read next OUT packet of request, maybe
1505 * reactiviting the fifo; stall on errors.
1506 */
1507 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1508 UDC_SYSCON2_REG = UDC_STALL_CMD;
1509 udc->ep0_pending = 0;
1510 stat = 0;
1511 } else if (stat == 0)
1512 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1513 UDC_EP_NUM_REG = 0;
1514
1515 /* activate status stage */
1516 if (stat == 1) {
1517 done(ep0, req, 0);
1518 /* that may have STALLed ep0... */
1519 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1520 UDC_CTRL_REG = UDC_CLR_EP;
1521 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1522 UDC_EP_NUM_REG = UDC_EP_DIR;
1523 udc->ep0_pending = 0;
1524 }
1525 } else {
1526 /* ack status stage of IN transfer */
1527 UDC_EP_NUM_REG = 0;
1528 if (req)
1529 done(ep0, req, 0);
1530 }
1531 } else if (stat & UDC_STALL) {
1532 UDC_CTRL_REG = UDC_CLR_HALT;
1533 UDC_EP_NUM_REG = 0;
1534 } else {
1535 UDC_EP_NUM_REG = 0;
1536 }
1537 }
1538
1539 /* SETUP starts all control transfers */
1540 if (irq_src & UDC_SETUP) {
1541 union u {
1542 u16 word[4];
1543 struct usb_ctrlrequest r;
1544 } u;
1545 int status = -EINVAL;
1546 struct omap_ep *ep;
1547
1548 /* read the (latest) SETUP message */
1549 do {
1550 UDC_EP_NUM_REG = UDC_SETUP_SEL;
1551 /* two bytes at a time */
1552 u.word[0] = UDC_DATA_REG;
1553 u.word[1] = UDC_DATA_REG;
1554 u.word[2] = UDC_DATA_REG;
1555 u.word[3] = UDC_DATA_REG;
1556 UDC_EP_NUM_REG = 0;
1557 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1558
1559 #define w_value le16_to_cpup (&u.r.wValue)
1560 #define w_index le16_to_cpup (&u.r.wIndex)
1561 #define w_length le16_to_cpup (&u.r.wLength)
1562
1563 /* Delegate almost all control requests to the gadget driver,
1564 * except for a handful of ch9 status/feature requests that
1565 * hardware doesn't autodecode _and_ the gadget API hides.
1566 */
1567 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1568 udc->ep0_set_config = 0;
1569 udc->ep0_pending = 1;
1570 ep0->stopped = 0;
1571 ep0->ackwait = 0;
1572 switch (u.r.bRequest) {
1573 case USB_REQ_SET_CONFIGURATION:
1574 /* udc needs to know when ep != 0 is valid */
1575 if (u.r.bRequestType != USB_RECIP_DEVICE)
1576 goto delegate;
1577 if (w_length != 0)
1578 goto do_stall;
1579 udc->ep0_set_config = 1;
1580 udc->ep0_reset_config = (w_value == 0);
1581 VDBG("set config %d\n", w_value);
1582
1583 /* update udc NOW since gadget driver may start
1584 * queueing requests immediately; clear config
1585 * later if it fails the request.
1586 */
1587 if (udc->ep0_reset_config)
1588 UDC_SYSCON2_REG = UDC_CLR_CFG;
1589 else
1590 UDC_SYSCON2_REG = UDC_DEV_CFG;
1591 update_otg(udc);
1592 goto delegate;
1593 case USB_REQ_CLEAR_FEATURE:
1594 /* clear endpoint halt */
1595 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1596 goto delegate;
1597 if (w_value != USB_ENDPOINT_HALT
1598 || w_length != 0)
1599 goto do_stall;
1600 ep = &udc->ep[w_index & 0xf];
1601 if (ep != ep0) {
1602 if (w_index & USB_DIR_IN)
1603 ep += 16;
1604 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1605 || !ep->desc)
1606 goto do_stall;
1607 use_ep(ep, 0);
1608 UDC_CTRL_REG = udc->clr_halt;
1609 ep->ackwait = 0;
1610 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1611 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1612 ep->ackwait = 1 + ep->double_buf;
1613 }
1614 /* NOTE: assumes the host behaves sanely,
1615 * only clearing real halts. Else we may
1616 * need to kill pending transfers and then
1617 * restart the queue... very messy for DMA!
1618 */
1619 }
1620 VDBG("%s halt cleared by host\n", ep->name);
1621 goto ep0out_status_stage;
1622 case USB_REQ_SET_FEATURE:
1623 /* set endpoint halt */
1624 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1625 goto delegate;
1626 if (w_value != USB_ENDPOINT_HALT
1627 || w_length != 0)
1628 goto do_stall;
1629 ep = &udc->ep[w_index & 0xf];
1630 if (w_index & USB_DIR_IN)
1631 ep += 16;
1632 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1633 || ep == ep0 || !ep->desc)
1634 goto do_stall;
1635 if (use_dma && ep->has_dma) {
1636 /* this has rude side-effects (aborts) and
1637 * can't really work if DMA-IN is active
1638 */
1639 DBG("%s host set_halt, NYET \n", ep->name);
1640 goto do_stall;
1641 }
1642 use_ep(ep, 0);
1643 /* can't halt if fifo isn't empty... */
1644 UDC_CTRL_REG = UDC_CLR_EP;
1645 UDC_CTRL_REG = UDC_SET_HALT;
1646 VDBG("%s halted by host\n", ep->name);
1647 ep0out_status_stage:
1648 status = 0;
1649 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1650 UDC_CTRL_REG = UDC_CLR_EP;
1651 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1652 UDC_EP_NUM_REG = UDC_EP_DIR;
1653 udc->ep0_pending = 0;
1654 break;
1655 case USB_REQ_GET_STATUS:
1656 /* return interface status. if we were pedantic,
1657 * we'd detect non-existent interfaces, and stall.
1658 */
1659 if (u.r.bRequestType
1660 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1661 goto delegate;
1662 /* return two zero bytes */
1663 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1664 UDC_DATA_REG = 0;
1665 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1666 UDC_EP_NUM_REG = UDC_EP_DIR;
1667 status = 0;
1668 VDBG("GET_STATUS, interface %d\n", w_index);
1669 /* next, status stage */
1670 break;
1671 default:
1672 delegate:
1673 /* activate the ep0out fifo right away */
1674 if (!udc->ep0_in && w_length) {
1675 UDC_EP_NUM_REG = 0;
1676 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1677 }
1678
1679 /* gadget drivers see class/vendor specific requests,
1680 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1681 * and more
1682 */
1683 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1684 u.r.bRequestType, u.r.bRequest,
1685 w_value, w_index, w_length);
1686
1687 #undef w_value
1688 #undef w_index
1689 #undef w_length
1690
1691 /* The gadget driver may return an error here,
1692 * causing an immediate protocol stall.
1693 *
1694 * Else it must issue a response, either queueing a
1695 * response buffer for the DATA stage, or halting ep0
1696 * (causing a protocol stall, not a real halt). A
1697 * zero length buffer means no DATA stage.
1698 *
1699 * It's fine to issue that response after the setup()
1700 * call returns, and this IRQ was handled.
1701 */
1702 udc->ep0_setup = 1;
1703 spin_unlock(&udc->lock);
1704 status = udc->driver->setup (&udc->gadget, &u.r);
1705 spin_lock(&udc->lock);
1706 udc->ep0_setup = 0;
1707 }
1708
1709 if (status < 0) {
1710 do_stall:
1711 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1712 u.r.bRequestType, u.r.bRequest, status);
1713 if (udc->ep0_set_config) {
1714 if (udc->ep0_reset_config)
1715 WARN("error resetting config?\n");
1716 else
1717 UDC_SYSCON2_REG = UDC_CLR_CFG;
1718 }
1719 UDC_SYSCON2_REG = UDC_STALL_CMD;
1720 udc->ep0_pending = 0;
1721 }
1722 }
1723 }
1724
1725 /*-------------------------------------------------------------------------*/
1726
1727 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1728
1729 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1730 {
1731 u16 devstat, change;
1732
1733 devstat = UDC_DEVSTAT_REG;
1734 change = devstat ^ udc->devstat;
1735 udc->devstat = devstat;
1736
1737 if (change & (UDC_USB_RESET|UDC_ATT)) {
1738 udc_quiesce(udc);
1739
1740 if (change & UDC_ATT) {
1741 /* driver for any external transceiver will
1742 * have called omap_vbus_session() already
1743 */
1744 if (devstat & UDC_ATT) {
1745 udc->gadget.speed = USB_SPEED_FULL;
1746 VDBG("connect\n");
1747 if (!udc->transceiver)
1748 pullup_enable(udc);
1749 // if (driver->connect) call it
1750 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1751 udc->gadget.speed = USB_SPEED_UNKNOWN;
1752 if (!udc->transceiver)
1753 pullup_disable(udc);
1754 DBG("disconnect, gadget %s\n",
1755 udc->driver->driver.name);
1756 if (udc->driver->disconnect) {
1757 spin_unlock(&udc->lock);
1758 udc->driver->disconnect(&udc->gadget);
1759 spin_lock(&udc->lock);
1760 }
1761 }
1762 change &= ~UDC_ATT;
1763 }
1764
1765 if (change & UDC_USB_RESET) {
1766 if (devstat & UDC_USB_RESET) {
1767 VDBG("RESET=1\n");
1768 } else {
1769 udc->gadget.speed = USB_SPEED_FULL;
1770 INFO("USB reset done, gadget %s\n",
1771 udc->driver->driver.name);
1772 /* ep0 traffic is legal from now on */
1773 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1774 }
1775 change &= ~UDC_USB_RESET;
1776 }
1777 }
1778 if (change & UDC_SUS) {
1779 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1780 // FIXME tell isp1301 to suspend/resume (?)
1781 if (devstat & UDC_SUS) {
1782 VDBG("suspend\n");
1783 update_otg(udc);
1784 /* HNP could be under way already */
1785 if (udc->gadget.speed == USB_SPEED_FULL
1786 && udc->driver->suspend) {
1787 spin_unlock(&udc->lock);
1788 udc->driver->suspend(&udc->gadget);
1789 spin_lock(&udc->lock);
1790 }
1791 if (udc->transceiver)
1792 otg_set_suspend(udc->transceiver, 1);
1793 } else {
1794 VDBG("resume\n");
1795 if (udc->transceiver)
1796 otg_set_suspend(udc->transceiver, 0);
1797 if (udc->gadget.speed == USB_SPEED_FULL
1798 && udc->driver->resume) {
1799 spin_unlock(&udc->lock);
1800 udc->driver->resume(&udc->gadget);
1801 spin_lock(&udc->lock);
1802 }
1803 }
1804 }
1805 change &= ~UDC_SUS;
1806 }
1807 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1808 update_otg(udc);
1809 change &= ~OTG_FLAGS;
1810 }
1811
1812 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1813 if (change)
1814 VDBG("devstat %03x, ignore change %03x\n",
1815 devstat, change);
1816
1817 UDC_IRQ_SRC_REG = UDC_DS_CHG;
1818 }
1819
1820 static irqreturn_t
1821 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1822 {
1823 struct omap_udc *udc = _udc;
1824 u16 irq_src;
1825 irqreturn_t status = IRQ_NONE;
1826 unsigned long flags;
1827
1828 spin_lock_irqsave(&udc->lock, flags);
1829 irq_src = UDC_IRQ_SRC_REG;
1830
1831 /* Device state change (usb ch9 stuff) */
1832 if (irq_src & UDC_DS_CHG) {
1833 devstate_irq(_udc, irq_src);
1834 status = IRQ_HANDLED;
1835 irq_src &= ~UDC_DS_CHG;
1836 }
1837
1838 /* EP0 control transfers */
1839 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1840 ep0_irq(_udc, irq_src);
1841 status = IRQ_HANDLED;
1842 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1843 }
1844
1845 /* DMA transfer completion */
1846 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1847 dma_irq(_udc, irq_src);
1848 status = IRQ_HANDLED;
1849 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1850 }
1851
1852 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1853 if (irq_src)
1854 DBG("udc_irq, unhandled %03x\n", irq_src);
1855 spin_unlock_irqrestore(&udc->lock, flags);
1856
1857 return status;
1858 }
1859
1860 /* workaround for seemingly-lost IRQs for RX ACKs... */
1861 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1862 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1863
1864 static void pio_out_timer(unsigned long _ep)
1865 {
1866 struct omap_ep *ep = (void *) _ep;
1867 unsigned long flags;
1868 u16 stat_flg;
1869
1870 spin_lock_irqsave(&ep->udc->lock, flags);
1871 if (!list_empty(&ep->queue) && ep->ackwait) {
1872 use_ep(ep, 0);
1873 stat_flg = UDC_STAT_FLG_REG;
1874
1875 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1876 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1877 struct omap_req *req;
1878
1879 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1880 req = container_of(ep->queue.next,
1881 struct omap_req, queue);
1882 UDC_EP_NUM_REG = ep->bEndpointAddress | UDC_EP_SEL;
1883 (void) read_fifo(ep, req);
1884 UDC_EP_NUM_REG = ep->bEndpointAddress;
1885 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1886 ep->ackwait = 1 + ep->double_buf;
1887 }
1888 }
1889 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1890 spin_unlock_irqrestore(&ep->udc->lock, flags);
1891 }
1892
1893 static irqreturn_t
1894 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1895 {
1896 u16 epn_stat, irq_src;
1897 irqreturn_t status = IRQ_NONE;
1898 struct omap_ep *ep;
1899 int epnum;
1900 struct omap_udc *udc = _dev;
1901 struct omap_req *req;
1902 unsigned long flags;
1903
1904 spin_lock_irqsave(&udc->lock, flags);
1905 epn_stat = UDC_EPN_STAT_REG;
1906 irq_src = UDC_IRQ_SRC_REG;
1907
1908 /* handle OUT first, to avoid some wasteful NAKs */
1909 if (irq_src & UDC_EPN_RX) {
1910 epnum = (epn_stat >> 8) & 0x0f;
1911 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1912 status = IRQ_HANDLED;
1913 ep = &udc->ep[epnum];
1914 ep->irqs++;
1915
1916 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1917 ep->fnf = 0;
1918 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1919 ep->ackwait--;
1920 if (!list_empty(&ep->queue)) {
1921 int stat;
1922 req = container_of(ep->queue.next,
1923 struct omap_req, queue);
1924 stat = read_fifo(ep, req);
1925 if (!ep->double_buf)
1926 ep->fnf = 1;
1927 }
1928 }
1929 /* min 6 clock delay before clearing EP_SEL ... */
1930 epn_stat = UDC_EPN_STAT_REG;
1931 epn_stat = UDC_EPN_STAT_REG;
1932 UDC_EP_NUM_REG = epnum;
1933
1934 /* enabling fifo _after_ clearing ACK, contrary to docs,
1935 * reduces lossage; timer still needed though (sigh).
1936 */
1937 if (ep->fnf) {
1938 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1939 ep->ackwait = 1 + ep->double_buf;
1940 }
1941 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1942 }
1943
1944 /* then IN transfers */
1945 else if (irq_src & UDC_EPN_TX) {
1946 epnum = epn_stat & 0x0f;
1947 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1948 status = IRQ_HANDLED;
1949 ep = &udc->ep[16 + epnum];
1950 ep->irqs++;
1951
1952 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1953 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1954 ep->ackwait = 0;
1955 if (!list_empty(&ep->queue)) {
1956 req = container_of(ep->queue.next,
1957 struct omap_req, queue);
1958 (void) write_fifo(ep, req);
1959 }
1960 }
1961 /* min 6 clock delay before clearing EP_SEL ... */
1962 epn_stat = UDC_EPN_STAT_REG;
1963 epn_stat = UDC_EPN_STAT_REG;
1964 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1965 /* then 6 clocks before it'd tx */
1966 }
1967
1968 spin_unlock_irqrestore(&udc->lock, flags);
1969 return status;
1970 }
1971
1972 #ifdef USE_ISO
1973 static irqreturn_t
1974 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
1975 {
1976 struct omap_udc *udc = _dev;
1977 struct omap_ep *ep;
1978 int pending = 0;
1979 unsigned long flags;
1980
1981 spin_lock_irqsave(&udc->lock, flags);
1982
1983 /* handle all non-DMA ISO transfers */
1984 list_for_each_entry (ep, &udc->iso, iso) {
1985 u16 stat;
1986 struct omap_req *req;
1987
1988 if (ep->has_dma || list_empty(&ep->queue))
1989 continue;
1990 req = list_entry(ep->queue.next, struct omap_req, queue);
1991
1992 use_ep(ep, UDC_EP_SEL);
1993 stat = UDC_STAT_FLG_REG;
1994
1995 /* NOTE: like the other controller drivers, this isn't
1996 * currently reporting lost or damaged frames.
1997 */
1998 if (ep->bEndpointAddress & USB_DIR_IN) {
1999 if (stat & UDC_MISS_IN)
2000 /* done(ep, req, -EPROTO) */;
2001 else
2002 write_fifo(ep, req);
2003 } else {
2004 int status = 0;
2005
2006 if (stat & UDC_NO_RXPACKET)
2007 status = -EREMOTEIO;
2008 else if (stat & UDC_ISO_ERR)
2009 status = -EILSEQ;
2010 else if (stat & UDC_DATA_FLUSH)
2011 status = -ENOSR;
2012
2013 if (status)
2014 /* done(ep, req, status) */;
2015 else
2016 read_fifo(ep, req);
2017 }
2018 deselect_ep();
2019 /* 6 wait states before next EP */
2020
2021 ep->irqs++;
2022 if (!list_empty(&ep->queue))
2023 pending = 1;
2024 }
2025 if (!pending)
2026 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2027 UDC_IRQ_SRC_REG = UDC_SOF;
2028
2029 spin_unlock_irqrestore(&udc->lock, flags);
2030 return IRQ_HANDLED;
2031 }
2032 #endif
2033
2034 /*-------------------------------------------------------------------------*/
2035
2036 static struct omap_udc *udc;
2037
2038 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2039 {
2040 int status = -ENODEV;
2041 struct omap_ep *ep;
2042 unsigned long flags;
2043
2044 /* basic sanity tests */
2045 if (!udc)
2046 return -ENODEV;
2047 if (!driver
2048 // FIXME if otg, check: driver->is_otg
2049 || driver->speed < USB_SPEED_FULL
2050 || !driver->bind
2051 || !driver->unbind
2052 || !driver->setup)
2053 return -EINVAL;
2054
2055 spin_lock_irqsave(&udc->lock, flags);
2056 if (udc->driver) {
2057 spin_unlock_irqrestore(&udc->lock, flags);
2058 return -EBUSY;
2059 }
2060
2061 /* reset state */
2062 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2063 ep->irqs = 0;
2064 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2065 continue;
2066 use_ep(ep, 0);
2067 UDC_CTRL_REG = UDC_SET_HALT;
2068 }
2069 udc->ep0_pending = 0;
2070 udc->ep[0].irqs = 0;
2071 udc->softconnect = 1;
2072
2073 /* hook up the driver */
2074 driver->driver.bus = NULL;
2075 udc->driver = driver;
2076 udc->gadget.dev.driver = &driver->driver;
2077 spin_unlock_irqrestore(&udc->lock, flags);
2078
2079 status = driver->bind (&udc->gadget);
2080 if (status) {
2081 DBG("bind to %s --> %d\n", driver->driver.name, status);
2082 udc->gadget.dev.driver = NULL;
2083 udc->driver = NULL;
2084 goto done;
2085 }
2086 DBG("bound to driver %s\n", driver->driver.name);
2087
2088 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2089
2090 /* connect to bus through transceiver */
2091 if (udc->transceiver) {
2092 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2093 if (status < 0) {
2094 ERR("can't bind to transceiver\n");
2095 driver->unbind (&udc->gadget);
2096 udc->gadget.dev.driver = NULL;
2097 udc->driver = NULL;
2098 goto done;
2099 }
2100 } else {
2101 if (can_pullup(udc))
2102 pullup_enable (udc);
2103 else
2104 pullup_disable (udc);
2105 }
2106
2107 /* boards that don't have VBUS sensing can't autogate 48MHz;
2108 * can't enter deep sleep while a gadget driver is active.
2109 */
2110 if (machine_is_omap_innovator() || machine_is_omap_osk())
2111 omap_vbus_session(&udc->gadget, 1);
2112
2113 done:
2114 return status;
2115 }
2116 EXPORT_SYMBOL(usb_gadget_register_driver);
2117
2118 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2119 {
2120 unsigned long flags;
2121 int status = -ENODEV;
2122
2123 if (!udc)
2124 return -ENODEV;
2125 if (!driver || driver != udc->driver)
2126 return -EINVAL;
2127
2128 if (machine_is_omap_innovator() || machine_is_omap_osk())
2129 omap_vbus_session(&udc->gadget, 0);
2130
2131 if (udc->transceiver)
2132 (void) otg_set_peripheral(udc->transceiver, NULL);
2133 else
2134 pullup_disable(udc);
2135
2136 spin_lock_irqsave(&udc->lock, flags);
2137 udc_quiesce(udc);
2138 spin_unlock_irqrestore(&udc->lock, flags);
2139
2140 driver->unbind(&udc->gadget);
2141 udc->gadget.dev.driver = NULL;
2142 udc->driver = NULL;
2143
2144 DBG("unregistered driver '%s'\n", driver->driver.name);
2145 return status;
2146 }
2147 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2148
2149
2150 /*-------------------------------------------------------------------------*/
2151
2152 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2153
2154 #include <linux/seq_file.h>
2155
2156 static const char proc_filename[] = "driver/udc";
2157
2158 #define FOURBITS "%s%s%s%s"
2159 #define EIGHTBITS FOURBITS FOURBITS
2160
2161 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2162 {
2163 u16 stat_flg;
2164 struct omap_req *req;
2165 char buf[20];
2166
2167 use_ep(ep, 0);
2168
2169 if (use_dma && ep->has_dma)
2170 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2171 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2172 ep->dma_channel - 1, ep->lch);
2173 else
2174 buf[0] = 0;
2175
2176 stat_flg = UDC_STAT_FLG_REG;
2177 seq_printf(s,
2178 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2179 ep->name, buf,
2180 ep->double_buf ? "dbuf " : "",
2181 ({char *s; switch(ep->ackwait){
2182 case 0: s = ""; break;
2183 case 1: s = "(ackw) "; break;
2184 case 2: s = "(ackw2) "; break;
2185 default: s = "(?) "; break;
2186 } s;}),
2187 ep->irqs, stat_flg,
2188 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2189 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2190 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2191 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2192 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2193 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2194 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2195 (stat_flg & UDC_STALL) ? "STALL " : "",
2196 (stat_flg & UDC_NAK) ? "NAK " : "",
2197 (stat_flg & UDC_ACK) ? "ACK " : "",
2198 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2199 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2200 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2201
2202 if (list_empty (&ep->queue))
2203 seq_printf(s, "\t(queue empty)\n");
2204 else
2205 list_for_each_entry (req, &ep->queue, queue) {
2206 unsigned length = req->req.actual;
2207
2208 if (use_dma && buf[0]) {
2209 length += ((ep->bEndpointAddress & USB_DIR_IN)
2210 ? dma_src_len : dma_dest_len)
2211 (ep, req->req.dma + length);
2212 buf[0] = 0;
2213 }
2214 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2215 &req->req, length,
2216 req->req.length, req->req.buf);
2217 }
2218 }
2219
2220 static char *trx_mode(unsigned m, int enabled)
2221 {
2222 switch (m) {
2223 case 0: return enabled ? "*6wire" : "unused";
2224 case 1: return "4wire";
2225 case 2: return "3wire";
2226 case 3: return "6wire";
2227 default: return "unknown";
2228 }
2229 }
2230
2231 static int proc_otg_show(struct seq_file *s)
2232 {
2233 u32 tmp;
2234 u32 trans;
2235
2236 tmp = OTG_REV_REG;
2237 trans = USB_TRANSCEIVER_CTRL_REG;
2238 seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2239 tmp >> 4, tmp & 0xf, trans);
2240 tmp = OTG_SYSCON_1_REG;
2241 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2242 FOURBITS "\n", tmp,
2243 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2244 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2245 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2246 ? "internal"
2247 : trx_mode(USB0_TRX_MODE(tmp), 1),
2248 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2249 (tmp & HST_IDLE_EN) ? " !host" : "",
2250 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2251 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2252 tmp = OTG_SYSCON_2_REG;
2253 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2254 " b_ase_brst=%d hmc=%d\n", tmp,
2255 (tmp & OTG_EN) ? " otg_en" : "",
2256 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2257 // much more SRP stuff
2258 (tmp & SRP_DATA) ? " srp_data" : "",
2259 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2260 (tmp & OTG_PADEN) ? " otg_paden" : "",
2261 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2262 (tmp & UHOST_EN) ? " uhost_en" : "",
2263 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2264 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2265 B_ASE_BRST(tmp),
2266 OTG_HMC(tmp));
2267 tmp = OTG_CTRL_REG;
2268 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2269 (tmp & OTG_ASESSVLD) ? " asess" : "",
2270 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2271 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2272 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2273 (tmp & OTG_ID) ? " id" : "",
2274 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2275 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2276 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2277 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2278 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2279 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2280 (tmp & OTG_PULLDOWN) ? " down" : "",
2281 (tmp & OTG_PULLUP) ? " up" : "",
2282 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2283 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2284 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2285 (tmp & OTG_PU_ID) ? " pu_id" : ""
2286 );
2287 tmp = OTG_IRQ_EN_REG;
2288 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2289 tmp = OTG_IRQ_SRC_REG;
2290 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2291 tmp = OTG_OUTCTRL_REG;
2292 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2293 tmp = OTG_TEST_REG;
2294 seq_printf(s, "otg_test %04x" "\n", tmp);
2295 return 0;
2296 }
2297
2298 static int proc_udc_show(struct seq_file *s, void *_)
2299 {
2300 u32 tmp;
2301 struct omap_ep *ep;
2302 unsigned long flags;
2303
2304 spin_lock_irqsave(&udc->lock, flags);
2305
2306 seq_printf(s, "%s, version: " DRIVER_VERSION
2307 #ifdef USE_ISO
2308 " (iso)"
2309 #endif
2310 "%s\n",
2311 driver_desc,
2312 use_dma ? " (dma)" : "");
2313
2314 tmp = UDC_REV_REG & 0xff;
2315 seq_printf(s,
2316 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2317 "hmc %d, transceiver %s\n",
2318 tmp >> 4, tmp & 0xf,
2319 fifo_mode,
2320 udc->driver ? udc->driver->driver.name : "(none)",
2321 HMC,
2322 udc->transceiver ? udc->transceiver->label : "(none)");
2323 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2324 __REG16(ULPD_CLOCK_CTRL),
2325 __REG16(ULPD_SOFT_REQ),
2326 __REG16(ULPD_STATUS_REQ));
2327
2328 /* OTG controller registers */
2329 if (!cpu_is_omap15xx())
2330 proc_otg_show(s);
2331
2332 tmp = UDC_SYSCON1_REG;
2333 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2334 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2335 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2336 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2337 (tmp & UDC_NAK_EN) ? " nak" : "",
2338 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2339 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2340 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2341 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2342 // syscon2 is write-only
2343
2344 /* UDC controller registers */
2345 if (!(tmp & UDC_PULLUP_EN)) {
2346 seq_printf(s, "(suspended)\n");
2347 spin_unlock_irqrestore(&udc->lock, flags);
2348 return 0;
2349 }
2350
2351 tmp = UDC_DEVSTAT_REG;
2352 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2353 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2354 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2355 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2356 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2357 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2358 (tmp & UDC_SUS) ? " SUS" : "",
2359 (tmp & UDC_CFG) ? " CFG" : "",
2360 (tmp & UDC_ADD) ? " ADD" : "",
2361 (tmp & UDC_DEF) ? " DEF" : "",
2362 (tmp & UDC_ATT) ? " ATT" : "");
2363 seq_printf(s, "sof %04x\n", UDC_SOF_REG);
2364 tmp = UDC_IRQ_EN_REG;
2365 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2366 (tmp & UDC_SOF_IE) ? " sof" : "",
2367 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2368 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2369 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2370 (tmp & UDC_EP0_IE) ? " ep0" : "");
2371 tmp = UDC_IRQ_SRC_REG;
2372 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2373 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2374 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2375 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2376 (tmp & UDC_SOF) ? " sof" : "",
2377 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2378 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2379 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2380 (tmp & UDC_SETUP) ? " setup" : "",
2381 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2382 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2383 if (use_dma) {
2384 unsigned i;
2385
2386 tmp = UDC_DMA_IRQ_EN_REG;
2387 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2388 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2389 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2390 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2391
2392 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2393 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2394 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2395
2396 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2397 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2398 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2399
2400 tmp = UDC_RXDMA_CFG_REG;
2401 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2402 if (tmp) {
2403 for (i = 0; i < 3; i++) {
2404 if ((tmp & (0x0f << (i * 4))) == 0)
2405 continue;
2406 seq_printf(s, "rxdma[%d] %04x\n", i,
2407 UDC_RXDMA_REG(i + 1));
2408 }
2409 }
2410 tmp = UDC_TXDMA_CFG_REG;
2411 seq_printf(s, "txdma_cfg %04x\n", tmp);
2412 if (tmp) {
2413 for (i = 0; i < 3; i++) {
2414 if (!(tmp & (0x0f << (i * 4))))
2415 continue;
2416 seq_printf(s, "txdma[%d] %04x\n", i,
2417 UDC_TXDMA_REG(i + 1));
2418 }
2419 }
2420 }
2421
2422 tmp = UDC_DEVSTAT_REG;
2423 if (tmp & UDC_ATT) {
2424 proc_ep_show(s, &udc->ep[0]);
2425 if (tmp & UDC_ADD) {
2426 list_for_each_entry (ep, &udc->gadget.ep_list,
2427 ep.ep_list) {
2428 if (ep->desc)
2429 proc_ep_show(s, ep);
2430 }
2431 }
2432 }
2433 spin_unlock_irqrestore(&udc->lock, flags);
2434 return 0;
2435 }
2436
2437 static int proc_udc_open(struct inode *inode, struct file *file)
2438 {
2439 return single_open(file, proc_udc_show, NULL);
2440 }
2441
2442 static struct file_operations proc_ops = {
2443 .open = proc_udc_open,
2444 .read = seq_read,
2445 .llseek = seq_lseek,
2446 .release = single_release,
2447 };
2448
2449 static void create_proc_file(void)
2450 {
2451 struct proc_dir_entry *pde;
2452
2453 pde = create_proc_entry (proc_filename, 0, NULL);
2454 if (pde)
2455 pde->proc_fops = &proc_ops;
2456 }
2457
2458 static void remove_proc_file(void)
2459 {
2460 remove_proc_entry(proc_filename, NULL);
2461 }
2462
2463 #else
2464
2465 static inline void create_proc_file(void) {}
2466 static inline void remove_proc_file(void) {}
2467
2468 #endif
2469
2470 /*-------------------------------------------------------------------------*/
2471
2472 /* Before this controller can enumerate, we need to pick an endpoint
2473 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2474 * buffer space among the endpoints we'll be operating.
2475 *
2476 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2477 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
2478 * capability yet though.
2479 */
2480 static unsigned __init
2481 omap_ep_setup(char *name, u8 addr, u8 type,
2482 unsigned buf, unsigned maxp, int dbuf)
2483 {
2484 struct omap_ep *ep;
2485 u16 epn_rxtx = 0;
2486
2487 /* OUT endpoints first, then IN */
2488 ep = &udc->ep[addr & 0xf];
2489 if (addr & USB_DIR_IN)
2490 ep += 16;
2491
2492 /* in case of ep init table bugs */
2493 BUG_ON(ep->name[0]);
2494
2495 /* chip setup ... bit values are same for IN, OUT */
2496 if (type == USB_ENDPOINT_XFER_ISOC) {
2497 switch (maxp) {
2498 case 8: epn_rxtx = 0 << 12; break;
2499 case 16: epn_rxtx = 1 << 12; break;
2500 case 32: epn_rxtx = 2 << 12; break;
2501 case 64: epn_rxtx = 3 << 12; break;
2502 case 128: epn_rxtx = 4 << 12; break;
2503 case 256: epn_rxtx = 5 << 12; break;
2504 case 512: epn_rxtx = 6 << 12; break;
2505 default: BUG();
2506 }
2507 epn_rxtx |= UDC_EPN_RX_ISO;
2508 dbuf = 1;
2509 } else {
2510 /* double-buffering "not supported" on 15xx,
2511 * and ignored for PIO-IN on 16xx
2512 */
2513 if (!use_dma || cpu_is_omap15xx())
2514 dbuf = 0;
2515
2516 switch (maxp) {
2517 case 8: epn_rxtx = 0 << 12; break;
2518 case 16: epn_rxtx = 1 << 12; break;
2519 case 32: epn_rxtx = 2 << 12; break;
2520 case 64: epn_rxtx = 3 << 12; break;
2521 default: BUG();
2522 }
2523 if (dbuf && addr)
2524 epn_rxtx |= UDC_EPN_RX_DB;
2525 init_timer(&ep->timer);
2526 ep->timer.function = pio_out_timer;
2527 ep->timer.data = (unsigned long) ep;
2528 }
2529 if (addr)
2530 epn_rxtx |= UDC_EPN_RX_VALID;
2531 BUG_ON(buf & 0x07);
2532 epn_rxtx |= buf >> 3;
2533
2534 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2535 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2536
2537 if (addr & USB_DIR_IN)
2538 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2539 else
2540 UDC_EP_RX_REG(addr) = epn_rxtx;
2541
2542 /* next endpoint's buffer starts after this one's */
2543 buf += maxp;
2544 if (dbuf)
2545 buf += maxp;
2546 BUG_ON(buf > 2048);
2547
2548 /* set up driver data structures */
2549 BUG_ON(strlen(name) >= sizeof ep->name);
2550 strlcpy(ep->name, name, sizeof ep->name);
2551 INIT_LIST_HEAD(&ep->queue);
2552 INIT_LIST_HEAD(&ep->iso);
2553 ep->bEndpointAddress = addr;
2554 ep->bmAttributes = type;
2555 ep->double_buf = dbuf;
2556 ep->udc = udc;
2557
2558 ep->ep.name = ep->name;
2559 ep->ep.ops = &omap_ep_ops;
2560 ep->ep.maxpacket = ep->maxpacket = maxp;
2561 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2562
2563 return buf;
2564 }
2565
2566 static void omap_udc_release(struct device *dev)
2567 {
2568 complete(udc->done);
2569 kfree (udc);
2570 udc = NULL;
2571 }
2572
2573 static int __init
2574 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2575 {
2576 unsigned tmp, buf;
2577
2578 /* abolish any previous hardware state */
2579 UDC_SYSCON1_REG = 0;
2580 UDC_IRQ_EN_REG = 0;
2581 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2582 UDC_DMA_IRQ_EN_REG = 0;
2583 UDC_RXDMA_CFG_REG = 0;
2584 UDC_TXDMA_CFG_REG = 0;
2585
2586 /* UDC_PULLUP_EN gates the chip clock */
2587 // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2588
2589 udc = kmalloc (sizeof *udc, SLAB_KERNEL);
2590 if (!udc)
2591 return -ENOMEM;
2592
2593 memset(udc, 0, sizeof *udc);
2594 spin_lock_init (&udc->lock);
2595
2596 udc->gadget.ops = &omap_gadget_ops;
2597 udc->gadget.ep0 = &udc->ep[0].ep;
2598 INIT_LIST_HEAD(&udc->gadget.ep_list);
2599 INIT_LIST_HEAD(&udc->iso);
2600 udc->gadget.speed = USB_SPEED_UNKNOWN;
2601 udc->gadget.name = driver_name;
2602
2603 device_initialize(&udc->gadget.dev);
2604 strcpy (udc->gadget.dev.bus_id, "gadget");
2605 udc->gadget.dev.release = omap_udc_release;
2606 udc->gadget.dev.parent = &odev->dev;
2607 if (use_dma)
2608 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2609
2610 udc->transceiver = xceiv;
2611
2612 /* ep0 is special; put it right after the SETUP buffer */
2613 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2614 8 /* after SETUP */, 64 /* maxpacket */, 0);
2615 list_del_init(&udc->ep[0].ep.ep_list);
2616
2617 /* initially disable all non-ep0 endpoints */
2618 for (tmp = 1; tmp < 15; tmp++) {
2619 UDC_EP_RX_REG(tmp) = 0;
2620 UDC_EP_TX_REG(tmp) = 0;
2621 }
2622
2623 #define OMAP_BULK_EP(name,addr) \
2624 buf = omap_ep_setup(name "-bulk", addr, \
2625 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2626 #define OMAP_INT_EP(name,addr, maxp) \
2627 buf = omap_ep_setup(name "-int", addr, \
2628 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2629 #define OMAP_ISO_EP(name,addr, maxp) \
2630 buf = omap_ep_setup(name "-iso", addr, \
2631 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2632
2633 switch (fifo_mode) {
2634 case 0:
2635 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2636 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2637 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2638 break;
2639 case 1:
2640 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2641 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2642 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2643
2644 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2645 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2646 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2647
2648 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2649 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2650 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2651
2652 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2653 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2654 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2655
2656 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2657 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2658 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2659 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2660
2661 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2662 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2663 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2664 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2665
2666 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2667 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2668
2669 break;
2670
2671 #ifdef USE_ISO
2672 case 2: /* mixed iso/bulk */
2673 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2674 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2675 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2676 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2677
2678 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2679
2680 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2681 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2682 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2683 break;
2684 case 3: /* mixed bulk/iso */
2685 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2686 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2687 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2688
2689 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2690 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2691 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2692
2693 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2694 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2695 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2696 break;
2697 #endif
2698
2699 /* add more modes as needed */
2700
2701 default:
2702 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2703 return -ENODEV;
2704 }
2705 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2706 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2707 return 0;
2708 }
2709
2710 static int __init omap_udc_probe(struct platform_device *pdev)
2711 {
2712 int status = -ENODEV;
2713 int hmc;
2714 struct otg_transceiver *xceiv = NULL;
2715 const char *type = NULL;
2716 struct omap_usb_config *config = pdev->dev.platform_data;
2717
2718 /* NOTE: "knows" the order of the resources! */
2719 if (!request_mem_region(pdev->resource[0].start,
2720 pdev->resource[0].end - pdev->resource[0].start + 1,
2721 driver_name)) {
2722 DBG("request_mem_region failed\n");
2723 return -EBUSY;
2724 }
2725
2726 INFO("OMAP UDC rev %d.%d%s\n",
2727 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2728 config->otg ? ", Mini-AB" : "");
2729
2730 /* use the mode given to us by board init code */
2731 if (cpu_is_omap15xx()) {
2732 hmc = HMC_1510;
2733 type = "(unknown)";
2734
2735 if (machine_is_omap_innovator()) {
2736 /* just set up software VBUS detect, and then
2737 * later rig it so we always report VBUS.
2738 * FIXME without really sensing VBUS, we can't
2739 * know when to turn PULLUP_EN on/off; and that
2740 * means we always "need" the 48MHz clock.
2741 */
2742 u32 tmp = FUNC_MUX_CTRL_0_REG;
2743
2744 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2745 tmp |= VBUS_MODE_1510;
2746 tmp &= ~VBUS_CTRL_1510;
2747 FUNC_MUX_CTRL_0_REG = tmp;
2748 }
2749 } else {
2750 /* The transceiver may package some GPIO logic or handle
2751 * loopback and/or transceiverless setup; if we find one,
2752 * use it. Except for OTG, we don't _need_ to talk to one;
2753 * but not having one probably means no VBUS detection.
2754 */
2755 xceiv = otg_get_transceiver();
2756 if (xceiv)
2757 type = xceiv->label;
2758 else if (config->otg) {
2759 DBG("OTG requires external transceiver!\n");
2760 goto cleanup0;
2761 }
2762
2763 hmc = HMC_1610;
2764 switch (hmc) {
2765 case 0: /* POWERUP DEFAULT == 0 */
2766 case 4:
2767 case 12:
2768 case 20:
2769 if (!cpu_is_omap1710()) {
2770 type = "integrated";
2771 break;
2772 }
2773 /* FALL THROUGH */
2774 case 3:
2775 case 11:
2776 case 16:
2777 case 19:
2778 case 25:
2779 if (!xceiv) {
2780 DBG("external transceiver not registered!\n");
2781 type = "unknown";
2782 }
2783 break;
2784 case 21: /* internal loopback */
2785 type = "loopback";
2786 break;
2787 case 14: /* transceiverless */
2788 if (cpu_is_omap1710())
2789 goto bad_on_1710;
2790 /* FALL THROUGH */
2791 case 13:
2792 case 15:
2793 type = "no";
2794 break;
2795
2796 default:
2797 bad_on_1710:
2798 ERR("unrecognized UDC HMC mode %d\n", hmc);
2799 goto cleanup0;
2800 }
2801 }
2802 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2803
2804 /* a "gadget" abstracts/virtualizes the controller */
2805 status = omap_udc_setup(pdev, xceiv);
2806 if (status) {
2807 goto cleanup0;
2808 }
2809 xceiv = NULL;
2810 // "udc" is now valid
2811 pullup_disable(udc);
2812 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2813 udc->gadget.is_otg = (config->otg != 0);
2814 #endif
2815
2816 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2817 if (UDC_REV_REG >= 0x61)
2818 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2819 else
2820 udc->clr_halt = UDC_RESET_EP;
2821
2822 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2823 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2824 SA_SAMPLE_RANDOM, driver_name, udc);
2825 if (status != 0) {
2826 ERR( "can't get irq %ld, err %d\n",
2827 pdev->resource[1].start, status);
2828 goto cleanup1;
2829 }
2830
2831 /* USB "non-iso" IRQ (PIO for all but ep0) */
2832 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2833 SA_SAMPLE_RANDOM, "omap_udc pio", udc);
2834 if (status != 0) {
2835 ERR( "can't get irq %ld, err %d\n",
2836 pdev->resource[2].start, status);
2837 goto cleanup2;
2838 }
2839 #ifdef USE_ISO
2840 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2841 SA_INTERRUPT, "omap_udc iso", udc);
2842 if (status != 0) {
2843 ERR("can't get irq %ld, err %d\n",
2844 pdev->resource[3].start, status);
2845 goto cleanup3;
2846 }
2847 #endif
2848
2849 create_proc_file();
2850 device_add(&udc->gadget.dev);
2851 return 0;
2852
2853 #ifdef USE_ISO
2854 cleanup3:
2855 free_irq(pdev->resource[2].start, udc);
2856 #endif
2857
2858 cleanup2:
2859 free_irq(pdev->resource[1].start, udc);
2860
2861 cleanup1:
2862 kfree (udc);
2863 udc = NULL;
2864
2865 cleanup0:
2866 if (xceiv)
2867 put_device(xceiv->dev);
2868 release_mem_region(pdev->resource[0].start,
2869 pdev->resource[0].end - pdev->resource[0].start + 1);
2870 return status;
2871 }
2872
2873 static int __exit omap_udc_remove(struct platform_device *pdev)
2874 {
2875 DECLARE_COMPLETION(done);
2876
2877 if (!udc)
2878 return -ENODEV;
2879
2880 udc->done = &done;
2881
2882 pullup_disable(udc);
2883 if (udc->transceiver) {
2884 put_device(udc->transceiver->dev);
2885 udc->transceiver = NULL;
2886 }
2887 UDC_SYSCON1_REG = 0;
2888
2889 remove_proc_file();
2890
2891 #ifdef USE_ISO
2892 free_irq(pdev->resource[3].start, udc);
2893 #endif
2894 free_irq(pdev->resource[2].start, udc);
2895 free_irq(pdev->resource[1].start, udc);
2896
2897 release_mem_region(pdev->resource[0].start,
2898 pdev->resource[0].end - pdev->resource[0].start + 1);
2899
2900 device_unregister(&udc->gadget.dev);
2901 wait_for_completion(&done);
2902
2903 return 0;
2904 }
2905
2906 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2907 * system is forced into deep sleep
2908 *
2909 * REVISIT we should probably reject suspend requests when there's a host
2910 * session active, rather than disconnecting, at least on boards that can
2911 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
2912 * make host resumes and VBUS detection trigger OMAP wakeup events; that
2913 * may involve talking to an external transceiver (e.g. isp1301).
2914 */
2915
2916 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2917 {
2918 u32 devstat;
2919
2920 devstat = UDC_DEVSTAT_REG;
2921
2922 /* we're requesting 48 MHz clock if the pullup is enabled
2923 * (== we're attached to the host) and we're not suspended,
2924 * which would prevent entry to deep sleep...
2925 */
2926 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2927 WARN("session active; suspend requires disconnect\n");
2928 omap_pullup(&udc->gadget, 0);
2929 }
2930
2931 udc->gadget.dev.power.power_state = PMSG_SUSPEND;
2932 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
2933 return 0;
2934 }
2935
2936 static int omap_udc_resume(struct platform_device *dev)
2937 {
2938 DBG("resume + wakeup/SRP\n");
2939 omap_pullup(&udc->gadget, 1);
2940
2941 /* maybe the host would enumerate us if we nudged it */
2942 msleep(100);
2943 return omap_wakeup(&udc->gadget);
2944 }
2945
2946 /*-------------------------------------------------------------------------*/
2947
2948 static struct platform_driver udc_driver = {
2949 .probe = omap_udc_probe,
2950 .remove = __exit_p(omap_udc_remove),
2951 .suspend = omap_udc_suspend,
2952 .resume = omap_udc_resume,
2953 .driver = {
2954 .owner = THIS_MODULE,
2955 .name = (char *) driver_name,
2956 },
2957 };
2958
2959 static int __init udc_init(void)
2960 {
2961 INFO("%s, version: " DRIVER_VERSION
2962 #ifdef USE_ISO
2963 " (iso)"
2964 #endif
2965 "%s\n", driver_desc,
2966 use_dma ? " (dma)" : "");
2967 return platform_driver_register(&udc_driver);
2968 }
2969 module_init(udc_init);
2970
2971 static void __exit udc_exit(void)
2972 {
2973 platform_driver_unregister(&udc_driver);
2974 }
2975 module_exit(udc_exit);
2976
2977 MODULE_DESCRIPTION(DRIVER_DESC);
2978 MODULE_LICENSE("GPL");
2979
kernel source for telekom puls (alcatel/mediatek)