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Merge tag 'v3.10.105' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / amd5536udc.c
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 /*
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17 *
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20 * by BIOS init).
21 *
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
25 */
26
27 /* debug control */
28 /* #define UDC_VERBOSE */
29
30 /* Driver strings */
31 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
32 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
33
34 /* system */
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
48 #include <linux/fs.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
52 #include <linux/io.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
55
56 #include <asm/byteorder.h>
57 #include <asm/unaligned.h>
58
59 /* gadget stack */
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
62
63 /* udc specific */
64 #include "amd5536udc.h"
65
66
67 static void udc_tasklet_disconnect(unsigned long);
68 static void empty_req_queue(struct udc_ep *);
69 static int udc_probe(struct udc *dev);
70 static void udc_basic_init(struct udc *dev);
71 static void udc_setup_endpoints(struct udc *dev);
72 static void udc_soft_reset(struct udc *dev);
73 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
74 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
75 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
76 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
77 unsigned long buf_len, gfp_t gfp_flags);
78 static int udc_remote_wakeup(struct udc *dev);
79 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
80 static void udc_pci_remove(struct pci_dev *pdev);
81
82 /* description */
83 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
84 static const char name[] = "amd5536udc";
85
86 /* structure to hold endpoint function pointers */
87 static const struct usb_ep_ops udc_ep_ops;
88
89 /* received setup data */
90 static union udc_setup_data setup_data;
91
92 /* pointer to device object */
93 static struct udc *udc;
94
95 /* irq spin lock for soft reset */
96 static DEFINE_SPINLOCK(udc_irq_spinlock);
97 /* stall spin lock */
98 static DEFINE_SPINLOCK(udc_stall_spinlock);
99
100 /*
101 * slave mode: pending bytes in rx fifo after nyet,
102 * used if EPIN irq came but no req was available
103 */
104 static unsigned int udc_rxfifo_pending;
105
106 /* count soft resets after suspend to avoid loop */
107 static int soft_reset_occured;
108 static int soft_reset_after_usbreset_occured;
109
110 /* timer */
111 static struct timer_list udc_timer;
112 static int stop_timer;
113
114 /* set_rde -- Is used to control enabling of RX DMA. Problem is
115 * that UDC has only one bit (RDE) to enable/disable RX DMA for
116 * all OUT endpoints. So we have to handle race conditions like
117 * when OUT data reaches the fifo but no request was queued yet.
118 * This cannot be solved by letting the RX DMA disabled until a
119 * request gets queued because there may be other OUT packets
120 * in the FIFO (important for not blocking control traffic).
121 * The value of set_rde controls the correspondig timer.
122 *
123 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
124 * set_rde 0 == do not touch RDE, do no start the RDE timer
125 * set_rde 1 == timer function will look whether FIFO has data
126 * set_rde 2 == set by timer function to enable RX DMA on next call
127 */
128 static int set_rde = -1;
129
130 static DECLARE_COMPLETION(on_exit);
131 static struct timer_list udc_pollstall_timer;
132 static int stop_pollstall_timer;
133 static DECLARE_COMPLETION(on_pollstall_exit);
134
135 /* tasklet for usb disconnect */
136 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
137 (unsigned long) &udc);
138
139
140 /* endpoint names used for print */
141 static const char ep0_string[] = "ep0in";
142 static const char *const ep_string[] = {
143 ep0_string,
144 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
145 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
146 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
147 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
148 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
149 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
150 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
151 };
152
153 /* DMA usage flag */
154 static bool use_dma = 1;
155 /* packet per buffer dma */
156 static bool use_dma_ppb = 1;
157 /* with per descr. update */
158 static bool use_dma_ppb_du;
159 /* buffer fill mode */
160 static int use_dma_bufferfill_mode;
161 /* full speed only mode */
162 static bool use_fullspeed;
163 /* tx buffer size for high speed */
164 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
165
166 /* module parameters */
167 module_param(use_dma, bool, S_IRUGO);
168 MODULE_PARM_DESC(use_dma, "true for DMA");
169 module_param(use_dma_ppb, bool, S_IRUGO);
170 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
171 module_param(use_dma_ppb_du, bool, S_IRUGO);
172 MODULE_PARM_DESC(use_dma_ppb_du,
173 "true for DMA in packet per buffer mode with descriptor update");
174 module_param(use_fullspeed, bool, S_IRUGO);
175 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
176
177 /*---------------------------------------------------------------------------*/
178 /* Prints UDC device registers and endpoint irq registers */
179 static void print_regs(struct udc *dev)
180 {
181 DBG(dev, "------- Device registers -------\n");
182 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
183 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
184 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
185 DBG(dev, "\n");
186 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
187 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
188 DBG(dev, "\n");
189 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
190 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
191 DBG(dev, "\n");
192 DBG(dev, "USE DMA = %d\n", use_dma);
193 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
194 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
195 "WITHOUT desc. update)\n");
196 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
197 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
198 DBG(dev, "DMA mode = PPBDU (packet per buffer "
199 "WITH desc. update)\n");
200 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
201 }
202 if (use_dma && use_dma_bufferfill_mode) {
203 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
204 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
205 }
206 if (!use_dma)
207 dev_info(&dev->pdev->dev, "FIFO mode\n");
208 DBG(dev, "-------------------------------------------------------\n");
209 }
210
211 /* Masks unused interrupts */
212 static int udc_mask_unused_interrupts(struct udc *dev)
213 {
214 u32 tmp;
215
216 /* mask all dev interrupts */
217 tmp = AMD_BIT(UDC_DEVINT_SVC) |
218 AMD_BIT(UDC_DEVINT_ENUM) |
219 AMD_BIT(UDC_DEVINT_US) |
220 AMD_BIT(UDC_DEVINT_UR) |
221 AMD_BIT(UDC_DEVINT_ES) |
222 AMD_BIT(UDC_DEVINT_SI) |
223 AMD_BIT(UDC_DEVINT_SOF)|
224 AMD_BIT(UDC_DEVINT_SC);
225 writel(tmp, &dev->regs->irqmsk);
226
227 /* mask all ep interrupts */
228 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
229
230 return 0;
231 }
232
233 /* Enables endpoint 0 interrupts */
234 static int udc_enable_ep0_interrupts(struct udc *dev)
235 {
236 u32 tmp;
237
238 DBG(dev, "udc_enable_ep0_interrupts()\n");
239
240 /* read irq mask */
241 tmp = readl(&dev->regs->ep_irqmsk);
242 /* enable ep0 irq's */
243 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
244 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
245 writel(tmp, &dev->regs->ep_irqmsk);
246
247 return 0;
248 }
249
250 /* Enables device interrupts for SET_INTF and SET_CONFIG */
251 static int udc_enable_dev_setup_interrupts(struct udc *dev)
252 {
253 u32 tmp;
254
255 DBG(dev, "enable device interrupts for setup data\n");
256
257 /* read irq mask */
258 tmp = readl(&dev->regs->irqmsk);
259
260 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
261 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
262 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
263 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
264 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
265 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
266 writel(tmp, &dev->regs->irqmsk);
267
268 return 0;
269 }
270
271 /* Calculates fifo start of endpoint based on preceding endpoints */
272 static int udc_set_txfifo_addr(struct udc_ep *ep)
273 {
274 struct udc *dev;
275 u32 tmp;
276 int i;
277
278 if (!ep || !(ep->in))
279 return -EINVAL;
280
281 dev = ep->dev;
282 ep->txfifo = dev->txfifo;
283
284 /* traverse ep's */
285 for (i = 0; i < ep->num; i++) {
286 if (dev->ep[i].regs) {
287 /* read fifo size */
288 tmp = readl(&dev->ep[i].regs->bufin_framenum);
289 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
290 ep->txfifo += tmp;
291 }
292 }
293 return 0;
294 }
295
296 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
297 static u32 cnak_pending;
298
299 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
300 {
301 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
302 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
303 cnak_pending |= 1 << (num);
304 ep->naking = 1;
305 } else
306 cnak_pending = cnak_pending & (~(1 << (num)));
307 }
308
309
310 /* Enables endpoint, is called by gadget driver */
311 static int
312 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
313 {
314 struct udc_ep *ep;
315 struct udc *dev;
316 u32 tmp;
317 unsigned long iflags;
318 u8 udc_csr_epix;
319 unsigned maxpacket;
320
321 if (!usbep
322 || usbep->name == ep0_string
323 || !desc
324 || desc->bDescriptorType != USB_DT_ENDPOINT)
325 return -EINVAL;
326
327 ep = container_of(usbep, struct udc_ep, ep);
328 dev = ep->dev;
329
330 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
331
332 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
333 return -ESHUTDOWN;
334
335 spin_lock_irqsave(&dev->lock, iflags);
336 ep->ep.desc = desc;
337
338 ep->halted = 0;
339
340 /* set traffic type */
341 tmp = readl(&dev->ep[ep->num].regs->ctl);
342 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
343 writel(tmp, &dev->ep[ep->num].regs->ctl);
344
345 /* set max packet size */
346 maxpacket = usb_endpoint_maxp(desc);
347 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
348 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
349 ep->ep.maxpacket = maxpacket;
350 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
351
352 /* IN ep */
353 if (ep->in) {
354
355 /* ep ix in UDC CSR register space */
356 udc_csr_epix = ep->num;
357
358 /* set buffer size (tx fifo entries) */
359 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
360 /* double buffering: fifo size = 2 x max packet size */
361 tmp = AMD_ADDBITS(
362 tmp,
363 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
364 / UDC_DWORD_BYTES,
365 UDC_EPIN_BUFF_SIZE);
366 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
367
368 /* calc. tx fifo base addr */
369 udc_set_txfifo_addr(ep);
370
371 /* flush fifo */
372 tmp = readl(&ep->regs->ctl);
373 tmp |= AMD_BIT(UDC_EPCTL_F);
374 writel(tmp, &ep->regs->ctl);
375
376 /* OUT ep */
377 } else {
378 /* ep ix in UDC CSR register space */
379 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
380
381 /* set max packet size UDC CSR */
382 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
383 tmp = AMD_ADDBITS(tmp, maxpacket,
384 UDC_CSR_NE_MAX_PKT);
385 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
386
387 if (use_dma && !ep->in) {
388 /* alloc and init BNA dummy request */
389 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
390 ep->bna_occurred = 0;
391 }
392
393 if (ep->num != UDC_EP0OUT_IX)
394 dev->data_ep_enabled = 1;
395 }
396
397 /* set ep values */
398 tmp = readl(&dev->csr->ne[udc_csr_epix]);
399 /* max packet */
400 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
401 /* ep number */
402 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
403 /* ep direction */
404 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
405 /* ep type */
406 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
407 /* ep config */
408 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
409 /* ep interface */
410 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
411 /* ep alt */
412 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
413 /* write reg */
414 writel(tmp, &dev->csr->ne[udc_csr_epix]);
415
416 /* enable ep irq */
417 tmp = readl(&dev->regs->ep_irqmsk);
418 tmp &= AMD_UNMASK_BIT(ep->num);
419 writel(tmp, &dev->regs->ep_irqmsk);
420
421 /*
422 * clear NAK by writing CNAK
423 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
424 */
425 if (!use_dma || ep->in) {
426 tmp = readl(&ep->regs->ctl);
427 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
428 writel(tmp, &ep->regs->ctl);
429 ep->naking = 0;
430 UDC_QUEUE_CNAK(ep, ep->num);
431 }
432 tmp = desc->bEndpointAddress;
433 DBG(dev, "%s enabled\n", usbep->name);
434
435 spin_unlock_irqrestore(&dev->lock, iflags);
436 return 0;
437 }
438
439 /* Resets endpoint */
440 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
441 {
442 u32 tmp;
443
444 VDBG(ep->dev, "ep-%d reset\n", ep->num);
445 ep->ep.desc = NULL;
446 ep->ep.ops = &udc_ep_ops;
447 INIT_LIST_HEAD(&ep->queue);
448
449 ep->ep.maxpacket = (u16) ~0;
450 /* set NAK */
451 tmp = readl(&ep->regs->ctl);
452 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
453 writel(tmp, &ep->regs->ctl);
454 ep->naking = 1;
455
456 /* disable interrupt */
457 tmp = readl(&regs->ep_irqmsk);
458 tmp |= AMD_BIT(ep->num);
459 writel(tmp, &regs->ep_irqmsk);
460
461 if (ep->in) {
462 /* unset P and IN bit of potential former DMA */
463 tmp = readl(&ep->regs->ctl);
464 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
465 writel(tmp, &ep->regs->ctl);
466
467 tmp = readl(&ep->regs->sts);
468 tmp |= AMD_BIT(UDC_EPSTS_IN);
469 writel(tmp, &ep->regs->sts);
470
471 /* flush the fifo */
472 tmp = readl(&ep->regs->ctl);
473 tmp |= AMD_BIT(UDC_EPCTL_F);
474 writel(tmp, &ep->regs->ctl);
475
476 }
477 /* reset desc pointer */
478 writel(0, &ep->regs->desptr);
479 }
480
481 /* Disables endpoint, is called by gadget driver */
482 static int udc_ep_disable(struct usb_ep *usbep)
483 {
484 struct udc_ep *ep = NULL;
485 unsigned long iflags;
486
487 if (!usbep)
488 return -EINVAL;
489
490 ep = container_of(usbep, struct udc_ep, ep);
491 if (usbep->name == ep0_string || !ep->ep.desc)
492 return -EINVAL;
493
494 DBG(ep->dev, "Disable ep-%d\n", ep->num);
495
496 spin_lock_irqsave(&ep->dev->lock, iflags);
497 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
498 empty_req_queue(ep);
499 ep_init(ep->dev->regs, ep);
500 spin_unlock_irqrestore(&ep->dev->lock, iflags);
501
502 return 0;
503 }
504
505 /* Allocates request packet, called by gadget driver */
506 static struct usb_request *
507 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
508 {
509 struct udc_request *req;
510 struct udc_data_dma *dma_desc;
511 struct udc_ep *ep;
512
513 if (!usbep)
514 return NULL;
515
516 ep = container_of(usbep, struct udc_ep, ep);
517
518 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
519 req = kzalloc(sizeof(struct udc_request), gfp);
520 if (!req)
521 return NULL;
522
523 req->req.dma = DMA_DONT_USE;
524 INIT_LIST_HEAD(&req->queue);
525
526 if (ep->dma) {
527 /* ep0 in requests are allocated from data pool here */
528 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
529 &req->td_phys);
530 if (!dma_desc) {
531 kfree(req);
532 return NULL;
533 }
534
535 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
536 "td_phys = %lx\n",
537 req, dma_desc,
538 (unsigned long)req->td_phys);
539 /* prevent from using desc. - set HOST BUSY */
540 dma_desc->status = AMD_ADDBITS(dma_desc->status,
541 UDC_DMA_STP_STS_BS_HOST_BUSY,
542 UDC_DMA_STP_STS_BS);
543 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
544 req->td_data = dma_desc;
545 req->td_data_last = NULL;
546 req->chain_len = 1;
547 }
548
549 return &req->req;
550 }
551
552 /* Frees request packet, called by gadget driver */
553 static void
554 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
555 {
556 struct udc_ep *ep;
557 struct udc_request *req;
558
559 if (!usbep || !usbreq)
560 return;
561
562 ep = container_of(usbep, struct udc_ep, ep);
563 req = container_of(usbreq, struct udc_request, req);
564 VDBG(ep->dev, "free_req req=%p\n", req);
565 BUG_ON(!list_empty(&req->queue));
566 if (req->td_data) {
567 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
568
569 /* free dma chain if created */
570 if (req->chain_len > 1)
571 udc_free_dma_chain(ep->dev, req);
572
573 pci_pool_free(ep->dev->data_requests, req->td_data,
574 req->td_phys);
575 }
576 kfree(req);
577 }
578
579 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
580 static void udc_init_bna_dummy(struct udc_request *req)
581 {
582 if (req) {
583 /* set last bit */
584 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
585 /* set next pointer to itself */
586 req->td_data->next = req->td_phys;
587 /* set HOST BUSY */
588 req->td_data->status
589 = AMD_ADDBITS(req->td_data->status,
590 UDC_DMA_STP_STS_BS_DMA_DONE,
591 UDC_DMA_STP_STS_BS);
592 #ifdef UDC_VERBOSE
593 pr_debug("bna desc = %p, sts = %08x\n",
594 req->td_data, req->td_data->status);
595 #endif
596 }
597 }
598
599 /* Allocate BNA dummy descriptor */
600 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
601 {
602 struct udc_request *req = NULL;
603 struct usb_request *_req = NULL;
604
605 /* alloc the dummy request */
606 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
607 if (_req) {
608 req = container_of(_req, struct udc_request, req);
609 ep->bna_dummy_req = req;
610 udc_init_bna_dummy(req);
611 }
612 return req;
613 }
614
615 /* Write data to TX fifo for IN packets */
616 static void
617 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
618 {
619 u8 *req_buf;
620 u32 *buf;
621 int i, j;
622 unsigned bytes = 0;
623 unsigned remaining = 0;
624
625 if (!req || !ep)
626 return;
627
628 req_buf = req->buf + req->actual;
629 prefetch(req_buf);
630 remaining = req->length - req->actual;
631
632 buf = (u32 *) req_buf;
633
634 bytes = ep->ep.maxpacket;
635 if (bytes > remaining)
636 bytes = remaining;
637
638 /* dwords first */
639 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
640 writel(*(buf + i), ep->txfifo);
641
642 /* remaining bytes must be written by byte access */
643 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
644 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
645 ep->txfifo);
646 }
647
648 /* dummy write confirm */
649 writel(0, &ep->regs->confirm);
650 }
651
652 /* Read dwords from RX fifo for OUT transfers */
653 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
654 {
655 int i;
656
657 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
658
659 for (i = 0; i < dwords; i++)
660 *(buf + i) = readl(dev->rxfifo);
661 return 0;
662 }
663
664 /* Read bytes from RX fifo for OUT transfers */
665 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
666 {
667 int i, j;
668 u32 tmp;
669
670 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
671
672 /* dwords first */
673 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
674 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
675
676 /* remaining bytes must be read by byte access */
677 if (bytes % UDC_DWORD_BYTES) {
678 tmp = readl(dev->rxfifo);
679 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
680 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
681 tmp = tmp >> UDC_BITS_PER_BYTE;
682 }
683 }
684
685 return 0;
686 }
687
688 /* Read data from RX fifo for OUT transfers */
689 static int
690 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
691 {
692 u8 *buf;
693 unsigned buf_space;
694 unsigned bytes = 0;
695 unsigned finished = 0;
696
697 /* received number bytes */
698 bytes = readl(&ep->regs->sts);
699 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
700
701 buf_space = req->req.length - req->req.actual;
702 buf = req->req.buf + req->req.actual;
703 if (bytes > buf_space) {
704 if ((buf_space % ep->ep.maxpacket) != 0) {
705 DBG(ep->dev,
706 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
707 ep->ep.name, bytes, buf_space);
708 req->req.status = -EOVERFLOW;
709 }
710 bytes = buf_space;
711 }
712 req->req.actual += bytes;
713
714 /* last packet ? */
715 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
716 || ((req->req.actual == req->req.length) && !req->req.zero))
717 finished = 1;
718
719 /* read rx fifo bytes */
720 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
721 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
722
723 return finished;
724 }
725
726 /* create/re-init a DMA descriptor or a DMA descriptor chain */
727 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
728 {
729 int retval = 0;
730 u32 tmp;
731
732 VDBG(ep->dev, "prep_dma\n");
733 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
734 ep->num, req->td_data);
735
736 /* set buffer pointer */
737 req->td_data->bufptr = req->req.dma;
738
739 /* set last bit */
740 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
741
742 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
743 if (use_dma_ppb) {
744
745 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
746 if (retval != 0) {
747 if (retval == -ENOMEM)
748 DBG(ep->dev, "Out of DMA memory\n");
749 return retval;
750 }
751 if (ep->in) {
752 if (req->req.length == ep->ep.maxpacket) {
753 /* write tx bytes */
754 req->td_data->status =
755 AMD_ADDBITS(req->td_data->status,
756 ep->ep.maxpacket,
757 UDC_DMA_IN_STS_TXBYTES);
758
759 }
760 }
761
762 }
763
764 if (ep->in) {
765 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
766 "maxpacket=%d ep%d\n",
767 use_dma_ppb, req->req.length,
768 ep->ep.maxpacket, ep->num);
769 /*
770 * if bytes < max packet then tx bytes must
771 * be written in packet per buffer mode
772 */
773 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
774 || ep->num == UDC_EP0OUT_IX
775 || ep->num == UDC_EP0IN_IX) {
776 /* write tx bytes */
777 req->td_data->status =
778 AMD_ADDBITS(req->td_data->status,
779 req->req.length,
780 UDC_DMA_IN_STS_TXBYTES);
781 /* reset frame num */
782 req->td_data->status =
783 AMD_ADDBITS(req->td_data->status,
784 0,
785 UDC_DMA_IN_STS_FRAMENUM);
786 }
787 /* set HOST BUSY */
788 req->td_data->status =
789 AMD_ADDBITS(req->td_data->status,
790 UDC_DMA_STP_STS_BS_HOST_BUSY,
791 UDC_DMA_STP_STS_BS);
792 } else {
793 VDBG(ep->dev, "OUT set host ready\n");
794 /* set HOST READY */
795 req->td_data->status =
796 AMD_ADDBITS(req->td_data->status,
797 UDC_DMA_STP_STS_BS_HOST_READY,
798 UDC_DMA_STP_STS_BS);
799
800
801 /* clear NAK by writing CNAK */
802 if (ep->naking) {
803 tmp = readl(&ep->regs->ctl);
804 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
805 writel(tmp, &ep->regs->ctl);
806 ep->naking = 0;
807 UDC_QUEUE_CNAK(ep, ep->num);
808 }
809
810 }
811
812 return retval;
813 }
814
815 /* Completes request packet ... caller MUST hold lock */
816 static void
817 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
818 __releases(ep->dev->lock)
819 __acquires(ep->dev->lock)
820 {
821 struct udc *dev;
822 unsigned halted;
823
824 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
825
826 dev = ep->dev;
827 /* unmap DMA */
828 if (ep->dma)
829 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
830
831 halted = ep->halted;
832 ep->halted = 1;
833
834 /* set new status if pending */
835 if (req->req.status == -EINPROGRESS)
836 req->req.status = sts;
837
838 /* remove from ep queue */
839 list_del_init(&req->queue);
840
841 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
842 &req->req, req->req.length, ep->ep.name, sts);
843
844 spin_unlock(&dev->lock);
845 req->req.complete(&ep->ep, &req->req);
846 spin_lock(&dev->lock);
847 ep->halted = halted;
848 }
849
850 /* frees pci pool descriptors of a DMA chain */
851 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
852 {
853
854 int ret_val = 0;
855 struct udc_data_dma *td;
856 struct udc_data_dma *td_last = NULL;
857 unsigned int i;
858
859 DBG(dev, "free chain req = %p\n", req);
860
861 /* do not free first desc., will be done by free for request */
862 td_last = req->td_data;
863 td = phys_to_virt(td_last->next);
864
865 for (i = 1; i < req->chain_len; i++) {
866
867 pci_pool_free(dev->data_requests, td,
868 (dma_addr_t) td_last->next);
869 td_last = td;
870 td = phys_to_virt(td_last->next);
871 }
872
873 return ret_val;
874 }
875
876 /* Iterates to the end of a DMA chain and returns last descriptor */
877 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
878 {
879 struct udc_data_dma *td;
880
881 td = req->td_data;
882 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
883 td = phys_to_virt(td->next);
884
885 return td;
886
887 }
888
889 /* Iterates to the end of a DMA chain and counts bytes received */
890 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
891 {
892 struct udc_data_dma *td;
893 u32 count;
894
895 td = req->td_data;
896 /* received number bytes */
897 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
898
899 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
900 td = phys_to_virt(td->next);
901 /* received number bytes */
902 if (td) {
903 count += AMD_GETBITS(td->status,
904 UDC_DMA_OUT_STS_RXBYTES);
905 }
906 }
907
908 return count;
909
910 }
911
912 /* Creates or re-inits a DMA chain */
913 static int udc_create_dma_chain(
914 struct udc_ep *ep,
915 struct udc_request *req,
916 unsigned long buf_len, gfp_t gfp_flags
917 )
918 {
919 unsigned long bytes = req->req.length;
920 unsigned int i;
921 dma_addr_t dma_addr;
922 struct udc_data_dma *td = NULL;
923 struct udc_data_dma *last = NULL;
924 unsigned long txbytes;
925 unsigned create_new_chain = 0;
926 unsigned len;
927
928 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
929 bytes, buf_len);
930 dma_addr = DMA_DONT_USE;
931
932 /* unset L bit in first desc for OUT */
933 if (!ep->in)
934 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
935
936 /* alloc only new desc's if not already available */
937 len = req->req.length / ep->ep.maxpacket;
938 if (req->req.length % ep->ep.maxpacket)
939 len++;
940
941 if (len > req->chain_len) {
942 /* shorter chain already allocated before */
943 if (req->chain_len > 1)
944 udc_free_dma_chain(ep->dev, req);
945 req->chain_len = len;
946 create_new_chain = 1;
947 }
948
949 td = req->td_data;
950 /* gen. required number of descriptors and buffers */
951 for (i = buf_len; i < bytes; i += buf_len) {
952 /* create or determine next desc. */
953 if (create_new_chain) {
954
955 td = pci_pool_alloc(ep->dev->data_requests,
956 gfp_flags, &dma_addr);
957 if (!td)
958 return -ENOMEM;
959
960 td->status = 0;
961 } else if (i == buf_len) {
962 /* first td */
963 td = (struct udc_data_dma *) phys_to_virt(
964 req->td_data->next);
965 td->status = 0;
966 } else {
967 td = (struct udc_data_dma *) phys_to_virt(last->next);
968 td->status = 0;
969 }
970
971
972 if (td)
973 td->bufptr = req->req.dma + i; /* assign buffer */
974 else
975 break;
976
977 /* short packet ? */
978 if ((bytes - i) >= buf_len) {
979 txbytes = buf_len;
980 } else {
981 /* short packet */
982 txbytes = bytes - i;
983 }
984
985 /* link td and assign tx bytes */
986 if (i == buf_len) {
987 if (create_new_chain)
988 req->td_data->next = dma_addr;
989 /*
990 else
991 req->td_data->next = virt_to_phys(td);
992 */
993 /* write tx bytes */
994 if (ep->in) {
995 /* first desc */
996 req->td_data->status =
997 AMD_ADDBITS(req->td_data->status,
998 ep->ep.maxpacket,
999 UDC_DMA_IN_STS_TXBYTES);
1000 /* second desc */
1001 td->status = AMD_ADDBITS(td->status,
1002 txbytes,
1003 UDC_DMA_IN_STS_TXBYTES);
1004 }
1005 } else {
1006 if (create_new_chain)
1007 last->next = dma_addr;
1008 /*
1009 else
1010 last->next = virt_to_phys(td);
1011 */
1012 if (ep->in) {
1013 /* write tx bytes */
1014 td->status = AMD_ADDBITS(td->status,
1015 txbytes,
1016 UDC_DMA_IN_STS_TXBYTES);
1017 }
1018 }
1019 last = td;
1020 }
1021 /* set last bit */
1022 if (td) {
1023 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1024 /* last desc. points to itself */
1025 req->td_data_last = td;
1026 }
1027
1028 return 0;
1029 }
1030
1031 /* Enabling RX DMA */
1032 static void udc_set_rde(struct udc *dev)
1033 {
1034 u32 tmp;
1035
1036 VDBG(dev, "udc_set_rde()\n");
1037 /* stop RDE timer */
1038 if (timer_pending(&udc_timer)) {
1039 set_rde = 0;
1040 mod_timer(&udc_timer, jiffies - 1);
1041 }
1042 /* set RDE */
1043 tmp = readl(&dev->regs->ctl);
1044 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1045 writel(tmp, &dev->regs->ctl);
1046 }
1047
1048 /* Queues a request packet, called by gadget driver */
1049 static int
1050 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1051 {
1052 int retval = 0;
1053 u8 open_rxfifo = 0;
1054 unsigned long iflags;
1055 struct udc_ep *ep;
1056 struct udc_request *req;
1057 struct udc *dev;
1058 u32 tmp;
1059
1060 /* check the inputs */
1061 req = container_of(usbreq, struct udc_request, req);
1062
1063 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1064 || !list_empty(&req->queue))
1065 return -EINVAL;
1066
1067 ep = container_of(usbep, struct udc_ep, ep);
1068 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1069 return -EINVAL;
1070
1071 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1072 dev = ep->dev;
1073
1074 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1075 return -ESHUTDOWN;
1076
1077 /* map dma (usually done before) */
1078 if (ep->dma) {
1079 VDBG(dev, "DMA map req %p\n", req);
1080 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1081 if (retval)
1082 return retval;
1083 }
1084
1085 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1086 usbep->name, usbreq, usbreq->length,
1087 req->td_data, usbreq->buf);
1088
1089 spin_lock_irqsave(&dev->lock, iflags);
1090 usbreq->actual = 0;
1091 usbreq->status = -EINPROGRESS;
1092 req->dma_done = 0;
1093
1094 /* on empty queue just do first transfer */
1095 if (list_empty(&ep->queue)) {
1096 /* zlp */
1097 if (usbreq->length == 0) {
1098 /* IN zlp's are handled by hardware */
1099 complete_req(ep, req, 0);
1100 VDBG(dev, "%s: zlp\n", ep->ep.name);
1101 /*
1102 * if set_config or set_intf is waiting for ack by zlp
1103 * then set CSR_DONE
1104 */
1105 if (dev->set_cfg_not_acked) {
1106 tmp = readl(&dev->regs->ctl);
1107 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1108 writel(tmp, &dev->regs->ctl);
1109 dev->set_cfg_not_acked = 0;
1110 }
1111 /* setup command is ACK'ed now by zlp */
1112 if (dev->waiting_zlp_ack_ep0in) {
1113 /* clear NAK by writing CNAK in EP0_IN */
1114 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1115 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1116 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1117 dev->ep[UDC_EP0IN_IX].naking = 0;
1118 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1119 UDC_EP0IN_IX);
1120 dev->waiting_zlp_ack_ep0in = 0;
1121 }
1122 goto finished;
1123 }
1124 if (ep->dma) {
1125 retval = prep_dma(ep, req, gfp);
1126 if (retval != 0)
1127 goto finished;
1128 /* write desc pointer to enable DMA */
1129 if (ep->in) {
1130 /* set HOST READY */
1131 req->td_data->status =
1132 AMD_ADDBITS(req->td_data->status,
1133 UDC_DMA_IN_STS_BS_HOST_READY,
1134 UDC_DMA_IN_STS_BS);
1135 }
1136
1137 /* disabled rx dma while descriptor update */
1138 if (!ep->in) {
1139 /* stop RDE timer */
1140 if (timer_pending(&udc_timer)) {
1141 set_rde = 0;
1142 mod_timer(&udc_timer, jiffies - 1);
1143 }
1144 /* clear RDE */
1145 tmp = readl(&dev->regs->ctl);
1146 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1147 writel(tmp, &dev->regs->ctl);
1148 open_rxfifo = 1;
1149
1150 /*
1151 * if BNA occurred then let BNA dummy desc.
1152 * point to current desc.
1153 */
1154 if (ep->bna_occurred) {
1155 VDBG(dev, "copy to BNA dummy desc.\n");
1156 memcpy(ep->bna_dummy_req->td_data,
1157 req->td_data,
1158 sizeof(struct udc_data_dma));
1159 }
1160 }
1161 /* write desc pointer */
1162 writel(req->td_phys, &ep->regs->desptr);
1163
1164 /* clear NAK by writing CNAK */
1165 if (ep->naking) {
1166 tmp = readl(&ep->regs->ctl);
1167 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1168 writel(tmp, &ep->regs->ctl);
1169 ep->naking = 0;
1170 UDC_QUEUE_CNAK(ep, ep->num);
1171 }
1172
1173 if (ep->in) {
1174 /* enable ep irq */
1175 tmp = readl(&dev->regs->ep_irqmsk);
1176 tmp &= AMD_UNMASK_BIT(ep->num);
1177 writel(tmp, &dev->regs->ep_irqmsk);
1178 }
1179 } else if (ep->in) {
1180 /* enable ep irq */
1181 tmp = readl(&dev->regs->ep_irqmsk);
1182 tmp &= AMD_UNMASK_BIT(ep->num);
1183 writel(tmp, &dev->regs->ep_irqmsk);
1184 }
1185
1186 } else if (ep->dma) {
1187
1188 /*
1189 * prep_dma not used for OUT ep's, this is not possible
1190 * for PPB modes, because of chain creation reasons
1191 */
1192 if (ep->in) {
1193 retval = prep_dma(ep, req, gfp);
1194 if (retval != 0)
1195 goto finished;
1196 }
1197 }
1198 VDBG(dev, "list_add\n");
1199 /* add request to ep queue */
1200 if (req) {
1201
1202 list_add_tail(&req->queue, &ep->queue);
1203
1204 /* open rxfifo if out data queued */
1205 if (open_rxfifo) {
1206 /* enable DMA */
1207 req->dma_going = 1;
1208 udc_set_rde(dev);
1209 if (ep->num != UDC_EP0OUT_IX)
1210 dev->data_ep_queued = 1;
1211 }
1212 /* stop OUT naking */
1213 if (!ep->in) {
1214 if (!use_dma && udc_rxfifo_pending) {
1215 DBG(dev, "udc_queue(): pending bytes in "
1216 "rxfifo after nyet\n");
1217 /*
1218 * read pending bytes afer nyet:
1219 * referring to isr
1220 */
1221 if (udc_rxfifo_read(ep, req)) {
1222 /* finish */
1223 complete_req(ep, req, 0);
1224 }
1225 udc_rxfifo_pending = 0;
1226
1227 }
1228 }
1229 }
1230
1231 finished:
1232 spin_unlock_irqrestore(&dev->lock, iflags);
1233 return retval;
1234 }
1235
1236 /* Empty request queue of an endpoint; caller holds spinlock */
1237 static void empty_req_queue(struct udc_ep *ep)
1238 {
1239 struct udc_request *req;
1240
1241 ep->halted = 1;
1242 while (!list_empty(&ep->queue)) {
1243 req = list_entry(ep->queue.next,
1244 struct udc_request,
1245 queue);
1246 complete_req(ep, req, -ESHUTDOWN);
1247 }
1248 }
1249
1250 /* Dequeues a request packet, called by gadget driver */
1251 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1252 {
1253 struct udc_ep *ep;
1254 struct udc_request *req;
1255 unsigned halted;
1256 unsigned long iflags;
1257
1258 ep = container_of(usbep, struct udc_ep, ep);
1259 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1260 && ep->num != UDC_EP0OUT_IX)))
1261 return -EINVAL;
1262
1263 req = container_of(usbreq, struct udc_request, req);
1264
1265 spin_lock_irqsave(&ep->dev->lock, iflags);
1266 halted = ep->halted;
1267 ep->halted = 1;
1268 /* request in processing or next one */
1269 if (ep->queue.next == &req->queue) {
1270 if (ep->dma && req->dma_going) {
1271 if (ep->in)
1272 ep->cancel_transfer = 1;
1273 else {
1274 u32 tmp;
1275 u32 dma_sts;
1276 /* stop potential receive DMA */
1277 tmp = readl(&udc->regs->ctl);
1278 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1279 &udc->regs->ctl);
1280 /*
1281 * Cancel transfer later in ISR
1282 * if descriptor was touched.
1283 */
1284 dma_sts = AMD_GETBITS(req->td_data->status,
1285 UDC_DMA_OUT_STS_BS);
1286 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1287 ep->cancel_transfer = 1;
1288 else {
1289 udc_init_bna_dummy(ep->req);
1290 writel(ep->bna_dummy_req->td_phys,
1291 &ep->regs->desptr);
1292 }
1293 writel(tmp, &udc->regs->ctl);
1294 }
1295 }
1296 }
1297 complete_req(ep, req, -ECONNRESET);
1298 ep->halted = halted;
1299
1300 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1301 return 0;
1302 }
1303
1304 /* Halt or clear halt of endpoint */
1305 static int
1306 udc_set_halt(struct usb_ep *usbep, int halt)
1307 {
1308 struct udc_ep *ep;
1309 u32 tmp;
1310 unsigned long iflags;
1311 int retval = 0;
1312
1313 if (!usbep)
1314 return -EINVAL;
1315
1316 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1317
1318 ep = container_of(usbep, struct udc_ep, ep);
1319 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1320 return -EINVAL;
1321 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1322 return -ESHUTDOWN;
1323
1324 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1325 /* halt or clear halt */
1326 if (halt) {
1327 if (ep->num == 0)
1328 ep->dev->stall_ep0in = 1;
1329 else {
1330 /*
1331 * set STALL
1332 * rxfifo empty not taken into acount
1333 */
1334 tmp = readl(&ep->regs->ctl);
1335 tmp |= AMD_BIT(UDC_EPCTL_S);
1336 writel(tmp, &ep->regs->ctl);
1337 ep->halted = 1;
1338
1339 /* setup poll timer */
1340 if (!timer_pending(&udc_pollstall_timer)) {
1341 udc_pollstall_timer.expires = jiffies +
1342 HZ * UDC_POLLSTALL_TIMER_USECONDS
1343 / (1000 * 1000);
1344 if (!stop_pollstall_timer) {
1345 DBG(ep->dev, "start polltimer\n");
1346 add_timer(&udc_pollstall_timer);
1347 }
1348 }
1349 }
1350 } else {
1351 /* ep is halted by set_halt() before */
1352 if (ep->halted) {
1353 tmp = readl(&ep->regs->ctl);
1354 /* clear stall bit */
1355 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1356 /* clear NAK by writing CNAK */
1357 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1358 writel(tmp, &ep->regs->ctl);
1359 ep->halted = 0;
1360 UDC_QUEUE_CNAK(ep, ep->num);
1361 }
1362 }
1363 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1364 return retval;
1365 }
1366
1367 /* gadget interface */
1368 static const struct usb_ep_ops udc_ep_ops = {
1369 .enable = udc_ep_enable,
1370 .disable = udc_ep_disable,
1371
1372 .alloc_request = udc_alloc_request,
1373 .free_request = udc_free_request,
1374
1375 .queue = udc_queue,
1376 .dequeue = udc_dequeue,
1377
1378 .set_halt = udc_set_halt,
1379 /* fifo ops not implemented */
1380 };
1381
1382 /*-------------------------------------------------------------------------*/
1383
1384 /* Get frame counter (not implemented) */
1385 static int udc_get_frame(struct usb_gadget *gadget)
1386 {
1387 return -EOPNOTSUPP;
1388 }
1389
1390 /* Remote wakeup gadget interface */
1391 static int udc_wakeup(struct usb_gadget *gadget)
1392 {
1393 struct udc *dev;
1394
1395 if (!gadget)
1396 return -EINVAL;
1397 dev = container_of(gadget, struct udc, gadget);
1398 udc_remote_wakeup(dev);
1399
1400 return 0;
1401 }
1402
1403 static int amd5536_udc_start(struct usb_gadget *g,
1404 struct usb_gadget_driver *driver);
1405 static int amd5536_udc_stop(struct usb_gadget *g,
1406 struct usb_gadget_driver *driver);
1407 /* gadget operations */
1408 static const struct usb_gadget_ops udc_ops = {
1409 .wakeup = udc_wakeup,
1410 .get_frame = udc_get_frame,
1411 .udc_start = amd5536_udc_start,
1412 .udc_stop = amd5536_udc_stop,
1413 };
1414
1415 /* Setups endpoint parameters, adds endpoints to linked list */
1416 static void make_ep_lists(struct udc *dev)
1417 {
1418 /* make gadget ep lists */
1419 INIT_LIST_HEAD(&dev->gadget.ep_list);
1420 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1421 &dev->gadget.ep_list);
1422 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1423 &dev->gadget.ep_list);
1424 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1425 &dev->gadget.ep_list);
1426
1427 /* fifo config */
1428 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1429 if (dev->gadget.speed == USB_SPEED_FULL)
1430 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1431 else if (dev->gadget.speed == USB_SPEED_HIGH)
1432 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1433 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1434 }
1435
1436 /* init registers at driver load time */
1437 static int startup_registers(struct udc *dev)
1438 {
1439 u32 tmp;
1440
1441 /* init controller by soft reset */
1442 udc_soft_reset(dev);
1443
1444 /* mask not needed interrupts */
1445 udc_mask_unused_interrupts(dev);
1446
1447 /* put into initial config */
1448 udc_basic_init(dev);
1449 /* link up all endpoints */
1450 udc_setup_endpoints(dev);
1451
1452 /* program speed */
1453 tmp = readl(&dev->regs->cfg);
1454 if (use_fullspeed)
1455 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1456 else
1457 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1458 writel(tmp, &dev->regs->cfg);
1459
1460 return 0;
1461 }
1462
1463 /* Inits UDC context */
1464 static void udc_basic_init(struct udc *dev)
1465 {
1466 u32 tmp;
1467
1468 DBG(dev, "udc_basic_init()\n");
1469
1470 dev->gadget.speed = USB_SPEED_UNKNOWN;
1471
1472 /* stop RDE timer */
1473 if (timer_pending(&udc_timer)) {
1474 set_rde = 0;
1475 mod_timer(&udc_timer, jiffies - 1);
1476 }
1477 /* stop poll stall timer */
1478 if (timer_pending(&udc_pollstall_timer))
1479 mod_timer(&udc_pollstall_timer, jiffies - 1);
1480 /* disable DMA */
1481 tmp = readl(&dev->regs->ctl);
1482 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1483 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1484 writel(tmp, &dev->regs->ctl);
1485
1486 /* enable dynamic CSR programming */
1487 tmp = readl(&dev->regs->cfg);
1488 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1489 /* set self powered */
1490 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1491 /* set remote wakeupable */
1492 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1493 writel(tmp, &dev->regs->cfg);
1494
1495 make_ep_lists(dev);
1496
1497 dev->data_ep_enabled = 0;
1498 dev->data_ep_queued = 0;
1499 }
1500
1501 /* Sets initial endpoint parameters */
1502 static void udc_setup_endpoints(struct udc *dev)
1503 {
1504 struct udc_ep *ep;
1505 u32 tmp;
1506 u32 reg;
1507
1508 DBG(dev, "udc_setup_endpoints()\n");
1509
1510 /* read enum speed */
1511 tmp = readl(&dev->regs->sts);
1512 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1513 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1514 dev->gadget.speed = USB_SPEED_HIGH;
1515 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1516 dev->gadget.speed = USB_SPEED_FULL;
1517
1518 /* set basic ep parameters */
1519 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1520 ep = &dev->ep[tmp];
1521 ep->dev = dev;
1522 ep->ep.name = ep_string[tmp];
1523 ep->num = tmp;
1524 /* txfifo size is calculated at enable time */
1525 ep->txfifo = dev->txfifo;
1526
1527 /* fifo size */
1528 if (tmp < UDC_EPIN_NUM) {
1529 ep->fifo_depth = UDC_TXFIFO_SIZE;
1530 ep->in = 1;
1531 } else {
1532 ep->fifo_depth = UDC_RXFIFO_SIZE;
1533 ep->in = 0;
1534
1535 }
1536 ep->regs = &dev->ep_regs[tmp];
1537 /*
1538 * ep will be reset only if ep was not enabled before to avoid
1539 * disabling ep interrupts when ENUM interrupt occurs but ep is
1540 * not enabled by gadget driver
1541 */
1542 if (!ep->ep.desc)
1543 ep_init(dev->regs, ep);
1544
1545 if (use_dma) {
1546 /*
1547 * ep->dma is not really used, just to indicate that
1548 * DMA is active: remove this
1549 * dma regs = dev control regs
1550 */
1551 ep->dma = &dev->regs->ctl;
1552
1553 /* nak OUT endpoints until enable - not for ep0 */
1554 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1555 && tmp > UDC_EPIN_NUM) {
1556 /* set NAK */
1557 reg = readl(&dev->ep[tmp].regs->ctl);
1558 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1559 writel(reg, &dev->ep[tmp].regs->ctl);
1560 dev->ep[tmp].naking = 1;
1561
1562 }
1563 }
1564 }
1565 /* EP0 max packet */
1566 if (dev->gadget.speed == USB_SPEED_FULL) {
1567 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1568 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1569 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1570 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1571 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1572 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1573 }
1574
1575 /*
1576 * with suspend bug workaround, ep0 params for gadget driver
1577 * are set at gadget driver bind() call
1578 */
1579 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1580 dev->ep[UDC_EP0IN_IX].halted = 0;
1581 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1582
1583 /* init cfg/alt/int */
1584 dev->cur_config = 0;
1585 dev->cur_intf = 0;
1586 dev->cur_alt = 0;
1587 }
1588
1589 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1590 static void usb_connect(struct udc *dev)
1591 {
1592
1593 dev_info(&dev->pdev->dev, "USB Connect\n");
1594
1595 dev->connected = 1;
1596
1597 /* put into initial config */
1598 udc_basic_init(dev);
1599
1600 /* enable device setup interrupts */
1601 udc_enable_dev_setup_interrupts(dev);
1602 }
1603
1604 /*
1605 * Calls gadget with disconnect event and resets the UDC and makes
1606 * initial bringup to be ready for ep0 events
1607 */
1608 static void usb_disconnect(struct udc *dev)
1609 {
1610
1611 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1612
1613 dev->connected = 0;
1614
1615 /* mask interrupts */
1616 udc_mask_unused_interrupts(dev);
1617
1618 /* REVISIT there doesn't seem to be a point to having this
1619 * talk to a tasklet ... do it directly, we already hold
1620 * the spinlock needed to process the disconnect.
1621 */
1622
1623 tasklet_schedule(&disconnect_tasklet);
1624 }
1625
1626 /* Tasklet for disconnect to be outside of interrupt context */
1627 static void udc_tasklet_disconnect(unsigned long par)
1628 {
1629 struct udc *dev = (struct udc *)(*((struct udc **) par));
1630 u32 tmp;
1631
1632 DBG(dev, "Tasklet disconnect\n");
1633 spin_lock_irq(&dev->lock);
1634
1635 if (dev->driver) {
1636 spin_unlock(&dev->lock);
1637 dev->driver->disconnect(&dev->gadget);
1638 spin_lock(&dev->lock);
1639
1640 /* empty queues */
1641 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1642 empty_req_queue(&dev->ep[tmp]);
1643
1644 }
1645
1646 /* disable ep0 */
1647 ep_init(dev->regs,
1648 &dev->ep[UDC_EP0IN_IX]);
1649
1650
1651 if (!soft_reset_occured) {
1652 /* init controller by soft reset */
1653 udc_soft_reset(dev);
1654 soft_reset_occured++;
1655 }
1656
1657 /* re-enable dev interrupts */
1658 udc_enable_dev_setup_interrupts(dev);
1659 /* back to full speed ? */
1660 if (use_fullspeed) {
1661 tmp = readl(&dev->regs->cfg);
1662 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1663 writel(tmp, &dev->regs->cfg);
1664 }
1665
1666 spin_unlock_irq(&dev->lock);
1667 }
1668
1669 /* Reset the UDC core */
1670 static void udc_soft_reset(struct udc *dev)
1671 {
1672 unsigned long flags;
1673
1674 DBG(dev, "Soft reset\n");
1675 /*
1676 * reset possible waiting interrupts, because int.
1677 * status is lost after soft reset,
1678 * ep int. status reset
1679 */
1680 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1681 /* device int. status reset */
1682 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1683
1684 spin_lock_irqsave(&udc_irq_spinlock, flags);
1685 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1686 readl(&dev->regs->cfg);
1687 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1688
1689 }
1690
1691 /* RDE timer callback to set RDE bit */
1692 static void udc_timer_function(unsigned long v)
1693 {
1694 u32 tmp;
1695
1696 spin_lock_irq(&udc_irq_spinlock);
1697
1698 if (set_rde > 0) {
1699 /*
1700 * open the fifo if fifo was filled on last timer call
1701 * conditionally
1702 */
1703 if (set_rde > 1) {
1704 /* set RDE to receive setup data */
1705 tmp = readl(&udc->regs->ctl);
1706 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1707 writel(tmp, &udc->regs->ctl);
1708 set_rde = -1;
1709 } else if (readl(&udc->regs->sts)
1710 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1711 /*
1712 * if fifo empty setup polling, do not just
1713 * open the fifo
1714 */
1715 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1716 if (!stop_timer)
1717 add_timer(&udc_timer);
1718 } else {
1719 /*
1720 * fifo contains data now, setup timer for opening
1721 * the fifo when timer expires to be able to receive
1722 * setup packets, when data packets gets queued by
1723 * gadget layer then timer will forced to expire with
1724 * set_rde=0 (RDE is set in udc_queue())
1725 */
1726 set_rde++;
1727 /* debug: lhadmot_timer_start = 221070 */
1728 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1729 if (!stop_timer)
1730 add_timer(&udc_timer);
1731 }
1732
1733 } else
1734 set_rde = -1; /* RDE was set by udc_queue() */
1735 spin_unlock_irq(&udc_irq_spinlock);
1736 if (stop_timer)
1737 complete(&on_exit);
1738
1739 }
1740
1741 /* Handle halt state, used in stall poll timer */
1742 static void udc_handle_halt_state(struct udc_ep *ep)
1743 {
1744 u32 tmp;
1745 /* set stall as long not halted */
1746 if (ep->halted == 1) {
1747 tmp = readl(&ep->regs->ctl);
1748 /* STALL cleared ? */
1749 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1750 /*
1751 * FIXME: MSC spec requires that stall remains
1752 * even on receivng of CLEAR_FEATURE HALT. So
1753 * we would set STALL again here to be compliant.
1754 * But with current mass storage drivers this does
1755 * not work (would produce endless host retries).
1756 * So we clear halt on CLEAR_FEATURE.
1757 *
1758 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1759 tmp |= AMD_BIT(UDC_EPCTL_S);
1760 writel(tmp, &ep->regs->ctl);*/
1761
1762 /* clear NAK by writing CNAK */
1763 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1764 writel(tmp, &ep->regs->ctl);
1765 ep->halted = 0;
1766 UDC_QUEUE_CNAK(ep, ep->num);
1767 }
1768 }
1769 }
1770
1771 /* Stall timer callback to poll S bit and set it again after */
1772 static void udc_pollstall_timer_function(unsigned long v)
1773 {
1774 struct udc_ep *ep;
1775 int halted = 0;
1776
1777 spin_lock_irq(&udc_stall_spinlock);
1778 /*
1779 * only one IN and OUT endpoints are handled
1780 * IN poll stall
1781 */
1782 ep = &udc->ep[UDC_EPIN_IX];
1783 udc_handle_halt_state(ep);
1784 if (ep->halted)
1785 halted = 1;
1786 /* OUT poll stall */
1787 ep = &udc->ep[UDC_EPOUT_IX];
1788 udc_handle_halt_state(ep);
1789 if (ep->halted)
1790 halted = 1;
1791
1792 /* setup timer again when still halted */
1793 if (!stop_pollstall_timer && halted) {
1794 udc_pollstall_timer.expires = jiffies +
1795 HZ * UDC_POLLSTALL_TIMER_USECONDS
1796 / (1000 * 1000);
1797 add_timer(&udc_pollstall_timer);
1798 }
1799 spin_unlock_irq(&udc_stall_spinlock);
1800
1801 if (stop_pollstall_timer)
1802 complete(&on_pollstall_exit);
1803 }
1804
1805 /* Inits endpoint 0 so that SETUP packets are processed */
1806 static void activate_control_endpoints(struct udc *dev)
1807 {
1808 u32 tmp;
1809
1810 DBG(dev, "activate_control_endpoints\n");
1811
1812 /* flush fifo */
1813 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1814 tmp |= AMD_BIT(UDC_EPCTL_F);
1815 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1816
1817 /* set ep0 directions */
1818 dev->ep[UDC_EP0IN_IX].in = 1;
1819 dev->ep[UDC_EP0OUT_IX].in = 0;
1820
1821 /* set buffer size (tx fifo entries) of EP0_IN */
1822 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1823 if (dev->gadget.speed == USB_SPEED_FULL)
1824 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1825 UDC_EPIN_BUFF_SIZE);
1826 else if (dev->gadget.speed == USB_SPEED_HIGH)
1827 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1828 UDC_EPIN_BUFF_SIZE);
1829 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1830
1831 /* set max packet size of EP0_IN */
1832 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1833 if (dev->gadget.speed == USB_SPEED_FULL)
1834 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1835 UDC_EP_MAX_PKT_SIZE);
1836 else if (dev->gadget.speed == USB_SPEED_HIGH)
1837 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1838 UDC_EP_MAX_PKT_SIZE);
1839 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1840
1841 /* set max packet size of EP0_OUT */
1842 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1843 if (dev->gadget.speed == USB_SPEED_FULL)
1844 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1845 UDC_EP_MAX_PKT_SIZE);
1846 else if (dev->gadget.speed == USB_SPEED_HIGH)
1847 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1848 UDC_EP_MAX_PKT_SIZE);
1849 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1850
1851 /* set max packet size of EP0 in UDC CSR */
1852 tmp = readl(&dev->csr->ne[0]);
1853 if (dev->gadget.speed == USB_SPEED_FULL)
1854 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1855 UDC_CSR_NE_MAX_PKT);
1856 else if (dev->gadget.speed == USB_SPEED_HIGH)
1857 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1858 UDC_CSR_NE_MAX_PKT);
1859 writel(tmp, &dev->csr->ne[0]);
1860
1861 if (use_dma) {
1862 dev->ep[UDC_EP0OUT_IX].td->status |=
1863 AMD_BIT(UDC_DMA_OUT_STS_L);
1864 /* write dma desc address */
1865 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1866 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1867 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1868 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1869 /* stop RDE timer */
1870 if (timer_pending(&udc_timer)) {
1871 set_rde = 0;
1872 mod_timer(&udc_timer, jiffies - 1);
1873 }
1874 /* stop pollstall timer */
1875 if (timer_pending(&udc_pollstall_timer))
1876 mod_timer(&udc_pollstall_timer, jiffies - 1);
1877 /* enable DMA */
1878 tmp = readl(&dev->regs->ctl);
1879 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1880 | AMD_BIT(UDC_DEVCTL_RDE)
1881 | AMD_BIT(UDC_DEVCTL_TDE);
1882 if (use_dma_bufferfill_mode)
1883 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1884 else if (use_dma_ppb_du)
1885 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1886 writel(tmp, &dev->regs->ctl);
1887 }
1888
1889 /* clear NAK by writing CNAK for EP0IN */
1890 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1891 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1893 dev->ep[UDC_EP0IN_IX].naking = 0;
1894 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1895
1896 /* clear NAK by writing CNAK for EP0OUT */
1897 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1898 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1899 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1900 dev->ep[UDC_EP0OUT_IX].naking = 0;
1901 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1902 }
1903
1904 /* Make endpoint 0 ready for control traffic */
1905 static int setup_ep0(struct udc *dev)
1906 {
1907 activate_control_endpoints(dev);
1908 /* enable ep0 interrupts */
1909 udc_enable_ep0_interrupts(dev);
1910 /* enable device setup interrupts */
1911 udc_enable_dev_setup_interrupts(dev);
1912
1913 return 0;
1914 }
1915
1916 /* Called by gadget driver to register itself */
1917 static int amd5536_udc_start(struct usb_gadget *g,
1918 struct usb_gadget_driver *driver)
1919 {
1920 struct udc *dev = to_amd5536_udc(g);
1921 u32 tmp;
1922
1923 driver->driver.bus = NULL;
1924 dev->driver = driver;
1925
1926 /* Some gadget drivers use both ep0 directions.
1927 * NOTE: to gadget driver, ep0 is just one endpoint...
1928 */
1929 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1930 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1931
1932 /* get ready for ep0 traffic */
1933 setup_ep0(dev);
1934
1935 /* clear SD */
1936 tmp = readl(&dev->regs->ctl);
1937 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1938 writel(tmp, &dev->regs->ctl);
1939
1940 usb_connect(dev);
1941
1942 return 0;
1943 }
1944
1945 /* shutdown requests and disconnect from gadget */
1946 static void
1947 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1948 __releases(dev->lock)
1949 __acquires(dev->lock)
1950 {
1951 int tmp;
1952
1953 /* empty queues and init hardware */
1954 udc_basic_init(dev);
1955
1956 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1957 empty_req_queue(&dev->ep[tmp]);
1958
1959 udc_setup_endpoints(dev);
1960 }
1961
1962 /* Called by gadget driver to unregister itself */
1963 static int amd5536_udc_stop(struct usb_gadget *g,
1964 struct usb_gadget_driver *driver)
1965 {
1966 struct udc *dev = to_amd5536_udc(g);
1967 unsigned long flags;
1968 u32 tmp;
1969
1970 spin_lock_irqsave(&dev->lock, flags);
1971 udc_mask_unused_interrupts(dev);
1972 shutdown(dev, driver);
1973 spin_unlock_irqrestore(&dev->lock, flags);
1974
1975 dev->driver = NULL;
1976
1977 /* set SD */
1978 tmp = readl(&dev->regs->ctl);
1979 tmp |= AMD_BIT(UDC_DEVCTL_SD);
1980 writel(tmp, &dev->regs->ctl);
1981
1982 return 0;
1983 }
1984
1985 /* Clear pending NAK bits */
1986 static void udc_process_cnak_queue(struct udc *dev)
1987 {
1988 u32 tmp;
1989 u32 reg;
1990
1991 /* check epin's */
1992 DBG(dev, "CNAK pending queue processing\n");
1993 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
1994 if (cnak_pending & (1 << tmp)) {
1995 DBG(dev, "CNAK pending for ep%d\n", tmp);
1996 /* clear NAK by writing CNAK */
1997 reg = readl(&dev->ep[tmp].regs->ctl);
1998 reg |= AMD_BIT(UDC_EPCTL_CNAK);
1999 writel(reg, &dev->ep[tmp].regs->ctl);
2000 dev->ep[tmp].naking = 0;
2001 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2002 }
2003 }
2004 /* ... and ep0out */
2005 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2006 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2007 /* clear NAK by writing CNAK */
2008 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2009 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2010 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2011 dev->ep[UDC_EP0OUT_IX].naking = 0;
2012 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2013 dev->ep[UDC_EP0OUT_IX].num);
2014 }
2015 }
2016
2017 /* Enabling RX DMA after setup packet */
2018 static void udc_ep0_set_rde(struct udc *dev)
2019 {
2020 if (use_dma) {
2021 /*
2022 * only enable RXDMA when no data endpoint enabled
2023 * or data is queued
2024 */
2025 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2026 udc_set_rde(dev);
2027 } else {
2028 /*
2029 * setup timer for enabling RDE (to not enable
2030 * RXFIFO DMA for data endpoints to early)
2031 */
2032 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2033 udc_timer.expires =
2034 jiffies + HZ/UDC_RDE_TIMER_DIV;
2035 set_rde = 1;
2036 if (!stop_timer)
2037 add_timer(&udc_timer);
2038 }
2039 }
2040 }
2041 }
2042
2043
2044 /* Interrupt handler for data OUT traffic */
2045 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2046 {
2047 irqreturn_t ret_val = IRQ_NONE;
2048 u32 tmp;
2049 struct udc_ep *ep;
2050 struct udc_request *req;
2051 unsigned int count;
2052 struct udc_data_dma *td = NULL;
2053 unsigned dma_done;
2054
2055 VDBG(dev, "ep%d irq\n", ep_ix);
2056 ep = &dev->ep[ep_ix];
2057
2058 tmp = readl(&ep->regs->sts);
2059 if (use_dma) {
2060 /* BNA event ? */
2061 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2062 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2063 ep->num, readl(&ep->regs->desptr));
2064 /* clear BNA */
2065 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2066 if (!ep->cancel_transfer)
2067 ep->bna_occurred = 1;
2068 else
2069 ep->cancel_transfer = 0;
2070 ret_val = IRQ_HANDLED;
2071 goto finished;
2072 }
2073 }
2074 /* HE event ? */
2075 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2076 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2077
2078 /* clear HE */
2079 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2080 ret_val = IRQ_HANDLED;
2081 goto finished;
2082 }
2083
2084 if (!list_empty(&ep->queue)) {
2085
2086 /* next request */
2087 req = list_entry(ep->queue.next,
2088 struct udc_request, queue);
2089 } else {
2090 req = NULL;
2091 udc_rxfifo_pending = 1;
2092 }
2093 VDBG(dev, "req = %p\n", req);
2094 /* fifo mode */
2095 if (!use_dma) {
2096
2097 /* read fifo */
2098 if (req && udc_rxfifo_read(ep, req)) {
2099 ret_val = IRQ_HANDLED;
2100
2101 /* finish */
2102 complete_req(ep, req, 0);
2103 /* next request */
2104 if (!list_empty(&ep->queue) && !ep->halted) {
2105 req = list_entry(ep->queue.next,
2106 struct udc_request, queue);
2107 } else
2108 req = NULL;
2109 }
2110
2111 /* DMA */
2112 } else if (!ep->cancel_transfer && req != NULL) {
2113 ret_val = IRQ_HANDLED;
2114
2115 /* check for DMA done */
2116 if (!use_dma_ppb) {
2117 dma_done = AMD_GETBITS(req->td_data->status,
2118 UDC_DMA_OUT_STS_BS);
2119 /* packet per buffer mode - rx bytes */
2120 } else {
2121 /*
2122 * if BNA occurred then recover desc. from
2123 * BNA dummy desc.
2124 */
2125 if (ep->bna_occurred) {
2126 VDBG(dev, "Recover desc. from BNA dummy\n");
2127 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2128 sizeof(struct udc_data_dma));
2129 ep->bna_occurred = 0;
2130 udc_init_bna_dummy(ep->req);
2131 }
2132 td = udc_get_last_dma_desc(req);
2133 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2134 }
2135 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2136 /* buffer fill mode - rx bytes */
2137 if (!use_dma_ppb) {
2138 /* received number bytes */
2139 count = AMD_GETBITS(req->td_data->status,
2140 UDC_DMA_OUT_STS_RXBYTES);
2141 VDBG(dev, "rx bytes=%u\n", count);
2142 /* packet per buffer mode - rx bytes */
2143 } else {
2144 VDBG(dev, "req->td_data=%p\n", req->td_data);
2145 VDBG(dev, "last desc = %p\n", td);
2146 /* received number bytes */
2147 if (use_dma_ppb_du) {
2148 /* every desc. counts bytes */
2149 count = udc_get_ppbdu_rxbytes(req);
2150 } else {
2151 /* last desc. counts bytes */
2152 count = AMD_GETBITS(td->status,
2153 UDC_DMA_OUT_STS_RXBYTES);
2154 if (!count && req->req.length
2155 == UDC_DMA_MAXPACKET) {
2156 /*
2157 * on 64k packets the RXBYTES
2158 * field is zero
2159 */
2160 count = UDC_DMA_MAXPACKET;
2161 }
2162 }
2163 VDBG(dev, "last desc rx bytes=%u\n", count);
2164 }
2165
2166 tmp = req->req.length - req->req.actual;
2167 if (count > tmp) {
2168 if ((tmp % ep->ep.maxpacket) != 0) {
2169 DBG(dev, "%s: rx %db, space=%db\n",
2170 ep->ep.name, count, tmp);
2171 req->req.status = -EOVERFLOW;
2172 }
2173 count = tmp;
2174 }
2175 req->req.actual += count;
2176 req->dma_going = 0;
2177 /* complete request */
2178 complete_req(ep, req, 0);
2179
2180 /* next request */
2181 if (!list_empty(&ep->queue) && !ep->halted) {
2182 req = list_entry(ep->queue.next,
2183 struct udc_request,
2184 queue);
2185 /*
2186 * DMA may be already started by udc_queue()
2187 * called by gadget drivers completion
2188 * routine. This happens when queue
2189 * holds one request only.
2190 */
2191 if (req->dma_going == 0) {
2192 /* next dma */
2193 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2194 goto finished;
2195 /* write desc pointer */
2196 writel(req->td_phys,
2197 &ep->regs->desptr);
2198 req->dma_going = 1;
2199 /* enable DMA */
2200 udc_set_rde(dev);
2201 }
2202 } else {
2203 /*
2204 * implant BNA dummy descriptor to allow
2205 * RXFIFO opening by RDE
2206 */
2207 if (ep->bna_dummy_req) {
2208 /* write desc pointer */
2209 writel(ep->bna_dummy_req->td_phys,
2210 &ep->regs->desptr);
2211 ep->bna_occurred = 0;
2212 }
2213
2214 /*
2215 * schedule timer for setting RDE if queue
2216 * remains empty to allow ep0 packets pass
2217 * through
2218 */
2219 if (set_rde != 0
2220 && !timer_pending(&udc_timer)) {
2221 udc_timer.expires =
2222 jiffies
2223 + HZ*UDC_RDE_TIMER_SECONDS;
2224 set_rde = 1;
2225 if (!stop_timer)
2226 add_timer(&udc_timer);
2227 }
2228 if (ep->num != UDC_EP0OUT_IX)
2229 dev->data_ep_queued = 0;
2230 }
2231
2232 } else {
2233 /*
2234 * RX DMA must be reenabled for each desc in PPBDU mode
2235 * and must be enabled for PPBNDU mode in case of BNA
2236 */
2237 udc_set_rde(dev);
2238 }
2239
2240 } else if (ep->cancel_transfer) {
2241 ret_val = IRQ_HANDLED;
2242 ep->cancel_transfer = 0;
2243 }
2244
2245 /* check pending CNAKS */
2246 if (cnak_pending) {
2247 /* CNAk processing when rxfifo empty only */
2248 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2249 udc_process_cnak_queue(dev);
2250 }
2251
2252 /* clear OUT bits in ep status */
2253 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2254 finished:
2255 return ret_val;
2256 }
2257
2258 /* Interrupt handler for data IN traffic */
2259 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2260 {
2261 irqreturn_t ret_val = IRQ_NONE;
2262 u32 tmp;
2263 u32 epsts;
2264 struct udc_ep *ep;
2265 struct udc_request *req;
2266 struct udc_data_dma *td;
2267 unsigned dma_done;
2268 unsigned len;
2269
2270 ep = &dev->ep[ep_ix];
2271
2272 epsts = readl(&ep->regs->sts);
2273 if (use_dma) {
2274 /* BNA ? */
2275 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2276 dev_err(&dev->pdev->dev,
2277 "BNA ep%din occurred - DESPTR = %08lx\n",
2278 ep->num,
2279 (unsigned long) readl(&ep->regs->desptr));
2280
2281 /* clear BNA */
2282 writel(epsts, &ep->regs->sts);
2283 ret_val = IRQ_HANDLED;
2284 goto finished;
2285 }
2286 }
2287 /* HE event ? */
2288 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2289 dev_err(&dev->pdev->dev,
2290 "HE ep%dn occurred - DESPTR = %08lx\n",
2291 ep->num, (unsigned long) readl(&ep->regs->desptr));
2292
2293 /* clear HE */
2294 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2295 ret_val = IRQ_HANDLED;
2296 goto finished;
2297 }
2298
2299 /* DMA completion */
2300 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2301 VDBG(dev, "TDC set- completion\n");
2302 ret_val = IRQ_HANDLED;
2303 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2304 req = list_entry(ep->queue.next,
2305 struct udc_request, queue);
2306 /*
2307 * length bytes transferred
2308 * check dma done of last desc. in PPBDU mode
2309 */
2310 if (use_dma_ppb_du) {
2311 td = udc_get_last_dma_desc(req);
2312 if (td) {
2313 dma_done =
2314 AMD_GETBITS(td->status,
2315 UDC_DMA_IN_STS_BS);
2316 /* don't care DMA done */
2317 req->req.actual = req->req.length;
2318 }
2319 } else {
2320 /* assume all bytes transferred */
2321 req->req.actual = req->req.length;
2322 }
2323
2324 if (req->req.actual == req->req.length) {
2325 /* complete req */
2326 complete_req(ep, req, 0);
2327 req->dma_going = 0;
2328 /* further request available ? */
2329 if (list_empty(&ep->queue)) {
2330 /* disable interrupt */
2331 tmp = readl(&dev->regs->ep_irqmsk);
2332 tmp |= AMD_BIT(ep->num);
2333 writel(tmp, &dev->regs->ep_irqmsk);
2334 }
2335 }
2336 }
2337 ep->cancel_transfer = 0;
2338
2339 }
2340 /*
2341 * status reg has IN bit set and TDC not set (if TDC was handled,
2342 * IN must not be handled (UDC defect) ?
2343 */
2344 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2345 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2346 ret_val = IRQ_HANDLED;
2347 if (!list_empty(&ep->queue)) {
2348 /* next request */
2349 req = list_entry(ep->queue.next,
2350 struct udc_request, queue);
2351 /* FIFO mode */
2352 if (!use_dma) {
2353 /* write fifo */
2354 udc_txfifo_write(ep, &req->req);
2355 len = req->req.length - req->req.actual;
2356 if (len > ep->ep.maxpacket)
2357 len = ep->ep.maxpacket;
2358 req->req.actual += len;
2359 if (req->req.actual == req->req.length
2360 || (len != ep->ep.maxpacket)) {
2361 /* complete req */
2362 complete_req(ep, req, 0);
2363 }
2364 /* DMA */
2365 } else if (req && !req->dma_going) {
2366 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2367 req, req->td_data);
2368 if (req->td_data) {
2369
2370 req->dma_going = 1;
2371
2372 /*
2373 * unset L bit of first desc.
2374 * for chain
2375 */
2376 if (use_dma_ppb && req->req.length >
2377 ep->ep.maxpacket) {
2378 req->td_data->status &=
2379 AMD_CLEAR_BIT(
2380 UDC_DMA_IN_STS_L);
2381 }
2382
2383 /* write desc pointer */
2384 writel(req->td_phys, &ep->regs->desptr);
2385
2386 /* set HOST READY */
2387 req->td_data->status =
2388 AMD_ADDBITS(
2389 req->td_data->status,
2390 UDC_DMA_IN_STS_BS_HOST_READY,
2391 UDC_DMA_IN_STS_BS);
2392
2393 /* set poll demand bit */
2394 tmp = readl(&ep->regs->ctl);
2395 tmp |= AMD_BIT(UDC_EPCTL_P);
2396 writel(tmp, &ep->regs->ctl);
2397 }
2398 }
2399
2400 } else if (!use_dma && ep->in) {
2401 /* disable interrupt */
2402 tmp = readl(
2403 &dev->regs->ep_irqmsk);
2404 tmp |= AMD_BIT(ep->num);
2405 writel(tmp,
2406 &dev->regs->ep_irqmsk);
2407 }
2408 }
2409 /* clear status bits */
2410 writel(epsts, &ep->regs->sts);
2411
2412 finished:
2413 return ret_val;
2414
2415 }
2416
2417 /* Interrupt handler for Control OUT traffic */
2418 static irqreturn_t udc_control_out_isr(struct udc *dev)
2419 __releases(dev->lock)
2420 __acquires(dev->lock)
2421 {
2422 irqreturn_t ret_val = IRQ_NONE;
2423 u32 tmp;
2424 int setup_supported;
2425 u32 count;
2426 int set = 0;
2427 struct udc_ep *ep;
2428 struct udc_ep *ep_tmp;
2429
2430 ep = &dev->ep[UDC_EP0OUT_IX];
2431
2432 /* clear irq */
2433 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2434
2435 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2436 /* check BNA and clear if set */
2437 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2438 VDBG(dev, "ep0: BNA set\n");
2439 writel(AMD_BIT(UDC_EPSTS_BNA),
2440 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2441 ep->bna_occurred = 1;
2442 ret_val = IRQ_HANDLED;
2443 goto finished;
2444 }
2445
2446 /* type of data: SETUP or DATA 0 bytes */
2447 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2448 VDBG(dev, "data_typ = %x\n", tmp);
2449
2450 /* setup data */
2451 if (tmp == UDC_EPSTS_OUT_SETUP) {
2452 ret_val = IRQ_HANDLED;
2453
2454 ep->dev->stall_ep0in = 0;
2455 dev->waiting_zlp_ack_ep0in = 0;
2456
2457 /* set NAK for EP0_IN */
2458 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2459 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2460 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2461 dev->ep[UDC_EP0IN_IX].naking = 1;
2462 /* get setup data */
2463 if (use_dma) {
2464
2465 /* clear OUT bits in ep status */
2466 writel(UDC_EPSTS_OUT_CLEAR,
2467 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2468
2469 setup_data.data[0] =
2470 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2471 setup_data.data[1] =
2472 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2473 /* set HOST READY */
2474 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2475 UDC_DMA_STP_STS_BS_HOST_READY;
2476 } else {
2477 /* read fifo */
2478 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2479 }
2480
2481 /* determine direction of control data */
2482 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2483 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2484 /* enable RDE */
2485 udc_ep0_set_rde(dev);
2486 set = 0;
2487 } else {
2488 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2489 /*
2490 * implant BNA dummy descriptor to allow RXFIFO opening
2491 * by RDE
2492 */
2493 if (ep->bna_dummy_req) {
2494 /* write desc pointer */
2495 writel(ep->bna_dummy_req->td_phys,
2496 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2497 ep->bna_occurred = 0;
2498 }
2499
2500 set = 1;
2501 dev->ep[UDC_EP0OUT_IX].naking = 1;
2502 /*
2503 * setup timer for enabling RDE (to not enable
2504 * RXFIFO DMA for data to early)
2505 */
2506 set_rde = 1;
2507 if (!timer_pending(&udc_timer)) {
2508 udc_timer.expires = jiffies +
2509 HZ/UDC_RDE_TIMER_DIV;
2510 if (!stop_timer)
2511 add_timer(&udc_timer);
2512 }
2513 }
2514
2515 /*
2516 * mass storage reset must be processed here because
2517 * next packet may be a CLEAR_FEATURE HALT which would not
2518 * clear the stall bit when no STALL handshake was received
2519 * before (autostall can cause this)
2520 */
2521 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2522 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2523 DBG(dev, "MSC Reset\n");
2524 /*
2525 * clear stall bits
2526 * only one IN and OUT endpoints are handled
2527 */
2528 ep_tmp = &udc->ep[UDC_EPIN_IX];
2529 udc_set_halt(&ep_tmp->ep, 0);
2530 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2531 udc_set_halt(&ep_tmp->ep, 0);
2532 }
2533
2534 /* call gadget with setup data received */
2535 spin_unlock(&dev->lock);
2536 setup_supported = dev->driver->setup(&dev->gadget,
2537 &setup_data.request);
2538 spin_lock(&dev->lock);
2539
2540 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2541 /* ep0 in returns data (not zlp) on IN phase */
2542 if (setup_supported >= 0 && setup_supported <
2543 UDC_EP0IN_MAXPACKET) {
2544 /* clear NAK by writing CNAK in EP0_IN */
2545 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2546 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2547 dev->ep[UDC_EP0IN_IX].naking = 0;
2548 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2549
2550 /* if unsupported request then stall */
2551 } else if (setup_supported < 0) {
2552 tmp |= AMD_BIT(UDC_EPCTL_S);
2553 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2554 } else
2555 dev->waiting_zlp_ack_ep0in = 1;
2556
2557
2558 /* clear NAK by writing CNAK in EP0_OUT */
2559 if (!set) {
2560 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2561 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2562 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2563 dev->ep[UDC_EP0OUT_IX].naking = 0;
2564 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2565 }
2566
2567 if (!use_dma) {
2568 /* clear OUT bits in ep status */
2569 writel(UDC_EPSTS_OUT_CLEAR,
2570 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2571 }
2572
2573 /* data packet 0 bytes */
2574 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2575 /* clear OUT bits in ep status */
2576 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2577
2578 /* get setup data: only 0 packet */
2579 if (use_dma) {
2580 /* no req if 0 packet, just reactivate */
2581 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2582 VDBG(dev, "ZLP\n");
2583
2584 /* set HOST READY */
2585 dev->ep[UDC_EP0OUT_IX].td->status =
2586 AMD_ADDBITS(
2587 dev->ep[UDC_EP0OUT_IX].td->status,
2588 UDC_DMA_OUT_STS_BS_HOST_READY,
2589 UDC_DMA_OUT_STS_BS);
2590 /* enable RDE */
2591 udc_ep0_set_rde(dev);
2592 ret_val = IRQ_HANDLED;
2593
2594 } else {
2595 /* control write */
2596 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2597 /* re-program desc. pointer for possible ZLPs */
2598 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2599 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2600 /* enable RDE */
2601 udc_ep0_set_rde(dev);
2602 }
2603 } else {
2604
2605 /* received number bytes */
2606 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2607 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2608 /* out data for fifo mode not working */
2609 count = 0;
2610
2611 /* 0 packet or real data ? */
2612 if (count != 0) {
2613 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2614 } else {
2615 /* dummy read confirm */
2616 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2617 ret_val = IRQ_HANDLED;
2618 }
2619 }
2620 }
2621
2622 /* check pending CNAKS */
2623 if (cnak_pending) {
2624 /* CNAk processing when rxfifo empty only */
2625 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2626 udc_process_cnak_queue(dev);
2627 }
2628
2629 finished:
2630 return ret_val;
2631 }
2632
2633 /* Interrupt handler for Control IN traffic */
2634 static irqreturn_t udc_control_in_isr(struct udc *dev)
2635 {
2636 irqreturn_t ret_val = IRQ_NONE;
2637 u32 tmp;
2638 struct udc_ep *ep;
2639 struct udc_request *req;
2640 unsigned len;
2641
2642 ep = &dev->ep[UDC_EP0IN_IX];
2643
2644 /* clear irq */
2645 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2646
2647 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2648 /* DMA completion */
2649 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2650 VDBG(dev, "isr: TDC clear\n");
2651 ret_val = IRQ_HANDLED;
2652
2653 /* clear TDC bit */
2654 writel(AMD_BIT(UDC_EPSTS_TDC),
2655 &dev->ep[UDC_EP0IN_IX].regs->sts);
2656
2657 /* status reg has IN bit set ? */
2658 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2659 ret_val = IRQ_HANDLED;
2660
2661 if (ep->dma) {
2662 /* clear IN bit */
2663 writel(AMD_BIT(UDC_EPSTS_IN),
2664 &dev->ep[UDC_EP0IN_IX].regs->sts);
2665 }
2666 if (dev->stall_ep0in) {
2667 DBG(dev, "stall ep0in\n");
2668 /* halt ep0in */
2669 tmp = readl(&ep->regs->ctl);
2670 tmp |= AMD_BIT(UDC_EPCTL_S);
2671 writel(tmp, &ep->regs->ctl);
2672 } else {
2673 if (!list_empty(&ep->queue)) {
2674 /* next request */
2675 req = list_entry(ep->queue.next,
2676 struct udc_request, queue);
2677
2678 if (ep->dma) {
2679 /* write desc pointer */
2680 writel(req->td_phys, &ep->regs->desptr);
2681 /* set HOST READY */
2682 req->td_data->status =
2683 AMD_ADDBITS(
2684 req->td_data->status,
2685 UDC_DMA_STP_STS_BS_HOST_READY,
2686 UDC_DMA_STP_STS_BS);
2687
2688 /* set poll demand bit */
2689 tmp =
2690 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2691 tmp |= AMD_BIT(UDC_EPCTL_P);
2692 writel(tmp,
2693 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2694
2695 /* all bytes will be transferred */
2696 req->req.actual = req->req.length;
2697
2698 /* complete req */
2699 complete_req(ep, req, 0);
2700
2701 } else {
2702 /* write fifo */
2703 udc_txfifo_write(ep, &req->req);
2704
2705 /* lengh bytes transferred */
2706 len = req->req.length - req->req.actual;
2707 if (len > ep->ep.maxpacket)
2708 len = ep->ep.maxpacket;
2709
2710 req->req.actual += len;
2711 if (req->req.actual == req->req.length
2712 || (len != ep->ep.maxpacket)) {
2713 /* complete req */
2714 complete_req(ep, req, 0);
2715 }
2716 }
2717
2718 }
2719 }
2720 ep->halted = 0;
2721 dev->stall_ep0in = 0;
2722 if (!ep->dma) {
2723 /* clear IN bit */
2724 writel(AMD_BIT(UDC_EPSTS_IN),
2725 &dev->ep[UDC_EP0IN_IX].regs->sts);
2726 }
2727 }
2728
2729 return ret_val;
2730 }
2731
2732
2733 /* Interrupt handler for global device events */
2734 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2735 __releases(dev->lock)
2736 __acquires(dev->lock)
2737 {
2738 irqreturn_t ret_val = IRQ_NONE;
2739 u32 tmp;
2740 u32 cfg;
2741 struct udc_ep *ep;
2742 u16 i;
2743 u8 udc_csr_epix;
2744
2745 /* SET_CONFIG irq ? */
2746 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2747 ret_val = IRQ_HANDLED;
2748
2749 /* read config value */
2750 tmp = readl(&dev->regs->sts);
2751 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2752 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2753 dev->cur_config = cfg;
2754 dev->set_cfg_not_acked = 1;
2755
2756 /* make usb request for gadget driver */
2757 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2758 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2759 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2760
2761 /* programm the NE registers */
2762 for (i = 0; i < UDC_EP_NUM; i++) {
2763 ep = &dev->ep[i];
2764 if (ep->in) {
2765
2766 /* ep ix in UDC CSR register space */
2767 udc_csr_epix = ep->num;
2768
2769
2770 /* OUT ep */
2771 } else {
2772 /* ep ix in UDC CSR register space */
2773 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2774 }
2775
2776 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2777 /* ep cfg */
2778 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2779 UDC_CSR_NE_CFG);
2780 /* write reg */
2781 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2782
2783 /* clear stall bits */
2784 ep->halted = 0;
2785 tmp = readl(&ep->regs->ctl);
2786 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2787 writel(tmp, &ep->regs->ctl);
2788 }
2789 /* call gadget zero with setup data received */
2790 spin_unlock(&dev->lock);
2791 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2792 spin_lock(&dev->lock);
2793
2794 } /* SET_INTERFACE ? */
2795 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2796 ret_val = IRQ_HANDLED;
2797
2798 dev->set_cfg_not_acked = 1;
2799 /* read interface and alt setting values */
2800 tmp = readl(&dev->regs->sts);
2801 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2802 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2803
2804 /* make usb request for gadget driver */
2805 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2806 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2807 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2808 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2809 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2810
2811 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2812 dev->cur_alt, dev->cur_intf);
2813
2814 /* programm the NE registers */
2815 for (i = 0; i < UDC_EP_NUM; i++) {
2816 ep = &dev->ep[i];
2817 if (ep->in) {
2818
2819 /* ep ix in UDC CSR register space */
2820 udc_csr_epix = ep->num;
2821
2822
2823 /* OUT ep */
2824 } else {
2825 /* ep ix in UDC CSR register space */
2826 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2827 }
2828
2829 /* UDC CSR reg */
2830 /* set ep values */
2831 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2832 /* ep interface */
2833 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2834 UDC_CSR_NE_INTF);
2835 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2836 /* ep alt */
2837 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2838 UDC_CSR_NE_ALT);
2839 /* write reg */
2840 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2841
2842 /* clear stall bits */
2843 ep->halted = 0;
2844 tmp = readl(&ep->regs->ctl);
2845 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2846 writel(tmp, &ep->regs->ctl);
2847 }
2848
2849 /* call gadget zero with setup data received */
2850 spin_unlock(&dev->lock);
2851 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2852 spin_lock(&dev->lock);
2853
2854 } /* USB reset */
2855 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2856 DBG(dev, "USB Reset interrupt\n");
2857 ret_val = IRQ_HANDLED;
2858
2859 /* allow soft reset when suspend occurs */
2860 soft_reset_occured = 0;
2861
2862 dev->waiting_zlp_ack_ep0in = 0;
2863 dev->set_cfg_not_acked = 0;
2864
2865 /* mask not needed interrupts */
2866 udc_mask_unused_interrupts(dev);
2867
2868 /* call gadget to resume and reset configs etc. */
2869 spin_unlock(&dev->lock);
2870 if (dev->sys_suspended && dev->driver->resume) {
2871 dev->driver->resume(&dev->gadget);
2872 dev->sys_suspended = 0;
2873 }
2874 dev->driver->disconnect(&dev->gadget);
2875 spin_lock(&dev->lock);
2876
2877 /* disable ep0 to empty req queue */
2878 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2879 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2880
2881 /* soft reset when rxfifo not empty */
2882 tmp = readl(&dev->regs->sts);
2883 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2884 && !soft_reset_after_usbreset_occured) {
2885 udc_soft_reset(dev);
2886 soft_reset_after_usbreset_occured++;
2887 }
2888
2889 /*
2890 * DMA reset to kill potential old DMA hw hang,
2891 * POLL bit is already reset by ep_init() through
2892 * disconnect()
2893 */
2894 DBG(dev, "DMA machine reset\n");
2895 tmp = readl(&dev->regs->cfg);
2896 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2897 writel(tmp, &dev->regs->cfg);
2898
2899 /* put into initial config */
2900 udc_basic_init(dev);
2901
2902 /* enable device setup interrupts */
2903 udc_enable_dev_setup_interrupts(dev);
2904
2905 /* enable suspend interrupt */
2906 tmp = readl(&dev->regs->irqmsk);
2907 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2908 writel(tmp, &dev->regs->irqmsk);
2909
2910 } /* USB suspend */
2911 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2912 DBG(dev, "USB Suspend interrupt\n");
2913 ret_val = IRQ_HANDLED;
2914 if (dev->driver->suspend) {
2915 spin_unlock(&dev->lock);
2916 dev->sys_suspended = 1;
2917 dev->driver->suspend(&dev->gadget);
2918 spin_lock(&dev->lock);
2919 }
2920 } /* new speed ? */
2921 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2922 DBG(dev, "ENUM interrupt\n");
2923 ret_val = IRQ_HANDLED;
2924 soft_reset_after_usbreset_occured = 0;
2925
2926 /* disable ep0 to empty req queue */
2927 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2928 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2929
2930 /* link up all endpoints */
2931 udc_setup_endpoints(dev);
2932 dev_info(&dev->pdev->dev, "Connect: %s\n",
2933 usb_speed_string(dev->gadget.speed));
2934
2935 /* init ep 0 */
2936 activate_control_endpoints(dev);
2937
2938 /* enable ep0 interrupts */
2939 udc_enable_ep0_interrupts(dev);
2940 }
2941 /* session valid change interrupt */
2942 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2943 DBG(dev, "USB SVC interrupt\n");
2944 ret_val = IRQ_HANDLED;
2945
2946 /* check that session is not valid to detect disconnect */
2947 tmp = readl(&dev->regs->sts);
2948 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2949 /* disable suspend interrupt */
2950 tmp = readl(&dev->regs->irqmsk);
2951 tmp |= AMD_BIT(UDC_DEVINT_US);
2952 writel(tmp, &dev->regs->irqmsk);
2953 DBG(dev, "USB Disconnect (session valid low)\n");
2954 /* cleanup on disconnect */
2955 usb_disconnect(udc);
2956 }
2957
2958 }
2959
2960 return ret_val;
2961 }
2962
2963 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2964 static irqreturn_t udc_irq(int irq, void *pdev)
2965 {
2966 struct udc *dev = pdev;
2967 u32 reg;
2968 u16 i;
2969 u32 ep_irq;
2970 irqreturn_t ret_val = IRQ_NONE;
2971
2972 spin_lock(&dev->lock);
2973
2974 /* check for ep irq */
2975 reg = readl(&dev->regs->ep_irqsts);
2976 if (reg) {
2977 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
2978 ret_val |= udc_control_out_isr(dev);
2979 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
2980 ret_val |= udc_control_in_isr(dev);
2981
2982 /*
2983 * data endpoint
2984 * iterate ep's
2985 */
2986 for (i = 1; i < UDC_EP_NUM; i++) {
2987 ep_irq = 1 << i;
2988 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
2989 continue;
2990
2991 /* clear irq status */
2992 writel(ep_irq, &dev->regs->ep_irqsts);
2993
2994 /* irq for out ep ? */
2995 if (i > UDC_EPIN_NUM)
2996 ret_val |= udc_data_out_isr(dev, i);
2997 else
2998 ret_val |= udc_data_in_isr(dev, i);
2999 }
3000
3001 }
3002
3003
3004 /* check for dev irq */
3005 reg = readl(&dev->regs->irqsts);
3006 if (reg) {
3007 /* clear irq */
3008 writel(reg, &dev->regs->irqsts);
3009 ret_val |= udc_dev_isr(dev, reg);
3010 }
3011
3012
3013 spin_unlock(&dev->lock);
3014 return ret_val;
3015 }
3016
3017 /* Tears down device */
3018 static void gadget_release(struct device *pdev)
3019 {
3020 struct amd5536udc *dev = dev_get_drvdata(pdev);
3021 kfree(dev);
3022 }
3023
3024 /* Cleanup on device remove */
3025 static void udc_remove(struct udc *dev)
3026 {
3027 /* remove timer */
3028 stop_timer++;
3029 if (timer_pending(&udc_timer))
3030 wait_for_completion(&on_exit);
3031 if (udc_timer.data)
3032 del_timer_sync(&udc_timer);
3033 /* remove pollstall timer */
3034 stop_pollstall_timer++;
3035 if (timer_pending(&udc_pollstall_timer))
3036 wait_for_completion(&on_pollstall_exit);
3037 if (udc_pollstall_timer.data)
3038 del_timer_sync(&udc_pollstall_timer);
3039 udc = NULL;
3040 }
3041
3042 /* Reset all pci context */
3043 static void udc_pci_remove(struct pci_dev *pdev)
3044 {
3045 struct udc *dev;
3046
3047 dev = pci_get_drvdata(pdev);
3048
3049 usb_del_gadget_udc(&udc->gadget);
3050 /* gadget driver must not be registered */
3051 BUG_ON(dev->driver != NULL);
3052
3053 /* dma pool cleanup */
3054 if (dev->data_requests)
3055 pci_pool_destroy(dev->data_requests);
3056
3057 if (dev->stp_requests) {
3058 /* cleanup DMA desc's for ep0in */
3059 pci_pool_free(dev->stp_requests,
3060 dev->ep[UDC_EP0OUT_IX].td_stp,
3061 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3062 pci_pool_free(dev->stp_requests,
3063 dev->ep[UDC_EP0OUT_IX].td,
3064 dev->ep[UDC_EP0OUT_IX].td_phys);
3065
3066 pci_pool_destroy(dev->stp_requests);
3067 }
3068
3069 /* reset controller */
3070 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3071 if (dev->irq_registered)
3072 free_irq(pdev->irq, dev);
3073 if (dev->regs)
3074 iounmap(dev->regs);
3075 if (dev->mem_region)
3076 release_mem_region(pci_resource_start(pdev, 0),
3077 pci_resource_len(pdev, 0));
3078 if (dev->active)
3079 pci_disable_device(pdev);
3080
3081 pci_set_drvdata(pdev, NULL);
3082
3083 udc_remove(dev);
3084 }
3085
3086 /* create dma pools on init */
3087 static int init_dma_pools(struct udc *dev)
3088 {
3089 struct udc_stp_dma *td_stp;
3090 struct udc_data_dma *td_data;
3091 int retval;
3092
3093 /* consistent DMA mode setting ? */
3094 if (use_dma_ppb) {
3095 use_dma_bufferfill_mode = 0;
3096 } else {
3097 use_dma_ppb_du = 0;
3098 use_dma_bufferfill_mode = 1;
3099 }
3100
3101 /* DMA setup */
3102 dev->data_requests = dma_pool_create("data_requests", NULL,
3103 sizeof(struct udc_data_dma), 0, 0);
3104 if (!dev->data_requests) {
3105 DBG(dev, "can't get request data pool\n");
3106 retval = -ENOMEM;
3107 goto finished;
3108 }
3109
3110 /* EP0 in dma regs = dev control regs */
3111 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3112
3113 /* dma desc for setup data */
3114 dev->stp_requests = dma_pool_create("setup requests", NULL,
3115 sizeof(struct udc_stp_dma), 0, 0);
3116 if (!dev->stp_requests) {
3117 DBG(dev, "can't get stp request pool\n");
3118 retval = -ENOMEM;
3119 goto finished;
3120 }
3121 /* setup */
3122 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3123 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3124 if (td_stp == NULL) {
3125 retval = -ENOMEM;
3126 goto finished;
3127 }
3128 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3129
3130 /* data: 0 packets !? */
3131 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3132 &dev->ep[UDC_EP0OUT_IX].td_phys);
3133 if (td_data == NULL) {
3134 retval = -ENOMEM;
3135 goto finished;
3136 }
3137 dev->ep[UDC_EP0OUT_IX].td = td_data;
3138 return 0;
3139
3140 finished:
3141 return retval;
3142 }
3143
3144 /* Called by pci bus driver to init pci context */
3145 static int udc_pci_probe(
3146 struct pci_dev *pdev,
3147 const struct pci_device_id *id
3148 )
3149 {
3150 struct udc *dev;
3151 unsigned long resource;
3152 unsigned long len;
3153 int retval = 0;
3154
3155 /* one udc only */
3156 if (udc) {
3157 dev_dbg(&pdev->dev, "already probed\n");
3158 return -EBUSY;
3159 }
3160
3161 /* init */
3162 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3163 if (!dev) {
3164 retval = -ENOMEM;
3165 goto finished;
3166 }
3167
3168 /* pci setup */
3169 if (pci_enable_device(pdev) < 0) {
3170 kfree(dev);
3171 dev = NULL;
3172 retval = -ENODEV;
3173 goto finished;
3174 }
3175 dev->active = 1;
3176
3177 /* PCI resource allocation */
3178 resource = pci_resource_start(pdev, 0);
3179 len = pci_resource_len(pdev, 0);
3180
3181 if (!request_mem_region(resource, len, name)) {
3182 dev_dbg(&pdev->dev, "pci device used already\n");
3183 kfree(dev);
3184 dev = NULL;
3185 retval = -EBUSY;
3186 goto finished;
3187 }
3188 dev->mem_region = 1;
3189
3190 dev->virt_addr = ioremap_nocache(resource, len);
3191 if (dev->virt_addr == NULL) {
3192 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3193 kfree(dev);
3194 dev = NULL;
3195 retval = -EFAULT;
3196 goto finished;
3197 }
3198
3199 if (!pdev->irq) {
3200 dev_err(&pdev->dev, "irq not set\n");
3201 kfree(dev);
3202 dev = NULL;
3203 retval = -ENODEV;
3204 goto finished;
3205 }
3206
3207 spin_lock_init(&dev->lock);
3208 /* udc csr registers base */
3209 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3210 /* dev registers base */
3211 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3212 /* ep registers base */
3213 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3214 /* fifo's base */
3215 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3216 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3217
3218 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3219 dev_dbg(&pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3220 kfree(dev);
3221 dev = NULL;
3222 retval = -EBUSY;
3223 goto finished;
3224 }
3225 dev->irq_registered = 1;
3226
3227 pci_set_drvdata(pdev, dev);
3228
3229 /* chip revision for Hs AMD5536 */
3230 dev->chiprev = pdev->revision;
3231
3232 pci_set_master(pdev);
3233 pci_try_set_mwi(pdev);
3234
3235 /* init dma pools */
3236 if (use_dma) {
3237 retval = init_dma_pools(dev);
3238 if (retval != 0)
3239 goto finished;
3240 }
3241
3242 dev->phys_addr = resource;
3243 dev->irq = pdev->irq;
3244 dev->pdev = pdev;
3245
3246 /* general probing */
3247 if (udc_probe(dev) == 0)
3248 return 0;
3249
3250 finished:
3251 if (dev)
3252 udc_pci_remove(pdev);
3253 return retval;
3254 }
3255
3256 /* general probe */
3257 static int udc_probe(struct udc *dev)
3258 {
3259 char tmp[128];
3260 u32 reg;
3261 int retval;
3262
3263 /* mark timer as not initialized */
3264 udc_timer.data = 0;
3265 udc_pollstall_timer.data = 0;
3266
3267 /* device struct setup */
3268 dev->gadget.ops = &udc_ops;
3269
3270 dev_set_name(&dev->gadget.dev, "gadget");
3271 dev->gadget.name = name;
3272 dev->gadget.max_speed = USB_SPEED_HIGH;
3273
3274 /* init registers, interrupts, ... */
3275 startup_registers(dev);
3276
3277 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3278
3279 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3280 dev_info(&dev->pdev->dev,
3281 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3282 tmp, dev->phys_addr, dev->chiprev,
3283 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3284 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3285 if (dev->chiprev == UDC_HSA0_REV) {
3286 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3287 retval = -ENODEV;
3288 goto finished;
3289 }
3290 dev_info(&dev->pdev->dev,
3291 "driver version: %s(for Geode5536 B1)\n", tmp);
3292 udc = dev;
3293
3294 retval = usb_add_gadget_udc_release(&udc->pdev->dev, &dev->gadget,
3295 gadget_release);
3296 if (retval)
3297 goto finished;
3298
3299 /* timer init */
3300 init_timer(&udc_timer);
3301 udc_timer.function = udc_timer_function;
3302 udc_timer.data = 1;
3303 /* timer pollstall init */
3304 init_timer(&udc_pollstall_timer);
3305 udc_pollstall_timer.function = udc_pollstall_timer_function;
3306 udc_pollstall_timer.data = 1;
3307
3308 /* set SD */
3309 reg = readl(&dev->regs->ctl);
3310 reg |= AMD_BIT(UDC_DEVCTL_SD);
3311 writel(reg, &dev->regs->ctl);
3312
3313 /* print dev register info */
3314 print_regs(dev);
3315
3316 return 0;
3317
3318 finished:
3319 return retval;
3320 }
3321
3322 /* Initiates a remote wakeup */
3323 static int udc_remote_wakeup(struct udc *dev)
3324 {
3325 unsigned long flags;
3326 u32 tmp;
3327
3328 DBG(dev, "UDC initiates remote wakeup\n");
3329
3330 spin_lock_irqsave(&dev->lock, flags);
3331
3332 tmp = readl(&dev->regs->ctl);
3333 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3334 writel(tmp, &dev->regs->ctl);
3335 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3336 writel(tmp, &dev->regs->ctl);
3337
3338 spin_unlock_irqrestore(&dev->lock, flags);
3339 return 0;
3340 }
3341
3342 /* PCI device parameters */
3343 static DEFINE_PCI_DEVICE_TABLE(pci_id) = {
3344 {
3345 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3346 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3347 .class_mask = 0xffffffff,
3348 },
3349 {},
3350 };
3351 MODULE_DEVICE_TABLE(pci, pci_id);
3352
3353 /* PCI functions */
3354 static struct pci_driver udc_pci_driver = {
3355 .name = (char *) name,
3356 .id_table = pci_id,
3357 .probe = udc_pci_probe,
3358 .remove = udc_pci_remove,
3359 };
3360
3361 module_pci_driver(udc_pci_driver);
3362
3363 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3364 MODULE_AUTHOR("Thomas Dahlmann");
3365 MODULE_LICENSE("GPL");
3366
kernel source for telekom puls (alcatel/mediatek)