drivers/usb/chipidea/ci13xxx_udc.h

   1 /*
   2  * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Description: MIPS USB IP core family device controller
  13  *              Structures, registers and logging macros
  14  */
  15
  16 #ifndef _CI13XXX_h_
  17 #define _CI13XXX_h_
  18
  19 /******************************************************************************
  20  * DEFINE
  21  *****************************************************************************/
  22 #define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
  23 #define ENDPT_MAX          32
  24 #define CTRL_PAYLOAD_MAX   64
  25 #define RX        0  /* similar to USB_DIR_OUT but can be used as an index */
  26 #define TX        1  /* similar to USB_DIR_IN  but can be used as an index */
  27
  28 /******************************************************************************
  29  * STRUCTURES
  30  *****************************************************************************/
  31 /* DMA layout of transfer descriptors */
  32 struct ci13xxx_td {
  33         /* 0 */
  34         u32 next;
  35 #define TD_TERMINATE          BIT(0)
  36 #define TD_ADDR_MASK          (0xFFFFFFEUL << 5)
  37         /* 1 */
  38         u32 token;
  39 #define TD_STATUS             (0x00FFUL <<  0)
  40 #define TD_STATUS_TR_ERR      BIT(3)
  41 #define TD_STATUS_DT_ERR      BIT(5)
  42 #define TD_STATUS_HALTED      BIT(6)
  43 #define TD_STATUS_ACTIVE      BIT(7)
  44 #define TD_MULTO              (0x0003UL << 10)
  45 #define TD_IOC                BIT(15)
  46 #define TD_TOTAL_BYTES        (0x7FFFUL << 16)
  47         /* 2 */
  48         u32 page[5];
  49 #define TD_CURR_OFFSET        (0x0FFFUL <<  0)
  50 #define TD_FRAME_NUM          (0x07FFUL <<  0)
  51 #define TD_RESERVED_MASK      (0x0FFFUL <<  0)
  52 } __attribute__ ((packed));
  53
  54 /* DMA layout of queue heads */
  55 struct ci13xxx_qh {
  56         /* 0 */
  57         u32 cap;
  58 #define QH_IOS                BIT(15)
  59 #define QH_MAX_PKT            (0x07FFUL << 16)
  60 #define QH_ZLT                BIT(29)
  61 #define QH_MULT               (0x0003UL << 30)
  62         /* 1 */
  63         u32 curr;
  64         /* 2 - 8 */
  65         struct ci13xxx_td        td;
  66         /* 9 */
  67         u32 RESERVED;
  68         struct usb_ctrlrequest   setup;
  69 } __attribute__ ((packed));
  70
  71 /* Extension of usb_request */
  72 struct ci13xxx_req {
  73         struct usb_request   req;
  74         unsigned             map;
  75         struct list_head     queue;
  76         struct ci13xxx_td   *ptr;
  77         dma_addr_t           dma;
  78         struct ci13xxx_td   *zptr;
  79         dma_addr_t           zdma;
  80 };
  81
  82 /* Extension of usb_ep */
  83 struct ci13xxx_ep {
  84         struct usb_ep                          ep;
  85         u8                                     dir;
  86         u8                                     num;
  87         u8                                     type;
  88         char                                   name[16];
  89         struct {
  90                 struct list_head   queue;
  91                 struct ci13xxx_qh *ptr;
  92                 dma_addr_t         dma;
  93         }                                      qh;
  94         int                                    wedge;
  95
  96         /* global resources */
  97         struct ci13xxx                        *udc;
  98         spinlock_t                            *lock;
  99         struct device                         *device;
 100         struct dma_pool                       *td_pool;
 101 };
 102
 103 struct ci13xxx;
 104 struct ci13xxx_udc_driver {
 105         const char      *name;
 106         /* offset of the capability registers */
 107         uintptr_t        capoffset;
 108         unsigned long    flags;
 109 #define CI13XXX_REGS_SHARED             BIT(0)
 110 #define CI13XXX_REQUIRE_TRANSCEIVER     BIT(1)
 111 #define CI13XXX_PULLUP_ON_VBUS          BIT(2)
 112 #define CI13XXX_DISABLE_STREAMING       BIT(3)
 113
 114 #define CI13XXX_CONTROLLER_RESET_EVENT          0
 115 #define CI13XXX_CONTROLLER_STOPPED_EVENT        1
 116         void    (*notify_event) (struct ci13xxx *udc, unsigned event);
 117 };
 118
 119 struct hw_bank {
 120         unsigned      lpm;    /* is LPM? */
 121         void __iomem *abs;    /* bus map offset */
 122         void __iomem *cap;    /* bus map offset + CAP offset */
 123         void __iomem *op;     /* bus map offset + OP offset */
 124         size_t        size;   /* bank size */
 125         void __iomem **regmap;
 126 };
 127
 128 /* CI13XXX UDC descriptor & global resources */
 129 struct ci13xxx {
 130         spinlock_t                 lock;      /* ctrl register bank access */
 131         void __iomem              *regs;      /* registers address space */
 132
 133         struct dma_pool           *qh_pool;   /* DMA pool for queue heads */
 134         struct dma_pool           *td_pool;   /* DMA pool for transfer descs */
 135         struct usb_request        *status;    /* ep0 status request */
 136
 137         struct device             *dev;
 138         struct usb_gadget          gadget;     /* USB slave device */
 139         struct ci13xxx_ep          ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
 140         u32                        ep0_dir;    /* ep0 direction */
 141         struct ci13xxx_ep          *ep0out, *ep0in;
 142         unsigned                   hw_ep_max;  /* number of hw endpoints */
 143
 144         bool                       setaddr;
 145         u8                         address;
 146         u8                         remote_wakeup; /* Is remote wakeup feature
 147                                                         enabled by the host? */
 148         u8                         suspended;  /* suspended by the host */
 149         u8                         test_mode;  /* the selected test mode */
 150
 151         struct hw_bank             hw_bank;
 152         int                        irq;
 153         struct usb_gadget_driver  *driver;     /* 3rd party gadget driver */
 154         struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
 155         int                        vbus_active; /* is VBUS active */
 156         struct usb_phy            *transceiver; /* Transceiver struct */
 157 };
 158
 159 /******************************************************************************
 160  * REGISTERS
 161  *****************************************************************************/
 162 /* Default offset of capability registers */
 163 #define DEF_CAPOFFSET           0x100
 164
 165 /* register size */
 166 #define REG_BITS   (32)
 167
 168 /* register indices */
 169 enum ci13xxx_regs {
 170         CAP_CAPLENGTH,
 171         CAP_HCCPARAMS,
 172         CAP_DCCPARAMS,
 173         CAP_TESTMODE,
 174         CAP_LAST = CAP_TESTMODE,
 175         OP_USBCMD,
 176         OP_USBSTS,
 177         OP_USBINTR,
 178         OP_DEVICEADDR,
 179         OP_ENDPTLISTADDR,
 180         OP_PORTSC,
 181         OP_DEVLC,
 182         OP_USBMODE,
 183         OP_ENDPTSETUPSTAT,
 184         OP_ENDPTPRIME,
 185         OP_ENDPTFLUSH,
 186         OP_ENDPTSTAT,
 187         OP_ENDPTCOMPLETE,
 188         OP_ENDPTCTRL,
 189         /* endptctrl1..15 follow */
 190         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 191 };
 192
 193 /* HCCPARAMS */
 194 #define HCCPARAMS_LEN         BIT(17)
 195
 196 /* DCCPARAMS */
 197 #define DCCPARAMS_DEN         (0x1F << 0)
 198 #define DCCPARAMS_DC          BIT(7)
 199
 200 /* TESTMODE */
 201 #define TESTMODE_FORCE        BIT(0)
 202
 203 /* USBCMD */
 204 #define USBCMD_RS             BIT(0)
 205 #define USBCMD_RST            BIT(1)
 206 #define USBCMD_SUTW           BIT(13)
 207 #define USBCMD_ATDTW          BIT(14)
 208
 209 /* USBSTS & USBINTR */
 210 #define USBi_UI               BIT(0)
 211 #define USBi_UEI              BIT(1)
 212 #define USBi_PCI              BIT(2)
 213 #define USBi_URI              BIT(6)
 214 #define USBi_SLI              BIT(8)
 215
 216 /* DEVICEADDR */
 217 #define DEVICEADDR_USBADRA    BIT(24)
 218 #define DEVICEADDR_USBADR     (0x7FUL << 25)
 219
 220 /* PORTSC */
 221 #define PORTSC_FPR            BIT(6)
 222 #define PORTSC_SUSP           BIT(7)
 223 #define PORTSC_HSP            BIT(9)
 224 #define PORTSC_PTC            (0x0FUL << 16)
 225
 226 /* DEVLC */
 227 #define DEVLC_PSPD            (0x03UL << 25)
 228 #define    DEVLC_PSPD_HS      (0x02UL << 25)
 229
 230 /* USBMODE */
 231 #define USBMODE_CM            (0x03UL <<  0)
 232 #define    USBMODE_CM_IDLE    (0x00UL <<  0)
 233 #define    USBMODE_CM_DEVICE  (0x02UL <<  0)
 234 #define    USBMODE_CM_HOST    (0x03UL <<  0)
 235 #define USBMODE_SLOM          BIT(3)
 236 #define USBMODE_SDIS          BIT(4)
 237
 238 /* ENDPTCTRL */
 239 #define ENDPTCTRL_RXS         BIT(0)
 240 #define ENDPTCTRL_RXT         (0x03UL <<  2)
 241 #define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
 242 #define ENDPTCTRL_RXE         BIT(7)
 243 #define ENDPTCTRL_TXS         BIT(16)
 244 #define ENDPTCTRL_TXT         (0x03UL << 18)
 245 #define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
 246 #define ENDPTCTRL_TXE         BIT(23)
 247
 248 #endif  /* _CI13XXX_h_ */