2 * ci13xxx_udc.c - MIPS USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
53 #include <linux/delay.h>
54 #include <linux/device.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/init.h>
58 #include <linux/platform_device.h>
59 #include <linux/module.h>
60 #include <linux/interrupt.h>
62 #include <linux/irq.h>
63 #include <linux/kernel.h>
64 #include <linux/slab.h>
65 #include <linux/pm_runtime.h>
66 #include <linux/usb/ch9.h>
67 #include <linux/usb/gadget.h>
68 #include <linux/usb/otg.h>
70 #include "ci13xxx_udc.h"
72 /******************************************************************************
74 *****************************************************************************/
76 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
78 /* control endpoint description */
79 static const struct usb_endpoint_descriptor
80 ctrl_endpt_out_desc
= {
81 .bLength
= USB_DT_ENDPOINT_SIZE
,
82 .bDescriptorType
= USB_DT_ENDPOINT
,
84 .bEndpointAddress
= USB_DIR_OUT
,
85 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
86 .wMaxPacketSize
= cpu_to_le16(CTRL_PAYLOAD_MAX
),
89 static const struct usb_endpoint_descriptor
90 ctrl_endpt_in_desc
= {
91 .bLength
= USB_DT_ENDPOINT_SIZE
,
92 .bDescriptorType
= USB_DT_ENDPOINT
,
94 .bEndpointAddress
= USB_DIR_IN
,
95 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
96 .wMaxPacketSize
= cpu_to_le16(CTRL_PAYLOAD_MAX
),
99 /* Interrupt statistics */
100 #define ISR_MASK 0x1F
117 * ffs_nr: find first (least significant) bit set
118 * @x: the word to search
120 * This function returns bit number (instead of position)
122 static int ffs_nr(u32 x
)
129 /******************************************************************************
131 *****************************************************************************/
134 #define ABS_AHBBURST (0x0090UL)
135 #define ABS_AHBMODE (0x0098UL)
136 /* UDC register map */
137 static uintptr_t ci_regs_nolpm
[] = {
138 [CAP_CAPLENGTH
] = 0x000UL
,
139 [CAP_HCCPARAMS
] = 0x008UL
,
140 [CAP_DCCPARAMS
] = 0x024UL
,
141 [CAP_TESTMODE
] = 0x038UL
,
142 [OP_USBCMD
] = 0x000UL
,
143 [OP_USBSTS
] = 0x004UL
,
144 [OP_USBINTR
] = 0x008UL
,
145 [OP_DEVICEADDR
] = 0x014UL
,
146 [OP_ENDPTLISTADDR
] = 0x018UL
,
147 [OP_PORTSC
] = 0x044UL
,
148 [OP_DEVLC
] = 0x084UL
,
149 [OP_USBMODE
] = 0x068UL
,
150 [OP_ENDPTSETUPSTAT
] = 0x06CUL
,
151 [OP_ENDPTPRIME
] = 0x070UL
,
152 [OP_ENDPTFLUSH
] = 0x074UL
,
153 [OP_ENDPTSTAT
] = 0x078UL
,
154 [OP_ENDPTCOMPLETE
] = 0x07CUL
,
155 [OP_ENDPTCTRL
] = 0x080UL
,
158 static uintptr_t ci_regs_lpm
[] = {
159 [CAP_CAPLENGTH
] = 0x000UL
,
160 [CAP_HCCPARAMS
] = 0x008UL
,
161 [CAP_DCCPARAMS
] = 0x024UL
,
162 [CAP_TESTMODE
] = 0x0FCUL
,
163 [OP_USBCMD
] = 0x000UL
,
164 [OP_USBSTS
] = 0x004UL
,
165 [OP_USBINTR
] = 0x008UL
,
166 [OP_DEVICEADDR
] = 0x014UL
,
167 [OP_ENDPTLISTADDR
] = 0x018UL
,
168 [OP_PORTSC
] = 0x044UL
,
169 [OP_DEVLC
] = 0x084UL
,
170 [OP_USBMODE
] = 0x0C8UL
,
171 [OP_ENDPTSETUPSTAT
] = 0x0D8UL
,
172 [OP_ENDPTPRIME
] = 0x0DCUL
,
173 [OP_ENDPTFLUSH
] = 0x0E0UL
,
174 [OP_ENDPTSTAT
] = 0x0E4UL
,
175 [OP_ENDPTCOMPLETE
] = 0x0E8UL
,
176 [OP_ENDPTCTRL
] = 0x0ECUL
,
179 static int hw_alloc_regmap(struct ci13xxx
*udc
, bool is_lpm
)
183 kfree(udc
->hw_bank
.regmap
);
185 udc
->hw_bank
.regmap
= kzalloc((OP_LAST
+ 1) * sizeof(void *),
187 if (!udc
->hw_bank
.regmap
)
190 for (i
= 0; i
< OP_ENDPTCTRL
; i
++)
191 udc
->hw_bank
.regmap
[i
] =
192 (i
<= CAP_LAST
? udc
->hw_bank
.cap
: udc
->hw_bank
.op
) +
193 (is_lpm
? ci_regs_lpm
[i
] : ci_regs_nolpm
[i
]);
195 for (; i
<= OP_LAST
; i
++)
196 udc
->hw_bank
.regmap
[i
] = udc
->hw_bank
.op
+
197 4 * (i
- OP_ENDPTCTRL
) +
199 ? ci_regs_lpm
[OP_ENDPTCTRL
]
200 : ci_regs_nolpm
[OP_ENDPTCTRL
]);
206 * hw_ep_bit: calculates the bit number
207 * @num: endpoint number
208 * @dir: endpoint direction
210 * This function returns bit number
212 static inline int hw_ep_bit(int num
, int dir
)
214 return num
+ (dir
? 16 : 0);
217 static int ep_to_bit(struct ci13xxx
*udc
, int n
)
219 int fill
= 16 - udc
->hw_ep_max
/ 2;
221 if (n
>= udc
->hw_ep_max
/ 2)
228 * hw_read: reads from a hw register
229 * @reg: register index
230 * @mask: bitfield mask
232 * This function returns register contents
234 static u32
hw_read(struct ci13xxx
*udc
, enum ci13xxx_regs reg
, u32 mask
)
236 return ioread32(udc
->hw_bank
.regmap
[reg
]) & mask
;
240 * hw_write: writes to a hw register
241 * @reg: register index
242 * @mask: bitfield mask
245 static void hw_write(struct ci13xxx
*udc
, enum ci13xxx_regs reg
, u32 mask
,
249 data
= (ioread32(udc
->hw_bank
.regmap
[reg
]) & ~mask
)
252 iowrite32(data
, udc
->hw_bank
.regmap
[reg
]);
256 * hw_test_and_clear: tests & clears a hw register
257 * @reg: register index
258 * @mask: bitfield mask
260 * This function returns register contents
262 static u32
hw_test_and_clear(struct ci13xxx
*udc
, enum ci13xxx_regs reg
,
265 u32 val
= ioread32(udc
->hw_bank
.regmap
[reg
]) & mask
;
267 iowrite32(val
, udc
->hw_bank
.regmap
[reg
]);
272 * hw_test_and_write: tests & writes a hw register
273 * @reg: register index
274 * @mask: bitfield mask
277 * This function returns register contents
279 static u32
hw_test_and_write(struct ci13xxx
*udc
, enum ci13xxx_regs reg
,
282 u32 val
= hw_read(udc
, reg
, ~0);
284 hw_write(udc
, reg
, mask
, data
);
285 return (val
& mask
) >> ffs_nr(mask
);
288 static int hw_device_init(struct ci13xxx
*udc
, void __iomem
*base
,
289 uintptr_t cap_offset
)
293 /* bank is a module variable */
294 udc
->hw_bank
.abs
= base
;
296 udc
->hw_bank
.cap
= udc
->hw_bank
.abs
;
297 udc
->hw_bank
.cap
+= cap_offset
;
298 udc
->hw_bank
.op
= udc
->hw_bank
.cap
+ ioread8(udc
->hw_bank
.cap
);
300 hw_alloc_regmap(udc
, false);
301 reg
= hw_read(udc
, CAP_HCCPARAMS
, HCCPARAMS_LEN
) >>
302 ffs_nr(HCCPARAMS_LEN
);
303 udc
->hw_bank
.lpm
= reg
;
304 hw_alloc_regmap(udc
, !!reg
);
305 udc
->hw_bank
.size
= udc
->hw_bank
.op
- udc
->hw_bank
.abs
;
306 udc
->hw_bank
.size
+= OP_LAST
;
307 udc
->hw_bank
.size
/= sizeof(u32
);
309 reg
= hw_read(udc
, CAP_DCCPARAMS
, DCCPARAMS_DEN
) >>
310 ffs_nr(DCCPARAMS_DEN
);
311 udc
->hw_ep_max
= reg
* 2; /* cache hw ENDPT_MAX */
313 if (udc
->hw_ep_max
== 0 || udc
->hw_ep_max
> ENDPT_MAX
)
316 dev_dbg(udc
->dev
, "ChipIdea UDC found, lpm: %d; cap: %p op: %p\n",
317 udc
->hw_bank
.lpm
, udc
->hw_bank
.cap
, udc
->hw_bank
.op
);
319 /* setup lock mode ? */
321 /* ENDPTSETUPSTAT is '0' by default */
323 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
328 * hw_device_reset: resets chip (execute without interruption)
329 * @base: register base address
331 * This function returns an error code
333 static int hw_device_reset(struct ci13xxx
*udc
)
335 /* should flush & stop before reset */
336 hw_write(udc
, OP_ENDPTFLUSH
, ~0, ~0);
337 hw_write(udc
, OP_USBCMD
, USBCMD_RS
, 0);
339 hw_write(udc
, OP_USBCMD
, USBCMD_RST
, USBCMD_RST
);
340 while (hw_read(udc
, OP_USBCMD
, USBCMD_RST
))
341 udelay(10); /* not RTOS friendly */
344 if (udc
->udc_driver
->notify_event
)
345 udc
->udc_driver
->notify_event(udc
,
346 CI13XXX_CONTROLLER_RESET_EVENT
);
348 if (udc
->udc_driver
->flags
& CI13XXX_DISABLE_STREAMING
)
349 hw_write(udc
, OP_USBMODE
, USBMODE_SDIS
, USBMODE_SDIS
);
351 /* USBMODE should be configured step by step */
352 hw_write(udc
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_IDLE
);
353 hw_write(udc
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_DEVICE
);
355 hw_write(udc
, OP_USBMODE
, USBMODE_SLOM
, USBMODE_SLOM
);
357 if (hw_read(udc
, OP_USBMODE
, USBMODE_CM
) != USBMODE_CM_DEVICE
) {
358 pr_err("cannot enter in device mode");
359 pr_err("lpm = %i", udc
->hw_bank
.lpm
);
367 * hw_device_state: enables/disables interrupts & starts/stops device (execute
368 * without interruption)
369 * @dma: 0 => disable, !0 => enable and set dma engine
371 * This function returns an error code
373 static int hw_device_state(struct ci13xxx
*udc
, u32 dma
)
376 hw_write(udc
, OP_ENDPTLISTADDR
, ~0, dma
);
377 /* interrupt, error, port change, reset, sleep/suspend */
378 hw_write(udc
, OP_USBINTR
, ~0,
379 USBi_UI
|USBi_UEI
|USBi_PCI
|USBi_URI
|USBi_SLI
);
380 hw_write(udc
, OP_USBCMD
, USBCMD_RS
, USBCMD_RS
);
382 hw_write(udc
, OP_USBCMD
, USBCMD_RS
, 0);
383 hw_write(udc
, OP_USBINTR
, ~0, 0);
389 * hw_ep_flush: flush endpoint fifo (execute without interruption)
390 * @num: endpoint number
391 * @dir: endpoint direction
393 * This function returns an error code
395 static int hw_ep_flush(struct ci13xxx
*udc
, int num
, int dir
)
397 int n
= hw_ep_bit(num
, dir
);
400 /* flush any pending transfer */
401 hw_write(udc
, OP_ENDPTFLUSH
, BIT(n
), BIT(n
));
402 while (hw_read(udc
, OP_ENDPTFLUSH
, BIT(n
)))
404 } while (hw_read(udc
, OP_ENDPTSTAT
, BIT(n
)));
410 * hw_ep_disable: disables endpoint (execute without interruption)
411 * @num: endpoint number
412 * @dir: endpoint direction
414 * This function returns an error code
416 static int hw_ep_disable(struct ci13xxx
*udc
, int num
, int dir
)
418 hw_ep_flush(udc
, num
, dir
);
419 hw_write(udc
, OP_ENDPTCTRL
+ num
,
420 dir
? ENDPTCTRL_TXE
: ENDPTCTRL_RXE
, 0);
425 * hw_ep_enable: enables endpoint (execute without interruption)
426 * @num: endpoint number
427 * @dir: endpoint direction
428 * @type: endpoint type
430 * This function returns an error code
432 static int hw_ep_enable(struct ci13xxx
*udc
, int num
, int dir
, int type
)
437 mask
= ENDPTCTRL_TXT
; /* type */
438 data
= type
<< ffs_nr(mask
);
440 mask
|= ENDPTCTRL_TXS
; /* unstall */
441 mask
|= ENDPTCTRL_TXR
; /* reset data toggle */
442 data
|= ENDPTCTRL_TXR
;
443 mask
|= ENDPTCTRL_TXE
; /* enable */
444 data
|= ENDPTCTRL_TXE
;
446 mask
= ENDPTCTRL_RXT
; /* type */
447 data
= type
<< ffs_nr(mask
);
449 mask
|= ENDPTCTRL_RXS
; /* unstall */
450 mask
|= ENDPTCTRL_RXR
; /* reset data toggle */
451 data
|= ENDPTCTRL_RXR
;
452 mask
|= ENDPTCTRL_RXE
; /* enable */
453 data
|= ENDPTCTRL_RXE
;
455 hw_write(udc
, OP_ENDPTCTRL
+ num
, mask
, data
);
460 * hw_ep_get_halt: return endpoint halt status
461 * @num: endpoint number
462 * @dir: endpoint direction
464 * This function returns 1 if endpoint halted
466 static int hw_ep_get_halt(struct ci13xxx
*udc
, int num
, int dir
)
468 u32 mask
= dir
? ENDPTCTRL_TXS
: ENDPTCTRL_RXS
;
470 return hw_read(udc
, OP_ENDPTCTRL
+ num
, mask
) ? 1 : 0;
474 * hw_test_and_clear_setup_status: test & clear setup status (execute without
476 * @n: endpoint number
478 * This function returns setup status
480 static int hw_test_and_clear_setup_status(struct ci13xxx
*udc
, int n
)
482 n
= ep_to_bit(udc
, n
);
483 return hw_test_and_clear(udc
, OP_ENDPTSETUPSTAT
, BIT(n
));
487 * hw_ep_prime: primes endpoint (execute without interruption)
488 * @num: endpoint number
489 * @dir: endpoint direction
490 * @is_ctrl: true if control endpoint
492 * This function returns an error code
494 static int hw_ep_prime(struct ci13xxx
*udc
, int num
, int dir
, int is_ctrl
)
496 int n
= hw_ep_bit(num
, dir
);
498 if (is_ctrl
&& dir
== RX
&& hw_read(udc
, OP_ENDPTSETUPSTAT
, BIT(num
)))
501 hw_write(udc
, OP_ENDPTPRIME
, BIT(n
), BIT(n
));
503 while (hw_read(udc
, OP_ENDPTPRIME
, BIT(n
)))
505 if (is_ctrl
&& dir
== RX
&& hw_read(udc
, OP_ENDPTSETUPSTAT
, BIT(num
)))
508 /* status shoult be tested according with manual but it doesn't work */
513 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
514 * without interruption)
515 * @num: endpoint number
516 * @dir: endpoint direction
517 * @value: true => stall, false => unstall
519 * This function returns an error code
521 static int hw_ep_set_halt(struct ci13xxx
*udc
, int num
, int dir
, int value
)
523 if (value
!= 0 && value
!= 1)
527 enum ci13xxx_regs reg
= OP_ENDPTCTRL
+ num
;
528 u32 mask_xs
= dir
? ENDPTCTRL_TXS
: ENDPTCTRL_RXS
;
529 u32 mask_xr
= dir
? ENDPTCTRL_TXR
: ENDPTCTRL_RXR
;
531 /* data toggle - reserved for EP0 but it's in ESS */
532 hw_write(udc
, reg
, mask_xs
|mask_xr
,
533 value
? mask_xs
: mask_xr
);
534 } while (value
!= hw_ep_get_halt(udc
, num
, dir
));
540 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
544 * This function returns an error code
546 static int hw_intr_clear(struct ci13xxx
*udc
, int n
)
551 hw_write(udc
, OP_USBINTR
, BIT(n
), 0);
552 hw_write(udc
, OP_USBSTS
, BIT(n
), BIT(n
));
557 * hw_intr_force: enables interrupt & forces interrupt status (execute without
561 * This function returns an error code
563 static int hw_intr_force(struct ci13xxx
*udc
, int n
)
568 hw_write(udc
, CAP_TESTMODE
, TESTMODE_FORCE
, TESTMODE_FORCE
);
569 hw_write(udc
, OP_USBINTR
, BIT(n
), BIT(n
));
570 hw_write(udc
, OP_USBSTS
, BIT(n
), BIT(n
));
571 hw_write(udc
, CAP_TESTMODE
, TESTMODE_FORCE
, 0);
576 * hw_is_port_high_speed: test if port is high speed
578 * This function returns true if high speed port
580 static int hw_port_is_high_speed(struct ci13xxx
*udc
)
582 return udc
->hw_bank
.lpm
? hw_read(udc
, OP_DEVLC
, DEVLC_PSPD
) :
583 hw_read(udc
, OP_PORTSC
, PORTSC_HSP
);
587 * hw_port_test_get: reads port test mode value
589 * This function returns port test mode value
591 static u8
hw_port_test_get(struct ci13xxx
*udc
)
593 return hw_read(udc
, OP_PORTSC
, PORTSC_PTC
) >> ffs_nr(PORTSC_PTC
);
597 * hw_port_test_set: writes port test mode (execute without interruption)
600 * This function returns an error code
602 static int hw_port_test_set(struct ci13xxx
*udc
, u8 mode
)
604 const u8 TEST_MODE_MAX
= 7;
606 if (mode
> TEST_MODE_MAX
)
609 hw_write(udc
, OP_PORTSC
, PORTSC_PTC
, mode
<< ffs_nr(PORTSC_PTC
));
614 * hw_read_intr_enable: returns interrupt enable register
616 * This function returns register data
618 static u32
hw_read_intr_enable(struct ci13xxx
*udc
)
620 return hw_read(udc
, OP_USBINTR
, ~0);
624 * hw_read_intr_status: returns interrupt status register
626 * This function returns register data
628 static u32
hw_read_intr_status(struct ci13xxx
*udc
)
630 return hw_read(udc
, OP_USBSTS
, ~0);
634 * hw_register_read: reads all device registers (execute without interruption)
635 * @buf: destination buffer
638 * This function returns number of registers read
640 static size_t hw_register_read(struct ci13xxx
*udc
, u32
*buf
, size_t size
)
644 if (size
> udc
->hw_bank
.size
)
645 size
= udc
->hw_bank
.size
;
647 for (i
= 0; i
< size
; i
++)
648 buf
[i
] = hw_read(udc
, i
* sizeof(u32
), ~0);
654 * hw_register_write: writes to register
655 * @addr: register address
656 * @data: register value
658 * This function returns an error code
660 static int hw_register_write(struct ci13xxx
*udc
, u16 addr
, u32 data
)
665 if (addr
>= udc
->hw_bank
.size
)
671 hw_write(udc
, addr
, ~0, data
);
676 * hw_test_and_clear_complete: test & clear complete status (execute without
678 * @n: endpoint number
680 * This function returns complete status
682 static int hw_test_and_clear_complete(struct ci13xxx
*udc
, int n
)
684 n
= ep_to_bit(udc
, n
);
685 return hw_test_and_clear(udc
, OP_ENDPTCOMPLETE
, BIT(n
));
689 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
690 * without interruption)
692 * This function returns active interrutps
694 static u32
hw_test_and_clear_intr_active(struct ci13xxx
*udc
)
696 u32 reg
= hw_read_intr_status(udc
) & hw_read_intr_enable(udc
);
698 hw_write(udc
, OP_USBSTS
, ~0, reg
);
703 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
706 * This function returns guard value
708 static int hw_test_and_clear_setup_guard(struct ci13xxx
*udc
)
710 return hw_test_and_write(udc
, OP_USBCMD
, USBCMD_SUTW
, 0);
714 * hw_test_and_set_setup_guard: test & set setup guard (execute without
717 * This function returns guard value
719 static int hw_test_and_set_setup_guard(struct ci13xxx
*udc
)
721 return hw_test_and_write(udc
, OP_USBCMD
, USBCMD_SUTW
, USBCMD_SUTW
);
725 * hw_usb_set_address: configures USB address (execute without interruption)
726 * @value: new USB address
728 * This function explicitly sets the address, without the "USBADRA" (advance)
729 * feature, which is not supported by older versions of the controller.
731 static void hw_usb_set_address(struct ci13xxx
*udc
, u8 value
)
733 hw_write(udc
, OP_DEVICEADDR
, DEVICEADDR_USBADR
,
734 value
<< ffs_nr(DEVICEADDR_USBADR
));
738 * hw_usb_reset: restart device after a bus reset (execute without
741 * This function returns an error code
743 static int hw_usb_reset(struct ci13xxx
*udc
)
745 hw_usb_set_address(udc
, 0);
747 /* ESS flushes only at end?!? */
748 hw_write(udc
, OP_ENDPTFLUSH
, ~0, ~0);
750 /* clear setup token semaphores */
751 hw_write(udc
, OP_ENDPTSETUPSTAT
, 0, 0);
753 /* clear complete status */
754 hw_write(udc
, OP_ENDPTCOMPLETE
, 0, 0);
756 /* wait until all bits cleared */
757 while (hw_read(udc
, OP_ENDPTPRIME
, ~0))
758 udelay(10); /* not RTOS friendly */
760 /* reset all endpoints ? */
762 /* reset internal status and wait for further instructions
763 no need to verify the port reset status (ESS does it) */
768 /******************************************************************************
770 *****************************************************************************/
772 * show_device: prints information about device capabilities and status
774 * Check "device.h" for details
776 static ssize_t
show_device(struct device
*dev
, struct device_attribute
*attr
,
779 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
780 struct usb_gadget
*gadget
= &udc
->gadget
;
783 if (attr
== NULL
|| buf
== NULL
) {
784 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
788 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "speed = %d\n",
790 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "max_speed = %d\n",
792 /* TODO: Scheduled for removal in 3.8. */
793 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "is_dualspeed = %d\n",
794 gadget_is_dualspeed(gadget
));
795 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "is_otg = %d\n",
797 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "is_a_peripheral = %d\n",
798 gadget
->is_a_peripheral
);
799 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "b_hnp_enable = %d\n",
800 gadget
->b_hnp_enable
);
801 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "a_hnp_support = %d\n",
802 gadget
->a_hnp_support
);
803 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "a_alt_hnp_support = %d\n",
804 gadget
->a_alt_hnp_support
);
805 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "name = %s\n",
806 (gadget
->name
? gadget
->name
: ""));
810 static DEVICE_ATTR(device
, S_IRUSR
, show_device
, NULL
);
813 * show_driver: prints information about attached gadget (if any)
815 * Check "device.h" for details
817 static ssize_t
show_driver(struct device
*dev
, struct device_attribute
*attr
,
820 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
821 struct usb_gadget_driver
*driver
= udc
->driver
;
824 if (attr
== NULL
|| buf
== NULL
) {
825 dev_err(dev
, "[%s] EINVAL\n", __func__
);
830 return scnprintf(buf
, PAGE_SIZE
,
831 "There is no gadget attached!\n");
833 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "function = %s\n",
834 (driver
->function
? driver
->function
: ""));
835 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "max speed = %d\n",
840 static DEVICE_ATTR(driver
, S_IRUSR
, show_driver
, NULL
);
842 /* Maximum event message length */
843 #define DBG_DATA_MSG 64UL
845 /* Maximum event messages */
846 #define DBG_DATA_MAX 128UL
848 /* Event buffer descriptor */
850 char (buf
[DBG_DATA_MAX
])[DBG_DATA_MSG
]; /* buffer */
851 unsigned idx
; /* index */
852 unsigned tty
; /* print to console? */
853 rwlock_t lck
; /* lock */
857 .lck
= __RW_LOCK_UNLOCKED(lck
)
861 * dbg_dec: decrements debug event index
864 static void dbg_dec(unsigned *idx
)
866 *idx
= (*idx
- 1) & (DBG_DATA_MAX
-1);
870 * dbg_inc: increments debug event index
873 static void dbg_inc(unsigned *idx
)
875 *idx
= (*idx
+ 1) & (DBG_DATA_MAX
-1);
879 * dbg_print: prints the common part of the event
880 * @addr: endpoint address
883 * @extra: extra information
885 static void dbg_print(u8 addr
, const char *name
, int status
, const char *extra
)
891 write_lock_irqsave(&dbg_data
.lck
, flags
);
893 do_gettimeofday(&tval
);
894 stamp
= tval
.tv_sec
& 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
895 stamp
= stamp
* 1000000 + tval
.tv_usec
;
897 scnprintf(dbg_data
.buf
[dbg_data
.idx
], DBG_DATA_MSG
,
898 "%04X\t? %02X %-7.7s %4i ?\t%s\n",
899 stamp
, addr
, name
, status
, extra
);
901 dbg_inc(&dbg_data
.idx
);
903 write_unlock_irqrestore(&dbg_data
.lck
, flags
);
905 if (dbg_data
.tty
!= 0)
906 pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
907 stamp
, addr
, name
, status
, extra
);
911 * dbg_done: prints a DONE event
912 * @addr: endpoint address
913 * @td: transfer descriptor
916 static void dbg_done(u8 addr
, const u32 token
, int status
)
918 char msg
[DBG_DATA_MSG
];
920 scnprintf(msg
, sizeof(msg
), "%d %02X",
921 (int)(token
& TD_TOTAL_BYTES
) >> ffs_nr(TD_TOTAL_BYTES
),
922 (int)(token
& TD_STATUS
) >> ffs_nr(TD_STATUS
));
923 dbg_print(addr
, "DONE", status
, msg
);
927 * dbg_event: prints a generic event
928 * @addr: endpoint address
932 static void dbg_event(u8 addr
, const char *name
, int status
)
935 dbg_print(addr
, name
, status
, "");
939 * dbg_queue: prints a QUEUE event
940 * @addr: endpoint address
944 static void dbg_queue(u8 addr
, const struct usb_request
*req
, int status
)
946 char msg
[DBG_DATA_MSG
];
949 scnprintf(msg
, sizeof(msg
),
950 "%d %d", !req
->no_interrupt
, req
->length
);
951 dbg_print(addr
, "QUEUE", status
, msg
);
956 * dbg_setup: prints a SETUP event
957 * @addr: endpoint address
958 * @req: setup request
960 static void dbg_setup(u8 addr
, const struct usb_ctrlrequest
*req
)
962 char msg
[DBG_DATA_MSG
];
965 scnprintf(msg
, sizeof(msg
),
966 "%02X %02X %04X %04X %d", req
->bRequestType
,
967 req
->bRequest
, le16_to_cpu(req
->wValue
),
968 le16_to_cpu(req
->wIndex
), le16_to_cpu(req
->wLength
));
969 dbg_print(addr
, "SETUP", 0, msg
);
974 * show_events: displays the event buffer
976 * Check "device.h" for details
978 static ssize_t
show_events(struct device
*dev
, struct device_attribute
*attr
,
982 unsigned i
, j
, n
= 0;
984 if (attr
== NULL
|| buf
== NULL
) {
985 dev_err(dev
->parent
, "[%s] EINVAL\n", __func__
);
989 read_lock_irqsave(&dbg_data
.lck
, flags
);
992 for (dbg_dec(&i
); i
!= dbg_data
.idx
; dbg_dec(&i
)) {
993 n
+= strlen(dbg_data
.buf
[i
]);
994 if (n
>= PAGE_SIZE
) {
995 n
-= strlen(dbg_data
.buf
[i
]);
999 for (j
= 0, dbg_inc(&i
); j
< n
; dbg_inc(&i
))
1000 j
+= scnprintf(buf
+ j
, PAGE_SIZE
- j
,
1001 "%s", dbg_data
.buf
[i
]);
1003 read_unlock_irqrestore(&dbg_data
.lck
, flags
);
1009 * store_events: configure if events are going to be also printed to console
1011 * Check "device.h" for details
1013 static ssize_t
store_events(struct device
*dev
, struct device_attribute
*attr
,
1014 const char *buf
, size_t count
)
1018 if (attr
== NULL
|| buf
== NULL
) {
1019 dev_err(dev
, "[%s] EINVAL\n", __func__
);
1023 if (sscanf(buf
, "%u", &tty
) != 1 || tty
> 1) {
1024 dev_err(dev
, "<1|0>: enable|disable console log\n");
1029 dev_info(dev
, "tty = %u", dbg_data
.tty
);
1034 static DEVICE_ATTR(events
, S_IRUSR
| S_IWUSR
, show_events
, store_events
);
1037 * show_inters: interrupt status, enable status and historic
1039 * Check "device.h" for details
1041 static ssize_t
show_inters(struct device
*dev
, struct device_attribute
*attr
,
1044 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1045 unsigned long flags
;
1047 unsigned i
, j
, n
= 0;
1049 if (attr
== NULL
|| buf
== NULL
) {
1050 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1054 spin_lock_irqsave(&udc
->lock
, flags
);
1056 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1057 "status = %08x\n", hw_read_intr_status(udc
));
1058 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1059 "enable = %08x\n", hw_read_intr_enable(udc
));
1061 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "*test = %d\n",
1062 isr_statistics
.test
);
1063 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "? ui = %d\n",
1065 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "? uei = %d\n",
1066 isr_statistics
.uei
);
1067 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "? pci = %d\n",
1068 isr_statistics
.pci
);
1069 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "? uri = %d\n",
1070 isr_statistics
.uri
);
1071 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "? sli = %d\n",
1072 isr_statistics
.sli
);
1073 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "*none = %d\n",
1074 isr_statistics
.none
);
1075 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "*hndl = %d\n",
1076 isr_statistics
.hndl
.cnt
);
1078 for (i
= isr_statistics
.hndl
.idx
, j
= 0; j
<= ISR_MASK
; j
++, i
++) {
1080 intr
= isr_statistics
.hndl
.buf
[i
];
1083 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "ui ");
1085 if (USBi_UEI
& intr
)
1086 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "uei ");
1088 if (USBi_PCI
& intr
)
1089 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "pci ");
1091 if (USBi_URI
& intr
)
1092 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "uri ");
1094 if (USBi_SLI
& intr
)
1095 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "sli ");
1098 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "??? ");
1099 if (isr_statistics
.hndl
.buf
[i
])
1100 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
, "\n");
1103 spin_unlock_irqrestore(&udc
->lock
, flags
);
1109 * store_inters: enable & force or disable an individual interrutps
1110 * (to be used for test purposes only)
1112 * Check "device.h" for details
1114 static ssize_t
store_inters(struct device
*dev
, struct device_attribute
*attr
,
1115 const char *buf
, size_t count
)
1117 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1118 unsigned long flags
;
1121 if (attr
== NULL
|| buf
== NULL
) {
1122 dev_err(udc
->dev
, "EINVAL\n");
1126 if (sscanf(buf
, "%u %u", &en
, &bit
) != 2 || en
> 1) {
1127 dev_err(udc
->dev
, "<1|0> <bit>: enable|disable interrupt\n");
1131 spin_lock_irqsave(&udc
->lock
, flags
);
1133 if (hw_intr_force(udc
, bit
))
1134 dev_err(dev
, "invalid bit number\n");
1136 isr_statistics
.test
++;
1138 if (hw_intr_clear(udc
, bit
))
1139 dev_err(dev
, "invalid bit number\n");
1141 spin_unlock_irqrestore(&udc
->lock
, flags
);
1146 static DEVICE_ATTR(inters
, S_IRUSR
| S_IWUSR
, show_inters
, store_inters
);
1149 * show_port_test: reads port test mode
1151 * Check "device.h" for details
1153 static ssize_t
show_port_test(struct device
*dev
,
1154 struct device_attribute
*attr
, char *buf
)
1156 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1157 unsigned long flags
;
1160 if (attr
== NULL
|| buf
== NULL
) {
1161 dev_err(udc
->dev
, "EINVAL\n");
1165 spin_lock_irqsave(&udc
->lock
, flags
);
1166 mode
= hw_port_test_get(udc
);
1167 spin_unlock_irqrestore(&udc
->lock
, flags
);
1169 return scnprintf(buf
, PAGE_SIZE
, "mode = %u\n", mode
);
1173 * store_port_test: writes port test mode
1175 * Check "device.h" for details
1177 static ssize_t
store_port_test(struct device
*dev
,
1178 struct device_attribute
*attr
,
1179 const char *buf
, size_t count
)
1181 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1182 unsigned long flags
;
1185 if (attr
== NULL
|| buf
== NULL
) {
1186 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1190 if (sscanf(buf
, "%u", &mode
) != 1) {
1191 dev_err(udc
->dev
, "<mode>: set port test mode");
1195 spin_lock_irqsave(&udc
->lock
, flags
);
1196 if (hw_port_test_set(udc
, mode
))
1197 dev_err(udc
->dev
, "invalid mode\n");
1198 spin_unlock_irqrestore(&udc
->lock
, flags
);
1203 static DEVICE_ATTR(port_test
, S_IRUSR
| S_IWUSR
,
1204 show_port_test
, store_port_test
);
1207 * show_qheads: DMA contents of all queue heads
1209 * Check "device.h" for details
1211 static ssize_t
show_qheads(struct device
*dev
, struct device_attribute
*attr
,
1214 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1215 unsigned long flags
;
1216 unsigned i
, j
, n
= 0;
1218 if (attr
== NULL
|| buf
== NULL
) {
1219 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1223 spin_lock_irqsave(&udc
->lock
, flags
);
1224 for (i
= 0; i
< udc
->hw_ep_max
/2; i
++) {
1225 struct ci13xxx_ep
*mEpRx
= &udc
->ci13xxx_ep
[i
];
1226 struct ci13xxx_ep
*mEpTx
=
1227 &udc
->ci13xxx_ep
[i
+ udc
->hw_ep_max
/2];
1228 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1229 "EP=%02i: RX=%08X TX=%08X\n",
1230 i
, (u32
)mEpRx
->qh
.dma
, (u32
)mEpTx
->qh
.dma
);
1231 for (j
= 0; j
< (sizeof(struct ci13xxx_qh
)/sizeof(u32
)); j
++) {
1232 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1233 " %04X: %08X %08X\n", j
,
1234 *((u32
*)mEpRx
->qh
.ptr
+ j
),
1235 *((u32
*)mEpTx
->qh
.ptr
+ j
));
1238 spin_unlock_irqrestore(&udc
->lock
, flags
);
1242 static DEVICE_ATTR(qheads
, S_IRUSR
, show_qheads
, NULL
);
1245 * show_registers: dumps all registers
1247 * Check "device.h" for details
1249 #define DUMP_ENTRIES 512
1250 static ssize_t
show_registers(struct device
*dev
,
1251 struct device_attribute
*attr
, char *buf
)
1253 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1254 unsigned long flags
;
1256 unsigned i
, k
, n
= 0;
1258 if (attr
== NULL
|| buf
== NULL
) {
1259 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1263 dump
= kmalloc(sizeof(u32
) * DUMP_ENTRIES
, GFP_KERNEL
);
1265 dev_err(udc
->dev
, "%s: out of memory\n", __func__
);
1269 spin_lock_irqsave(&udc
->lock
, flags
);
1270 k
= hw_register_read(udc
, dump
, DUMP_ENTRIES
);
1271 spin_unlock_irqrestore(&udc
->lock
, flags
);
1273 for (i
= 0; i
< k
; i
++) {
1274 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1275 "reg[0x%04X] = 0x%08X\n",
1276 i
* (unsigned)sizeof(u32
), dump
[i
]);
1284 * store_registers: writes value to register address
1286 * Check "device.h" for details
1288 static ssize_t
store_registers(struct device
*dev
,
1289 struct device_attribute
*attr
,
1290 const char *buf
, size_t count
)
1292 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1293 unsigned long addr
, data
, flags
;
1295 if (attr
== NULL
|| buf
== NULL
) {
1296 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1300 if (sscanf(buf
, "%li %li", &addr
, &data
) != 2) {
1302 "<addr> <data>: write data to register address\n");
1306 spin_lock_irqsave(&udc
->lock
, flags
);
1307 if (hw_register_write(udc
, addr
, data
))
1308 dev_err(udc
->dev
, "invalid address range\n");
1309 spin_unlock_irqrestore(&udc
->lock
, flags
);
1314 static DEVICE_ATTR(registers
, S_IRUSR
| S_IWUSR
,
1315 show_registers
, store_registers
);
1318 * show_requests: DMA contents of all requests currently queued (all endpts)
1320 * Check "device.h" for details
1322 static ssize_t
show_requests(struct device
*dev
, struct device_attribute
*attr
,
1325 struct ci13xxx
*udc
= container_of(dev
, struct ci13xxx
, gadget
.dev
);
1326 unsigned long flags
;
1327 struct list_head
*ptr
= NULL
;
1328 struct ci13xxx_req
*req
= NULL
;
1329 unsigned i
, j
, n
= 0, qSize
= sizeof(struct ci13xxx_td
)/sizeof(u32
);
1331 if (attr
== NULL
|| buf
== NULL
) {
1332 dev_err(udc
->dev
, "[%s] EINVAL\n", __func__
);
1336 spin_lock_irqsave(&udc
->lock
, flags
);
1337 for (i
= 0; i
< udc
->hw_ep_max
; i
++)
1338 list_for_each(ptr
, &udc
->ci13xxx_ep
[i
].qh
.queue
)
1340 req
= list_entry(ptr
, struct ci13xxx_req
, queue
);
1342 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1343 "EP=%02i: TD=%08X %s\n",
1344 i
% udc
->hw_ep_max
/2, (u32
)req
->dma
,
1345 ((i
< udc
->hw_ep_max
/2) ? "RX" : "TX"));
1347 for (j
= 0; j
< qSize
; j
++)
1348 n
+= scnprintf(buf
+ n
, PAGE_SIZE
- n
,
1350 *((u32
*)req
->ptr
+ j
));
1352 spin_unlock_irqrestore(&udc
->lock
, flags
);
1356 static DEVICE_ATTR(requests
, S_IRUSR
, show_requests
, NULL
);
1359 * dbg_create_files: initializes the attribute interface
1362 * This function returns an error code
1364 __maybe_unused
static int dbg_create_files(struct device
*dev
)
1370 retval
= device_create_file(dev
, &dev_attr_device
);
1373 retval
= device_create_file(dev
, &dev_attr_driver
);
1376 retval
= device_create_file(dev
, &dev_attr_events
);
1379 retval
= device_create_file(dev
, &dev_attr_inters
);
1382 retval
= device_create_file(dev
, &dev_attr_port_test
);
1385 retval
= device_create_file(dev
, &dev_attr_qheads
);
1388 retval
= device_create_file(dev
, &dev_attr_registers
);
1391 retval
= device_create_file(dev
, &dev_attr_requests
);
1397 device_remove_file(dev
, &dev_attr_registers
);
1399 device_remove_file(dev
, &dev_attr_qheads
);
1401 device_remove_file(dev
, &dev_attr_port_test
);
1403 device_remove_file(dev
, &dev_attr_inters
);
1405 device_remove_file(dev
, &dev_attr_events
);
1407 device_remove_file(dev
, &dev_attr_driver
);
1409 device_remove_file(dev
, &dev_attr_device
);
1415 * dbg_remove_files: destroys the attribute interface
1418 * This function returns an error code
1420 __maybe_unused
static int dbg_remove_files(struct device
*dev
)
1424 device_remove_file(dev
, &dev_attr_requests
);
1425 device_remove_file(dev
, &dev_attr_registers
);
1426 device_remove_file(dev
, &dev_attr_qheads
);
1427 device_remove_file(dev
, &dev_attr_port_test
);
1428 device_remove_file(dev
, &dev_attr_inters
);
1429 device_remove_file(dev
, &dev_attr_events
);
1430 device_remove_file(dev
, &dev_attr_driver
);
1431 device_remove_file(dev
, &dev_attr_device
);
1435 /******************************************************************************
1437 *****************************************************************************/
1439 * _usb_addr: calculates endpoint address from direction & number
1442 static inline u8
_usb_addr(struct ci13xxx_ep
*ep
)
1444 return ((ep
->dir
== TX
) ? USB_ENDPOINT_DIR_MASK
: 0) | ep
->num
;
1448 * _hardware_queue: configures a request at hardware level
1452 * This function returns an error code
1454 static int _hardware_enqueue(struct ci13xxx_ep
*mEp
, struct ci13xxx_req
*mReq
)
1456 struct ci13xxx
*udc
= mEp
->udc
;
1459 unsigned length
= mReq
->req
.length
;
1461 /* don't queue twice */
1462 if (mReq
->req
.status
== -EALREADY
)
1465 mReq
->req
.status
= -EALREADY
;
1466 if (length
&& mReq
->req
.dma
== DMA_ADDR_INVALID
) {
1468 dma_map_single(mEp
->device
, mReq
->req
.buf
,
1469 length
, mEp
->dir
? DMA_TO_DEVICE
:
1471 if (mReq
->req
.dma
== 0)
1477 if (mReq
->req
.zero
&& length
&& (length
% mEp
->ep
.maxpacket
== 0)) {
1478 mReq
->zptr
= dma_pool_alloc(mEp
->td_pool
, GFP_ATOMIC
,
1480 if (mReq
->zptr
== NULL
) {
1482 dma_unmap_single(mEp
->device
, mReq
->req
.dma
,
1483 length
, mEp
->dir
? DMA_TO_DEVICE
:
1485 mReq
->req
.dma
= DMA_ADDR_INVALID
;
1490 memset(mReq
->zptr
, 0, sizeof(*mReq
->zptr
));
1491 mReq
->zptr
->next
= TD_TERMINATE
;
1492 mReq
->zptr
->token
= TD_STATUS_ACTIVE
;
1493 if (!mReq
->req
.no_interrupt
)
1494 mReq
->zptr
->token
|= TD_IOC
;
1498 * TODO - handle requests which spawns into several TDs
1500 memset(mReq
->ptr
, 0, sizeof(*mReq
->ptr
));
1501 mReq
->ptr
->token
= length
<< ffs_nr(TD_TOTAL_BYTES
);
1502 mReq
->ptr
->token
&= TD_TOTAL_BYTES
;
1503 mReq
->ptr
->token
|= TD_STATUS_ACTIVE
;
1505 mReq
->ptr
->next
= mReq
->zdma
;
1507 mReq
->ptr
->next
= TD_TERMINATE
;
1508 if (!mReq
->req
.no_interrupt
)
1509 mReq
->ptr
->token
|= TD_IOC
;
1511 mReq
->ptr
->page
[0] = mReq
->req
.dma
;
1512 for (i
= 1; i
< 5; i
++)
1513 mReq
->ptr
->page
[i
] =
1514 (mReq
->req
.dma
+ i
* CI13XXX_PAGE_SIZE
) & ~TD_RESERVED_MASK
;
1516 if (!list_empty(&mEp
->qh
.queue
)) {
1517 struct ci13xxx_req
*mReqPrev
;
1518 int n
= hw_ep_bit(mEp
->num
, mEp
->dir
);
1521 mReqPrev
= list_entry(mEp
->qh
.queue
.prev
,
1522 struct ci13xxx_req
, queue
);
1524 mReqPrev
->zptr
->next
= mReq
->dma
& TD_ADDR_MASK
;
1526 mReqPrev
->ptr
->next
= mReq
->dma
& TD_ADDR_MASK
;
1528 if (hw_read(udc
, OP_ENDPTPRIME
, BIT(n
)))
1531 hw_write(udc
, OP_USBCMD
, USBCMD_ATDTW
, USBCMD_ATDTW
);
1532 tmp_stat
= hw_read(udc
, OP_ENDPTSTAT
, BIT(n
));
1533 } while (!hw_read(udc
, OP_USBCMD
, USBCMD_ATDTW
));
1534 hw_write(udc
, OP_USBCMD
, USBCMD_ATDTW
, 0);
1539 /* QH configuration */
1540 mEp
->qh
.ptr
->td
.next
= mReq
->dma
; /* TERMINATE = 0 */
1541 mEp
->qh
.ptr
->td
.token
&= ~TD_STATUS
; /* clear status */
1542 mEp
->qh
.ptr
->cap
|= QH_ZLT
;
1544 wmb(); /* synchronize before ep prime */
1546 ret
= hw_ep_prime(udc
, mEp
->num
, mEp
->dir
,
1547 mEp
->type
== USB_ENDPOINT_XFER_CONTROL
);
1553 * _hardware_dequeue: handles a request at hardware level
1557 * This function returns an error code
1559 static int _hardware_dequeue(struct ci13xxx_ep
*mEp
, struct ci13xxx_req
*mReq
)
1561 if (mReq
->req
.status
!= -EALREADY
)
1564 if ((TD_STATUS_ACTIVE
& mReq
->ptr
->token
) != 0)
1568 if ((TD_STATUS_ACTIVE
& mReq
->zptr
->token
) != 0)
1570 dma_pool_free(mEp
->td_pool
, mReq
->zptr
, mReq
->zdma
);
1574 mReq
->req
.status
= 0;
1577 dma_unmap_single(mEp
->device
, mReq
->req
.dma
, mReq
->req
.length
,
1578 mEp
->dir
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1579 mReq
->req
.dma
= DMA_ADDR_INVALID
;
1583 mReq
->req
.status
= mReq
->ptr
->token
& TD_STATUS
;
1584 if ((TD_STATUS_HALTED
& mReq
->req
.status
) != 0)
1585 mReq
->req
.status
= -1;
1586 else if ((TD_STATUS_DT_ERR
& mReq
->req
.status
) != 0)
1587 mReq
->req
.status
= -1;
1588 else if ((TD_STATUS_TR_ERR
& mReq
->req
.status
) != 0)
1589 mReq
->req
.status
= -1;
1591 mReq
->req
.actual
= mReq
->ptr
->token
& TD_TOTAL_BYTES
;
1592 mReq
->req
.actual
>>= ffs_nr(TD_TOTAL_BYTES
);
1593 mReq
->req
.actual
= mReq
->req
.length
- mReq
->req
.actual
;
1594 mReq
->req
.actual
= mReq
->req
.status
? 0 : mReq
->req
.actual
;
1596 return mReq
->req
.actual
;
1600 * _ep_nuke: dequeues all endpoint requests
1603 * This function returns an error code
1604 * Caller must hold lock
1606 static int _ep_nuke(struct ci13xxx_ep
*mEp
)
1607 __releases(mEp
->lock
)
1608 __acquires(mEp
->lock
)
1613 hw_ep_flush(mEp
->udc
, mEp
->num
, mEp
->dir
);
1615 while (!list_empty(&mEp
->qh
.queue
)) {
1617 /* pop oldest request */
1618 struct ci13xxx_req
*mReq
= \
1619 list_entry(mEp
->qh
.queue
.next
,
1620 struct ci13xxx_req
, queue
);
1621 list_del_init(&mReq
->queue
);
1622 mReq
->req
.status
= -ESHUTDOWN
;
1624 if (mReq
->req
.complete
!= NULL
) {
1625 spin_unlock(mEp
->lock
);
1626 mReq
->req
.complete(&mEp
->ep
, &mReq
->req
);
1627 spin_lock(mEp
->lock
);
1634 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1637 * This function returns an error code
1639 static int _gadget_stop_activity(struct usb_gadget
*gadget
)
1642 struct ci13xxx
*udc
= container_of(gadget
, struct ci13xxx
, gadget
);
1643 unsigned long flags
;
1648 spin_lock_irqsave(&udc
->lock
, flags
);
1649 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1650 udc
->remote_wakeup
= 0;
1652 spin_unlock_irqrestore(&udc
->lock
, flags
);
1654 /* flush all endpoints */
1655 gadget_for_each_ep(ep
, gadget
) {
1656 usb_ep_fifo_flush(ep
);
1658 usb_ep_fifo_flush(&udc
->ep0out
->ep
);
1659 usb_ep_fifo_flush(&udc
->ep0in
->ep
);
1662 udc
->driver
->disconnect(gadget
);
1664 /* make sure to disable all endpoints */
1665 gadget_for_each_ep(ep
, gadget
) {
1669 if (udc
->status
!= NULL
) {
1670 usb_ep_free_request(&udc
->ep0in
->ep
, udc
->status
);
1677 /******************************************************************************
1679 *****************************************************************************/
1681 * isr_reset_handler: USB reset interrupt handler
1684 * This function resets USB engine after a bus reset occurred
1686 static void isr_reset_handler(struct ci13xxx
*udc
)
1687 __releases(udc
->lock
)
1688 __acquires(udc
->lock
)
1692 dbg_event(0xFF, "BUS RST", 0);
1694 spin_unlock(&udc
->lock
);
1695 retval
= _gadget_stop_activity(&udc
->gadget
);
1699 retval
= hw_usb_reset(udc
);
1703 udc
->status
= usb_ep_alloc_request(&udc
->ep0in
->ep
, GFP_ATOMIC
);
1704 if (udc
->status
== NULL
)
1707 spin_lock(&udc
->lock
);
1711 dev_err(udc
->dev
, "error: %i\n", retval
);
1715 * isr_get_status_complete: get_status request complete function
1717 * @req: request handled
1719 * Caller must release lock
1721 static void isr_get_status_complete(struct usb_ep
*ep
, struct usb_request
*req
)
1723 if (ep
== NULL
|| req
== NULL
)
1727 usb_ep_free_request(ep
, req
);
1731 * isr_get_status_response: get_status request response
1733 * @setup: setup request packet
1735 * This function returns an error code
1737 static int isr_get_status_response(struct ci13xxx
*udc
,
1738 struct usb_ctrlrequest
*setup
)
1739 __releases(mEp
->lock
)
1740 __acquires(mEp
->lock
)
1742 struct ci13xxx_ep
*mEp
= udc
->ep0in
;
1743 struct usb_request
*req
= NULL
;
1744 gfp_t gfp_flags
= GFP_ATOMIC
;
1745 int dir
, num
, retval
;
1747 if (mEp
== NULL
|| setup
== NULL
)
1750 spin_unlock(mEp
->lock
);
1751 req
= usb_ep_alloc_request(&mEp
->ep
, gfp_flags
);
1752 spin_lock(mEp
->lock
);
1756 req
->complete
= isr_get_status_complete
;
1758 req
->buf
= kzalloc(req
->length
, gfp_flags
);
1759 if (req
->buf
== NULL
) {
1764 if ((setup
->bRequestType
& USB_RECIP_MASK
) == USB_RECIP_DEVICE
) {
1765 /* Assume that device is bus powered for now. */
1766 *(u16
*)req
->buf
= udc
->remote_wakeup
<< 1;
1768 } else if ((setup
->bRequestType
& USB_RECIP_MASK
) \
1769 == USB_RECIP_ENDPOINT
) {
1770 dir
= (le16_to_cpu(setup
->wIndex
) & USB_ENDPOINT_DIR_MASK
) ?
1772 num
= le16_to_cpu(setup
->wIndex
) & USB_ENDPOINT_NUMBER_MASK
;
1773 *(u16
*)req
->buf
= hw_ep_get_halt(udc
, num
, dir
);
1775 /* else do nothing; reserved for future use */
1777 spin_unlock(mEp
->lock
);
1778 retval
= usb_ep_queue(&mEp
->ep
, req
, gfp_flags
);
1779 spin_lock(mEp
->lock
);
1788 spin_unlock(mEp
->lock
);
1789 usb_ep_free_request(&mEp
->ep
, req
);
1790 spin_lock(mEp
->lock
);
1795 * isr_setup_status_complete: setup_status request complete function
1797 * @req: request handled
1799 * Caller must release lock. Put the port in test mode if test mode
1800 * feature is selected.
1803 isr_setup_status_complete(struct usb_ep
*ep
, struct usb_request
*req
)
1805 struct ci13xxx
*udc
= req
->context
;
1806 unsigned long flags
;
1809 hw_usb_set_address(udc
, udc
->address
);
1810 udc
->setaddr
= false;
1813 spin_lock_irqsave(&udc
->lock
, flags
);
1815 hw_port_test_set(udc
, udc
->test_mode
);
1816 spin_unlock_irqrestore(&udc
->lock
, flags
);
1820 * isr_setup_status_phase: queues the status phase of a setup transation
1823 * This function returns an error code
1825 static int isr_setup_status_phase(struct ci13xxx
*udc
)
1826 __releases(mEp
->lock
)
1827 __acquires(mEp
->lock
)
1830 struct ci13xxx_ep
*mEp
;
1832 mEp
= (udc
->ep0_dir
== TX
) ? udc
->ep0out
: udc
->ep0in
;
1833 udc
->status
->context
= udc
;
1834 udc
->status
->complete
= isr_setup_status_complete
;
1836 spin_unlock(mEp
->lock
);
1837 retval
= usb_ep_queue(&mEp
->ep
, udc
->status
, GFP_ATOMIC
);
1838 spin_lock(mEp
->lock
);
1844 * isr_tr_complete_low: transaction complete low level handler
1847 * This function returns an error code
1848 * Caller must hold lock
1850 static int isr_tr_complete_low(struct ci13xxx_ep
*mEp
)
1851 __releases(mEp
->lock
)
1852 __acquires(mEp
->lock
)
1854 struct ci13xxx_req
*mReq
, *mReqTemp
;
1855 struct ci13xxx_ep
*mEpTemp
= mEp
;
1856 int uninitialized_var(retval
);
1858 if (list_empty(&mEp
->qh
.queue
))
1861 list_for_each_entry_safe(mReq
, mReqTemp
, &mEp
->qh
.queue
,
1863 retval
= _hardware_dequeue(mEp
, mReq
);
1866 list_del_init(&mReq
->queue
);
1867 dbg_done(_usb_addr(mEp
), mReq
->ptr
->token
, retval
);
1868 if (mReq
->req
.complete
!= NULL
) {
1869 spin_unlock(mEp
->lock
);
1870 if ((mEp
->type
== USB_ENDPOINT_XFER_CONTROL
) &&
1872 mEpTemp
= mEp
->udc
->ep0in
;
1873 mReq
->req
.complete(&mEpTemp
->ep
, &mReq
->req
);
1874 spin_lock(mEp
->lock
);
1878 if (retval
== -EBUSY
)
1881 dbg_event(_usb_addr(mEp
), "DONE", retval
);
1887 * isr_tr_complete_handler: transaction complete interrupt handler
1888 * @udc: UDC descriptor
1890 * This function handles traffic events
1892 static void isr_tr_complete_handler(struct ci13xxx
*udc
)
1893 __releases(udc
->lock
)
1894 __acquires(udc
->lock
)
1899 for (i
= 0; i
< udc
->hw_ep_max
; i
++) {
1900 struct ci13xxx_ep
*mEp
= &udc
->ci13xxx_ep
[i
];
1901 int type
, num
, dir
, err
= -EINVAL
;
1902 struct usb_ctrlrequest req
;
1904 if (mEp
->ep
.desc
== NULL
)
1905 continue; /* not configured */
1907 if (hw_test_and_clear_complete(udc
, i
)) {
1908 err
= isr_tr_complete_low(mEp
);
1909 if (mEp
->type
== USB_ENDPOINT_XFER_CONTROL
) {
1910 if (err
> 0) /* needs status phase */
1911 err
= isr_setup_status_phase(udc
);
1913 dbg_event(_usb_addr(mEp
),
1915 spin_unlock(&udc
->lock
);
1916 if (usb_ep_set_halt(&mEp
->ep
))
1918 "error: ep_set_halt\n");
1919 spin_lock(&udc
->lock
);
1924 if (mEp
->type
!= USB_ENDPOINT_XFER_CONTROL
||
1925 !hw_test_and_clear_setup_status(udc
, i
))
1929 dev_warn(udc
->dev
, "ctrl traffic at endpoint %d\n", i
);
1934 * Flush data and handshake transactions of previous
1937 _ep_nuke(udc
->ep0out
);
1938 _ep_nuke(udc
->ep0in
);
1940 /* read_setup_packet */
1942 hw_test_and_set_setup_guard(udc
);
1943 memcpy(&req
, &mEp
->qh
.ptr
->setup
, sizeof(req
));
1944 } while (!hw_test_and_clear_setup_guard(udc
));
1946 type
= req
.bRequestType
;
1948 udc
->ep0_dir
= (type
& USB_DIR_IN
) ? TX
: RX
;
1950 dbg_setup(_usb_addr(mEp
), &req
);
1952 switch (req
.bRequest
) {
1953 case USB_REQ_CLEAR_FEATURE
:
1954 if (type
== (USB_DIR_OUT
|USB_RECIP_ENDPOINT
) &&
1955 le16_to_cpu(req
.wValue
) ==
1956 USB_ENDPOINT_HALT
) {
1957 if (req
.wLength
!= 0)
1959 num
= le16_to_cpu(req
.wIndex
);
1960 dir
= num
& USB_ENDPOINT_DIR_MASK
;
1961 num
&= USB_ENDPOINT_NUMBER_MASK
;
1963 num
+= udc
->hw_ep_max
/2;
1964 if (!udc
->ci13xxx_ep
[num
].wedge
) {
1965 spin_unlock(&udc
->lock
);
1966 err
= usb_ep_clear_halt(
1967 &udc
->ci13xxx_ep
[num
].ep
);
1968 spin_lock(&udc
->lock
);
1972 err
= isr_setup_status_phase(udc
);
1973 } else if (type
== (USB_DIR_OUT
|USB_RECIP_DEVICE
) &&
1974 le16_to_cpu(req
.wValue
) ==
1975 USB_DEVICE_REMOTE_WAKEUP
) {
1976 if (req
.wLength
!= 0)
1978 udc
->remote_wakeup
= 0;
1979 err
= isr_setup_status_phase(udc
);
1984 case USB_REQ_GET_STATUS
:
1985 if (type
!= (USB_DIR_IN
|USB_RECIP_DEVICE
) &&
1986 type
!= (USB_DIR_IN
|USB_RECIP_ENDPOINT
) &&
1987 type
!= (USB_DIR_IN
|USB_RECIP_INTERFACE
))
1989 if (le16_to_cpu(req
.wLength
) != 2 ||
1990 le16_to_cpu(req
.wValue
) != 0)
1992 err
= isr_get_status_response(udc
, &req
);
1994 case USB_REQ_SET_ADDRESS
:
1995 if (type
!= (USB_DIR_OUT
|USB_RECIP_DEVICE
))
1997 if (le16_to_cpu(req
.wLength
) != 0 ||
1998 le16_to_cpu(req
.wIndex
) != 0)
2000 udc
->address
= (u8
)le16_to_cpu(req
.wValue
);
2001 udc
->setaddr
= true;
2002 err
= isr_setup_status_phase(udc
);
2004 case USB_REQ_SET_FEATURE
:
2005 if (type
== (USB_DIR_OUT
|USB_RECIP_ENDPOINT
) &&
2006 le16_to_cpu(req
.wValue
) ==
2007 USB_ENDPOINT_HALT
) {
2008 if (req
.wLength
!= 0)
2010 num
= le16_to_cpu(req
.wIndex
);
2011 dir
= num
& USB_ENDPOINT_DIR_MASK
;
2012 num
&= USB_ENDPOINT_NUMBER_MASK
;
2014 num
+= udc
->hw_ep_max
/2;
2016 spin_unlock(&udc
->lock
);
2017 err
= usb_ep_set_halt(&udc
->ci13xxx_ep
[num
].ep
);
2018 spin_lock(&udc
->lock
);
2020 isr_setup_status_phase(udc
);
2021 } else if (type
== (USB_DIR_OUT
|USB_RECIP_DEVICE
)) {
2022 if (req
.wLength
!= 0)
2024 switch (le16_to_cpu(req
.wValue
)) {
2025 case USB_DEVICE_REMOTE_WAKEUP
:
2026 udc
->remote_wakeup
= 1;
2027 err
= isr_setup_status_phase(udc
);
2029 case USB_DEVICE_TEST_MODE
:
2030 tmode
= le16_to_cpu(req
.wIndex
) >> 8;
2037 udc
->test_mode
= tmode
;
2038 err
= isr_setup_status_phase(
2053 if (req
.wLength
== 0) /* no data phase */
2056 spin_unlock(&udc
->lock
);
2057 err
= udc
->driver
->setup(&udc
->gadget
, &req
);
2058 spin_lock(&udc
->lock
);
2063 dbg_event(_usb_addr(mEp
), "ERROR", err
);
2065 spin_unlock(&udc
->lock
);
2066 if (usb_ep_set_halt(&mEp
->ep
))
2067 dev_err(udc
->dev
, "error: ep_set_halt\n");
2068 spin_lock(&udc
->lock
);
2073 /******************************************************************************
2075 *****************************************************************************/
2077 * ep_enable: configure endpoint, making it usable
2079 * Check usb_ep_enable() at "usb_gadget.h" for details
2081 static int ep_enable(struct usb_ep
*ep
,
2082 const struct usb_endpoint_descriptor
*desc
)
2084 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2086 unsigned long flags
;
2088 if (ep
== NULL
|| desc
== NULL
)
2091 spin_lock_irqsave(mEp
->lock
, flags
);
2093 /* only internal SW should enable ctrl endpts */
2095 mEp
->ep
.desc
= desc
;
2097 if (!list_empty(&mEp
->qh
.queue
))
2098 dev_warn(mEp
->udc
->dev
, "enabling a non-empty endpoint!\n");
2100 mEp
->dir
= usb_endpoint_dir_in(desc
) ? TX
: RX
;
2101 mEp
->num
= usb_endpoint_num(desc
);
2102 mEp
->type
= usb_endpoint_type(desc
);
2104 mEp
->ep
.maxpacket
= usb_endpoint_maxp(desc
);
2106 dbg_event(_usb_addr(mEp
), "ENABLE", 0);
2108 mEp
->qh
.ptr
->cap
= 0;
2110 if (mEp
->type
== USB_ENDPOINT_XFER_CONTROL
)
2111 mEp
->qh
.ptr
->cap
|= QH_IOS
;
2112 else if (mEp
->type
== USB_ENDPOINT_XFER_ISOC
)
2113 mEp
->qh
.ptr
->cap
&= ~QH_MULT
;
2115 mEp
->qh
.ptr
->cap
&= ~QH_ZLT
;
2118 (mEp
->ep
.maxpacket
<< ffs_nr(QH_MAX_PKT
)) & QH_MAX_PKT
;
2119 mEp
->qh
.ptr
->td
.next
|= TD_TERMINATE
; /* needed? */
2122 * Enable endpoints in the HW other than ep0 as ep0
2126 retval
|= hw_ep_enable(mEp
->udc
, mEp
->num
, mEp
->dir
, mEp
->type
);
2128 spin_unlock_irqrestore(mEp
->lock
, flags
);
2133 * ep_disable: endpoint is no longer usable
2135 * Check usb_ep_disable() at "usb_gadget.h" for details
2137 static int ep_disable(struct usb_ep
*ep
)
2139 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2140 int direction
, retval
= 0;
2141 unsigned long flags
;
2145 else if (mEp
->ep
.desc
== NULL
)
2148 spin_lock_irqsave(mEp
->lock
, flags
);
2150 /* only internal SW should disable ctrl endpts */
2152 direction
= mEp
->dir
;
2154 dbg_event(_usb_addr(mEp
), "DISABLE", 0);
2156 retval
|= _ep_nuke(mEp
);
2157 retval
|= hw_ep_disable(mEp
->udc
, mEp
->num
, mEp
->dir
);
2159 if (mEp
->type
== USB_ENDPOINT_XFER_CONTROL
)
2160 mEp
->dir
= (mEp
->dir
== TX
) ? RX
: TX
;
2162 } while (mEp
->dir
!= direction
);
2164 mEp
->ep
.desc
= NULL
;
2166 spin_unlock_irqrestore(mEp
->lock
, flags
);
2171 * ep_alloc_request: allocate a request object to use with this endpoint
2173 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2175 static struct usb_request
*ep_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
2177 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2178 struct ci13xxx_req
*mReq
= NULL
;
2183 mReq
= kzalloc(sizeof(struct ci13xxx_req
), gfp_flags
);
2185 INIT_LIST_HEAD(&mReq
->queue
);
2186 mReq
->req
.dma
= DMA_ADDR_INVALID
;
2188 mReq
->ptr
= dma_pool_alloc(mEp
->td_pool
, gfp_flags
,
2190 if (mReq
->ptr
== NULL
) {
2196 dbg_event(_usb_addr(mEp
), "ALLOC", mReq
== NULL
);
2198 return (mReq
== NULL
) ? NULL
: &mReq
->req
;
2202 * ep_free_request: frees a request object
2204 * Check usb_ep_free_request() at "usb_gadget.h" for details
2206 static void ep_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
2208 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2209 struct ci13xxx_req
*mReq
= container_of(req
, struct ci13xxx_req
, req
);
2210 unsigned long flags
;
2212 if (ep
== NULL
|| req
== NULL
) {
2214 } else if (!list_empty(&mReq
->queue
)) {
2215 dev_err(mEp
->udc
->dev
, "freeing queued request\n");
2219 spin_lock_irqsave(mEp
->lock
, flags
);
2222 dma_pool_free(mEp
->td_pool
, mReq
->ptr
, mReq
->dma
);
2225 dbg_event(_usb_addr(mEp
), "FREE", 0);
2227 spin_unlock_irqrestore(mEp
->lock
, flags
);
2231 * ep_queue: queues (submits) an I/O request to an endpoint
2233 * Check usb_ep_queue()* at usb_gadget.h" for details
2235 static int ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
2236 gfp_t __maybe_unused gfp_flags
)
2238 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2239 struct ci13xxx_req
*mReq
= container_of(req
, struct ci13xxx_req
, req
);
2240 struct ci13xxx
*udc
= mEp
->udc
;
2242 unsigned long flags
;
2244 if (ep
== NULL
|| req
== NULL
|| mEp
->ep
.desc
== NULL
)
2247 spin_lock_irqsave(mEp
->lock
, flags
);
2249 if (mEp
->type
== USB_ENDPOINT_XFER_CONTROL
) {
2251 mEp
= (udc
->ep0_dir
== RX
) ?
2252 udc
->ep0out
: udc
->ep0in
;
2253 if (!list_empty(&mEp
->qh
.queue
)) {
2255 retval
= -EOVERFLOW
;
2256 dev_warn(mEp
->udc
->dev
, "endpoint ctrl %X nuked\n",
2261 /* first nuke then test link, e.g. previous status has not sent */
2262 if (!list_empty(&mReq
->queue
)) {
2264 dev_err(mEp
->udc
->dev
, "request already in queue\n");
2268 if (req
->length
> 4 * CI13XXX_PAGE_SIZE
) {
2269 req
->length
= 4 * CI13XXX_PAGE_SIZE
;
2271 dev_warn(mEp
->udc
->dev
, "request length truncated\n");
2274 dbg_queue(_usb_addr(mEp
), req
, retval
);
2277 mReq
->req
.status
= -EINPROGRESS
;
2278 mReq
->req
.actual
= 0;
2280 retval
= _hardware_enqueue(mEp
, mReq
);
2282 if (retval
== -EALREADY
) {
2283 dbg_event(_usb_addr(mEp
), "QUEUE", retval
);
2287 list_add_tail(&mReq
->queue
, &mEp
->qh
.queue
);
2290 spin_unlock_irqrestore(mEp
->lock
, flags
);
2295 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2297 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2299 static int ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2301 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2302 struct ci13xxx_req
*mReq
= container_of(req
, struct ci13xxx_req
, req
);
2303 unsigned long flags
;
2305 if (ep
== NULL
|| req
== NULL
|| mReq
->req
.status
!= -EALREADY
||
2306 mEp
->ep
.desc
== NULL
|| list_empty(&mReq
->queue
) ||
2307 list_empty(&mEp
->qh
.queue
))
2310 spin_lock_irqsave(mEp
->lock
, flags
);
2312 dbg_event(_usb_addr(mEp
), "DEQUEUE", 0);
2314 hw_ep_flush(mEp
->udc
, mEp
->num
, mEp
->dir
);
2317 list_del_init(&mReq
->queue
);
2319 dma_unmap_single(mEp
->device
, mReq
->req
.dma
, mReq
->req
.length
,
2320 mEp
->dir
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2321 mReq
->req
.dma
= DMA_ADDR_INVALID
;
2324 req
->status
= -ECONNRESET
;
2326 if (mReq
->req
.complete
!= NULL
) {
2327 spin_unlock(mEp
->lock
);
2328 mReq
->req
.complete(&mEp
->ep
, &mReq
->req
);
2329 spin_lock(mEp
->lock
);
2332 spin_unlock_irqrestore(mEp
->lock
, flags
);
2337 * ep_set_halt: sets the endpoint halt feature
2339 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2341 static int ep_set_halt(struct usb_ep
*ep
, int value
)
2343 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2344 int direction
, retval
= 0;
2345 unsigned long flags
;
2347 if (ep
== NULL
|| mEp
->ep
.desc
== NULL
)
2350 spin_lock_irqsave(mEp
->lock
, flags
);
2353 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2354 if (value
&& mEp
->type
== USB_ENDPOINT_XFER_BULK
&& mEp
->dir
== TX
&&
2355 !list_empty(&mEp
->qh
.queue
)) {
2356 spin_unlock_irqrestore(mEp
->lock
, flags
);
2361 direction
= mEp
->dir
;
2363 dbg_event(_usb_addr(mEp
), "HALT", value
);
2364 retval
|= hw_ep_set_halt(mEp
->udc
, mEp
->num
, mEp
->dir
, value
);
2369 if (mEp
->type
== USB_ENDPOINT_XFER_CONTROL
)
2370 mEp
->dir
= (mEp
->dir
== TX
) ? RX
: TX
;
2372 } while (mEp
->dir
!= direction
);
2374 spin_unlock_irqrestore(mEp
->lock
, flags
);
2379 * ep_set_wedge: sets the halt feature and ignores clear requests
2381 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2383 static int ep_set_wedge(struct usb_ep
*ep
)
2385 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2386 unsigned long flags
;
2388 if (ep
== NULL
|| mEp
->ep
.desc
== NULL
)
2391 spin_lock_irqsave(mEp
->lock
, flags
);
2393 dbg_event(_usb_addr(mEp
), "WEDGE", 0);
2396 spin_unlock_irqrestore(mEp
->lock
, flags
);
2398 return usb_ep_set_halt(ep
);
2402 * ep_fifo_flush: flushes contents of a fifo
2404 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2406 static void ep_fifo_flush(struct usb_ep
*ep
)
2408 struct ci13xxx_ep
*mEp
= container_of(ep
, struct ci13xxx_ep
, ep
);
2409 unsigned long flags
;
2412 dev_err(mEp
->udc
->dev
, "%02X: -EINVAL\n", _usb_addr(mEp
));
2416 spin_lock_irqsave(mEp
->lock
, flags
);
2418 dbg_event(_usb_addr(mEp
), "FFLUSH", 0);
2419 hw_ep_flush(mEp
->udc
, mEp
->num
, mEp
->dir
);
2421 spin_unlock_irqrestore(mEp
->lock
, flags
);
2425 * Endpoint-specific part of the API to the USB controller hardware
2426 * Check "usb_gadget.h" for details
2428 static const struct usb_ep_ops usb_ep_ops
= {
2429 .enable
= ep_enable
,
2430 .disable
= ep_disable
,
2431 .alloc_request
= ep_alloc_request
,
2432 .free_request
= ep_free_request
,
2434 .dequeue
= ep_dequeue
,
2435 .set_halt
= ep_set_halt
,
2436 .set_wedge
= ep_set_wedge
,
2437 .fifo_flush
= ep_fifo_flush
,
2440 /******************************************************************************
2442 *****************************************************************************/
2443 static int ci13xxx_vbus_session(struct usb_gadget
*_gadget
, int is_active
)
2445 struct ci13xxx
*udc
= container_of(_gadget
, struct ci13xxx
, gadget
);
2446 unsigned long flags
;
2447 int gadget_ready
= 0;
2449 if (!(udc
->udc_driver
->flags
& CI13XXX_PULLUP_ON_VBUS
))
2452 spin_lock_irqsave(&udc
->lock
, flags
);
2453 udc
->vbus_active
= is_active
;
2456 spin_unlock_irqrestore(&udc
->lock
, flags
);
2460 pm_runtime_get_sync(&_gadget
->dev
);
2461 hw_device_reset(udc
);
2462 hw_device_state(udc
, udc
->ep0out
->qh
.dma
);
2464 hw_device_state(udc
, 0);
2465 if (udc
->udc_driver
->notify_event
)
2466 udc
->udc_driver
->notify_event(udc
,
2467 CI13XXX_CONTROLLER_STOPPED_EVENT
);
2468 _gadget_stop_activity(&udc
->gadget
);
2469 pm_runtime_put_sync(&_gadget
->dev
);
2476 static int ci13xxx_wakeup(struct usb_gadget
*_gadget
)
2478 struct ci13xxx
*udc
= container_of(_gadget
, struct ci13xxx
, gadget
);
2479 unsigned long flags
;
2482 spin_lock_irqsave(&udc
->lock
, flags
);
2483 if (!udc
->remote_wakeup
) {
2487 if (!hw_read(udc
, OP_PORTSC
, PORTSC_SUSP
)) {
2491 hw_write(udc
, OP_PORTSC
, PORTSC_FPR
, PORTSC_FPR
);
2493 spin_unlock_irqrestore(&udc
->lock
, flags
);
2497 static int ci13xxx_vbus_draw(struct usb_gadget
*_gadget
, unsigned mA
)
2499 struct ci13xxx
*udc
= container_of(_gadget
, struct ci13xxx
, gadget
);
2501 if (udc
->transceiver
)
2502 return usb_phy_set_power(udc
->transceiver
, mA
);
2506 static int ci13xxx_start(struct usb_gadget
*gadget
,
2507 struct usb_gadget_driver
*driver
);
2508 static int ci13xxx_stop(struct usb_gadget
*gadget
,
2509 struct usb_gadget_driver
*driver
);
2511 * Device operations part of the API to the USB controller hardware,
2512 * which don't involve endpoints (or i/o)
2513 * Check "usb_gadget.h" for details
2515 static const struct usb_gadget_ops usb_gadget_ops
= {
2516 .vbus_session
= ci13xxx_vbus_session
,
2517 .wakeup
= ci13xxx_wakeup
,
2518 .vbus_draw
= ci13xxx_vbus_draw
,
2519 .udc_start
= ci13xxx_start
,
2520 .udc_stop
= ci13xxx_stop
,
2523 static int init_eps(struct ci13xxx
*udc
)
2525 int retval
= 0, i
, j
;
2527 for (i
= 0; i
< udc
->hw_ep_max
/2; i
++)
2528 for (j
= RX
; j
<= TX
; j
++) {
2529 int k
= i
+ j
* udc
->hw_ep_max
/2;
2530 struct ci13xxx_ep
*mEp
= &udc
->ci13xxx_ep
[k
];
2532 scnprintf(mEp
->name
, sizeof(mEp
->name
), "ep%i%s", i
,
2533 (j
== TX
) ? "in" : "out");
2536 mEp
->lock
= &udc
->lock
;
2537 mEp
->device
= &udc
->gadget
.dev
;
2538 mEp
->td_pool
= udc
->td_pool
;
2540 mEp
->ep
.name
= mEp
->name
;
2541 mEp
->ep
.ops
= &usb_ep_ops
;
2542 mEp
->ep
.maxpacket
= CTRL_PAYLOAD_MAX
;
2544 INIT_LIST_HEAD(&mEp
->qh
.queue
);
2545 mEp
->qh
.ptr
= dma_pool_alloc(udc
->qh_pool
, GFP_KERNEL
,
2547 if (mEp
->qh
.ptr
== NULL
)
2550 memset(mEp
->qh
.ptr
, 0, sizeof(*mEp
->qh
.ptr
));
2553 * set up shorthands for ep0 out and in endpoints,
2554 * don't add to gadget's ep_list
2565 list_add_tail(&mEp
->ep
.ep_list
, &udc
->gadget
.ep_list
);
2572 * ci13xxx_start: register a gadget driver
2573 * @gadget: our gadget
2574 * @driver: the driver being registered
2576 * Interrupts are enabled here.
2578 static int ci13xxx_start(struct usb_gadget
*gadget
,
2579 struct usb_gadget_driver
*driver
)
2581 struct ci13xxx
*udc
= container_of(gadget
, struct ci13xxx
, gadget
);
2582 unsigned long flags
;
2583 int retval
= -ENOMEM
;
2585 if (driver
->disconnect
== NULL
)
2589 udc
->ep0out
->ep
.desc
= &ctrl_endpt_out_desc
;
2590 retval
= usb_ep_enable(&udc
->ep0out
->ep
);
2594 udc
->ep0in
->ep
.desc
= &ctrl_endpt_in_desc
;
2595 retval
= usb_ep_enable(&udc
->ep0in
->ep
);
2598 spin_lock_irqsave(&udc
->lock
, flags
);
2600 udc
->driver
= driver
;
2601 pm_runtime_get_sync(&udc
->gadget
.dev
);
2602 if (udc
->udc_driver
->flags
& CI13XXX_PULLUP_ON_VBUS
) {
2603 if (udc
->vbus_active
) {
2604 if (udc
->udc_driver
->flags
& CI13XXX_REGS_SHARED
)
2605 hw_device_reset(udc
);
2607 pm_runtime_put_sync(&udc
->gadget
.dev
);
2612 retval
= hw_device_state(udc
, udc
->ep0out
->qh
.dma
);
2614 pm_runtime_put_sync(&udc
->gadget
.dev
);
2617 spin_unlock_irqrestore(&udc
->lock
, flags
);
2622 * ci13xxx_stop: unregister a gadget driver
2624 static int ci13xxx_stop(struct usb_gadget
*gadget
,
2625 struct usb_gadget_driver
*driver
)
2627 struct ci13xxx
*udc
= container_of(gadget
, struct ci13xxx
, gadget
);
2628 unsigned long flags
;
2630 spin_lock_irqsave(&udc
->lock
, flags
);
2632 if (!(udc
->udc_driver
->flags
& CI13XXX_PULLUP_ON_VBUS
) ||
2634 hw_device_state(udc
, 0);
2635 if (udc
->udc_driver
->notify_event
)
2636 udc
->udc_driver
->notify_event(udc
,
2637 CI13XXX_CONTROLLER_STOPPED_EVENT
);
2639 spin_unlock_irqrestore(&udc
->lock
, flags
);
2640 _gadget_stop_activity(&udc
->gadget
);
2641 spin_lock_irqsave(&udc
->lock
, flags
);
2642 pm_runtime_put(&udc
->gadget
.dev
);
2645 spin_unlock_irqrestore(&udc
->lock
, flags
);
2650 /******************************************************************************
2652 *****************************************************************************/
2654 * udc_irq: global interrupt handler
2656 * This function returns IRQ_HANDLED if the IRQ has been handled
2657 * It locks access to registers
2659 static irqreturn_t
udc_irq(int irq
, void *data
)
2661 struct ci13xxx
*udc
= data
;
2668 spin_lock(&udc
->lock
);
2670 if (udc
->udc_driver
->flags
& CI13XXX_REGS_SHARED
) {
2671 if (hw_read(udc
, OP_USBMODE
, USBMODE_CM
) !=
2672 USBMODE_CM_DEVICE
) {
2673 spin_unlock(&udc
->lock
);
2677 intr
= hw_test_and_clear_intr_active(udc
);
2679 isr_statistics
.hndl
.buf
[isr_statistics
.hndl
.idx
++] = intr
;
2680 isr_statistics
.hndl
.idx
&= ISR_MASK
;
2681 isr_statistics
.hndl
.cnt
++;
2683 /* order defines priority - do NOT change it */
2684 if (USBi_URI
& intr
) {
2685 isr_statistics
.uri
++;
2686 isr_reset_handler(udc
);
2688 if (USBi_PCI
& intr
) {
2689 isr_statistics
.pci
++;
2690 udc
->gadget
.speed
= hw_port_is_high_speed(udc
) ?
2691 USB_SPEED_HIGH
: USB_SPEED_FULL
;
2692 if (udc
->suspended
&& udc
->driver
->resume
) {
2693 spin_unlock(&udc
->lock
);
2694 udc
->driver
->resume(&udc
->gadget
);
2695 spin_lock(&udc
->lock
);
2699 if (USBi_UEI
& intr
)
2700 isr_statistics
.uei
++;
2701 if (USBi_UI
& intr
) {
2702 isr_statistics
.ui
++;
2703 isr_tr_complete_handler(udc
);
2705 if (USBi_SLI
& intr
) {
2706 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
&&
2707 udc
->driver
->suspend
) {
2709 spin_unlock(&udc
->lock
);
2710 udc
->driver
->suspend(&udc
->gadget
);
2711 spin_lock(&udc
->lock
);
2713 isr_statistics
.sli
++;
2715 retval
= IRQ_HANDLED
;
2717 isr_statistics
.none
++;
2720 spin_unlock(&udc
->lock
);
2726 * udc_release: driver release function
2729 * Currently does nothing
2731 static void udc_release(struct device
*dev
)
2736 * udc_probe: parent probe must call this to initialize UDC
2737 * @dev: parent device
2738 * @regs: registers base address
2739 * @name: driver name
2741 * This function returns an error code
2742 * No interrupts active, the IRQ has not been requested yet
2743 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2745 static int udc_probe(struct ci13xxx_udc_driver
*driver
, struct device
*dev
,
2746 void __iomem
*regs
, struct ci13xxx
**_udc
)
2748 struct ci13xxx
*udc
;
2751 if (dev
== NULL
|| regs
== NULL
|| driver
== NULL
||
2752 driver
->name
== NULL
)
2755 udc
= kzalloc(sizeof(struct ci13xxx
), GFP_KERNEL
);
2759 spin_lock_init(&udc
->lock
);
2761 udc
->udc_driver
= driver
;
2763 udc
->gadget
.ops
= &usb_gadget_ops
;
2764 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2765 udc
->gadget
.max_speed
= USB_SPEED_HIGH
;
2766 udc
->gadget
.is_otg
= 0;
2767 udc
->gadget
.name
= driver
->name
;
2769 INIT_LIST_HEAD(&udc
->gadget
.ep_list
);
2771 dev_set_name(&udc
->gadget
.dev
, "gadget");
2772 udc
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
2773 udc
->gadget
.dev
.coherent_dma_mask
= dev
->coherent_dma_mask
;
2774 udc
->gadget
.dev
.parent
= dev
;
2775 udc
->gadget
.dev
.release
= udc_release
;
2779 /* alloc resources */
2780 udc
->qh_pool
= dma_pool_create("ci13xxx_qh", dev
,
2781 sizeof(struct ci13xxx_qh
),
2782 64, CI13XXX_PAGE_SIZE
);
2783 if (udc
->qh_pool
== NULL
) {
2788 udc
->td_pool
= dma_pool_create("ci13xxx_td", dev
,
2789 sizeof(struct ci13xxx_td
),
2790 64, CI13XXX_PAGE_SIZE
);
2791 if (udc
->td_pool
== NULL
) {
2796 retval
= hw_device_init(udc
, regs
, driver
->capoffset
);
2800 retval
= init_eps(udc
);
2804 udc
->gadget
.ep0
= &udc
->ep0in
->ep
;
2806 udc
->transceiver
= usb_get_transceiver();
2808 if (udc
->udc_driver
->flags
& CI13XXX_REQUIRE_TRANSCEIVER
) {
2809 if (udc
->transceiver
== NULL
) {
2815 if (!(udc
->udc_driver
->flags
& CI13XXX_REGS_SHARED
)) {
2816 retval
= hw_device_reset(udc
);
2818 goto put_transceiver
;
2821 retval
= device_register(&udc
->gadget
.dev
);
2823 put_device(&udc
->gadget
.dev
);
2824 goto put_transceiver
;
2827 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2828 retval
= dbg_create_files(&udc
->gadget
.dev
);
2833 if (udc
->transceiver
) {
2834 retval
= otg_set_peripheral(udc
->transceiver
->otg
,
2840 retval
= usb_add_gadget_udc(dev
, &udc
->gadget
);
2844 pm_runtime_no_callbacks(&udc
->gadget
.dev
);
2845 pm_runtime_enable(&udc
->gadget
.dev
);
2851 if (udc
->transceiver
) {
2852 otg_set_peripheral(udc
->transceiver
->otg
, &udc
->gadget
);
2853 usb_put_transceiver(udc
->transceiver
);
2856 dev_err(dev
, "error = %i\n", retval
);
2858 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2859 dbg_remove_files(&udc
->gadget
.dev
);
2862 device_unregister(&udc
->gadget
.dev
);
2864 if (udc
->transceiver
)
2865 usb_put_transceiver(udc
->transceiver
);
2867 dma_pool_destroy(udc
->td_pool
);
2869 dma_pool_destroy(udc
->qh_pool
);
2877 * udc_remove: parent remove must call this to remove UDC
2879 * No interrupts active, the IRQ has been released
2881 static void udc_remove(struct ci13xxx
*udc
)
2888 usb_del_gadget_udc(&udc
->gadget
);
2890 for (i
= 0; i
< udc
->hw_ep_max
; i
++) {
2891 struct ci13xxx_ep
*mEp
= &udc
->ci13xxx_ep
[i
];
2893 dma_pool_free(udc
->qh_pool
, mEp
->qh
.ptr
, mEp
->qh
.dma
);
2896 dma_pool_destroy(udc
->td_pool
);
2897 dma_pool_destroy(udc
->qh_pool
);
2899 if (udc
->transceiver
) {
2900 otg_set_peripheral(udc
->transceiver
->otg
, &udc
->gadget
);
2901 usb_put_transceiver(udc
->transceiver
);
2903 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2904 dbg_remove_files(&udc
->gadget
.dev
);
2906 device_unregister(&udc
->gadget
.dev
);
2908 kfree(udc
->hw_bank
.regmap
);
2912 static int __devinit
ci_udc_probe(struct platform_device
*pdev
)
2914 struct device
*dev
= &pdev
->dev
;
2915 struct ci13xxx_udc_driver
*driver
= dev
->platform_data
;
2916 struct ci13xxx
*udc
;
2917 struct resource
*res
;
2922 dev_err(dev
, "platform data missing\n");
2926 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2928 dev_err(dev
, "missing resource\n");
2932 base
= devm_request_and_ioremap(dev
, res
);
2934 dev_err(dev
, "can't request and ioremap resource\n");
2938 ret
= udc_probe(driver
, dev
, base
, &udc
);
2942 udc
->irq
= platform_get_irq(pdev
, 0);
2944 dev_err(dev
, "missing IRQ\n");
2949 platform_set_drvdata(pdev
, udc
);
2950 ret
= request_irq(udc
->irq
, udc_irq
, IRQF_SHARED
, driver
->name
, udc
);
2959 static int __devexit
ci_udc_remove(struct platform_device
*pdev
)
2961 struct ci13xxx
*udc
= platform_get_drvdata(pdev
);
2963 free_irq(udc
->irq
, udc
);
2969 static struct platform_driver ci_udc_driver
= {
2970 .probe
= ci_udc_probe
,
2971 .remove
= __devexit_p(ci_udc_remove
),
2977 module_platform_driver(ci_udc_driver
);
2979 MODULE_ALIAS("platform:ci_udc");
2980 MODULE_ALIAS("platform:ci13xxx");
2981 MODULE_LICENSE("GPL v2");
2982 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
2983 MODULE_DESCRIPTION("ChipIdea UDC Driver");