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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / imx.c
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * Copyright (C) 2009 emlix GmbH
12 * Author: Fabian Godehardt (added IrDA support for iMX)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * [29-Mar-2005] Mike Lee
29 * Added hardware handshake
30 */
31
32 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/platform_device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/clk.h>
47 #include <linux/delay.h>
48 #include <linux/rational.h>
49 #include <linux/slab.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/hardware.h>
54 #include <mach/imx-uart.h>
55
56 /* Register definitions */
57 #define URXD0 0x0 /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */
71 #define MX2_ONEMS 0xb0 /* One Millisecond register */
72 #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
119 #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
120 #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129 #define UCR4_IRSC (1<<5) /* IR special case */
130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152 #define USR2_IDLE (1<<12) /* Idle condition */
153 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
154 #define USR2_WAKE (1<<7) /* Wake */
155 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
156 #define USR2_TXDC (1<<3) /* Transmitter complete */
157 #define USR2_BRCD (1<<2) /* Break condition */
158 #define USR2_ORE (1<<1) /* Overrun error */
159 #define USR2_RDR (1<<0) /* Recv data ready */
160 #define UTS_FRCPERR (1<<13) /* Force parity error */
161 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
163 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
164 #define UTS_TXFULL (1<<4) /* TxFIFO full */
165 #define UTS_RXFULL (1<<3) /* RxFIFO full */
166 #define UTS_SOFTRST (1<<0) /* Software reset */
167
168 /* We've been assigned a range on the "Low-density serial ports" major */
169 #define SERIAL_IMX_MAJOR 207
170 #define MINOR_START 16
171 #define DEV_NAME "ttymxc"
172 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
173
174 /*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180 #define MCTRL_TIMEOUT (250*HZ/1000)
181
182 #define DRIVER_NAME "IMX-uart"
183
184 #define UART_NR 8
185
186 struct imx_port {
187 struct uart_port port;
188 struct timer_list timer;
189 unsigned int old_status;
190 int txirq,rxirq,rtsirq;
191 unsigned int have_rtscts:1;
192 unsigned int use_irda:1;
193 unsigned int irda_inv_rx:1;
194 unsigned int irda_inv_tx:1;
195 unsigned short trcv_delay; /* transceiver delay */
196 struct clk *clk;
197 };
198
199 #ifdef CONFIG_IRDA
200 #define USE_IRDA(sport) ((sport)->use_irda)
201 #else
202 #define USE_IRDA(sport) (0)
203 #endif
204
205 /*
206 * Handle any change of modem status signal since we were last called.
207 */
208 static void imx_mctrl_check(struct imx_port *sport)
209 {
210 unsigned int status, changed;
211
212 status = sport->port.ops->get_mctrl(&sport->port);
213 changed = status ^ sport->old_status;
214
215 if (changed == 0)
216 return;
217
218 sport->old_status = status;
219
220 if (changed & TIOCM_RI)
221 sport->port.icount.rng++;
222 if (changed & TIOCM_DSR)
223 sport->port.icount.dsr++;
224 if (changed & TIOCM_CAR)
225 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
226 if (changed & TIOCM_CTS)
227 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
228
229 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
230 }
231
232 /*
233 * This is our per-port timeout handler, for checking the
234 * modem status signals.
235 */
236 static void imx_timeout(unsigned long data)
237 {
238 struct imx_port *sport = (struct imx_port *)data;
239 unsigned long flags;
240
241 if (sport->port.state) {
242 spin_lock_irqsave(&sport->port.lock, flags);
243 imx_mctrl_check(sport);
244 spin_unlock_irqrestore(&sport->port.lock, flags);
245
246 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
247 }
248 }
249
250 /*
251 * interrupts disabled on entry
252 */
253 static void imx_stop_tx(struct uart_port *port)
254 {
255 struct imx_port *sport = (struct imx_port *)port;
256 unsigned long temp;
257
258 if (USE_IRDA(sport)) {
259 /* half duplex - wait for end of transmission */
260 int n = 256;
261 while ((--n > 0) &&
262 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
263 udelay(5);
264 barrier();
265 }
266 /*
267 * irda transceiver - wait a bit more to avoid
268 * cutoff, hardware dependent
269 */
270 udelay(sport->trcv_delay);
271
272 /*
273 * half duplex - reactivate receive mode,
274 * flush receive pipe echo crap
275 */
276 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
277 temp = readl(sport->port.membase + UCR1);
278 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
279 writel(temp, sport->port.membase + UCR1);
280
281 temp = readl(sport->port.membase + UCR4);
282 temp &= ~(UCR4_TCEN);
283 writel(temp, sport->port.membase + UCR4);
284
285 while (readl(sport->port.membase + URXD0) &
286 URXD_CHARRDY)
287 barrier();
288
289 temp = readl(sport->port.membase + UCR1);
290 temp |= UCR1_RRDYEN;
291 writel(temp, sport->port.membase + UCR1);
292
293 temp = readl(sport->port.membase + UCR4);
294 temp |= UCR4_DREN;
295 writel(temp, sport->port.membase + UCR4);
296 }
297 return;
298 }
299
300 temp = readl(sport->port.membase + UCR1);
301 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
302 }
303
304 /*
305 * interrupts disabled on entry
306 */
307 static void imx_stop_rx(struct uart_port *port)
308 {
309 struct imx_port *sport = (struct imx_port *)port;
310 unsigned long temp;
311
312 temp = readl(sport->port.membase + UCR2);
313 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
314 }
315
316 /*
317 * Set the modem control timer to fire immediately.
318 */
319 static void imx_enable_ms(struct uart_port *port)
320 {
321 struct imx_port *sport = (struct imx_port *)port;
322
323 mod_timer(&sport->timer, jiffies);
324 }
325
326 static inline void imx_transmit_buffer(struct imx_port *sport)
327 {
328 struct circ_buf *xmit = &sport->port.state->xmit;
329
330 while (!uart_circ_empty(xmit) &&
331 !(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
332 /* send xmit->buf[xmit->tail]
333 * out the port here */
334 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
335 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
336 sport->port.icount.tx++;
337 }
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(&sport->port);
341
342 if (uart_circ_empty(xmit))
343 imx_stop_tx(&sport->port);
344 }
345
346 /*
347 * interrupts disabled on entry
348 */
349 static void imx_start_tx(struct uart_port *port)
350 {
351 struct imx_port *sport = (struct imx_port *)port;
352 unsigned long temp;
353
354 if (USE_IRDA(sport)) {
355 /* half duplex in IrDA mode; have to disable receive mode */
356 temp = readl(sport->port.membase + UCR4);
357 temp &= ~(UCR4_DREN);
358 writel(temp, sport->port.membase + UCR4);
359
360 temp = readl(sport->port.membase + UCR1);
361 temp &= ~(UCR1_RRDYEN);
362 writel(temp, sport->port.membase + UCR1);
363 }
364
365 temp = readl(sport->port.membase + UCR1);
366 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
367
368 if (USE_IRDA(sport)) {
369 temp = readl(sport->port.membase + UCR1);
370 temp |= UCR1_TRDYEN;
371 writel(temp, sport->port.membase + UCR1);
372
373 temp = readl(sport->port.membase + UCR4);
374 temp |= UCR4_TCEN;
375 writel(temp, sport->port.membase + UCR4);
376 }
377
378 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
379 imx_transmit_buffer(sport);
380 }
381
382 static irqreturn_t imx_rtsint(int irq, void *dev_id)
383 {
384 struct imx_port *sport = dev_id;
385 unsigned int val;
386 unsigned long flags;
387
388 spin_lock_irqsave(&sport->port.lock, flags);
389
390 writel(USR1_RTSD, sport->port.membase + USR1);
391 val = readl(sport->port.membase + USR1) & USR1_RTSS;
392 uart_handle_cts_change(&sport->port, !!val);
393 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
394
395 spin_unlock_irqrestore(&sport->port.lock, flags);
396 return IRQ_HANDLED;
397 }
398
399 static irqreturn_t imx_txint(int irq, void *dev_id)
400 {
401 struct imx_port *sport = dev_id;
402 struct circ_buf *xmit = &sport->port.state->xmit;
403 unsigned long flags;
404
405 spin_lock_irqsave(&sport->port.lock,flags);
406 if (sport->port.x_char)
407 {
408 /* Send next char */
409 writel(sport->port.x_char, sport->port.membase + URTX0);
410 goto out;
411 }
412
413 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
414 imx_stop_tx(&sport->port);
415 goto out;
416 }
417
418 imx_transmit_buffer(sport);
419
420 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
421 uart_write_wakeup(&sport->port);
422
423 out:
424 spin_unlock_irqrestore(&sport->port.lock,flags);
425 return IRQ_HANDLED;
426 }
427
428 static irqreturn_t imx_rxint(int irq, void *dev_id)
429 {
430 struct imx_port *sport = dev_id;
431 unsigned int rx,flg,ignored = 0;
432 struct tty_struct *tty = sport->port.state->port.tty;
433 unsigned long flags, temp;
434
435 spin_lock_irqsave(&sport->port.lock,flags);
436
437 while (readl(sport->port.membase + USR2) & USR2_RDR) {
438 flg = TTY_NORMAL;
439 sport->port.icount.rx++;
440
441 rx = readl(sport->port.membase + URXD0);
442
443 temp = readl(sport->port.membase + USR2);
444 if (temp & USR2_BRCD) {
445 writel(USR2_BRCD, sport->port.membase + USR2);
446 if (uart_handle_break(&sport->port))
447 continue;
448 }
449
450 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
451 continue;
452
453 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
454 if (rx & URXD_PRERR)
455 sport->port.icount.parity++;
456 else if (rx & URXD_FRMERR)
457 sport->port.icount.frame++;
458 if (rx & URXD_OVRRUN)
459 sport->port.icount.overrun++;
460
461 if (rx & sport->port.ignore_status_mask) {
462 if (++ignored > 100)
463 goto out;
464 continue;
465 }
466
467 rx &= sport->port.read_status_mask;
468
469 if (rx & URXD_PRERR)
470 flg = TTY_PARITY;
471 else if (rx & URXD_FRMERR)
472 flg = TTY_FRAME;
473 if (rx & URXD_OVRRUN)
474 flg = TTY_OVERRUN;
475
476 #ifdef SUPPORT_SYSRQ
477 sport->port.sysrq = 0;
478 #endif
479 }
480
481 tty_insert_flip_char(tty, rx, flg);
482 }
483
484 out:
485 spin_unlock_irqrestore(&sport->port.lock,flags);
486 tty_flip_buffer_push(tty);
487 return IRQ_HANDLED;
488 }
489
490 static irqreturn_t imx_int(int irq, void *dev_id)
491 {
492 struct imx_port *sport = dev_id;
493 unsigned int sts;
494
495 sts = readl(sport->port.membase + USR1);
496
497 if (sts & USR1_RRDY)
498 imx_rxint(irq, dev_id);
499
500 if (sts & USR1_TRDY &&
501 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
502 imx_txint(irq, dev_id);
503
504 if (sts & USR1_RTSD)
505 imx_rtsint(irq, dev_id);
506
507 return IRQ_HANDLED;
508 }
509
510 /*
511 * Return TIOCSER_TEMT when transmitter is not busy.
512 */
513 static unsigned int imx_tx_empty(struct uart_port *port)
514 {
515 struct imx_port *sport = (struct imx_port *)port;
516
517 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
518 }
519
520 /*
521 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
522 */
523 static unsigned int imx_get_mctrl(struct uart_port *port)
524 {
525 struct imx_port *sport = (struct imx_port *)port;
526 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
527
528 if (readl(sport->port.membase + USR1) & USR1_RTSS)
529 tmp |= TIOCM_CTS;
530
531 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
532 tmp |= TIOCM_RTS;
533
534 return tmp;
535 }
536
537 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
538 {
539 struct imx_port *sport = (struct imx_port *)port;
540 unsigned long temp;
541
542 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
543
544 if (mctrl & TIOCM_RTS)
545 temp |= UCR2_CTS;
546
547 writel(temp, sport->port.membase + UCR2);
548 }
549
550 /*
551 * Interrupts always disabled.
552 */
553 static void imx_break_ctl(struct uart_port *port, int break_state)
554 {
555 struct imx_port *sport = (struct imx_port *)port;
556 unsigned long flags, temp;
557
558 spin_lock_irqsave(&sport->port.lock, flags);
559
560 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
561
562 if ( break_state != 0 )
563 temp |= UCR1_SNDBRK;
564
565 writel(temp, sport->port.membase + UCR1);
566
567 spin_unlock_irqrestore(&sport->port.lock, flags);
568 }
569
570 #define TXTL 2 /* reset default */
571 #define RXTL 1 /* reset default */
572
573 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
574 {
575 unsigned int val;
576 unsigned int ufcr_rfdiv;
577
578 /* set receiver / transmitter trigger level.
579 * RFDIV is set such way to satisfy requested uartclk value
580 */
581 val = TXTL << 10 | RXTL;
582 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
583 / sport->port.uartclk;
584
585 if(!ufcr_rfdiv)
586 ufcr_rfdiv = 1;
587
588 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
589
590 writel(val, sport->port.membase + UFCR);
591
592 return 0;
593 }
594
595 /* half the RX buffer size */
596 #define CTSTL 16
597
598 static int imx_startup(struct uart_port *port)
599 {
600 struct imx_port *sport = (struct imx_port *)port;
601 int retval;
602 unsigned long flags, temp;
603
604 imx_setup_ufcr(sport, 0);
605
606 /* disable the DREN bit (Data Ready interrupt enable) before
607 * requesting IRQs
608 */
609 temp = readl(sport->port.membase + UCR4);
610
611 if (USE_IRDA(sport))
612 temp |= UCR4_IRSC;
613
614 /* set the trigger level for CTS */
615 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
616 temp |= CTSTL<< UCR4_CTSTL_SHF;
617
618 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
619
620 if (USE_IRDA(sport)) {
621 /* reset fifo's and state machines */
622 int i = 100;
623 temp = readl(sport->port.membase + UCR2);
624 temp &= ~UCR2_SRST;
625 writel(temp, sport->port.membase + UCR2);
626 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
627 (--i > 0)) {
628 udelay(1);
629 }
630 }
631
632 /*
633 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
634 * chips only have one interrupt.
635 */
636 if (sport->txirq > 0) {
637 retval = request_irq(sport->rxirq, imx_rxint, 0,
638 DRIVER_NAME, sport);
639 if (retval)
640 goto error_out1;
641
642 retval = request_irq(sport->txirq, imx_txint, 0,
643 DRIVER_NAME, sport);
644 if (retval)
645 goto error_out2;
646
647 /* do not use RTS IRQ on IrDA */
648 if (!USE_IRDA(sport)) {
649 retval = request_irq(sport->rtsirq, imx_rtsint,
650 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
651 IRQF_TRIGGER_FALLING |
652 IRQF_TRIGGER_RISING,
653 DRIVER_NAME, sport);
654 if (retval)
655 goto error_out3;
656 }
657 } else {
658 retval = request_irq(sport->port.irq, imx_int, 0,
659 DRIVER_NAME, sport);
660 if (retval) {
661 free_irq(sport->port.irq, sport);
662 goto error_out1;
663 }
664 }
665
666 /*
667 * Finally, clear and enable interrupts
668 */
669 writel(USR1_RTSD, sport->port.membase + USR1);
670
671 temp = readl(sport->port.membase + UCR1);
672 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
673
674 if (USE_IRDA(sport)) {
675 temp |= UCR1_IREN;
676 temp &= ~(UCR1_RTSDEN);
677 }
678
679 writel(temp, sport->port.membase + UCR1);
680
681 temp = readl(sport->port.membase + UCR2);
682 temp |= (UCR2_RXEN | UCR2_TXEN);
683 writel(temp, sport->port.membase + UCR2);
684
685 if (USE_IRDA(sport)) {
686 /* clear RX-FIFO */
687 int i = 64;
688 while ((--i > 0) &&
689 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
690 barrier();
691 }
692 }
693
694 if (!cpu_is_mx1()) {
695 temp = readl(sport->port.membase + UCR3);
696 temp |= MX2_UCR3_RXDMUXSEL;
697 writel(temp, sport->port.membase + UCR3);
698 }
699
700 if (USE_IRDA(sport)) {
701 temp = readl(sport->port.membase + UCR4);
702 if (sport->irda_inv_rx)
703 temp |= UCR4_INVR;
704 else
705 temp &= ~(UCR4_INVR);
706 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
707
708 temp = readl(sport->port.membase + UCR3);
709 if (sport->irda_inv_tx)
710 temp |= UCR3_INVT;
711 else
712 temp &= ~(UCR3_INVT);
713 writel(temp, sport->port.membase + UCR3);
714 }
715
716 /*
717 * Enable modem status interrupts
718 */
719 spin_lock_irqsave(&sport->port.lock,flags);
720 imx_enable_ms(&sport->port);
721 spin_unlock_irqrestore(&sport->port.lock,flags);
722
723 if (USE_IRDA(sport)) {
724 struct imxuart_platform_data *pdata;
725 pdata = sport->port.dev->platform_data;
726 sport->irda_inv_rx = pdata->irda_inv_rx;
727 sport->irda_inv_tx = pdata->irda_inv_tx;
728 sport->trcv_delay = pdata->transceiver_delay;
729 if (pdata->irda_enable)
730 pdata->irda_enable(1);
731 }
732
733 return 0;
734
735 error_out3:
736 if (sport->txirq)
737 free_irq(sport->txirq, sport);
738 error_out2:
739 if (sport->rxirq)
740 free_irq(sport->rxirq, sport);
741 error_out1:
742 return retval;
743 }
744
745 static void imx_shutdown(struct uart_port *port)
746 {
747 struct imx_port *sport = (struct imx_port *)port;
748 unsigned long temp;
749
750 temp = readl(sport->port.membase + UCR2);
751 temp &= ~(UCR2_TXEN);
752 writel(temp, sport->port.membase + UCR2);
753
754 if (USE_IRDA(sport)) {
755 struct imxuart_platform_data *pdata;
756 pdata = sport->port.dev->platform_data;
757 if (pdata->irda_enable)
758 pdata->irda_enable(0);
759 }
760
761 /*
762 * Stop our timer.
763 */
764 del_timer_sync(&sport->timer);
765
766 /*
767 * Free the interrupts
768 */
769 if (sport->txirq > 0) {
770 if (!USE_IRDA(sport))
771 free_irq(sport->rtsirq, sport);
772 free_irq(sport->txirq, sport);
773 free_irq(sport->rxirq, sport);
774 } else
775 free_irq(sport->port.irq, sport);
776
777 /*
778 * Disable all interrupts, port and break condition.
779 */
780
781 temp = readl(sport->port.membase + UCR1);
782 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
783 if (USE_IRDA(sport))
784 temp &= ~(UCR1_IREN);
785
786 writel(temp, sport->port.membase + UCR1);
787 }
788
789 static void
790 imx_set_termios(struct uart_port *port, struct ktermios *termios,
791 struct ktermios *old)
792 {
793 struct imx_port *sport = (struct imx_port *)port;
794 unsigned long flags;
795 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
796 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
797 unsigned int div, ufcr;
798 unsigned long num, denom;
799 uint64_t tdiv64;
800
801 /*
802 * If we don't support modem control lines, don't allow
803 * these to be set.
804 */
805 if (0) {
806 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
807 termios->c_cflag |= CLOCAL;
808 }
809
810 /*
811 * We only support CS7 and CS8.
812 */
813 while ((termios->c_cflag & CSIZE) != CS7 &&
814 (termios->c_cflag & CSIZE) != CS8) {
815 termios->c_cflag &= ~CSIZE;
816 termios->c_cflag |= old_csize;
817 old_csize = CS8;
818 }
819
820 if ((termios->c_cflag & CSIZE) == CS8)
821 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
822 else
823 ucr2 = UCR2_SRST | UCR2_IRTS;
824
825 if (termios->c_cflag & CRTSCTS) {
826 if( sport->have_rtscts ) {
827 ucr2 &= ~UCR2_IRTS;
828 ucr2 |= UCR2_CTSC;
829 } else {
830 termios->c_cflag &= ~CRTSCTS;
831 }
832 }
833
834 if (termios->c_cflag & CSTOPB)
835 ucr2 |= UCR2_STPB;
836 if (termios->c_cflag & PARENB) {
837 ucr2 |= UCR2_PREN;
838 if (termios->c_cflag & PARODD)
839 ucr2 |= UCR2_PROE;
840 }
841
842 /*
843 * Ask the core to calculate the divisor for us.
844 */
845 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
846 quot = uart_get_divisor(port, baud);
847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
850 sport->port.read_status_mask = 0;
851 if (termios->c_iflag & INPCK)
852 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
853 if (termios->c_iflag & (BRKINT | PARMRK))
854 sport->port.read_status_mask |= URXD_BRK;
855
856 /*
857 * Characters to ignore
858 */
859 sport->port.ignore_status_mask = 0;
860 if (termios->c_iflag & IGNPAR)
861 sport->port.ignore_status_mask |= URXD_PRERR;
862 if (termios->c_iflag & IGNBRK) {
863 sport->port.ignore_status_mask |= URXD_BRK;
864 /*
865 * If we're ignoring parity and break indicators,
866 * ignore overruns too (for real raw support).
867 */
868 if (termios->c_iflag & IGNPAR)
869 sport->port.ignore_status_mask |= URXD_OVRRUN;
870 }
871
872 del_timer_sync(&sport->timer);
873
874 /*
875 * Update the per-port timeout.
876 */
877 uart_update_timeout(port, termios->c_cflag, baud);
878
879 /*
880 * disable interrupts and drain transmitter
881 */
882 old_ucr1 = readl(sport->port.membase + UCR1);
883 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
884 sport->port.membase + UCR1);
885
886 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
887 barrier();
888
889 /* then, disable everything */
890 old_txrxen = readl(sport->port.membase + UCR2);
891 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
892 sport->port.membase + UCR2);
893 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
894
895 if (USE_IRDA(sport)) {
896 /*
897 * use maximum available submodule frequency to
898 * avoid missing short pulses due to low sampling rate
899 */
900 div = 1;
901 } else {
902 div = sport->port.uartclk / (baud * 16);
903 if (div > 7)
904 div = 7;
905 if (!div)
906 div = 1;
907 }
908
909 rational_best_approximation(16 * div * baud, sport->port.uartclk,
910 1 << 16, 1 << 16, &num, &denom);
911
912 tdiv64 = sport->port.uartclk;
913 tdiv64 *= num;
914 do_div(tdiv64, denom * 16 * div);
915 tty_termios_encode_baud_rate(termios,
916 (speed_t)tdiv64, (speed_t)tdiv64);
917
918 num -= 1;
919 denom -= 1;
920
921 ufcr = readl(sport->port.membase + UFCR);
922 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
923 writel(ufcr, sport->port.membase + UFCR);
924
925 writel(num, sport->port.membase + UBIR);
926 writel(denom, sport->port.membase + UBMR);
927
928 if (!cpu_is_mx1())
929 writel(sport->port.uartclk / div / 1000,
930 sport->port.membase + MX2_ONEMS);
931
932 writel(old_ucr1, sport->port.membase + UCR1);
933
934 /* set the parity, stop bits and data size */
935 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
936
937 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
938 imx_enable_ms(&sport->port);
939
940 spin_unlock_irqrestore(&sport->port.lock, flags);
941 }
942
943 static const char *imx_type(struct uart_port *port)
944 {
945 struct imx_port *sport = (struct imx_port *)port;
946
947 return sport->port.type == PORT_IMX ? "IMX" : NULL;
948 }
949
950 /*
951 * Release the memory region(s) being used by 'port'.
952 */
953 static void imx_release_port(struct uart_port *port)
954 {
955 struct platform_device *pdev = to_platform_device(port->dev);
956 struct resource *mmres;
957
958 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
959 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
960 }
961
962 /*
963 * Request the memory region(s) being used by 'port'.
964 */
965 static int imx_request_port(struct uart_port *port)
966 {
967 struct platform_device *pdev = to_platform_device(port->dev);
968 struct resource *mmres;
969 void *ret;
970
971 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
972 if (!mmres)
973 return -ENODEV;
974
975 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
976 "imx-uart");
977
978 return ret ? 0 : -EBUSY;
979 }
980
981 /*
982 * Configure/autoconfigure the port.
983 */
984 static void imx_config_port(struct uart_port *port, int flags)
985 {
986 struct imx_port *sport = (struct imx_port *)port;
987
988 if (flags & UART_CONFIG_TYPE &&
989 imx_request_port(&sport->port) == 0)
990 sport->port.type = PORT_IMX;
991 }
992
993 /*
994 * Verify the new serial_struct (for TIOCSSERIAL).
995 * The only change we allow are to the flags and type, and
996 * even then only between PORT_IMX and PORT_UNKNOWN
997 */
998 static int
999 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1000 {
1001 struct imx_port *sport = (struct imx_port *)port;
1002 int ret = 0;
1003
1004 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1005 ret = -EINVAL;
1006 if (sport->port.irq != ser->irq)
1007 ret = -EINVAL;
1008 if (ser->io_type != UPIO_MEM)
1009 ret = -EINVAL;
1010 if (sport->port.uartclk / 16 != ser->baud_base)
1011 ret = -EINVAL;
1012 if ((void *)sport->port.mapbase != ser->iomem_base)
1013 ret = -EINVAL;
1014 if (sport->port.iobase != ser->port)
1015 ret = -EINVAL;
1016 if (ser->hub6 != 0)
1017 ret = -EINVAL;
1018 return ret;
1019 }
1020
1021 static struct uart_ops imx_pops = {
1022 .tx_empty = imx_tx_empty,
1023 .set_mctrl = imx_set_mctrl,
1024 .get_mctrl = imx_get_mctrl,
1025 .stop_tx = imx_stop_tx,
1026 .start_tx = imx_start_tx,
1027 .stop_rx = imx_stop_rx,
1028 .enable_ms = imx_enable_ms,
1029 .break_ctl = imx_break_ctl,
1030 .startup = imx_startup,
1031 .shutdown = imx_shutdown,
1032 .set_termios = imx_set_termios,
1033 .type = imx_type,
1034 .release_port = imx_release_port,
1035 .request_port = imx_request_port,
1036 .config_port = imx_config_port,
1037 .verify_port = imx_verify_port,
1038 };
1039
1040 static struct imx_port *imx_ports[UART_NR];
1041
1042 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1043 static void imx_console_putchar(struct uart_port *port, int ch)
1044 {
1045 struct imx_port *sport = (struct imx_port *)port;
1046
1047 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1048 barrier();
1049
1050 writel(ch, sport->port.membase + URTX0);
1051 }
1052
1053 /*
1054 * Interrupts are disabled on entering
1055 */
1056 static void
1057 imx_console_write(struct console *co, const char *s, unsigned int count)
1058 {
1059 struct imx_port *sport = imx_ports[co->index];
1060 unsigned int old_ucr1, old_ucr2, ucr1;
1061
1062 /*
1063 * First, save UCR1/2 and then disable interrupts
1064 */
1065 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1066 old_ucr2 = readl(sport->port.membase + UCR2);
1067
1068 if (cpu_is_mx1())
1069 ucr1 |= MX1_UCR1_UARTCLKEN;
1070 ucr1 |= UCR1_UARTEN;
1071 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1072
1073 writel(ucr1, sport->port.membase + UCR1);
1074
1075 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1076
1077 uart_console_write(&sport->port, s, count, imx_console_putchar);
1078
1079 /*
1080 * Finally, wait for transmitter to become empty
1081 * and restore UCR1/2
1082 */
1083 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1084
1085 writel(old_ucr1, sport->port.membase + UCR1);
1086 writel(old_ucr2, sport->port.membase + UCR2);
1087 }
1088
1089 /*
1090 * If the port was already initialised (eg, by a boot loader),
1091 * try to determine the current setup.
1092 */
1093 static void __init
1094 imx_console_get_options(struct imx_port *sport, int *baud,
1095 int *parity, int *bits)
1096 {
1097
1098 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1099 /* ok, the port was enabled */
1100 unsigned int ucr2, ubir,ubmr, uartclk;
1101 unsigned int baud_raw;
1102 unsigned int ucfr_rfdiv;
1103
1104 ucr2 = readl(sport->port.membase + UCR2);
1105
1106 *parity = 'n';
1107 if (ucr2 & UCR2_PREN) {
1108 if (ucr2 & UCR2_PROE)
1109 *parity = 'o';
1110 else
1111 *parity = 'e';
1112 }
1113
1114 if (ucr2 & UCR2_WS)
1115 *bits = 8;
1116 else
1117 *bits = 7;
1118
1119 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1120 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1121
1122 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1123 if (ucfr_rfdiv == 6)
1124 ucfr_rfdiv = 7;
1125 else
1126 ucfr_rfdiv = 6 - ucfr_rfdiv;
1127
1128 uartclk = clk_get_rate(sport->clk);
1129 uartclk /= ucfr_rfdiv;
1130
1131 { /*
1132 * The next code provides exact computation of
1133 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1134 * without need of float support or long long division,
1135 * which would be required to prevent 32bit arithmetic overflow
1136 */
1137 unsigned int mul = ubir + 1;
1138 unsigned int div = 16 * (ubmr + 1);
1139 unsigned int rem = uartclk % div;
1140
1141 baud_raw = (uartclk / div) * mul;
1142 baud_raw += (rem * mul + div / 2) / div;
1143 *baud = (baud_raw + 50) / 100 * 100;
1144 }
1145
1146 if(*baud != baud_raw)
1147 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1148 baud_raw, *baud);
1149 }
1150 }
1151
1152 static int __init
1153 imx_console_setup(struct console *co, char *options)
1154 {
1155 struct imx_port *sport;
1156 int baud = 9600;
1157 int bits = 8;
1158 int parity = 'n';
1159 int flow = 'n';
1160
1161 /*
1162 * Check whether an invalid uart number has been specified, and
1163 * if so, search for the first available port that does have
1164 * console support.
1165 */
1166 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1167 co->index = 0;
1168 sport = imx_ports[co->index];
1169 if(sport == NULL)
1170 return -ENODEV;
1171
1172 if (options)
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1174 else
1175 imx_console_get_options(sport, &baud, &parity, &bits);
1176
1177 imx_setup_ufcr(sport, 0);
1178
1179 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1180 }
1181
1182 static struct uart_driver imx_reg;
1183 static struct console imx_console = {
1184 .name = DEV_NAME,
1185 .write = imx_console_write,
1186 .device = uart_console_device,
1187 .setup = imx_console_setup,
1188 .flags = CON_PRINTBUFFER,
1189 .index = -1,
1190 .data = &imx_reg,
1191 };
1192
1193 #define IMX_CONSOLE &imx_console
1194 #else
1195 #define IMX_CONSOLE NULL
1196 #endif
1197
1198 static struct uart_driver imx_reg = {
1199 .owner = THIS_MODULE,
1200 .driver_name = DRIVER_NAME,
1201 .dev_name = DEV_NAME,
1202 .major = SERIAL_IMX_MAJOR,
1203 .minor = MINOR_START,
1204 .nr = ARRAY_SIZE(imx_ports),
1205 .cons = IMX_CONSOLE,
1206 };
1207
1208 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1209 {
1210 struct imx_port *sport = platform_get_drvdata(dev);
1211
1212 if (sport)
1213 uart_suspend_port(&imx_reg, &sport->port);
1214
1215 return 0;
1216 }
1217
1218 static int serial_imx_resume(struct platform_device *dev)
1219 {
1220 struct imx_port *sport = platform_get_drvdata(dev);
1221
1222 if (sport)
1223 uart_resume_port(&imx_reg, &sport->port);
1224
1225 return 0;
1226 }
1227
1228 static int serial_imx_probe(struct platform_device *pdev)
1229 {
1230 struct imx_port *sport;
1231 struct imxuart_platform_data *pdata;
1232 void __iomem *base;
1233 int ret = 0;
1234 struct resource *res;
1235
1236 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1237 if (!sport)
1238 return -ENOMEM;
1239
1240 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1241 if (!res) {
1242 ret = -ENODEV;
1243 goto free;
1244 }
1245
1246 base = ioremap(res->start, PAGE_SIZE);
1247 if (!base) {
1248 ret = -ENOMEM;
1249 goto free;
1250 }
1251
1252 sport->port.dev = &pdev->dev;
1253 sport->port.mapbase = res->start;
1254 sport->port.membase = base;
1255 sport->port.type = PORT_IMX,
1256 sport->port.iotype = UPIO_MEM;
1257 sport->port.irq = platform_get_irq(pdev, 0);
1258 sport->rxirq = platform_get_irq(pdev, 0);
1259 sport->txirq = platform_get_irq(pdev, 1);
1260 sport->rtsirq = platform_get_irq(pdev, 2);
1261 sport->port.fifosize = 32;
1262 sport->port.ops = &imx_pops;
1263 sport->port.flags = UPF_BOOT_AUTOCONF;
1264 sport->port.line = pdev->id;
1265 init_timer(&sport->timer);
1266 sport->timer.function = imx_timeout;
1267 sport->timer.data = (unsigned long)sport;
1268
1269 sport->clk = clk_get(&pdev->dev, "uart");
1270 if (IS_ERR(sport->clk)) {
1271 ret = PTR_ERR(sport->clk);
1272 goto unmap;
1273 }
1274 clk_enable(sport->clk);
1275
1276 sport->port.uartclk = clk_get_rate(sport->clk);
1277
1278 imx_ports[pdev->id] = sport;
1279
1280 pdata = pdev->dev.platform_data;
1281 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1282 sport->have_rtscts = 1;
1283
1284 #ifdef CONFIG_IRDA
1285 if (pdata && (pdata->flags & IMXUART_IRDA))
1286 sport->use_irda = 1;
1287 #endif
1288
1289 if (pdata && pdata->init) {
1290 ret = pdata->init(pdev);
1291 if (ret)
1292 goto clkput;
1293 }
1294
1295 ret = uart_add_one_port(&imx_reg, &sport->port);
1296 if (ret)
1297 goto deinit;
1298 platform_set_drvdata(pdev, &sport->port);
1299
1300 return 0;
1301 deinit:
1302 if (pdata && pdata->exit)
1303 pdata->exit(pdev);
1304 clkput:
1305 clk_put(sport->clk);
1306 clk_disable(sport->clk);
1307 unmap:
1308 iounmap(sport->port.membase);
1309 free:
1310 kfree(sport);
1311
1312 return ret;
1313 }
1314
1315 static int serial_imx_remove(struct platform_device *pdev)
1316 {
1317 struct imxuart_platform_data *pdata;
1318 struct imx_port *sport = platform_get_drvdata(pdev);
1319
1320 pdata = pdev->dev.platform_data;
1321
1322 platform_set_drvdata(pdev, NULL);
1323
1324 if (sport) {
1325 uart_remove_one_port(&imx_reg, &sport->port);
1326 clk_put(sport->clk);
1327 }
1328
1329 clk_disable(sport->clk);
1330
1331 if (pdata && pdata->exit)
1332 pdata->exit(pdev);
1333
1334 iounmap(sport->port.membase);
1335 kfree(sport);
1336
1337 return 0;
1338 }
1339
1340 static struct platform_driver serial_imx_driver = {
1341 .probe = serial_imx_probe,
1342 .remove = serial_imx_remove,
1343
1344 .suspend = serial_imx_suspend,
1345 .resume = serial_imx_resume,
1346 .driver = {
1347 .name = "imx-uart",
1348 .owner = THIS_MODULE,
1349 },
1350 };
1351
1352 static int __init imx_serial_init(void)
1353 {
1354 int ret;
1355
1356 printk(KERN_INFO "Serial: IMX driver\n");
1357
1358 ret = uart_register_driver(&imx_reg);
1359 if (ret)
1360 return ret;
1361
1362 ret = platform_driver_register(&serial_imx_driver);
1363 if (ret != 0)
1364 uart_unregister_driver(&imx_reg);
1365
1366 return 0;
1367 }
1368
1369 static void __exit imx_serial_exit(void)
1370 {
1371 platform_driver_unregister(&serial_imx_driver);
1372 uart_unregister_driver(&imx_reg);
1373 }
1374
1375 module_init(imx_serial_init);
1376 module_exit(imx_serial_exit);
1377
1378 MODULE_AUTHOR("Sascha Hauer");
1379 MODULE_DESCRIPTION("IMX generic serial port driver");
1380 MODULE_LICENSE("GPL");
1381 MODULE_ALIAS("platform:imx-uart");
kernel source for telekom puls (alcatel/mediatek)