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TTY: switch tty_insert_flip_char
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / crisv10.c
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/string.h>
22 #include <linux/fcntl.h>
23 #include <linux/mm.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/mutex.h>
28 #include <linux/bitops.h>
29 #include <linux/seq_file.h>
30 #include <linux/delay.h>
31 #include <linux/module.h>
32 #include <linux/uaccess.h>
33 #include <linux/io.h>
34
35 #include <asm/irq.h>
36 #include <asm/dma.h>
37
38 #include <arch/svinto.h>
39 #include <arch/system.h>
40
41 /* non-arch dependent serial structures are in linux/serial.h */
42 #include <linux/serial.h>
43 /* while we keep our own stuff (struct e100_serial) in a local .h file */
44 #include "crisv10.h"
45 #include <asm/fasttimer.h>
46 #include <arch/io_interface_mux.h>
47
48 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49 #ifndef CONFIG_ETRAX_FAST_TIMER
50 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51 #endif
52 #endif
53
54 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57 #endif
58
59 #if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
60 #error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
61 #endif
62
63 /*
64 * All of the compatibilty code so we can compile serial.c against
65 * older kernels is hidden in serial_compat.h
66 */
67 #if defined(LOCAL_HEADERS)
68 #include "serial_compat.h"
69 #endif
70
71 struct tty_driver *serial_driver;
72
73 /* number of characters left in xmit buffer before we ask for more */
74 #define WAKEUP_CHARS 256
75
76 //#define SERIAL_DEBUG_INTR
77 //#define SERIAL_DEBUG_OPEN
78 //#define SERIAL_DEBUG_FLOW
79 //#define SERIAL_DEBUG_DATA
80 //#define SERIAL_DEBUG_THROTTLE
81 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
82 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
83
84 /* Enable this to use serial interrupts to handle when you
85 expect the first received event on the serial port to
86 be an error, break or similar. Used to be able to flash IRMA
87 from eLinux */
88 #define SERIAL_HANDLE_EARLY_ERRORS
89
90 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
91 #define SERIAL_DESCR_BUF_SIZE 256
92
93 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
94 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
95
96 /* We don't want to load the system with massive fast timer interrupt
97 * on high baudrates so limit it to 250 us (4kHz) */
98 #define MIN_FLUSH_TIME_USEC 250
99
100 /* Add an x here to log a lot of timer stuff */
101 #define TIMERD(x)
102 /* Debug details of interrupt handling */
103 #define DINTR1(x) /* irq on/off, errors */
104 #define DINTR2(x) /* tx and rx */
105 /* Debug flip buffer stuff */
106 #define DFLIP(x)
107 /* Debug flow control and overview of data flow */
108 #define DFLOW(x)
109 #define DBAUD(x)
110 #define DLOG_INT_TRIG(x)
111
112 //#define DEBUG_LOG_INCLUDED
113 #ifndef DEBUG_LOG_INCLUDED
114 #define DEBUG_LOG(line, string, value)
115 #else
116 struct debug_log_info
117 {
118 unsigned long time;
119 unsigned long timer_data;
120 // int line;
121 const char *string;
122 int value;
123 };
124 #define DEBUG_LOG_SIZE 4096
125
126 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
127 int debug_log_pos = 0;
128
129 #define DEBUG_LOG(_line, _string, _value) do { \
130 if ((_line) == SERIAL_DEBUG_LINE) {\
131 debug_log_func(_line, _string, _value); \
132 }\
133 }while(0)
134
135 void debug_log_func(int line, const char *string, int value)
136 {
137 if (debug_log_pos < DEBUG_LOG_SIZE) {
138 debug_log[debug_log_pos].time = jiffies;
139 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
140 // debug_log[debug_log_pos].line = line;
141 debug_log[debug_log_pos].string = string;
142 debug_log[debug_log_pos].value = value;
143 debug_log_pos++;
144 }
145 /*printk(string, value);*/
146 }
147 #endif
148
149 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
150 /* Default number of timer ticks before flushing rx fifo
151 * When using "little data, low latency applications: use 0
152 * When using "much data applications (PPP)" use ~5
153 */
154 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
155 #endif
156
157 unsigned long timer_data_to_ns(unsigned long timer_data);
158
159 static void change_speed(struct e100_serial *info);
160 static void rs_throttle(struct tty_struct * tty);
161 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
162 static int rs_write(struct tty_struct *tty,
163 const unsigned char *buf, int count);
164 #ifdef CONFIG_ETRAX_RS485
165 static int e100_write_rs485(struct tty_struct *tty,
166 const unsigned char *buf, int count);
167 #endif
168 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
169
170
171 #define DEF_BAUD 115200 /* 115.2 kbit/s */
172 #define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
173 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
174 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
175 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
176
177 /* offsets from R_SERIALx_CTRL */
178
179 #define REG_DATA 0
180 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
181 #define REG_TR_DATA 0
182 #define REG_STATUS 1
183 #define REG_TR_CTRL 1
184 #define REG_REC_CTRL 2
185 #define REG_BAUD 3
186 #define REG_XOFF 4 /* this is a 32 bit register */
187
188 /* The bitfields are the same for all serial ports */
189 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
190 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
191 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
192 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
193 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
194
195 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
196
197 /* Values for info->errorcode */
198 #define ERRCODE_SET_BREAK (TTY_BREAK)
199 #define ERRCODE_INSERT 0x100
200 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
201
202 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
203
204 /*
205 * General note regarding the use of IO_* macros in this file:
206 *
207 * We will use the bits defined for DMA channel 6 when using various
208 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
209 * the same for all channels (which of course they are).
210 *
211 * We will also use the bits defined for serial port 0 when writing commands
212 * to the different ports, as these bits too are the same for all ports.
213 */
214
215
216 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
217 static const unsigned long e100_ser_int_mask = 0
218 #ifdef CONFIG_ETRAX_SERIAL_PORT0
219 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
220 #endif
221 #ifdef CONFIG_ETRAX_SERIAL_PORT1
222 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
223 #endif
224 #ifdef CONFIG_ETRAX_SERIAL_PORT2
225 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
226 #endif
227 #ifdef CONFIG_ETRAX_SERIAL_PORT3
228 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
229 #endif
230 ;
231 unsigned long r_alt_ser_baudrate_shadow = 0;
232
233 /* this is the data for the four serial ports in the etrax100 */
234 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
235 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
236
237 static struct e100_serial rs_table[] = {
238 { .baud = DEF_BAUD,
239 .ioport = (unsigned char *)R_SERIAL0_CTRL,
240 .irq = 1U << 12, /* uses DMA 6 and 7 */
241 .oclrintradr = R_DMA_CH6_CLR_INTR,
242 .ofirstadr = R_DMA_CH6_FIRST,
243 .ocmdadr = R_DMA_CH6_CMD,
244 .ostatusadr = R_DMA_CH6_STATUS,
245 .iclrintradr = R_DMA_CH7_CLR_INTR,
246 .ifirstadr = R_DMA_CH7_FIRST,
247 .icmdadr = R_DMA_CH7_CMD,
248 .idescradr = R_DMA_CH7_DESCR,
249 .flags = STD_FLAGS,
250 .rx_ctrl = DEF_RX,
251 .tx_ctrl = DEF_TX,
252 .iseteop = 2,
253 .dma_owner = dma_ser0,
254 .io_if = if_serial_0,
255 #ifdef CONFIG_ETRAX_SERIAL_PORT0
256 .enabled = 1,
257 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
258 .dma_out_enabled = 1,
259 .dma_out_nbr = SER0_TX_DMA_NBR,
260 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
261 .dma_out_irq_flags = 0,
262 .dma_out_irq_description = "serial 0 dma tr",
263 #else
264 .dma_out_enabled = 0,
265 .dma_out_nbr = UINT_MAX,
266 .dma_out_irq_nbr = 0,
267 .dma_out_irq_flags = 0,
268 .dma_out_irq_description = NULL,
269 #endif
270 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
271 .dma_in_enabled = 1,
272 .dma_in_nbr = SER0_RX_DMA_NBR,
273 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
274 .dma_in_irq_flags = 0,
275 .dma_in_irq_description = "serial 0 dma rec",
276 #else
277 .dma_in_enabled = 0,
278 .dma_in_nbr = UINT_MAX,
279 .dma_in_irq_nbr = 0,
280 .dma_in_irq_flags = 0,
281 .dma_in_irq_description = NULL,
282 #endif
283 #else
284 .enabled = 0,
285 .io_if_description = NULL,
286 .dma_out_enabled = 0,
287 .dma_in_enabled = 0
288 #endif
289
290 }, /* ttyS0 */
291 #ifndef CONFIG_SVINTO_SIM
292 { .baud = DEF_BAUD,
293 .ioport = (unsigned char *)R_SERIAL1_CTRL,
294 .irq = 1U << 16, /* uses DMA 8 and 9 */
295 .oclrintradr = R_DMA_CH8_CLR_INTR,
296 .ofirstadr = R_DMA_CH8_FIRST,
297 .ocmdadr = R_DMA_CH8_CMD,
298 .ostatusadr = R_DMA_CH8_STATUS,
299 .iclrintradr = R_DMA_CH9_CLR_INTR,
300 .ifirstadr = R_DMA_CH9_FIRST,
301 .icmdadr = R_DMA_CH9_CMD,
302 .idescradr = R_DMA_CH9_DESCR,
303 .flags = STD_FLAGS,
304 .rx_ctrl = DEF_RX,
305 .tx_ctrl = DEF_TX,
306 .iseteop = 3,
307 .dma_owner = dma_ser1,
308 .io_if = if_serial_1,
309 #ifdef CONFIG_ETRAX_SERIAL_PORT1
310 .enabled = 1,
311 .io_if_description = "ser1",
312 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
313 .dma_out_enabled = 1,
314 .dma_out_nbr = SER1_TX_DMA_NBR,
315 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
316 .dma_out_irq_flags = 0,
317 .dma_out_irq_description = "serial 1 dma tr",
318 #else
319 .dma_out_enabled = 0,
320 .dma_out_nbr = UINT_MAX,
321 .dma_out_irq_nbr = 0,
322 .dma_out_irq_flags = 0,
323 .dma_out_irq_description = NULL,
324 #endif
325 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
326 .dma_in_enabled = 1,
327 .dma_in_nbr = SER1_RX_DMA_NBR,
328 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
329 .dma_in_irq_flags = 0,
330 .dma_in_irq_description = "serial 1 dma rec",
331 #else
332 .dma_in_enabled = 0,
333 .dma_in_enabled = 0,
334 .dma_in_nbr = UINT_MAX,
335 .dma_in_irq_nbr = 0,
336 .dma_in_irq_flags = 0,
337 .dma_in_irq_description = NULL,
338 #endif
339 #else
340 .enabled = 0,
341 .io_if_description = NULL,
342 .dma_in_irq_nbr = 0,
343 .dma_out_enabled = 0,
344 .dma_in_enabled = 0
345 #endif
346 }, /* ttyS1 */
347
348 { .baud = DEF_BAUD,
349 .ioport = (unsigned char *)R_SERIAL2_CTRL,
350 .irq = 1U << 4, /* uses DMA 2 and 3 */
351 .oclrintradr = R_DMA_CH2_CLR_INTR,
352 .ofirstadr = R_DMA_CH2_FIRST,
353 .ocmdadr = R_DMA_CH2_CMD,
354 .ostatusadr = R_DMA_CH2_STATUS,
355 .iclrintradr = R_DMA_CH3_CLR_INTR,
356 .ifirstadr = R_DMA_CH3_FIRST,
357 .icmdadr = R_DMA_CH3_CMD,
358 .idescradr = R_DMA_CH3_DESCR,
359 .flags = STD_FLAGS,
360 .rx_ctrl = DEF_RX,
361 .tx_ctrl = DEF_TX,
362 .iseteop = 0,
363 .dma_owner = dma_ser2,
364 .io_if = if_serial_2,
365 #ifdef CONFIG_ETRAX_SERIAL_PORT2
366 .enabled = 1,
367 .io_if_description = "ser2",
368 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
369 .dma_out_enabled = 1,
370 .dma_out_nbr = SER2_TX_DMA_NBR,
371 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
372 .dma_out_irq_flags = 0,
373 .dma_out_irq_description = "serial 2 dma tr",
374 #else
375 .dma_out_enabled = 0,
376 .dma_out_nbr = UINT_MAX,
377 .dma_out_irq_nbr = 0,
378 .dma_out_irq_flags = 0,
379 .dma_out_irq_description = NULL,
380 #endif
381 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
382 .dma_in_enabled = 1,
383 .dma_in_nbr = SER2_RX_DMA_NBR,
384 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
385 .dma_in_irq_flags = 0,
386 .dma_in_irq_description = "serial 2 dma rec",
387 #else
388 .dma_in_enabled = 0,
389 .dma_in_nbr = UINT_MAX,
390 .dma_in_irq_nbr = 0,
391 .dma_in_irq_flags = 0,
392 .dma_in_irq_description = NULL,
393 #endif
394 #else
395 .enabled = 0,
396 .io_if_description = NULL,
397 .dma_out_enabled = 0,
398 .dma_in_enabled = 0
399 #endif
400 }, /* ttyS2 */
401
402 { .baud = DEF_BAUD,
403 .ioport = (unsigned char *)R_SERIAL3_CTRL,
404 .irq = 1U << 8, /* uses DMA 4 and 5 */
405 .oclrintradr = R_DMA_CH4_CLR_INTR,
406 .ofirstadr = R_DMA_CH4_FIRST,
407 .ocmdadr = R_DMA_CH4_CMD,
408 .ostatusadr = R_DMA_CH4_STATUS,
409 .iclrintradr = R_DMA_CH5_CLR_INTR,
410 .ifirstadr = R_DMA_CH5_FIRST,
411 .icmdadr = R_DMA_CH5_CMD,
412 .idescradr = R_DMA_CH5_DESCR,
413 .flags = STD_FLAGS,
414 .rx_ctrl = DEF_RX,
415 .tx_ctrl = DEF_TX,
416 .iseteop = 1,
417 .dma_owner = dma_ser3,
418 .io_if = if_serial_3,
419 #ifdef CONFIG_ETRAX_SERIAL_PORT3
420 .enabled = 1,
421 .io_if_description = "ser3",
422 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
423 .dma_out_enabled = 1,
424 .dma_out_nbr = SER3_TX_DMA_NBR,
425 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
426 .dma_out_irq_flags = 0,
427 .dma_out_irq_description = "serial 3 dma tr",
428 #else
429 .dma_out_enabled = 0,
430 .dma_out_nbr = UINT_MAX,
431 .dma_out_irq_nbr = 0,
432 .dma_out_irq_flags = 0,
433 .dma_out_irq_description = NULL,
434 #endif
435 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
436 .dma_in_enabled = 1,
437 .dma_in_nbr = SER3_RX_DMA_NBR,
438 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
439 .dma_in_irq_flags = 0,
440 .dma_in_irq_description = "serial 3 dma rec",
441 #else
442 .dma_in_enabled = 0,
443 .dma_in_nbr = UINT_MAX,
444 .dma_in_irq_nbr = 0,
445 .dma_in_irq_flags = 0,
446 .dma_in_irq_description = NULL
447 #endif
448 #else
449 .enabled = 0,
450 .io_if_description = NULL,
451 .dma_out_enabled = 0,
452 .dma_in_enabled = 0
453 #endif
454 } /* ttyS3 */
455 #endif
456 };
457
458
459 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
460
461 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
462 static struct fast_timer fast_timers[NR_PORTS];
463 #endif
464
465 #ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
466 #define PROCSTAT(x) x
467 struct ser_statistics_type {
468 int overrun_cnt;
469 int early_errors_cnt;
470 int ser_ints_ok_cnt;
471 int errors_cnt;
472 unsigned long int processing_flip;
473 unsigned long processing_flip_still_room;
474 unsigned long int timeout_flush_cnt;
475 int rx_dma_ints;
476 int tx_dma_ints;
477 int rx_tot;
478 int tx_tot;
479 };
480
481 static struct ser_statistics_type ser_stat[NR_PORTS];
482
483 #else
484
485 #define PROCSTAT(x)
486
487 #endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
488
489 /* RS-485 */
490 #if defined(CONFIG_ETRAX_RS485)
491 #ifdef CONFIG_ETRAX_FAST_TIMER
492 static struct fast_timer fast_timers_rs485[NR_PORTS];
493 #endif
494 #if defined(CONFIG_ETRAX_RS485_ON_PA)
495 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
496 #endif
497 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
498 static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
499 #endif
500 #endif
501
502 /* Info and macros needed for each ports extra control/status signals. */
503 #define E100_STRUCT_PORT(line, pinname) \
504 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
505 (R_PORT_PA_DATA): ( \
506 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
507 (R_PORT_PB_DATA):&dummy_ser[line]))
508
509 #define E100_STRUCT_SHADOW(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (&port_pa_data_shadow): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (&port_pb_data_shadow):&dummy_ser[line]))
514 #define E100_STRUCT_MASK(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
519
520 #define DUMMY_DTR_MASK 1
521 #define DUMMY_RI_MASK 2
522 #define DUMMY_DSR_MASK 4
523 #define DUMMY_CD_MASK 8
524 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
525
526 /* If not all status pins are used or disabled, use mixed mode */
527 #ifdef CONFIG_ETRAX_SERIAL_PORT0
528
529 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
530
531 #if SER0_PA_BITSUM != -4
532 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
533 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535 # endif
536 # endif
537 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
538 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540 # endif
541 # endif
542 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
543 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545 # endif
546 # endif
547 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
548 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550 # endif
551 # endif
552 #endif
553
554 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
555
556 #if SER0_PB_BITSUM != -4
557 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
558 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560 # endif
561 # endif
562 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
563 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565 # endif
566 # endif
567 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
568 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570 # endif
571 # endif
572 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
573 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575 # endif
576 # endif
577 #endif
578
579 #endif /* PORT0 */
580
581
582 #ifdef CONFIG_ETRAX_SERIAL_PORT1
583
584 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
585
586 #if SER1_PA_BITSUM != -4
587 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
588 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590 # endif
591 # endif
592 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
593 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595 # endif
596 # endif
597 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
598 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600 # endif
601 # endif
602 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
603 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605 # endif
606 # endif
607 #endif
608
609 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
610
611 #if SER1_PB_BITSUM != -4
612 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
613 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615 # endif
616 # endif
617 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
618 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620 # endif
621 # endif
622 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
623 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625 # endif
626 # endif
627 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
628 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630 # endif
631 # endif
632 #endif
633
634 #endif /* PORT1 */
635
636 #ifdef CONFIG_ETRAX_SERIAL_PORT2
637
638 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
639
640 #if SER2_PA_BITSUM != -4
641 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
642 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644 # endif
645 # endif
646 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
647 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649 # endif
650 # endif
651 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
652 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654 # endif
655 # endif
656 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
657 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659 # endif
660 # endif
661 #endif
662
663 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
664
665 #if SER2_PB_BITSUM != -4
666 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
667 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669 # endif
670 # endif
671 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
672 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674 # endif
675 # endif
676 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
677 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679 # endif
680 # endif
681 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
682 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684 # endif
685 # endif
686 #endif
687
688 #endif /* PORT2 */
689
690 #ifdef CONFIG_ETRAX_SERIAL_PORT3
691
692 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
693
694 #if SER3_PA_BITSUM != -4
695 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
696 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698 # endif
699 # endif
700 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
701 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703 # endif
704 # endif
705 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
706 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708 # endif
709 # endif
710 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
711 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713 # endif
714 # endif
715 #endif
716
717 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
718
719 #if SER3_PB_BITSUM != -4
720 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
721 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723 # endif
724 # endif
725 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
726 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728 # endif
729 # endif
730 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
731 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733 # endif
734 # endif
735 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
736 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738 # endif
739 # endif
740 #endif
741
742 #endif /* PORT3 */
743
744
745 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
746 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
749 #define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
750 #endif
751
752 #ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
753 /* The pins can be mixed on PA and PB */
754 #define CONTROL_PINS_PORT_NOT_USED(line) \
755 &dummy_ser[line], &dummy_ser[line], \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
760
761
762 struct control_pins
763 {
764 volatile unsigned char *dtr_port;
765 unsigned char *dtr_shadow;
766 volatile unsigned char *ri_port;
767 unsigned char *ri_shadow;
768 volatile unsigned char *dsr_port;
769 unsigned char *dsr_shadow;
770 volatile unsigned char *cd_port;
771 unsigned char *cd_shadow;
772
773 unsigned char dtr_mask;
774 unsigned char ri_mask;
775 unsigned char dsr_mask;
776 unsigned char cd_mask;
777 };
778
779 static const struct control_pins e100_modem_pins[NR_PORTS] =
780 {
781 /* Ser 0 */
782 {
783 #ifdef CONFIG_ETRAX_SERIAL_PORT0
784 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
785 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
786 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
787 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
788 E100_STRUCT_MASK(0,DTR),
789 E100_STRUCT_MASK(0,RI),
790 E100_STRUCT_MASK(0,DSR),
791 E100_STRUCT_MASK(0,CD)
792 #else
793 CONTROL_PINS_PORT_NOT_USED(0)
794 #endif
795 },
796
797 /* Ser 1 */
798 {
799 #ifdef CONFIG_ETRAX_SERIAL_PORT1
800 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
801 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
802 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
803 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
804 E100_STRUCT_MASK(1,DTR),
805 E100_STRUCT_MASK(1,RI),
806 E100_STRUCT_MASK(1,DSR),
807 E100_STRUCT_MASK(1,CD)
808 #else
809 CONTROL_PINS_PORT_NOT_USED(1)
810 #endif
811 },
812
813 /* Ser 2 */
814 {
815 #ifdef CONFIG_ETRAX_SERIAL_PORT2
816 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
817 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
818 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
819 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
820 E100_STRUCT_MASK(2,DTR),
821 E100_STRUCT_MASK(2,RI),
822 E100_STRUCT_MASK(2,DSR),
823 E100_STRUCT_MASK(2,CD)
824 #else
825 CONTROL_PINS_PORT_NOT_USED(2)
826 #endif
827 },
828
829 /* Ser 3 */
830 {
831 #ifdef CONFIG_ETRAX_SERIAL_PORT3
832 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
833 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
834 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
835 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
836 E100_STRUCT_MASK(3,DTR),
837 E100_STRUCT_MASK(3,RI),
838 E100_STRUCT_MASK(3,DSR),
839 E100_STRUCT_MASK(3,CD)
840 #else
841 CONTROL_PINS_PORT_NOT_USED(3)
842 #endif
843 }
844 };
845 #else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
846
847 /* All pins are on either PA or PB for each serial port */
848 #define CONTROL_PINS_PORT_NOT_USED(line) \
849 &dummy_ser[line], &dummy_ser[line], \
850 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
851
852
853 struct control_pins
854 {
855 volatile unsigned char *port;
856 unsigned char *shadow;
857
858 unsigned char dtr_mask;
859 unsigned char ri_mask;
860 unsigned char dsr_mask;
861 unsigned char cd_mask;
862 };
863
864 #define dtr_port port
865 #define dtr_shadow shadow
866 #define ri_port port
867 #define ri_shadow shadow
868 #define dsr_port port
869 #define dsr_shadow shadow
870 #define cd_port port
871 #define cd_shadow shadow
872
873 static const struct control_pins e100_modem_pins[NR_PORTS] =
874 {
875 /* Ser 0 */
876 {
877 #ifdef CONFIG_ETRAX_SERIAL_PORT0
878 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
879 E100_STRUCT_MASK(0,DTR),
880 E100_STRUCT_MASK(0,RI),
881 E100_STRUCT_MASK(0,DSR),
882 E100_STRUCT_MASK(0,CD)
883 #else
884 CONTROL_PINS_PORT_NOT_USED(0)
885 #endif
886 },
887
888 /* Ser 1 */
889 {
890 #ifdef CONFIG_ETRAX_SERIAL_PORT1
891 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
892 E100_STRUCT_MASK(1,DTR),
893 E100_STRUCT_MASK(1,RI),
894 E100_STRUCT_MASK(1,DSR),
895 E100_STRUCT_MASK(1,CD)
896 #else
897 CONTROL_PINS_PORT_NOT_USED(1)
898 #endif
899 },
900
901 /* Ser 2 */
902 {
903 #ifdef CONFIG_ETRAX_SERIAL_PORT2
904 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
905 E100_STRUCT_MASK(2,DTR),
906 E100_STRUCT_MASK(2,RI),
907 E100_STRUCT_MASK(2,DSR),
908 E100_STRUCT_MASK(2,CD)
909 #else
910 CONTROL_PINS_PORT_NOT_USED(2)
911 #endif
912 },
913
914 /* Ser 3 */
915 {
916 #ifdef CONFIG_ETRAX_SERIAL_PORT3
917 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
918 E100_STRUCT_MASK(3,DTR),
919 E100_STRUCT_MASK(3,RI),
920 E100_STRUCT_MASK(3,DSR),
921 E100_STRUCT_MASK(3,CD)
922 #else
923 CONTROL_PINS_PORT_NOT_USED(3)
924 #endif
925 }
926 };
927 #endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
928
929 #define E100_RTS_MASK 0x20
930 #define E100_CTS_MASK 0x40
931
932 /* All serial port signals are active low:
933 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
934 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
935 *
936 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
937 */
938
939 /* Output */
940 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
941 /* Input */
942 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
943
944 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
945 /* Is an output */
946 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
947
948 /* Normally inputs */
949 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
950 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
951
952 /* Input */
953 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
954
955 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
956 static void update_char_time(struct e100_serial * info)
957 {
958 tcflag_t cflags = info->port.tty->termios.c_cflag;
959 int bits;
960
961 /* calc. number of bits / data byte */
962 /* databits + startbit and 1 stopbit */
963 if ((cflags & CSIZE) == CS7)
964 bits = 9;
965 else
966 bits = 10;
967
968 if (cflags & CSTOPB) /* 2 stopbits ? */
969 bits++;
970
971 if (cflags & PARENB) /* parity bit ? */
972 bits++;
973
974 /* calc timeout */
975 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
976 info->flush_time_usec = 4*info->char_time_usec;
977 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
978 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
979
980 }
981
982 /*
983 * This function maps from the Bxxxx defines in asm/termbits.h into real
984 * baud rates.
985 */
986
987 static int
988 cflag_to_baud(unsigned int cflag)
989 {
990 static int baud_table[] = {
991 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
992 4800, 9600, 19200, 38400 };
993
994 static int ext_baud_table[] = {
995 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
996 0, 0, 0, 0, 0, 0, 0, 0 };
997
998 if (cflag & CBAUDEX)
999 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1000 else
1001 return baud_table[cflag & CBAUD];
1002 }
1003
1004 /* and this maps to an etrax100 hardware baud constant */
1005
1006 static unsigned char
1007 cflag_to_etrax_baud(unsigned int cflag)
1008 {
1009 char retval;
1010
1011 static char baud_table[] = {
1012 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1013
1014 static char ext_baud_table[] = {
1015 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1016
1017 if (cflag & CBAUDEX)
1018 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1019 else
1020 retval = baud_table[cflag & CBAUD];
1021
1022 if (retval < 0) {
1023 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1024 retval = 5; /* choose default 9600 instead */
1025 }
1026
1027 return retval | (retval << 4); /* choose same for both TX and RX */
1028 }
1029
1030
1031 /* Various static support functions */
1032
1033 /* Functions to set or clear DTR/RTS on the requested line */
1034 /* It is complicated by the fact that RTS is a serial port register, while
1035 * DTR might not be implemented in the HW at all, and if it is, it can be on
1036 * any general port.
1037 */
1038
1039
1040 static inline void
1041 e100_dtr(struct e100_serial *info, int set)
1042 {
1043 #ifndef CONFIG_SVINTO_SIM
1044 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1045
1046 #ifdef SERIAL_DEBUG_IO
1047 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1048 printk("ser%i shadow before 0x%02X get: %i\n",
1049 info->line, *e100_modem_pins[info->line].dtr_shadow,
1050 E100_DTR_GET(info));
1051 #endif
1052 /* DTR is active low */
1053 {
1054 unsigned long flags;
1055
1056 local_irq_save(flags);
1057 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1058 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1059 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1060 local_irq_restore(flags);
1061 }
1062
1063 #ifdef SERIAL_DEBUG_IO
1064 printk("ser%i shadow after 0x%02X get: %i\n",
1065 info->line, *e100_modem_pins[info->line].dtr_shadow,
1066 E100_DTR_GET(info));
1067 #endif
1068 #endif
1069 }
1070
1071 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1072 * 0=0V , 1=3.3V
1073 */
1074 static inline void
1075 e100_rts(struct e100_serial *info, int set)
1076 {
1077 #ifndef CONFIG_SVINTO_SIM
1078 unsigned long flags;
1079 local_irq_save(flags);
1080 info->rx_ctrl &= ~E100_RTS_MASK;
1081 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1082 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1083 local_irq_restore(flags);
1084 #ifdef SERIAL_DEBUG_IO
1085 printk("ser%i rts %i\n", info->line, set);
1086 #endif
1087 #endif
1088 }
1089
1090
1091 /* If this behaves as a modem, RI and CD is an output */
1092 static inline void
1093 e100_ri_out(struct e100_serial *info, int set)
1094 {
1095 #ifndef CONFIG_SVINTO_SIM
1096 /* RI is active low */
1097 {
1098 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1099 unsigned long flags;
1100
1101 local_irq_save(flags);
1102 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1103 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1104 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1105 local_irq_restore(flags);
1106 }
1107 #endif
1108 }
1109 static inline void
1110 e100_cd_out(struct e100_serial *info, int set)
1111 {
1112 #ifndef CONFIG_SVINTO_SIM
1113 /* CD is active low */
1114 {
1115 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1116 unsigned long flags;
1117
1118 local_irq_save(flags);
1119 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1120 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1121 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1122 local_irq_restore(flags);
1123 }
1124 #endif
1125 }
1126
1127 static inline void
1128 e100_disable_rx(struct e100_serial *info)
1129 {
1130 #ifndef CONFIG_SVINTO_SIM
1131 /* disable the receiver */
1132 info->ioport[REG_REC_CTRL] =
1133 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1134 #endif
1135 }
1136
1137 static inline void
1138 e100_enable_rx(struct e100_serial *info)
1139 {
1140 #ifndef CONFIG_SVINTO_SIM
1141 /* enable the receiver */
1142 info->ioport[REG_REC_CTRL] =
1143 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1144 #endif
1145 }
1146
1147 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1148
1149 static inline void
1150 e100_disable_rxdma_irq(struct e100_serial *info)
1151 {
1152 #ifdef SERIAL_DEBUG_INTR
1153 printk("rxdma_irq(%d): 0\n",info->line);
1154 #endif
1155 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1156 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1157 }
1158
1159 static inline void
1160 e100_enable_rxdma_irq(struct e100_serial *info)
1161 {
1162 #ifdef SERIAL_DEBUG_INTR
1163 printk("rxdma_irq(%d): 1\n",info->line);
1164 #endif
1165 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1166 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1167 }
1168
1169 /* the tx DMA uses only dma_descr interrupt */
1170
1171 static void e100_disable_txdma_irq(struct e100_serial *info)
1172 {
1173 #ifdef SERIAL_DEBUG_INTR
1174 printk("txdma_irq(%d): 0\n",info->line);
1175 #endif
1176 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1177 *R_IRQ_MASK2_CLR = info->irq;
1178 }
1179
1180 static void e100_enable_txdma_irq(struct e100_serial *info)
1181 {
1182 #ifdef SERIAL_DEBUG_INTR
1183 printk("txdma_irq(%d): 1\n",info->line);
1184 #endif
1185 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1186 *R_IRQ_MASK2_SET = info->irq;
1187 }
1188
1189 static void e100_disable_txdma_channel(struct e100_serial *info)
1190 {
1191 unsigned long flags;
1192
1193 /* Disable output DMA channel for the serial port in question
1194 * ( set to something other than serialX)
1195 */
1196 local_irq_save(flags);
1197 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1198 if (info->line == 0) {
1199 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1200 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1201 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1202 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1203 }
1204 } else if (info->line == 1) {
1205 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1206 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1207 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1208 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1209 }
1210 } else if (info->line == 2) {
1211 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1212 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1213 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1214 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1215 }
1216 } else if (info->line == 3) {
1217 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1218 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1221 }
1222 }
1223 *R_GEN_CONFIG = genconfig_shadow;
1224 local_irq_restore(flags);
1225 }
1226
1227
1228 static void e100_enable_txdma_channel(struct e100_serial *info)
1229 {
1230 unsigned long flags;
1231
1232 local_irq_save(flags);
1233 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1234 /* Enable output DMA channel for the serial port in question */
1235 if (info->line == 0) {
1236 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1237 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1238 } else if (info->line == 1) {
1239 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1240 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1241 } else if (info->line == 2) {
1242 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1243 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1244 } else if (info->line == 3) {
1245 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1246 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1247 }
1248 *R_GEN_CONFIG = genconfig_shadow;
1249 local_irq_restore(flags);
1250 }
1251
1252 static void e100_disable_rxdma_channel(struct e100_serial *info)
1253 {
1254 unsigned long flags;
1255
1256 /* Disable input DMA channel for the serial port in question
1257 * ( set to something other than serialX)
1258 */
1259 local_irq_save(flags);
1260 if (info->line == 0) {
1261 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1262 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1263 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1264 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1265 }
1266 } else if (info->line == 1) {
1267 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1268 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1269 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1270 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1271 }
1272 } else if (info->line == 2) {
1273 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1274 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1275 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1276 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1277 }
1278 } else if (info->line == 3) {
1279 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1280 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1281 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1282 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1283 }
1284 }
1285 *R_GEN_CONFIG = genconfig_shadow;
1286 local_irq_restore(flags);
1287 }
1288
1289
1290 static void e100_enable_rxdma_channel(struct e100_serial *info)
1291 {
1292 unsigned long flags;
1293
1294 local_irq_save(flags);
1295 /* Enable input DMA channel for the serial port in question */
1296 if (info->line == 0) {
1297 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1298 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1299 } else if (info->line == 1) {
1300 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1301 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1302 } else if (info->line == 2) {
1303 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1304 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1305 } else if (info->line == 3) {
1306 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1307 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1308 }
1309 *R_GEN_CONFIG = genconfig_shadow;
1310 local_irq_restore(flags);
1311 }
1312
1313 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1314 /* in order to detect and fix errors on the first byte
1315 we have to use the serial interrupts as well. */
1316
1317 static inline void
1318 e100_disable_serial_data_irq(struct e100_serial *info)
1319 {
1320 #ifdef SERIAL_DEBUG_INTR
1321 printk("ser_irq(%d): 0\n",info->line);
1322 #endif
1323 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1324 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1325 }
1326
1327 static inline void
1328 e100_enable_serial_data_irq(struct e100_serial *info)
1329 {
1330 #ifdef SERIAL_DEBUG_INTR
1331 printk("ser_irq(%d): 1\n",info->line);
1332 printk("**** %d = %d\n",
1333 (8+2*info->line),
1334 (1U << (8+2*info->line)));
1335 #endif
1336 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1337 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1338 }
1339 #endif
1340
1341 static inline void
1342 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1343 {
1344 #ifdef SERIAL_DEBUG_INTR
1345 printk("ser_tx_irq(%d): 0\n",info->line);
1346 #endif
1347 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1348 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1349 }
1350
1351 static inline void
1352 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1353 {
1354 #ifdef SERIAL_DEBUG_INTR
1355 printk("ser_tx_irq(%d): 1\n",info->line);
1356 printk("**** %d = %d\n",
1357 (8+1+2*info->line),
1358 (1U << (8+1+2*info->line)));
1359 #endif
1360 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1361 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1362 }
1363
1364 static inline void e100_enable_rx_irq(struct e100_serial *info)
1365 {
1366 if (info->uses_dma_in)
1367 e100_enable_rxdma_irq(info);
1368 else
1369 e100_enable_serial_data_irq(info);
1370 }
1371 static inline void e100_disable_rx_irq(struct e100_serial *info)
1372 {
1373 if (info->uses_dma_in)
1374 e100_disable_rxdma_irq(info);
1375 else
1376 e100_disable_serial_data_irq(info);
1377 }
1378
1379 #if defined(CONFIG_ETRAX_RS485)
1380 /* Enable RS-485 mode on selected port. This is UGLY. */
1381 static int
1382 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1383 {
1384 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1385
1386 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1387 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1388 #endif
1389 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1390 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1391 rs485_port_g_bit, 1);
1392 #endif
1393 #if defined(CONFIG_ETRAX_RS485_LTC1387)
1394 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1395 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1396 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1397 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1398 #endif
1399
1400 info->rs485 = *r;
1401
1402 /* Maximum delay before RTS equal to 1000 */
1403 if (info->rs485.delay_rts_before_send >= 1000)
1404 info->rs485.delay_rts_before_send = 1000;
1405
1406 /* printk("rts: on send = %i, after = %i, enabled = %i",
1407 info->rs485.rts_on_send,
1408 info->rs485.rts_after_sent,
1409 info->rs485.enabled
1410 );
1411 */
1412 return 0;
1413 }
1414
1415 static int
1416 e100_write_rs485(struct tty_struct *tty,
1417 const unsigned char *buf, int count)
1418 {
1419 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1420 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1421
1422 /* rs485 is always implicitly enabled if we're using the ioctl()
1423 * but it doesn't have to be set in the serial_rs485
1424 * (to be backward compatible with old apps)
1425 * So we store, set and restore it.
1426 */
1427 info->rs485.flags |= SER_RS485_ENABLED;
1428 /* rs_write now deals with RS485 if enabled */
1429 count = rs_write(tty, buf, count);
1430 if (!old_value)
1431 info->rs485.flags &= ~(SER_RS485_ENABLED);
1432 return count;
1433 }
1434
1435 #ifdef CONFIG_ETRAX_FAST_TIMER
1436 /* Timer function to toggle RTS when using FAST_TIMER */
1437 static void rs485_toggle_rts_timer_function(unsigned long data)
1438 {
1439 struct e100_serial *info = (struct e100_serial *)data;
1440
1441 fast_timers_rs485[info->line].function = NULL;
1442 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1443 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1444 e100_enable_rx(info);
1445 e100_enable_rx_irq(info);
1446 #endif
1447 }
1448 #endif
1449 #endif /* CONFIG_ETRAX_RS485 */
1450
1451 /*
1452 * ------------------------------------------------------------
1453 * rs_stop() and rs_start()
1454 *
1455 * This routines are called before setting or resetting tty->stopped.
1456 * They enable or disable transmitter using the XOFF registers, as necessary.
1457 * ------------------------------------------------------------
1458 */
1459
1460 static void
1461 rs_stop(struct tty_struct *tty)
1462 {
1463 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1464 if (info) {
1465 unsigned long flags;
1466 unsigned long xoff;
1467
1468 local_irq_save(flags);
1469 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1470 CIRC_CNT(info->xmit.head,
1471 info->xmit.tail,SERIAL_XMIT_SIZE)));
1472
1473 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1474 STOP_CHAR(info->port.tty));
1475 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1476 if (tty->termios.c_iflag & IXON ) {
1477 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1478 }
1479
1480 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1481 local_irq_restore(flags);
1482 }
1483 }
1484
1485 static void
1486 rs_start(struct tty_struct *tty)
1487 {
1488 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1489 if (info) {
1490 unsigned long flags;
1491 unsigned long xoff;
1492
1493 local_irq_save(flags);
1494 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1495 CIRC_CNT(info->xmit.head,
1496 info->xmit.tail,SERIAL_XMIT_SIZE)));
1497 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1498 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1499 if (tty->termios.c_iflag & IXON ) {
1500 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1501 }
1502
1503 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1504 if (!info->uses_dma_out &&
1505 info->xmit.head != info->xmit.tail && info->xmit.buf)
1506 e100_enable_serial_tx_ready_irq(info);
1507
1508 local_irq_restore(flags);
1509 }
1510 }
1511
1512 /*
1513 * ----------------------------------------------------------------------
1514 *
1515 * Here starts the interrupt handling routines. All of the following
1516 * subroutines are declared as inline and are folded into
1517 * rs_interrupt(). They were separated out for readability's sake.
1518 *
1519 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1520 * runs with interrupts turned off. People who may want to modify
1521 * rs_interrupt() should try to keep the interrupt handler as fast as
1522 * possible. After you are done making modifications, it is not a bad
1523 * idea to do:
1524 *
1525 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1526 *
1527 * and look at the resulting assemble code in serial.s.
1528 *
1529 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1530 * -----------------------------------------------------------------------
1531 */
1532
1533 /*
1534 * This routine is used by the interrupt handler to schedule
1535 * processing in the software interrupt portion of the driver.
1536 */
1537 static void rs_sched_event(struct e100_serial *info, int event)
1538 {
1539 if (info->event & (1 << event))
1540 return;
1541 info->event |= 1 << event;
1542 schedule_work(&info->work);
1543 }
1544
1545 /* The output DMA channel is free - use it to send as many chars as possible
1546 * NOTES:
1547 * We don't pay attention to info->x_char, which means if the TTY wants to
1548 * use XON/XOFF it will set info->x_char but we won't send any X char!
1549 *
1550 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1551 * buffer containing the X char, and skip updating xmit. We'd also have to
1552 * check if the last sent char was the X char when we enter this function
1553 * the next time, to avoid updating xmit with the sent X value.
1554 */
1555
1556 static void
1557 transmit_chars_dma(struct e100_serial *info)
1558 {
1559 unsigned int c, sentl;
1560 struct etrax_dma_descr *descr;
1561
1562 #ifdef CONFIG_SVINTO_SIM
1563 /* This will output too little if tail is not 0 always since
1564 * we don't reloop to send the other part. Anyway this SHOULD be a
1565 * no-op - transmit_chars_dma would never really be called during sim
1566 * since rs_write does not write into the xmit buffer then.
1567 */
1568 if (info->xmit.tail)
1569 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1570 if (info->xmit.head != info->xmit.tail) {
1571 SIMCOUT(info->xmit.buf + info->xmit.tail,
1572 CIRC_CNT(info->xmit.head,
1573 info->xmit.tail,
1574 SERIAL_XMIT_SIZE));
1575 info->xmit.head = info->xmit.tail; /* move back head */
1576 info->tr_running = 0;
1577 }
1578 return;
1579 #endif
1580 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1581 *info->oclrintradr =
1582 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1583 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1584
1585 #ifdef SERIAL_DEBUG_INTR
1586 if (info->line == SERIAL_DEBUG_LINE)
1587 printk("tc\n");
1588 #endif
1589 if (!info->tr_running) {
1590 /* weirdo... we shouldn't get here! */
1591 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1592 return;
1593 }
1594
1595 descr = &info->tr_descr;
1596
1597 /* first get the amount of bytes sent during the last DMA transfer,
1598 and update xmit accordingly */
1599
1600 /* if the stop bit was not set, all data has been sent */
1601 if (!(descr->status & d_stop)) {
1602 sentl = descr->sw_len;
1603 } else
1604 /* otherwise we find the amount of data sent here */
1605 sentl = descr->hw_len;
1606
1607 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1608
1609 /* update stats */
1610 info->icount.tx += sentl;
1611
1612 /* update xmit buffer */
1613 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1614
1615 /* if there is only a few chars left in the buf, wake up the blocked
1616 write if any */
1617 if (CIRC_CNT(info->xmit.head,
1618 info->xmit.tail,
1619 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1620 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1621
1622 /* find out the largest amount of consecutive bytes we want to send now */
1623
1624 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1625
1626 /* Don't send all in one DMA transfer - divide it so we wake up
1627 * application before all is sent
1628 */
1629
1630 if (c >= 4*WAKEUP_CHARS)
1631 c = c/2;
1632
1633 if (c <= 0) {
1634 /* our job here is done, don't schedule any new DMA transfer */
1635 info->tr_running = 0;
1636
1637 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1638 if (info->rs485.flags & SER_RS485_ENABLED) {
1639 /* Set a short timer to toggle RTS */
1640 start_one_shot_timer(&fast_timers_rs485[info->line],
1641 rs485_toggle_rts_timer_function,
1642 (unsigned long)info,
1643 info->char_time_usec*2,
1644 "RS-485");
1645 }
1646 #endif /* RS485 */
1647 return;
1648 }
1649
1650 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1651 /* set up the descriptor correctly for output */
1652 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1653 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1654 descr->sw_len = c;
1655 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1656 descr->status = 0;
1657
1658 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1659 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1660
1661 /* DMA is now running (hopefully) */
1662 } /* transmit_chars_dma */
1663
1664 static void
1665 start_transmit(struct e100_serial *info)
1666 {
1667 #if 0
1668 if (info->line == SERIAL_DEBUG_LINE)
1669 printk("x\n");
1670 #endif
1671
1672 info->tr_descr.sw_len = 0;
1673 info->tr_descr.hw_len = 0;
1674 info->tr_descr.status = 0;
1675 info->tr_running = 1;
1676 if (info->uses_dma_out)
1677 transmit_chars_dma(info);
1678 else
1679 e100_enable_serial_tx_ready_irq(info);
1680 } /* start_transmit */
1681
1682 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1683 static int serial_fast_timer_started = 0;
1684 static int serial_fast_timer_expired = 0;
1685 static void flush_timeout_function(unsigned long data);
1686 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1687 unsigned long timer_flags; \
1688 local_irq_save(timer_flags); \
1689 if (fast_timers[info->line].function == NULL) { \
1690 serial_fast_timer_started++; \
1691 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1692 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1693 start_one_shot_timer(&fast_timers[info->line], \
1694 flush_timeout_function, \
1695 (unsigned long)info, \
1696 (usec), \
1697 string); \
1698 } \
1699 else { \
1700 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1701 } \
1702 local_irq_restore(timer_flags); \
1703 }
1704 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1705
1706 #else
1707 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1708 #define START_FLUSH_FAST_TIMER(info, string)
1709 #endif
1710
1711 static struct etrax_recv_buffer *
1712 alloc_recv_buffer(unsigned int size)
1713 {
1714 struct etrax_recv_buffer *buffer;
1715
1716 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1717 return NULL;
1718
1719 buffer->next = NULL;
1720 buffer->length = 0;
1721 buffer->error = TTY_NORMAL;
1722
1723 return buffer;
1724 }
1725
1726 static void
1727 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1728 {
1729 unsigned long flags;
1730
1731 local_irq_save(flags);
1732
1733 if (!info->first_recv_buffer)
1734 info->first_recv_buffer = buffer;
1735 else
1736 info->last_recv_buffer->next = buffer;
1737
1738 info->last_recv_buffer = buffer;
1739
1740 info->recv_cnt += buffer->length;
1741 if (info->recv_cnt > info->max_recv_cnt)
1742 info->max_recv_cnt = info->recv_cnt;
1743
1744 local_irq_restore(flags);
1745 }
1746
1747 static int
1748 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1749 {
1750 struct etrax_recv_buffer *buffer;
1751 if (info->uses_dma_in) {
1752 if (!(buffer = alloc_recv_buffer(4)))
1753 return 0;
1754
1755 buffer->length = 1;
1756 buffer->error = flag;
1757 buffer->buffer[0] = data;
1758
1759 append_recv_buffer(info, buffer);
1760
1761 info->icount.rx++;
1762 } else {
1763 tty_insert_flip_char(&info->port, data, flag);
1764 info->icount.rx++;
1765 }
1766
1767 return 1;
1768 }
1769
1770 static unsigned int handle_descr_data(struct e100_serial *info,
1771 struct etrax_dma_descr *descr,
1772 unsigned int recvl)
1773 {
1774 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1775
1776 if (info->recv_cnt + recvl > 65536) {
1777 printk(KERN_WARNING
1778 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1779 return 0;
1780 }
1781
1782 buffer->length = recvl;
1783
1784 if (info->errorcode == ERRCODE_SET_BREAK)
1785 buffer->error = TTY_BREAK;
1786 info->errorcode = 0;
1787
1788 append_recv_buffer(info, buffer);
1789
1790 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1791 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1792
1793 descr->buf = virt_to_phys(buffer->buffer);
1794
1795 return recvl;
1796 }
1797
1798 static unsigned int handle_all_descr_data(struct e100_serial *info)
1799 {
1800 struct etrax_dma_descr *descr;
1801 unsigned int recvl;
1802 unsigned int ret = 0;
1803
1804 while (1)
1805 {
1806 descr = &info->rec_descr[info->cur_rec_descr];
1807
1808 if (descr == phys_to_virt(*info->idescradr))
1809 break;
1810
1811 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1812 info->cur_rec_descr = 0;
1813
1814 /* find out how many bytes were read */
1815
1816 /* if the eop bit was not set, all data has been received */
1817 if (!(descr->status & d_eop)) {
1818 recvl = descr->sw_len;
1819 } else {
1820 /* otherwise we find the amount of data received here */
1821 recvl = descr->hw_len;
1822 }
1823
1824 /* Reset the status information */
1825 descr->status = 0;
1826
1827 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1828 if (info->port.tty->stopped) {
1829 unsigned char *buf = phys_to_virt(descr->buf);
1830 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1831 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1832 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1833 }
1834 );
1835
1836 /* update stats */
1837 info->icount.rx += recvl;
1838
1839 ret += handle_descr_data(info, descr, recvl);
1840 }
1841
1842 return ret;
1843 }
1844
1845 static void receive_chars_dma(struct e100_serial *info)
1846 {
1847 struct tty_struct *tty;
1848 unsigned char rstat;
1849
1850 #ifdef CONFIG_SVINTO_SIM
1851 /* No receive in the simulator. Will probably be when the rest of
1852 * the serial interface works, and this piece will just be removed.
1853 */
1854 return;
1855 #endif
1856
1857 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1858 *info->iclrintradr =
1859 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1860 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1861
1862 tty = info->port.tty;
1863 if (!tty) /* Something wrong... */
1864 return;
1865
1866 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1867 if (info->uses_dma_in)
1868 e100_enable_serial_data_irq(info);
1869 #endif
1870
1871 if (info->errorcode == ERRCODE_INSERT_BREAK)
1872 add_char_and_flag(info, '\0', TTY_BREAK);
1873
1874 handle_all_descr_data(info);
1875
1876 /* Read the status register to detect errors */
1877 rstat = info->ioport[REG_STATUS];
1878 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1879 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1880 }
1881
1882 if (rstat & SER_ERROR_MASK) {
1883 /* If we got an error, we must reset it by reading the
1884 * data_in field
1885 */
1886 unsigned char data = info->ioport[REG_DATA];
1887
1888 PROCSTAT(ser_stat[info->line].errors_cnt++);
1889 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1890 ((rstat & SER_ERROR_MASK) << 8) | data);
1891
1892 if (rstat & SER_PAR_ERR_MASK)
1893 add_char_and_flag(info, data, TTY_PARITY);
1894 else if (rstat & SER_OVERRUN_MASK)
1895 add_char_and_flag(info, data, TTY_OVERRUN);
1896 else if (rstat & SER_FRAMING_ERR_MASK)
1897 add_char_and_flag(info, data, TTY_FRAME);
1898 }
1899
1900 START_FLUSH_FAST_TIMER(info, "receive_chars");
1901
1902 /* Restart the receiving DMA */
1903 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1904 }
1905
1906 static int start_recv_dma(struct e100_serial *info)
1907 {
1908 struct etrax_dma_descr *descr = info->rec_descr;
1909 struct etrax_recv_buffer *buffer;
1910 int i;
1911
1912 /* Set up the receiving descriptors */
1913 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1914 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1915 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1916
1917 descr[i].ctrl = d_int;
1918 descr[i].buf = virt_to_phys(buffer->buffer);
1919 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1920 descr[i].hw_len = 0;
1921 descr[i].status = 0;
1922 descr[i].next = virt_to_phys(&descr[i+1]);
1923 }
1924
1925 /* Link the last descriptor to the first */
1926 descr[i-1].next = virt_to_phys(&descr[0]);
1927
1928 /* Start with the first descriptor in the list */
1929 info->cur_rec_descr = 0;
1930
1931 /* Start the DMA */
1932 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1933 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1934
1935 /* Input DMA should be running now */
1936 return 1;
1937 }
1938
1939 static void
1940 start_receive(struct e100_serial *info)
1941 {
1942 #ifdef CONFIG_SVINTO_SIM
1943 /* No receive in the simulator. Will probably be when the rest of
1944 * the serial interface works, and this piece will just be removed.
1945 */
1946 return;
1947 #endif
1948 if (info->uses_dma_in) {
1949 /* reset the input dma channel to be sure it works */
1950
1951 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1952 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1953 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1954
1955 start_recv_dma(info);
1956 }
1957 }
1958
1959
1960 /* the bits in the MASK2 register are laid out like this:
1961 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1962 where I is the input channel and O is the output channel for the port.
1963 info->irq is the bit number for the DMAO_DESCR so to check the others we
1964 shift info->irq to the left.
1965 */
1966
1967 /* dma output channel interrupt handler
1968 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1969 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1970 */
1971
1972 static irqreturn_t
1973 tr_interrupt(int irq, void *dev_id)
1974 {
1975 struct e100_serial *info;
1976 unsigned long ireg;
1977 int i;
1978 int handled = 0;
1979
1980 #ifdef CONFIG_SVINTO_SIM
1981 /* No receive in the simulator. Will probably be when the rest of
1982 * the serial interface works, and this piece will just be removed.
1983 */
1984 {
1985 const char *s = "What? tr_interrupt in simulator??\n";
1986 SIMCOUT(s,strlen(s));
1987 }
1988 return IRQ_HANDLED;
1989 #endif
1990
1991 /* find out the line that caused this irq and get it from rs_table */
1992
1993 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1994
1995 for (i = 0; i < NR_PORTS; i++) {
1996 info = rs_table + i;
1997 if (!info->enabled || !info->uses_dma_out)
1998 continue;
1999 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2000 if (ireg & info->irq) {
2001 handled = 1;
2002 /* we can send a new dma bunch. make it so. */
2003 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2004 /* Read jiffies_usec first,
2005 * we want this time to be as late as possible
2006 */
2007 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2008 info->last_tx_active_usec = GET_JIFFIES_USEC();
2009 info->last_tx_active = jiffies;
2010 transmit_chars_dma(info);
2011 }
2012
2013 /* FIXME: here we should really check for a change in the
2014 status lines and if so call status_handle(info) */
2015 }
2016 return IRQ_RETVAL(handled);
2017 } /* tr_interrupt */
2018
2019 /* dma input channel interrupt handler */
2020
2021 static irqreturn_t
2022 rec_interrupt(int irq, void *dev_id)
2023 {
2024 struct e100_serial *info;
2025 unsigned long ireg;
2026 int i;
2027 int handled = 0;
2028
2029 #ifdef CONFIG_SVINTO_SIM
2030 /* No receive in the simulator. Will probably be when the rest of
2031 * the serial interface works, and this piece will just be removed.
2032 */
2033 {
2034 const char *s = "What? rec_interrupt in simulator??\n";
2035 SIMCOUT(s,strlen(s));
2036 }
2037 return IRQ_HANDLED;
2038 #endif
2039
2040 /* find out the line that caused this irq and get it from rs_table */
2041
2042 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2043
2044 for (i = 0; i < NR_PORTS; i++) {
2045 info = rs_table + i;
2046 if (!info->enabled || !info->uses_dma_in)
2047 continue;
2048 /* check for both dma_eop and dma_descr for the input dma channel */
2049 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2050 handled = 1;
2051 /* we have received something */
2052 receive_chars_dma(info);
2053 }
2054
2055 /* FIXME: here we should really check for a change in the
2056 status lines and if so call status_handle(info) */
2057 }
2058 return IRQ_RETVAL(handled);
2059 } /* rec_interrupt */
2060
2061 static int force_eop_if_needed(struct e100_serial *info)
2062 {
2063 /* We check data_avail bit to determine if data has
2064 * arrived since last time
2065 */
2066 unsigned char rstat = info->ioport[REG_STATUS];
2067
2068 /* error or datavail? */
2069 if (rstat & SER_ERROR_MASK) {
2070 /* Some error has occurred. If there has been valid data, an
2071 * EOP interrupt will be made automatically. If no data, the
2072 * normal ser_interrupt should be enabled and handle it.
2073 * So do nothing!
2074 */
2075 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2076 rstat | (info->line << 8));
2077 return 0;
2078 }
2079
2080 if (rstat & SER_DATA_AVAIL_MASK) {
2081 /* Ok data, no error, count it */
2082 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2083 rstat | (info->line << 8)));
2084 /* Read data to clear status flags */
2085 (void)info->ioport[REG_DATA];
2086
2087 info->forced_eop = 0;
2088 START_FLUSH_FAST_TIMER(info, "magic");
2089 return 0;
2090 }
2091
2092 /* hit the timeout, force an EOP for the input
2093 * dma channel if we haven't already
2094 */
2095 if (!info->forced_eop) {
2096 info->forced_eop = 1;
2097 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2098 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2099 FORCE_EOP(info);
2100 }
2101
2102 return 1;
2103 }
2104
2105 static void flush_to_flip_buffer(struct e100_serial *info)
2106 {
2107 struct tty_struct *tty;
2108 struct etrax_recv_buffer *buffer;
2109 unsigned long flags;
2110
2111 local_irq_save(flags);
2112 tty = info->port.tty;
2113
2114 if (!tty) {
2115 local_irq_restore(flags);
2116 return;
2117 }
2118
2119 while ((buffer = info->first_recv_buffer) != NULL) {
2120 unsigned int count = buffer->length;
2121
2122 tty_insert_flip_string(tty, buffer->buffer, count);
2123 info->recv_cnt -= count;
2124
2125 if (count == buffer->length) {
2126 info->first_recv_buffer = buffer->next;
2127 kfree(buffer);
2128 } else {
2129 buffer->length -= count;
2130 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2131 buffer->error = TTY_NORMAL;
2132 }
2133 }
2134
2135 if (!info->first_recv_buffer)
2136 info->last_recv_buffer = NULL;
2137
2138 local_irq_restore(flags);
2139
2140 /* This includes a check for low-latency */
2141 tty_flip_buffer_push(tty);
2142 }
2143
2144 static void check_flush_timeout(struct e100_serial *info)
2145 {
2146 /* Flip what we've got (if we can) */
2147 flush_to_flip_buffer(info);
2148
2149 /* We might need to flip later, but not to fast
2150 * since the system is busy processing input... */
2151 if (info->first_recv_buffer)
2152 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2153
2154 /* Force eop last, since data might have come while we're processing
2155 * and if we started the slow timer above, we won't start a fast
2156 * below.
2157 */
2158 force_eop_if_needed(info);
2159 }
2160
2161 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2162 static void flush_timeout_function(unsigned long data)
2163 {
2164 struct e100_serial *info = (struct e100_serial *)data;
2165
2166 fast_timers[info->line].function = NULL;
2167 serial_fast_timer_expired++;
2168 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2169 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2170 check_flush_timeout(info);
2171 }
2172
2173 #else
2174
2175 /* dma fifo/buffer timeout handler
2176 forces an end-of-packet for the dma input channel if no chars
2177 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2178 */
2179
2180 static struct timer_list flush_timer;
2181
2182 static void
2183 timed_flush_handler(unsigned long ptr)
2184 {
2185 struct e100_serial *info;
2186 int i;
2187
2188 #ifdef CONFIG_SVINTO_SIM
2189 return;
2190 #endif
2191
2192 for (i = 0; i < NR_PORTS; i++) {
2193 info = rs_table + i;
2194 if (info->uses_dma_in)
2195 check_flush_timeout(info);
2196 }
2197
2198 /* restart flush timer */
2199 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2200 }
2201 #endif
2202
2203 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2204
2205 /* If there is an error (ie break) when the DMA is running and
2206 * there are no bytes in the fifo the DMA is stopped and we get no
2207 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2208 * transfer, and if it is without error we can turn the serial
2209 * interrupts off.
2210 */
2211
2212 /*
2213 BREAK handling on ETRAX 100:
2214 ETRAX will generate interrupt although there is no stop bit between the
2215 characters.
2216
2217 Depending on how long the break sequence is, the end of the breaksequence
2218 will look differently:
2219 | indicates start/end of a character.
2220
2221 B= Break character (0x00) with framing error.
2222 E= Error byte with parity error received after B characters.
2223 F= "Faked" valid byte received immediately after B characters.
2224 V= Valid byte
2225
2226 1.
2227 B BL ___________________________ V
2228 .._|__________|__________| |valid data |
2229
2230 Multiple frame errors with data == 0x00 (B),
2231 the timing matches up "perfectly" so no extra ending char is detected.
2232 The RXD pin is 1 in the last interrupt, in that case
2233 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2234 know if another byte will come and this really is case 2. below
2235 (e.g F=0xFF or 0xFE)
2236 If RXD pin is 0 we can expect another character (see 2. below).
2237
2238
2239 2.
2240
2241 B B E or F__________________..__ V
2242 .._|__________|__________|______ | |valid data
2243 "valid" or
2244 parity error
2245
2246 Multiple frame errors with data == 0x00 (B),
2247 but the part of the break trigs is interpreted as a start bit (and possibly
2248 some 0 bits followed by a number of 1 bits and a stop bit).
2249 Depending on parity settings etc. this last character can be either
2250 a fake "valid" char (F) or have a parity error (E).
2251
2252 If the character is valid it will be put in the buffer,
2253 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2254 will set the flags so the tty will handle it,
2255 if it's an error byte it will not be put in the buffer
2256 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2257
2258 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2259 of the last faulty char (B) and compares it with the current time:
2260 If the time elapsed time is less then 2*char_time_usec we will assume
2261 it's a faked F char and not a Valid char and set
2262 info->errorcode = ERRCODE_SET_BREAK.
2263
2264 Flaws in the above solution:
2265 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2266 We use the timer to distinguish a F character from a V character,
2267 if a V character is to close after the break we might make the wrong decision.
2268
2269 TODO: The break will be delayed until an F or V character is received.
2270
2271 */
2272
2273 static
2274 struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2275 {
2276 unsigned long data_read;
2277 struct tty_struct *tty = info->port.tty;
2278
2279 if (!tty) {
2280 printk("!NO TTY!\n");
2281 return info;
2282 }
2283
2284 /* Read data and status at the same time */
2285 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2286 more_data:
2287 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2288 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2289 }
2290 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2291
2292 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2293 IO_MASK(R_SERIAL0_READ, par_err) |
2294 IO_MASK(R_SERIAL0_READ, overrun) )) {
2295 /* An error */
2296 info->last_rx_active_usec = GET_JIFFIES_USEC();
2297 info->last_rx_active = jiffies;
2298 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2299 DLOG_INT_TRIG(
2300 if (!log_int_trig1_pos) {
2301 log_int_trig1_pos = log_int_pos;
2302 log_int(rdpc(), 0, 0);
2303 }
2304 );
2305
2306
2307 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2308 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2309 /* Most likely a break, but we get interrupts over and
2310 * over again.
2311 */
2312
2313 if (!info->break_detected_cnt) {
2314 DEBUG_LOG(info->line, "#BRK start\n", 0);
2315 }
2316 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2317 /* The RX pin is high now, so the break
2318 * must be over, but....
2319 * we can't really know if we will get another
2320 * last byte ending the break or not.
2321 * And we don't know if the byte (if any) will
2322 * have an error or look valid.
2323 */
2324 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2325 info->errorcode = ERRCODE_INSERT_BREAK;
2326 }
2327 info->break_detected_cnt++;
2328 } else {
2329 /* The error does not look like a break, but could be
2330 * the end of one
2331 */
2332 if (info->break_detected_cnt) {
2333 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2334 info->errorcode = ERRCODE_INSERT_BREAK;
2335 } else {
2336 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2337 data_in, data_read);
2338 char flag = TTY_NORMAL;
2339 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2340 tty_insert_flip_char(&info->port, 0, flag);
2341 info->icount.rx++;
2342 }
2343
2344 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2345 info->icount.parity++;
2346 flag = TTY_PARITY;
2347 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2348 info->icount.overrun++;
2349 flag = TTY_OVERRUN;
2350 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2351 info->icount.frame++;
2352 flag = TTY_FRAME;
2353 }
2354 tty_insert_flip_char(&info->port, data, flag);
2355 info->errorcode = 0;
2356 }
2357 info->break_detected_cnt = 0;
2358 }
2359 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2360 /* No error */
2361 DLOG_INT_TRIG(
2362 if (!log_int_trig1_pos) {
2363 if (log_int_pos >= log_int_size) {
2364 log_int_pos = 0;
2365 }
2366 log_int_trig0_pos = log_int_pos;
2367 log_int(rdpc(), 0, 0);
2368 }
2369 );
2370 tty_insert_flip_char(&info->port,
2371 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2372 TTY_NORMAL);
2373 } else {
2374 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2375 }
2376
2377
2378 info->icount.rx++;
2379 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2380 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2381 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2382 goto more_data;
2383 }
2384
2385 tty_flip_buffer_push(info->port.tty);
2386 return info;
2387 }
2388
2389 static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2390 {
2391 unsigned char rstat;
2392
2393 #ifdef SERIAL_DEBUG_INTR
2394 printk("Interrupt from serport %d\n", i);
2395 #endif
2396 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2397 if (!info->uses_dma_in) {
2398 return handle_ser_rx_interrupt_no_dma(info);
2399 }
2400 /* DMA is used */
2401 rstat = info->ioport[REG_STATUS];
2402 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2403 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2404 }
2405
2406 if (rstat & SER_ERROR_MASK) {
2407 unsigned char data;
2408
2409 info->last_rx_active_usec = GET_JIFFIES_USEC();
2410 info->last_rx_active = jiffies;
2411 /* If we got an error, we must reset it by reading the
2412 * data_in field
2413 */
2414 data = info->ioport[REG_DATA];
2415 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2416 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2417 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2418 /* Most likely a break, but we get interrupts over and
2419 * over again.
2420 */
2421
2422 if (!info->break_detected_cnt) {
2423 DEBUG_LOG(info->line, "#BRK start\n", 0);
2424 }
2425 if (rstat & SER_RXD_MASK) {
2426 /* The RX pin is high now, so the break
2427 * must be over, but....
2428 * we can't really know if we will get another
2429 * last byte ending the break or not.
2430 * And we don't know if the byte (if any) will
2431 * have an error or look valid.
2432 */
2433 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2434 info->errorcode = ERRCODE_INSERT_BREAK;
2435 }
2436 info->break_detected_cnt++;
2437 } else {
2438 /* The error does not look like a break, but could be
2439 * the end of one
2440 */
2441 if (info->break_detected_cnt) {
2442 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2443 info->errorcode = ERRCODE_INSERT_BREAK;
2444 } else {
2445 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2446 info->icount.brk++;
2447 add_char_and_flag(info, '\0', TTY_BREAK);
2448 }
2449
2450 if (rstat & SER_PAR_ERR_MASK) {
2451 info->icount.parity++;
2452 add_char_and_flag(info, data, TTY_PARITY);
2453 } else if (rstat & SER_OVERRUN_MASK) {
2454 info->icount.overrun++;
2455 add_char_and_flag(info, data, TTY_OVERRUN);
2456 } else if (rstat & SER_FRAMING_ERR_MASK) {
2457 info->icount.frame++;
2458 add_char_and_flag(info, data, TTY_FRAME);
2459 }
2460
2461 info->errorcode = 0;
2462 }
2463 info->break_detected_cnt = 0;
2464 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2465 ((rstat & SER_ERROR_MASK) << 8) | data);
2466 }
2467 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2468 } else { /* It was a valid byte, now let the DMA do the rest */
2469 unsigned long curr_time_u = GET_JIFFIES_USEC();
2470 unsigned long curr_time = jiffies;
2471
2472 if (info->break_detected_cnt) {
2473 /* Detect if this character is a new valid char or the
2474 * last char in a break sequence: If LSBits are 0 and
2475 * MSBits are high AND the time is close to the
2476 * previous interrupt we should discard it.
2477 */
2478 long elapsed_usec =
2479 (curr_time - info->last_rx_active) * (1000000/HZ) +
2480 curr_time_u - info->last_rx_active_usec;
2481 if (elapsed_usec < 2*info->char_time_usec) {
2482 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2483 /* Report as BREAK (error) and let
2484 * receive_chars_dma() handle it
2485 */
2486 info->errorcode = ERRCODE_SET_BREAK;
2487 } else {
2488 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2489 }
2490 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2491 }
2492
2493 #ifdef SERIAL_DEBUG_INTR
2494 printk("** OK, disabling ser_interrupts\n");
2495 #endif
2496 e100_disable_serial_data_irq(info);
2497 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2498 info->break_detected_cnt = 0;
2499
2500 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2501 }
2502 /* Restarting the DMA never hurts */
2503 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2504 START_FLUSH_FAST_TIMER(info, "ser_int");
2505 return info;
2506 } /* handle_ser_rx_interrupt */
2507
2508 static void handle_ser_tx_interrupt(struct e100_serial *info)
2509 {
2510 unsigned long flags;
2511
2512 if (info->x_char) {
2513 unsigned char rstat;
2514 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2515 local_irq_save(flags);
2516 rstat = info->ioport[REG_STATUS];
2517 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2518
2519 info->ioport[REG_TR_DATA] = info->x_char;
2520 info->icount.tx++;
2521 info->x_char = 0;
2522 /* We must enable since it is disabled in ser_interrupt */
2523 e100_enable_serial_tx_ready_irq(info);
2524 local_irq_restore(flags);
2525 return;
2526 }
2527 if (info->uses_dma_out) {
2528 unsigned char rstat;
2529 int i;
2530 /* We only use normal tx interrupt when sending x_char */
2531 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2532 local_irq_save(flags);
2533 rstat = info->ioport[REG_STATUS];
2534 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2535 e100_disable_serial_tx_ready_irq(info);
2536 if (info->port.tty->stopped)
2537 rs_stop(info->port.tty);
2538 /* Enable the DMA channel and tell it to continue */
2539 e100_enable_txdma_channel(info);
2540 /* Wait 12 cycles before doing the DMA command */
2541 for(i = 6; i > 0; i--)
2542 nop();
2543
2544 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2545 local_irq_restore(flags);
2546 return;
2547 }
2548 /* Normal char-by-char interrupt */
2549 if (info->xmit.head == info->xmit.tail
2550 || info->port.tty->stopped
2551 || info->port.tty->hw_stopped) {
2552 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2553 info->port.tty->stopped));
2554 e100_disable_serial_tx_ready_irq(info);
2555 info->tr_running = 0;
2556 return;
2557 }
2558 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2559 /* Send a byte, rs485 timing is critical so turn of ints */
2560 local_irq_save(flags);
2561 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2562 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2563 info->icount.tx++;
2564 if (info->xmit.head == info->xmit.tail) {
2565 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2566 if (info->rs485.flags & SER_RS485_ENABLED) {
2567 /* Set a short timer to toggle RTS */
2568 start_one_shot_timer(&fast_timers_rs485[info->line],
2569 rs485_toggle_rts_timer_function,
2570 (unsigned long)info,
2571 info->char_time_usec*2,
2572 "RS-485");
2573 }
2574 #endif /* RS485 */
2575 info->last_tx_active_usec = GET_JIFFIES_USEC();
2576 info->last_tx_active = jiffies;
2577 e100_disable_serial_tx_ready_irq(info);
2578 info->tr_running = 0;
2579 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2580 } else {
2581 /* We must enable since it is disabled in ser_interrupt */
2582 e100_enable_serial_tx_ready_irq(info);
2583 }
2584 local_irq_restore(flags);
2585
2586 if (CIRC_CNT(info->xmit.head,
2587 info->xmit.tail,
2588 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2589 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2590
2591 } /* handle_ser_tx_interrupt */
2592
2593 /* result of time measurements:
2594 * RX duration 54-60 us when doing something, otherwise 6-9 us
2595 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2596 */
2597 static irqreturn_t
2598 ser_interrupt(int irq, void *dev_id)
2599 {
2600 static volatile int tx_started = 0;
2601 struct e100_serial *info;
2602 int i;
2603 unsigned long flags;
2604 unsigned long irq_mask1_rd;
2605 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2606 int handled = 0;
2607 static volatile unsigned long reentered_ready_mask = 0;
2608
2609 local_irq_save(flags);
2610 irq_mask1_rd = *R_IRQ_MASK1_RD;
2611 /* First handle all rx interrupts with ints disabled */
2612 info = rs_table;
2613 irq_mask1_rd &= e100_ser_int_mask;
2614 for (i = 0; i < NR_PORTS; i++) {
2615 /* Which line caused the data irq? */
2616 if (irq_mask1_rd & data_mask) {
2617 handled = 1;
2618 handle_ser_rx_interrupt(info);
2619 }
2620 info += 1;
2621 data_mask <<= 2;
2622 }
2623 /* Handle tx interrupts with interrupts enabled so we
2624 * can take care of new data interrupts while transmitting
2625 * We protect the tx part with the tx_started flag.
2626 * We disable the tr_ready interrupts we are about to handle and
2627 * unblock the serial interrupt so new serial interrupts may come.
2628 *
2629 * If we get a new interrupt:
2630 * - it migth be due to synchronous serial ports.
2631 * - serial irq will be blocked by general irq handler.
2632 * - async data will be handled above (sync will be ignored).
2633 * - tx_started flag will prevent us from trying to send again and
2634 * we will exit fast - no need to unblock serial irq.
2635 * - Next (sync) serial interrupt handler will be runned with
2636 * disabled interrupt due to restore_flags() at end of function,
2637 * so sync handler will not be preempted or reentered.
2638 */
2639 if (!tx_started) {
2640 unsigned long ready_mask;
2641 unsigned long
2642 tx_started = 1;
2643 /* Only the tr_ready interrupts left */
2644 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2645 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2646 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2647 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2648 while (irq_mask1_rd) {
2649 /* Disable those we are about to handle */
2650 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2651 /* Unblock the serial interrupt */
2652 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2653
2654 local_irq_enable();
2655 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2656 info = rs_table;
2657 for (i = 0; i < NR_PORTS; i++) {
2658 /* Which line caused the ready irq? */
2659 if (irq_mask1_rd & ready_mask) {
2660 handled = 1;
2661 handle_ser_tx_interrupt(info);
2662 }
2663 info += 1;
2664 ready_mask <<= 2;
2665 }
2666 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2667 local_irq_disable();
2668 /* Handle reentered TX interrupt */
2669 irq_mask1_rd = reentered_ready_mask;
2670 }
2671 local_irq_disable();
2672 tx_started = 0;
2673 } else {
2674 unsigned long ready_mask;
2675 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2676 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2677 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2678 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2679 if (ready_mask) {
2680 reentered_ready_mask |= ready_mask;
2681 /* Disable those we are about to handle */
2682 *R_IRQ_MASK1_CLR = ready_mask;
2683 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2684 }
2685 }
2686
2687 local_irq_restore(flags);
2688 return IRQ_RETVAL(handled);
2689 } /* ser_interrupt */
2690 #endif
2691
2692 /*
2693 * -------------------------------------------------------------------
2694 * Here ends the serial interrupt routines.
2695 * -------------------------------------------------------------------
2696 */
2697
2698 /*
2699 * This routine is used to handle the "bottom half" processing for the
2700 * serial driver, known also the "software interrupt" processing.
2701 * This processing is done at the kernel interrupt level, after the
2702 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2703 * is where time-consuming activities which can not be done in the
2704 * interrupt driver proper are done; the interrupt driver schedules
2705 * them using rs_sched_event(), and they get done here.
2706 */
2707 static void
2708 do_softint(struct work_struct *work)
2709 {
2710 struct e100_serial *info;
2711 struct tty_struct *tty;
2712
2713 info = container_of(work, struct e100_serial, work);
2714
2715 tty = info->port.tty;
2716 if (!tty)
2717 return;
2718
2719 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2720 tty_wakeup(tty);
2721 }
2722
2723 static int
2724 startup(struct e100_serial * info)
2725 {
2726 unsigned long flags;
2727 unsigned long xmit_page;
2728 int i;
2729
2730 xmit_page = get_zeroed_page(GFP_KERNEL);
2731 if (!xmit_page)
2732 return -ENOMEM;
2733
2734 local_irq_save(flags);
2735
2736 /* if it was already initialized, skip this */
2737
2738 if (info->flags & ASYNC_INITIALIZED) {
2739 local_irq_restore(flags);
2740 free_page(xmit_page);
2741 return 0;
2742 }
2743
2744 if (info->xmit.buf)
2745 free_page(xmit_page);
2746 else
2747 info->xmit.buf = (unsigned char *) xmit_page;
2748
2749 #ifdef SERIAL_DEBUG_OPEN
2750 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2751 #endif
2752
2753 #ifdef CONFIG_SVINTO_SIM
2754 /* Bits and pieces collected from below. Better to have them
2755 in one ifdef:ed clause than to mix in a lot of ifdefs,
2756 right? */
2757 if (info->port.tty)
2758 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2759
2760 info->xmit.head = info->xmit.tail = 0;
2761 info->first_recv_buffer = info->last_recv_buffer = NULL;
2762 info->recv_cnt = info->max_recv_cnt = 0;
2763
2764 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2765 info->rec_descr[i].buf = NULL;
2766
2767 /* No real action in the simulator, but may set info important
2768 to ioctl. */
2769 change_speed(info);
2770 #else
2771
2772 /*
2773 * Clear the FIFO buffers and disable them
2774 * (they will be reenabled in change_speed())
2775 */
2776
2777 /*
2778 * Reset the DMA channels and make sure their interrupts are cleared
2779 */
2780
2781 if (info->dma_in_enabled) {
2782 info->uses_dma_in = 1;
2783 e100_enable_rxdma_channel(info);
2784
2785 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2786
2787 /* Wait until reset cycle is complete */
2788 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2789 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2790
2791 /* Make sure the irqs are cleared */
2792 *info->iclrintradr =
2793 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2794 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2795 } else {
2796 e100_disable_rxdma_channel(info);
2797 }
2798
2799 if (info->dma_out_enabled) {
2800 info->uses_dma_out = 1;
2801 e100_enable_txdma_channel(info);
2802 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2803
2804 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2805 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2806
2807 /* Make sure the irqs are cleared */
2808 *info->oclrintradr =
2809 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2810 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2811 } else {
2812 e100_disable_txdma_channel(info);
2813 }
2814
2815 if (info->port.tty)
2816 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2817
2818 info->xmit.head = info->xmit.tail = 0;
2819 info->first_recv_buffer = info->last_recv_buffer = NULL;
2820 info->recv_cnt = info->max_recv_cnt = 0;
2821
2822 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2823 info->rec_descr[i].buf = 0;
2824
2825 /*
2826 * and set the speed and other flags of the serial port
2827 * this will start the rx/tx as well
2828 */
2829 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2830 e100_enable_serial_data_irq(info);
2831 #endif
2832 change_speed(info);
2833
2834 /* dummy read to reset any serial errors */
2835
2836 (void)info->ioport[REG_DATA];
2837
2838 /* enable the interrupts */
2839 if (info->uses_dma_out)
2840 e100_enable_txdma_irq(info);
2841
2842 e100_enable_rx_irq(info);
2843
2844 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2845
2846 /* setup the dma input descriptor and start dma */
2847
2848 start_receive(info);
2849
2850 /* for safety, make sure the descriptors last result is 0 bytes written */
2851
2852 info->tr_descr.sw_len = 0;
2853 info->tr_descr.hw_len = 0;
2854 info->tr_descr.status = 0;
2855
2856 /* enable RTS/DTR last */
2857
2858 e100_rts(info, 1);
2859 e100_dtr(info, 1);
2860
2861 #endif /* CONFIG_SVINTO_SIM */
2862
2863 info->flags |= ASYNC_INITIALIZED;
2864
2865 local_irq_restore(flags);
2866 return 0;
2867 }
2868
2869 /*
2870 * This routine will shutdown a serial port; interrupts are disabled, and
2871 * DTR is dropped if the hangup on close termio flag is on.
2872 */
2873 static void
2874 shutdown(struct e100_serial * info)
2875 {
2876 unsigned long flags;
2877 struct etrax_dma_descr *descr = info->rec_descr;
2878 struct etrax_recv_buffer *buffer;
2879 int i;
2880
2881 #ifndef CONFIG_SVINTO_SIM
2882 /* shut down the transmitter and receiver */
2883 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2884 e100_disable_rx(info);
2885 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2886
2887 /* disable interrupts, reset dma channels */
2888 if (info->uses_dma_in) {
2889 e100_disable_rxdma_irq(info);
2890 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2891 info->uses_dma_in = 0;
2892 } else {
2893 e100_disable_serial_data_irq(info);
2894 }
2895
2896 if (info->uses_dma_out) {
2897 e100_disable_txdma_irq(info);
2898 info->tr_running = 0;
2899 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2900 info->uses_dma_out = 0;
2901 } else {
2902 e100_disable_serial_tx_ready_irq(info);
2903 info->tr_running = 0;
2904 }
2905
2906 #endif /* CONFIG_SVINTO_SIM */
2907
2908 if (!(info->flags & ASYNC_INITIALIZED))
2909 return;
2910
2911 #ifdef SERIAL_DEBUG_OPEN
2912 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2913 info->irq);
2914 #endif
2915
2916 local_irq_save(flags);
2917
2918 if (info->xmit.buf) {
2919 free_page((unsigned long)info->xmit.buf);
2920 info->xmit.buf = NULL;
2921 }
2922
2923 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2924 if (descr[i].buf) {
2925 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2926 kfree(buffer);
2927 descr[i].buf = 0;
2928 }
2929
2930 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
2931 /* hang up DTR and RTS if HUPCL is enabled */
2932 e100_dtr(info, 0);
2933 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2934 }
2935
2936 if (info->port.tty)
2937 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2938
2939 info->flags &= ~ASYNC_INITIALIZED;
2940 local_irq_restore(flags);
2941 }
2942
2943
2944 /* change baud rate and other assorted parameters */
2945
2946 static void
2947 change_speed(struct e100_serial *info)
2948 {
2949 unsigned int cflag;
2950 unsigned long xoff;
2951 unsigned long flags;
2952 /* first some safety checks */
2953
2954 if (!info->port.tty)
2955 return;
2956 if (!info->ioport)
2957 return;
2958
2959 cflag = info->port.tty->termios.c_cflag;
2960
2961 /* possibly, the tx/rx should be disabled first to do this safely */
2962
2963 /* change baud-rate and write it to the hardware */
2964 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2965 /* Special baudrate */
2966 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2967 unsigned long alt_source =
2968 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2969 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2970 /* R_ALT_SER_BAUDRATE selects the source */
2971 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2972 (unsigned long)info->baud_base, info->custom_divisor));
2973 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2974 /* 0, 2-65535 (0=65536) */
2975 u16 divisor = info->custom_divisor;
2976 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2977 /* baudrate is 3.125MHz/custom_divisor */
2978 alt_source =
2979 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2980 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2981 alt_source = 0x11;
2982 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2983 *R_SERIAL_PRESCALE = divisor;
2984 info->baud = SERIAL_PRESCALE_BASE/divisor;
2985 }
2986 #ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
2987 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
2988 info->custom_divisor == 1) ||
2989 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
2990 info->custom_divisor == 8)) {
2991 /* ext_clk selected */
2992 alt_source =
2993 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
2995 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
2996 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
2997 }
2998 #endif
2999 else
3000 {
3001 /* Bad baudbase, we don't support using timer0
3002 * for baudrate.
3003 */
3004 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3005 (unsigned long)info->baud_base, info->custom_divisor);
3006 }
3007 r_alt_ser_baudrate_shadow &= ~mask;
3008 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3009 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3010 } else {
3011 /* Normal baudrate */
3012 /* Make sure we use normal baudrate */
3013 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3014 unsigned long alt_source =
3015 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3016 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3017 r_alt_ser_baudrate_shadow &= ~mask;
3018 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3019 #ifndef CONFIG_SVINTO_SIM
3020 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3021 #endif /* CONFIG_SVINTO_SIM */
3022
3023 info->baud = cflag_to_baud(cflag);
3024 #ifndef CONFIG_SVINTO_SIM
3025 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3026 #endif /* CONFIG_SVINTO_SIM */
3027 }
3028
3029 #ifndef CONFIG_SVINTO_SIM
3030 /* start with default settings and then fill in changes */
3031 local_irq_save(flags);
3032 /* 8 bit, no/even parity */
3033 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3034 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3035 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3036
3037 /* 8 bit, no/even parity, 1 stop bit, no cts */
3038 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3039 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3040 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3041 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3042 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3043
3044 if ((cflag & CSIZE) == CS7) {
3045 /* set 7 bit mode */
3046 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3047 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3048 }
3049
3050 if (cflag & CSTOPB) {
3051 /* set 2 stop bit mode */
3052 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3053 }
3054
3055 if (cflag & PARENB) {
3056 /* enable parity */
3057 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3058 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3059 }
3060
3061 if (cflag & CMSPAR) {
3062 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3063 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3064 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3065 }
3066 if (cflag & PARODD) {
3067 /* set odd parity (or Mark if CMSPAR) */
3068 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3069 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3070 }
3071
3072 if (cflag & CRTSCTS) {
3073 /* enable automatic CTS handling */
3074 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3075 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3076 }
3077
3078 /* make sure the tx and rx are enabled */
3079
3080 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3081 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3082
3083 /* actually write the control regs to the hardware */
3084
3085 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3086 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3087 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3088 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3089 if (info->port.tty->termios.c_iflag & IXON ) {
3090 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3091 STOP_CHAR(info->port.tty)));
3092 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3093 }
3094
3095 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3096 local_irq_restore(flags);
3097 #endif /* !CONFIG_SVINTO_SIM */
3098
3099 update_char_time(info);
3100
3101 } /* change_speed */
3102
3103 /* start transmitting chars NOW */
3104
3105 static void
3106 rs_flush_chars(struct tty_struct *tty)
3107 {
3108 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3109 unsigned long flags;
3110
3111 if (info->tr_running ||
3112 info->xmit.head == info->xmit.tail ||
3113 tty->stopped ||
3114 tty->hw_stopped ||
3115 !info->xmit.buf)
3116 return;
3117
3118 #ifdef SERIAL_DEBUG_FLOW
3119 printk("rs_flush_chars\n");
3120 #endif
3121
3122 /* this protection might not exactly be necessary here */
3123
3124 local_irq_save(flags);
3125 start_transmit(info);
3126 local_irq_restore(flags);
3127 }
3128
3129 static int rs_raw_write(struct tty_struct *tty,
3130 const unsigned char *buf, int count)
3131 {
3132 int c, ret = 0;
3133 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3134 unsigned long flags;
3135
3136 /* first some sanity checks */
3137
3138 if (!tty || !info->xmit.buf)
3139 return 0;
3140
3141 #ifdef SERIAL_DEBUG_DATA
3142 if (info->line == SERIAL_DEBUG_LINE)
3143 printk("rs_raw_write (%d), status %d\n",
3144 count, info->ioport[REG_STATUS]);
3145 #endif
3146
3147 #ifdef CONFIG_SVINTO_SIM
3148 /* Really simple. The output is here and now. */
3149 SIMCOUT(buf, count);
3150 return count;
3151 #endif
3152 local_save_flags(flags);
3153 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3154 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3155
3156
3157 /* The local_irq_disable/restore_flags pairs below are needed
3158 * because the DMA interrupt handler moves the info->xmit values.
3159 * the memcpy needs to be in the critical region unfortunately,
3160 * because we need to read xmit values, memcpy, write xmit values
3161 * in one atomic operation... this could perhaps be avoided by
3162 * more clever design.
3163 */
3164 local_irq_disable();
3165 while (count) {
3166 c = CIRC_SPACE_TO_END(info->xmit.head,
3167 info->xmit.tail,
3168 SERIAL_XMIT_SIZE);
3169
3170 if (count < c)
3171 c = count;
3172 if (c <= 0)
3173 break;
3174
3175 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3176 info->xmit.head = (info->xmit.head + c) &
3177 (SERIAL_XMIT_SIZE-1);
3178 buf += c;
3179 count -= c;
3180 ret += c;
3181 }
3182 local_irq_restore(flags);
3183
3184 /* enable transmitter if not running, unless the tty is stopped
3185 * this does not need IRQ protection since if tr_running == 0
3186 * the IRQ's are not running anyway for this port.
3187 */
3188 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3189
3190 if (info->xmit.head != info->xmit.tail &&
3191 !tty->stopped &&
3192 !tty->hw_stopped &&
3193 !info->tr_running) {
3194 start_transmit(info);
3195 }
3196
3197 return ret;
3198 } /* raw_raw_write() */
3199
3200 static int
3201 rs_write(struct tty_struct *tty,
3202 const unsigned char *buf, int count)
3203 {
3204 #if defined(CONFIG_ETRAX_RS485)
3205 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3206
3207 if (info->rs485.flags & SER_RS485_ENABLED)
3208 {
3209 /* If we are in RS-485 mode, we need to toggle RTS and disable
3210 * the receiver before initiating a DMA transfer
3211 */
3212 #ifdef CONFIG_ETRAX_FAST_TIMER
3213 /* Abort any started timer */
3214 fast_timers_rs485[info->line].function = NULL;
3215 del_fast_timer(&fast_timers_rs485[info->line]);
3216 #endif
3217 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3218 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3219 e100_disable_rx(info);
3220 e100_enable_rx_irq(info);
3221 #endif
3222 if (info->rs485.delay_rts_before_send > 0)
3223 msleep(info->rs485.delay_rts_before_send);
3224 }
3225 #endif /* CONFIG_ETRAX_RS485 */
3226
3227 count = rs_raw_write(tty, buf, count);
3228
3229 #if defined(CONFIG_ETRAX_RS485)
3230 if (info->rs485.flags & SER_RS485_ENABLED)
3231 {
3232 unsigned int val;
3233 /* If we are in RS-485 mode the following has to be done:
3234 * wait until DMA is ready
3235 * wait on transmit shift register
3236 * toggle RTS
3237 * enable the receiver
3238 */
3239
3240 /* Sleep until all sent */
3241 tty_wait_until_sent(tty, 0);
3242 #ifdef CONFIG_ETRAX_FAST_TIMER
3243 /* Now sleep a little more so that shift register is empty */
3244 schedule_usleep(info->char_time_usec * 2);
3245 #endif
3246 /* wait on transmit shift register */
3247 do{
3248 get_lsr_info(info, &val);
3249 }while (!(val & TIOCSER_TEMT));
3250
3251 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3252
3253 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3254 e100_enable_rx(info);
3255 e100_enable_rxdma_irq(info);
3256 #endif
3257 }
3258 #endif /* CONFIG_ETRAX_RS485 */
3259
3260 return count;
3261 } /* rs_write */
3262
3263
3264 /* how much space is available in the xmit buffer? */
3265
3266 static int
3267 rs_write_room(struct tty_struct *tty)
3268 {
3269 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3270
3271 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3272 }
3273
3274 /* How many chars are in the xmit buffer?
3275 * This does not include any chars in the transmitter FIFO.
3276 * Use wait_until_sent for waiting for FIFO drain.
3277 */
3278
3279 static int
3280 rs_chars_in_buffer(struct tty_struct *tty)
3281 {
3282 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3283
3284 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3285 }
3286
3287 /* discard everything in the xmit buffer */
3288
3289 static void
3290 rs_flush_buffer(struct tty_struct *tty)
3291 {
3292 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3293 unsigned long flags;
3294
3295 local_irq_save(flags);
3296 info->xmit.head = info->xmit.tail = 0;
3297 local_irq_restore(flags);
3298
3299 tty_wakeup(tty);
3300 }
3301
3302 /*
3303 * This function is used to send a high-priority XON/XOFF character to
3304 * the device
3305 *
3306 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3307 * but we do it in handle_ser_tx_interrupt().
3308 * We disable DMA channel and enable tx ready interrupt and write the
3309 * character when possible.
3310 */
3311 static void rs_send_xchar(struct tty_struct *tty, char ch)
3312 {
3313 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3314 unsigned long flags;
3315 local_irq_save(flags);
3316 if (info->uses_dma_out) {
3317 /* Put the DMA on hold and disable the channel */
3318 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3319 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3320 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3321 e100_disable_txdma_channel(info);
3322 }
3323
3324 /* Must make sure transmitter is not stopped before we can transmit */
3325 if (tty->stopped)
3326 rs_start(tty);
3327
3328 /* Enable manual transmit interrupt and send from there */
3329 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3330 info->x_char = ch;
3331 e100_enable_serial_tx_ready_irq(info);
3332 local_irq_restore(flags);
3333 }
3334
3335 /*
3336 * ------------------------------------------------------------
3337 * rs_throttle()
3338 *
3339 * This routine is called by the upper-layer tty layer to signal that
3340 * incoming characters should be throttled.
3341 * ------------------------------------------------------------
3342 */
3343 static void
3344 rs_throttle(struct tty_struct * tty)
3345 {
3346 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3347 #ifdef SERIAL_DEBUG_THROTTLE
3348 char buf[64];
3349
3350 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3351 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3352 #endif
3353 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3354
3355 /* Do RTS before XOFF since XOFF might take some time */
3356 if (tty->termios.c_cflag & CRTSCTS) {
3357 /* Turn off RTS line */
3358 e100_rts(info, 0);
3359 }
3360 if (I_IXOFF(tty))
3361 rs_send_xchar(tty, STOP_CHAR(tty));
3362
3363 }
3364
3365 static void
3366 rs_unthrottle(struct tty_struct * tty)
3367 {
3368 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3369 #ifdef SERIAL_DEBUG_THROTTLE
3370 char buf[64];
3371
3372 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3373 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3374 #endif
3375 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3376 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3377 /* Do RTS before XOFF since XOFF might take some time */
3378 if (tty->termios.c_cflag & CRTSCTS) {
3379 /* Assert RTS line */
3380 e100_rts(info, 1);
3381 }
3382
3383 if (I_IXOFF(tty)) {
3384 if (info->x_char)
3385 info->x_char = 0;
3386 else
3387 rs_send_xchar(tty, START_CHAR(tty));
3388 }
3389
3390 }
3391
3392 /*
3393 * ------------------------------------------------------------
3394 * rs_ioctl() and friends
3395 * ------------------------------------------------------------
3396 */
3397
3398 static int
3399 get_serial_info(struct e100_serial * info,
3400 struct serial_struct * retinfo)
3401 {
3402 struct serial_struct tmp;
3403
3404 /* this is all probably wrong, there are a lot of fields
3405 * here that we don't have in e100_serial and maybe we
3406 * should set them to something else than 0.
3407 */
3408
3409 if (!retinfo)
3410 return -EFAULT;
3411 memset(&tmp, 0, sizeof(tmp));
3412 tmp.type = info->type;
3413 tmp.line = info->line;
3414 tmp.port = (int)info->ioport;
3415 tmp.irq = info->irq;
3416 tmp.flags = info->flags;
3417 tmp.baud_base = info->baud_base;
3418 tmp.close_delay = info->close_delay;
3419 tmp.closing_wait = info->closing_wait;
3420 tmp.custom_divisor = info->custom_divisor;
3421 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3422 return -EFAULT;
3423 return 0;
3424 }
3425
3426 static int
3427 set_serial_info(struct e100_serial *info,
3428 struct serial_struct *new_info)
3429 {
3430 struct serial_struct new_serial;
3431 struct e100_serial old_info;
3432 int retval = 0;
3433
3434 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3435 return -EFAULT;
3436
3437 old_info = *info;
3438
3439 if (!capable(CAP_SYS_ADMIN)) {
3440 if ((new_serial.type != info->type) ||
3441 (new_serial.close_delay != info->close_delay) ||
3442 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3443 (info->flags & ~ASYNC_USR_MASK)))
3444 return -EPERM;
3445 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3446 (new_serial.flags & ASYNC_USR_MASK));
3447 goto check_and_exit;
3448 }
3449
3450 if (info->count > 1)
3451 return -EBUSY;
3452
3453 /*
3454 * OK, past this point, all the error checking has been done.
3455 * At this point, we start making changes.....
3456 */
3457
3458 info->baud_base = new_serial.baud_base;
3459 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3460 (new_serial.flags & ASYNC_FLAGS));
3461 info->custom_divisor = new_serial.custom_divisor;
3462 info->type = new_serial.type;
3463 info->close_delay = new_serial.close_delay;
3464 info->closing_wait = new_serial.closing_wait;
3465 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3466
3467 check_and_exit:
3468 if (info->flags & ASYNC_INITIALIZED) {
3469 change_speed(info);
3470 } else
3471 retval = startup(info);
3472 return retval;
3473 }
3474
3475 /*
3476 * get_lsr_info - get line status register info
3477 *
3478 * Purpose: Let user call ioctl() to get info when the UART physically
3479 * is emptied. On bus types like RS485, the transmitter must
3480 * release the bus after transmitting. This must be done when
3481 * the transmit shift register is empty, not be done when the
3482 * transmit holding register is empty. This functionality
3483 * allows an RS485 driver to be written in user space.
3484 */
3485 static int
3486 get_lsr_info(struct e100_serial * info, unsigned int *value)
3487 {
3488 unsigned int result = TIOCSER_TEMT;
3489 #ifndef CONFIG_SVINTO_SIM
3490 unsigned long curr_time = jiffies;
3491 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3492 unsigned long elapsed_usec =
3493 (curr_time - info->last_tx_active) * 1000000/HZ +
3494 curr_time_usec - info->last_tx_active_usec;
3495
3496 if (info->xmit.head != info->xmit.tail ||
3497 elapsed_usec < 2*info->char_time_usec) {
3498 result = 0;
3499 }
3500 #endif
3501
3502 if (copy_to_user(value, &result, sizeof(int)))
3503 return -EFAULT;
3504 return 0;
3505 }
3506
3507 #ifdef SERIAL_DEBUG_IO
3508 struct state_str
3509 {
3510 int state;
3511 const char *str;
3512 };
3513
3514 const struct state_str control_state_str[] = {
3515 {TIOCM_DTR, "DTR" },
3516 {TIOCM_RTS, "RTS"},
3517 {TIOCM_ST, "ST?" },
3518 {TIOCM_SR, "SR?" },
3519 {TIOCM_CTS, "CTS" },
3520 {TIOCM_CD, "CD" },
3521 {TIOCM_RI, "RI" },
3522 {TIOCM_DSR, "DSR" },
3523 {0, NULL }
3524 };
3525
3526 char *get_control_state_str(int MLines, char *s)
3527 {
3528 int i = 0;
3529
3530 s[0]='\0';
3531 while (control_state_str[i].str != NULL) {
3532 if (MLines & control_state_str[i].state) {
3533 if (s[0] != '\0') {
3534 strcat(s, ", ");
3535 }
3536 strcat(s, control_state_str[i].str);
3537 }
3538 i++;
3539 }
3540 return s;
3541 }
3542 #endif
3543
3544 static int
3545 rs_break(struct tty_struct *tty, int break_state)
3546 {
3547 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3548 unsigned long flags;
3549
3550 if (!info->ioport)
3551 return -EIO;
3552
3553 local_irq_save(flags);
3554 if (break_state == -1) {
3555 /* Go to manual mode and set the txd pin to 0 */
3556 /* Clear bit 7 (txd) and 6 (tr_enable) */
3557 info->tx_ctrl &= 0x3F;
3558 } else {
3559 /* Set bit 7 (txd) and 6 (tr_enable) */
3560 info->tx_ctrl |= (0x80 | 0x40);
3561 }
3562 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3563 local_irq_restore(flags);
3564 return 0;
3565 }
3566
3567 static int
3568 rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
3569 {
3570 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3571 unsigned long flags;
3572
3573 local_irq_save(flags);
3574
3575 if (clear & TIOCM_RTS)
3576 e100_rts(info, 0);
3577 if (clear & TIOCM_DTR)
3578 e100_dtr(info, 0);
3579 /* Handle FEMALE behaviour */
3580 if (clear & TIOCM_RI)
3581 e100_ri_out(info, 0);
3582 if (clear & TIOCM_CD)
3583 e100_cd_out(info, 0);
3584
3585 if (set & TIOCM_RTS)
3586 e100_rts(info, 1);
3587 if (set & TIOCM_DTR)
3588 e100_dtr(info, 1);
3589 /* Handle FEMALE behaviour */
3590 if (set & TIOCM_RI)
3591 e100_ri_out(info, 1);
3592 if (set & TIOCM_CD)
3593 e100_cd_out(info, 1);
3594
3595 local_irq_restore(flags);
3596 return 0;
3597 }
3598
3599 static int
3600 rs_tiocmget(struct tty_struct *tty)
3601 {
3602 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3603 unsigned int result;
3604 unsigned long flags;
3605
3606 local_irq_save(flags);
3607
3608 result =
3609 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3610 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3611 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3612 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3613 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3614 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3615
3616 local_irq_restore(flags);
3617
3618 #ifdef SERIAL_DEBUG_IO
3619 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3620 info->line, result, result);
3621 {
3622 char s[100];
3623
3624 get_control_state_str(result, s);
3625 printk(KERN_DEBUG "state: %s\n", s);
3626 }
3627 #endif
3628 return result;
3629
3630 }
3631
3632
3633 static int
3634 rs_ioctl(struct tty_struct *tty,
3635 unsigned int cmd, unsigned long arg)
3636 {
3637 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3638
3639 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3640 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3641 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3642 if (tty->flags & (1 << TTY_IO_ERROR))
3643 return -EIO;
3644 }
3645
3646 switch (cmd) {
3647 case TIOCGSERIAL:
3648 return get_serial_info(info,
3649 (struct serial_struct *) arg);
3650 case TIOCSSERIAL:
3651 return set_serial_info(info,
3652 (struct serial_struct *) arg);
3653 case TIOCSERGETLSR: /* Get line status register */
3654 return get_lsr_info(info, (unsigned int *) arg);
3655
3656 case TIOCSERGSTRUCT:
3657 if (copy_to_user((struct e100_serial *) arg,
3658 info, sizeof(struct e100_serial)))
3659 return -EFAULT;
3660 return 0;
3661
3662 #if defined(CONFIG_ETRAX_RS485)
3663 case TIOCSERSETRS485:
3664 {
3665 /* In this ioctl we still use the old structure
3666 * rs485_control for backward compatibility
3667 * (if we use serial_rs485, then old user-level code
3668 * wouldn't work anymore...).
3669 * The use of this ioctl is deprecated: use TIOCSRS485
3670 * instead.*/
3671 struct rs485_control rs485ctrl;
3672 struct serial_rs485 rs485data;
3673 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3674 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3675 sizeof(rs485ctrl)))
3676 return -EFAULT;
3677
3678 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3679 rs485data.flags = 0;
3680
3681 if (rs485ctrl.enabled)
3682 rs485data.flags |= SER_RS485_ENABLED;
3683 else
3684 rs485data.flags &= ~(SER_RS485_ENABLED);
3685
3686 if (rs485ctrl.rts_on_send)
3687 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3688 else
3689 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3690
3691 if (rs485ctrl.rts_after_sent)
3692 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3693 else
3694 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3695
3696 return e100_enable_rs485(tty, &rs485data);
3697 }
3698
3699 case TIOCSRS485:
3700 {
3701 /* This is the new version of TIOCSRS485, with new
3702 * data structure serial_rs485 */
3703 struct serial_rs485 rs485data;
3704 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3705 sizeof(rs485data)))
3706 return -EFAULT;
3707
3708 return e100_enable_rs485(tty, &rs485data);
3709 }
3710
3711 case TIOCGRS485:
3712 {
3713 struct serial_rs485 *rs485data =
3714 &(((struct e100_serial *)tty->driver_data)->rs485);
3715 /* This is the ioctl to get RS485 data from user-space */
3716 if (copy_to_user((struct serial_rs485 *) arg,
3717 rs485data,
3718 sizeof(struct serial_rs485)))
3719 return -EFAULT;
3720 break;
3721 }
3722
3723 case TIOCSERWRRS485:
3724 {
3725 struct rs485_write rs485wr;
3726 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3727 sizeof(rs485wr)))
3728 return -EFAULT;
3729
3730 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3731 }
3732 #endif
3733
3734 default:
3735 return -ENOIOCTLCMD;
3736 }
3737 return 0;
3738 }
3739
3740 static void
3741 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3742 {
3743 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3744
3745 change_speed(info);
3746
3747 /* Handle turning off CRTSCTS */
3748 if ((old_termios->c_cflag & CRTSCTS) &&
3749 !(tty->termios.c_cflag & CRTSCTS)) {
3750 tty->hw_stopped = 0;
3751 rs_start(tty);
3752 }
3753
3754 }
3755
3756 /*
3757 * ------------------------------------------------------------
3758 * rs_close()
3759 *
3760 * This routine is called when the serial port gets closed. First, we
3761 * wait for the last remaining data to be sent. Then, we unlink its
3762 * S structure from the interrupt chain if necessary, and we free
3763 * that IRQ if nothing is left in the chain.
3764 * ------------------------------------------------------------
3765 */
3766 static void
3767 rs_close(struct tty_struct *tty, struct file * filp)
3768 {
3769 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3770 unsigned long flags;
3771
3772 if (!info)
3773 return;
3774
3775 /* interrupts are disabled for this entire function */
3776
3777 local_irq_save(flags);
3778
3779 if (tty_hung_up_p(filp)) {
3780 local_irq_restore(flags);
3781 return;
3782 }
3783
3784 #ifdef SERIAL_DEBUG_OPEN
3785 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3786 info->line, info->count);
3787 #endif
3788 if ((tty->count == 1) && (info->count != 1)) {
3789 /*
3790 * Uh, oh. tty->count is 1, which means that the tty
3791 * structure will be freed. Info->count should always
3792 * be one in these conditions. If it's greater than
3793 * one, we've got real problems, since it means the
3794 * serial port won't be shutdown.
3795 */
3796 printk(KERN_ERR
3797 "rs_close: bad serial port count; tty->count is 1, "
3798 "info->count is %d\n", info->count);
3799 info->count = 1;
3800 }
3801 if (--info->count < 0) {
3802 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
3803 info->line, info->count);
3804 info->count = 0;
3805 }
3806 if (info->count) {
3807 local_irq_restore(flags);
3808 return;
3809 }
3810 info->flags |= ASYNC_CLOSING;
3811 /*
3812 * Save the termios structure, since this port may have
3813 * separate termios for callout and dialin.
3814 */
3815 if (info->flags & ASYNC_NORMAL_ACTIVE)
3816 info->normal_termios = tty->termios;
3817 /*
3818 * Now we wait for the transmit buffer to clear; and we notify
3819 * the line discipline to only process XON/XOFF characters.
3820 */
3821 tty->closing = 1;
3822 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3823 tty_wait_until_sent(tty, info->closing_wait);
3824 /*
3825 * At this point we stop accepting input. To do this, we
3826 * disable the serial receiver and the DMA receive interrupt.
3827 */
3828 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3829 e100_disable_serial_data_irq(info);
3830 #endif
3831
3832 #ifndef CONFIG_SVINTO_SIM
3833 e100_disable_rx(info);
3834 e100_disable_rx_irq(info);
3835
3836 if (info->flags & ASYNC_INITIALIZED) {
3837 /*
3838 * Before we drop DTR, make sure the UART transmitter
3839 * has completely drained; this is especially
3840 * important as we have a transmit FIFO!
3841 */
3842 rs_wait_until_sent(tty, HZ);
3843 }
3844 #endif
3845
3846 shutdown(info);
3847 rs_flush_buffer(tty);
3848 tty_ldisc_flush(tty);
3849 tty->closing = 0;
3850 info->event = 0;
3851 info->port.tty = NULL;
3852 if (info->blocked_open) {
3853 if (info->close_delay)
3854 schedule_timeout_interruptible(info->close_delay);
3855 wake_up_interruptible(&info->open_wait);
3856 }
3857 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3858 wake_up_interruptible(&info->close_wait);
3859 local_irq_restore(flags);
3860
3861 /* port closed */
3862
3863 #if defined(CONFIG_ETRAX_RS485)
3864 if (info->rs485.flags & SER_RS485_ENABLED) {
3865 info->rs485.flags &= ~(SER_RS485_ENABLED);
3866 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3867 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3868 #endif
3869 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3870 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3871 rs485_port_g_bit, 0);
3872 #endif
3873 #if defined(CONFIG_ETRAX_RS485_LTC1387)
3874 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3875 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3876 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3877 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3878 #endif
3879 }
3880 #endif
3881
3882 /*
3883 * Release any allocated DMA irq's.
3884 */
3885 if (info->dma_in_enabled) {
3886 free_irq(info->dma_in_irq_nbr, info);
3887 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3888 info->uses_dma_in = 0;
3889 #ifdef SERIAL_DEBUG_OPEN
3890 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3891 info->dma_in_irq_description);
3892 #endif
3893 }
3894 if (info->dma_out_enabled) {
3895 free_irq(info->dma_out_irq_nbr, info);
3896 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3897 info->uses_dma_out = 0;
3898 #ifdef SERIAL_DEBUG_OPEN
3899 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3900 info->dma_out_irq_description);
3901 #endif
3902 }
3903 }
3904
3905 /*
3906 * rs_wait_until_sent() --- wait until the transmitter is empty
3907 */
3908 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3909 {
3910 unsigned long orig_jiffies;
3911 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3912 unsigned long curr_time = jiffies;
3913 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3914 long elapsed_usec =
3915 (curr_time - info->last_tx_active) * (1000000/HZ) +
3916 curr_time_usec - info->last_tx_active_usec;
3917
3918 /*
3919 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3920 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3921 */
3922 orig_jiffies = jiffies;
3923 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3924 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3925 (elapsed_usec < 2*info->char_time_usec)) {
3926 schedule_timeout_interruptible(1);
3927 if (signal_pending(current))
3928 break;
3929 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3930 break;
3931 curr_time = jiffies;
3932 curr_time_usec = GET_JIFFIES_USEC();
3933 elapsed_usec =
3934 (curr_time - info->last_tx_active) * (1000000/HZ) +
3935 curr_time_usec - info->last_tx_active_usec;
3936 }
3937 set_current_state(TASK_RUNNING);
3938 }
3939
3940 /*
3941 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3942 */
3943 void
3944 rs_hangup(struct tty_struct *tty)
3945 {
3946 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3947
3948 rs_flush_buffer(tty);
3949 shutdown(info);
3950 info->event = 0;
3951 info->count = 0;
3952 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3953 info->port.tty = NULL;
3954 wake_up_interruptible(&info->open_wait);
3955 }
3956
3957 /*
3958 * ------------------------------------------------------------
3959 * rs_open() and friends
3960 * ------------------------------------------------------------
3961 */
3962 static int
3963 block_til_ready(struct tty_struct *tty, struct file * filp,
3964 struct e100_serial *info)
3965 {
3966 DECLARE_WAITQUEUE(wait, current);
3967 unsigned long flags;
3968 int retval;
3969 int do_clocal = 0, extra_count = 0;
3970
3971 /*
3972 * If the device is in the middle of being closed, then block
3973 * until it's done, and then try again.
3974 */
3975 if (tty_hung_up_p(filp) ||
3976 (info->flags & ASYNC_CLOSING)) {
3977 wait_event_interruptible_tty(tty, info->close_wait,
3978 !(info->flags & ASYNC_CLOSING));
3979 #ifdef SERIAL_DO_RESTART
3980 if (info->flags & ASYNC_HUP_NOTIFY)
3981 return -EAGAIN;
3982 else
3983 return -ERESTARTSYS;
3984 #else
3985 return -EAGAIN;
3986 #endif
3987 }
3988
3989 /*
3990 * If non-blocking mode is set, or the port is not enabled,
3991 * then make the check up front and then exit.
3992 */
3993 if ((filp->f_flags & O_NONBLOCK) ||
3994 (tty->flags & (1 << TTY_IO_ERROR))) {
3995 info->flags |= ASYNC_NORMAL_ACTIVE;
3996 return 0;
3997 }
3998
3999 if (tty->termios.c_cflag & CLOCAL) {
4000 do_clocal = 1;
4001 }
4002
4003 /*
4004 * Block waiting for the carrier detect and the line to become
4005 * free (i.e., not in use by the callout). While we are in
4006 * this loop, info->count is dropped by one, so that
4007 * rs_close() knows when to free things. We restore it upon
4008 * exit, either normal or abnormal.
4009 */
4010 retval = 0;
4011 add_wait_queue(&info->open_wait, &wait);
4012 #ifdef SERIAL_DEBUG_OPEN
4013 printk("block_til_ready before block: ttyS%d, count = %d\n",
4014 info->line, info->count);
4015 #endif
4016 local_irq_save(flags);
4017 if (!tty_hung_up_p(filp)) {
4018 extra_count++;
4019 info->count--;
4020 }
4021 local_irq_restore(flags);
4022 info->blocked_open++;
4023 while (1) {
4024 local_irq_save(flags);
4025 /* assert RTS and DTR */
4026 e100_rts(info, 1);
4027 e100_dtr(info, 1);
4028 local_irq_restore(flags);
4029 set_current_state(TASK_INTERRUPTIBLE);
4030 if (tty_hung_up_p(filp) ||
4031 !(info->flags & ASYNC_INITIALIZED)) {
4032 #ifdef SERIAL_DO_RESTART
4033 if (info->flags & ASYNC_HUP_NOTIFY)
4034 retval = -EAGAIN;
4035 else
4036 retval = -ERESTARTSYS;
4037 #else
4038 retval = -EAGAIN;
4039 #endif
4040 break;
4041 }
4042 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4043 /* && (do_clocal || DCD_IS_ASSERTED) */
4044 break;
4045 if (signal_pending(current)) {
4046 retval = -ERESTARTSYS;
4047 break;
4048 }
4049 #ifdef SERIAL_DEBUG_OPEN
4050 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4051 info->line, info->count);
4052 #endif
4053 tty_unlock(tty);
4054 schedule();
4055 tty_lock(tty);
4056 }
4057 set_current_state(TASK_RUNNING);
4058 remove_wait_queue(&info->open_wait, &wait);
4059 if (extra_count)
4060 info->count++;
4061 info->blocked_open--;
4062 #ifdef SERIAL_DEBUG_OPEN
4063 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4064 info->line, info->count);
4065 #endif
4066 if (retval)
4067 return retval;
4068 info->flags |= ASYNC_NORMAL_ACTIVE;
4069 return 0;
4070 }
4071
4072 static void
4073 deinit_port(struct e100_serial *info)
4074 {
4075 if (info->dma_out_enabled) {
4076 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4077 free_irq(info->dma_out_irq_nbr, info);
4078 }
4079 if (info->dma_in_enabled) {
4080 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4081 free_irq(info->dma_in_irq_nbr, info);
4082 }
4083 }
4084
4085 /*
4086 * This routine is called whenever a serial port is opened.
4087 * It performs the serial-specific initialization for the tty structure.
4088 */
4089 static int
4090 rs_open(struct tty_struct *tty, struct file * filp)
4091 {
4092 struct e100_serial *info;
4093 int retval;
4094 int allocated_resources = 0;
4095
4096 info = rs_table + tty->index;
4097 if (!info->enabled)
4098 return -ENODEV;
4099
4100 #ifdef SERIAL_DEBUG_OPEN
4101 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4102 info->count);
4103 #endif
4104
4105 info->count++;
4106 tty->driver_data = info;
4107 info->port.tty = tty;
4108
4109 tty->low_latency = !!(info->flags & ASYNC_LOW_LATENCY);
4110
4111 /*
4112 * If the port is in the middle of closing, bail out now
4113 */
4114 if (tty_hung_up_p(filp) ||
4115 (info->flags & ASYNC_CLOSING)) {
4116 wait_event_interruptible_tty(tty, info->close_wait,
4117 !(info->flags & ASYNC_CLOSING));
4118 #ifdef SERIAL_DO_RESTART
4119 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4120 -EAGAIN : -ERESTARTSYS);
4121 #else
4122 return -EAGAIN;
4123 #endif
4124 }
4125
4126 /*
4127 * If DMA is enabled try to allocate the irq's.
4128 */
4129 if (info->count == 1) {
4130 allocated_resources = 1;
4131 if (info->dma_in_enabled) {
4132 if (request_irq(info->dma_in_irq_nbr,
4133 rec_interrupt,
4134 info->dma_in_irq_flags,
4135 info->dma_in_irq_description,
4136 info)) {
4137 printk(KERN_WARNING "DMA irq '%s' busy; "
4138 "falling back to non-DMA mode\n",
4139 info->dma_in_irq_description);
4140 /* Make sure we never try to use DMA in */
4141 /* for the port again. */
4142 info->dma_in_enabled = 0;
4143 } else if (cris_request_dma(info->dma_in_nbr,
4144 info->dma_in_irq_description,
4145 DMA_VERBOSE_ON_ERROR,
4146 info->dma_owner)) {
4147 free_irq(info->dma_in_irq_nbr, info);
4148 printk(KERN_WARNING "DMA '%s' busy; "
4149 "falling back to non-DMA mode\n",
4150 info->dma_in_irq_description);
4151 /* Make sure we never try to use DMA in */
4152 /* for the port again. */
4153 info->dma_in_enabled = 0;
4154 }
4155 #ifdef SERIAL_DEBUG_OPEN
4156 else
4157 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4158 info->dma_in_irq_description);
4159 #endif
4160 }
4161 if (info->dma_out_enabled) {
4162 if (request_irq(info->dma_out_irq_nbr,
4163 tr_interrupt,
4164 info->dma_out_irq_flags,
4165 info->dma_out_irq_description,
4166 info)) {
4167 printk(KERN_WARNING "DMA irq '%s' busy; "
4168 "falling back to non-DMA mode\n",
4169 info->dma_out_irq_description);
4170 /* Make sure we never try to use DMA out */
4171 /* for the port again. */
4172 info->dma_out_enabled = 0;
4173 } else if (cris_request_dma(info->dma_out_nbr,
4174 info->dma_out_irq_description,
4175 DMA_VERBOSE_ON_ERROR,
4176 info->dma_owner)) {
4177 free_irq(info->dma_out_irq_nbr, info);
4178 printk(KERN_WARNING "DMA '%s' busy; "
4179 "falling back to non-DMA mode\n",
4180 info->dma_out_irq_description);
4181 /* Make sure we never try to use DMA out */
4182 /* for the port again. */
4183 info->dma_out_enabled = 0;
4184 }
4185 #ifdef SERIAL_DEBUG_OPEN
4186 else
4187 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4188 info->dma_out_irq_description);
4189 #endif
4190 }
4191 }
4192
4193 /*
4194 * Start up the serial port
4195 */
4196
4197 retval = startup(info);
4198 if (retval) {
4199 if (allocated_resources)
4200 deinit_port(info);
4201
4202 /* FIXME Decrease count info->count here too? */
4203 return retval;
4204 }
4205
4206
4207 retval = block_til_ready(tty, filp, info);
4208 if (retval) {
4209 #ifdef SERIAL_DEBUG_OPEN
4210 printk("rs_open returning after block_til_ready with %d\n",
4211 retval);
4212 #endif
4213 if (allocated_resources)
4214 deinit_port(info);
4215
4216 return retval;
4217 }
4218
4219 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4220 tty->termios = info->normal_termios;
4221 change_speed(info);
4222 }
4223
4224 #ifdef SERIAL_DEBUG_OPEN
4225 printk("rs_open ttyS%d successful...\n", info->line);
4226 #endif
4227 DLOG_INT_TRIG( log_int_pos = 0);
4228
4229 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4230 info->icount.rx = 0;
4231 } );
4232
4233 return 0;
4234 }
4235
4236 #ifdef CONFIG_PROC_FS
4237 /*
4238 * /proc fs routines....
4239 */
4240
4241 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4242 {
4243 unsigned long tmp;
4244
4245 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4246 info->line, (unsigned long)info->ioport, info->irq);
4247
4248 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4249 seq_printf(m, "\n");
4250 return;
4251 }
4252
4253 seq_printf(m, " baud:%d", info->baud);
4254 seq_printf(m, " tx:%lu rx:%lu",
4255 (unsigned long)info->icount.tx,
4256 (unsigned long)info->icount.rx);
4257 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4258 if (tmp)
4259 seq_printf(m, " tx_pend:%lu/%lu",
4260 (unsigned long)tmp,
4261 (unsigned long)SERIAL_XMIT_SIZE);
4262
4263 seq_printf(m, " rx_pend:%lu/%lu",
4264 (unsigned long)info->recv_cnt,
4265 (unsigned long)info->max_recv_cnt);
4266
4267 #if 1
4268 if (info->port.tty) {
4269 if (info->port.tty->stopped)
4270 seq_printf(m, " stopped:%i",
4271 (int)info->port.tty->stopped);
4272 if (info->port.tty->hw_stopped)
4273 seq_printf(m, " hw_stopped:%i",
4274 (int)info->port.tty->hw_stopped);
4275 }
4276
4277 {
4278 unsigned char rstat = info->ioport[REG_STATUS];
4279 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4280 seq_printf(m, " xoff_detect:1");
4281 }
4282
4283 #endif
4284
4285 if (info->icount.frame)
4286 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4287
4288 if (info->icount.parity)
4289 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4290
4291 if (info->icount.brk)
4292 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4293
4294 if (info->icount.overrun)
4295 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4296
4297 /*
4298 * Last thing is the RS-232 status lines
4299 */
4300 if (!E100_RTS_GET(info))
4301 seq_puts(m, "|RTS");
4302 if (!E100_CTS_GET(info))
4303 seq_puts(m, "|CTS");
4304 if (!E100_DTR_GET(info))
4305 seq_puts(m, "|DTR");
4306 if (!E100_DSR_GET(info))
4307 seq_puts(m, "|DSR");
4308 if (!E100_CD_GET(info))
4309 seq_puts(m, "|CD");
4310 if (!E100_RI_GET(info))
4311 seq_puts(m, "|RI");
4312 seq_puts(m, "\n");
4313 }
4314
4315
4316 static int crisv10_proc_show(struct seq_file *m, void *v)
4317 {
4318 int i;
4319
4320 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4321
4322 for (i = 0; i < NR_PORTS; i++) {
4323 if (!rs_table[i].enabled)
4324 continue;
4325 seq_line_info(m, &rs_table[i]);
4326 }
4327 #ifdef DEBUG_LOG_INCLUDED
4328 for (i = 0; i < debug_log_pos; i++) {
4329 seq_printf(m, "%-4i %lu.%lu ",
4330 i, debug_log[i].time,
4331 timer_data_to_ns(debug_log[i].timer_data));
4332 seq_printf(m, debug_log[i].string, debug_log[i].value);
4333 }
4334 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4335 debug_log_pos = 0;
4336 #endif
4337 return 0;
4338 }
4339
4340 static int crisv10_proc_open(struct inode *inode, struct file *file)
4341 {
4342 return single_open(file, crisv10_proc_show, NULL);
4343 }
4344
4345 static const struct file_operations crisv10_proc_fops = {
4346 .owner = THIS_MODULE,
4347 .open = crisv10_proc_open,
4348 .read = seq_read,
4349 .llseek = seq_lseek,
4350 .release = single_release,
4351 };
4352 #endif
4353
4354
4355 /* Finally, routines used to initialize the serial driver. */
4356
4357 static void show_serial_version(void)
4358 {
4359 printk(KERN_INFO
4360 "ETRAX 100LX serial-driver %s, "
4361 "(c) 2000-2004 Axis Communications AB\r\n",
4362 &serial_version[11]); /* "$Revision: x.yy" */
4363 }
4364
4365 /* rs_init inits the driver at boot (using the module_init chain) */
4366
4367 static const struct tty_operations rs_ops = {
4368 .open = rs_open,
4369 .close = rs_close,
4370 .write = rs_write,
4371 .flush_chars = rs_flush_chars,
4372 .write_room = rs_write_room,
4373 .chars_in_buffer = rs_chars_in_buffer,
4374 .flush_buffer = rs_flush_buffer,
4375 .ioctl = rs_ioctl,
4376 .throttle = rs_throttle,
4377 .unthrottle = rs_unthrottle,
4378 .set_termios = rs_set_termios,
4379 .stop = rs_stop,
4380 .start = rs_start,
4381 .hangup = rs_hangup,
4382 .break_ctl = rs_break,
4383 .send_xchar = rs_send_xchar,
4384 .wait_until_sent = rs_wait_until_sent,
4385 .tiocmget = rs_tiocmget,
4386 .tiocmset = rs_tiocmset,
4387 #ifdef CONFIG_PROC_FS
4388 .proc_fops = &crisv10_proc_fops,
4389 #endif
4390 };
4391
4392 static int __init rs_init(void)
4393 {
4394 int i;
4395 struct e100_serial *info;
4396 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4397
4398 if (!driver)
4399 return -ENOMEM;
4400
4401 show_serial_version();
4402
4403 /* Setup the timed flush handler system */
4404
4405 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4406 setup_timer(&flush_timer, timed_flush_handler, 0);
4407 mod_timer(&flush_timer, jiffies + 5);
4408 #endif
4409
4410 #if defined(CONFIG_ETRAX_RS485)
4411 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4412 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
4413 rs485_pa_bit)) {
4414 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4415 "RS485 pin\n");
4416 put_tty_driver(driver);
4417 return -EBUSY;
4418 }
4419 #endif
4420 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4421 if (cris_io_interface_allocate_pins(if_serial_0, 'g', rs485_pa_bit,
4422 rs485_port_g_bit)) {
4423 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4424 "RS485 pin\n");
4425 put_tty_driver(driver);
4426 return -EBUSY;
4427 }
4428 #endif
4429 #endif
4430
4431 /* Initialize the tty_driver structure */
4432
4433 driver->driver_name = "serial";
4434 driver->name = "ttyS";
4435 driver->major = TTY_MAJOR;
4436 driver->minor_start = 64;
4437 driver->type = TTY_DRIVER_TYPE_SERIAL;
4438 driver->subtype = SERIAL_TYPE_NORMAL;
4439 driver->init_termios = tty_std_termios;
4440 driver->init_termios.c_cflag =
4441 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4442 driver->init_termios.c_ispeed = 115200;
4443 driver->init_termios.c_ospeed = 115200;
4444 driver->flags = TTY_DRIVER_REAL_RAW;
4445
4446 tty_set_operations(driver, &rs_ops);
4447 serial_driver = driver;
4448
4449 /* do some initializing for the separate ports */
4450 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4451 if (info->enabled) {
4452 if (cris_request_io_interface(info->io_if,
4453 info->io_if_description)) {
4454 printk(KERN_ERR "ETRAX100LX async serial: "
4455 "Could not allocate IO pins for "
4456 "%s, port %d\n",
4457 info->io_if_description, i);
4458 info->enabled = 0;
4459 }
4460 }
4461 tty_port_init(&info->port);
4462 info->uses_dma_in = 0;
4463 info->uses_dma_out = 0;
4464 info->line = i;
4465 info->port.tty = NULL;
4466 info->type = PORT_ETRAX;
4467 info->tr_running = 0;
4468 info->forced_eop = 0;
4469 info->baud_base = DEF_BAUD_BASE;
4470 info->custom_divisor = 0;
4471 info->flags = 0;
4472 info->close_delay = 5*HZ/10;
4473 info->closing_wait = 30*HZ;
4474 info->x_char = 0;
4475 info->event = 0;
4476 info->count = 0;
4477 info->blocked_open = 0;
4478 info->normal_termios = driver->init_termios;
4479 init_waitqueue_head(&info->open_wait);
4480 init_waitqueue_head(&info->close_wait);
4481 info->xmit.buf = NULL;
4482 info->xmit.tail = info->xmit.head = 0;
4483 info->first_recv_buffer = info->last_recv_buffer = NULL;
4484 info->recv_cnt = info->max_recv_cnt = 0;
4485 info->last_tx_active_usec = 0;
4486 info->last_tx_active = 0;
4487
4488 #if defined(CONFIG_ETRAX_RS485)
4489 /* Set sane defaults */
4490 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4491 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4492 info->rs485.delay_rts_before_send = 0;
4493 info->rs485.flags &= ~(SER_RS485_ENABLED);
4494 #endif
4495 INIT_WORK(&info->work, do_softint);
4496
4497 if (info->enabled) {
4498 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4499 serial_driver->name, info->line, info->ioport);
4500 }
4501 tty_port_link_device(&info->port, driver, i);
4502 }
4503
4504 if (tty_register_driver(driver))
4505 panic("Couldn't register serial driver\n");
4506
4507 #ifdef CONFIG_ETRAX_FAST_TIMER
4508 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4509 memset(fast_timers, 0, sizeof(fast_timers));
4510 #endif
4511 #ifdef CONFIG_ETRAX_RS485
4512 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4513 #endif
4514 fast_timer_init();
4515 #endif
4516
4517 #ifndef CONFIG_SVINTO_SIM
4518 #ifndef CONFIG_ETRAX_KGDB
4519 /* Not needed in simulator. May only complicate stuff. */
4520 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4521
4522 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4523 IRQF_SHARED, "serial ", driver))
4524 panic("%s: Failed to request irq8", __func__);
4525
4526 #endif
4527 #endif /* CONFIG_SVINTO_SIM */
4528
4529 return 0;
4530 }
4531
4532 /* this makes sure that rs_init is called during kernel boot */
4533
4534 module_init(rs_init);
kernel source for telekom puls (alcatel/mediatek)