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mm: mm_event: fix compact_scan
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / thermal / rockchip_thermal.c
1 /*
2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Caesar Wang <wxt@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/thermal.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /**
31 * If the temperature over a period of time High,
32 * the resulting TSHUT gave CRU module,let it reset the entire chip,
33 * or via GPIO give PMIC.
34 */
35 enum tshut_mode {
36 TSHUT_MODE_CRU = 0,
37 TSHUT_MODE_GPIO,
38 };
39
40 /**
41 * The system Temperature Sensors tshut(tshut) polarity
42 * the bit 8 is tshut polarity.
43 * 0: low active, 1: high active
44 */
45 enum tshut_polarity {
46 TSHUT_LOW_ACTIVE = 0,
47 TSHUT_HIGH_ACTIVE,
48 };
49
50 /**
51 * The system has two Temperature Sensors.
52 * sensor0 is for CPU, and sensor1 is for GPU.
53 */
54 enum sensor_id {
55 SENSOR_CPU = 0,
56 SENSOR_GPU,
57 };
58
59 /**
60 * The conversion table has the adc value and temperature.
61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
63 */
64 enum adc_sort_mode {
65 ADC_DECREMENT = 0,
66 ADC_INCREMENT,
67 };
68
69 /**
70 * The max sensors is two in rockchip SoCs.
71 * Two sensors: CPU and GPU sensor.
72 */
73 #define SOC_MAX_SENSORS 2
74
75 /**
76 * struct chip_tsadc_table - hold information about chip-specific differences
77 * @id: conversion table
78 * @length: size of conversion table
79 * @data_mask: mask to apply on data inputs
80 * @mode: sort mode of this adc variant (incrementing or decrementing)
81 */
82 struct chip_tsadc_table {
83 const struct tsadc_table *id;
84 unsigned int length;
85 u32 data_mask;
86 enum adc_sort_mode mode;
87 };
88
89 /**
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @tshut_temp: the hardware-controlled shutdown temperature value
94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
96 * @initialize: SoC special initialize tsadc controller method
97 * @irq_ack: clear the interrupt
98 * @get_temp: get the temperature
99 * @set_alarm_temp: set the high temperature interrupt
100 * @set_tshut_temp: set the hardware-controlled shutdown temperature
101 * @set_tshut_mode: set the hardware-controlled shutdown mode
102 * @table: the chip-specific conversion table
103 */
104 struct rockchip_tsadc_chip {
105 /* The sensor id of chip correspond to the ADC channel */
106 int chn_id[SOC_MAX_SENSORS];
107 int chn_num;
108
109 /* The hardware-controlled tshut property */
110 int tshut_temp;
111 enum tshut_mode tshut_mode;
112 enum tshut_polarity tshut_polarity;
113
114 /* Chip-wide methods */
115 void (*initialize)(struct regmap *grf,
116 void __iomem *reg, enum tshut_polarity p);
117 void (*irq_ack)(void __iomem *reg);
118 void (*control)(void __iomem *reg, bool on);
119
120 /* Per-sensor methods */
121 int (*get_temp)(const struct chip_tsadc_table *table,
122 int chn, void __iomem *reg, int *temp);
123 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
124 int chn, void __iomem *reg, int temp);
125 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
126 int chn, void __iomem *reg, int temp);
127 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
128
129 /* Per-table methods */
130 struct chip_tsadc_table table;
131 };
132
133 /**
134 * struct rockchip_thermal_sensor - hold the information of thermal sensor
135 * @thermal: pointer to the platform/configuration data
136 * @tzd: pointer to a thermal zone
137 * @id: identifier of the thermal sensor
138 */
139 struct rockchip_thermal_sensor {
140 struct rockchip_thermal_data *thermal;
141 struct thermal_zone_device *tzd;
142 int id;
143 };
144
145 /**
146 * struct rockchip_thermal_data - hold the private data of thermal driver
147 * @chip: pointer to the platform/configuration data
148 * @pdev: platform device of thermal
149 * @reset: the reset controller of tsadc
150 * @sensors[SOC_MAX_SENSORS]: the thermal sensor
151 * @clk: the controller clock is divided by the exteral 24MHz
152 * @pclk: the advanced peripherals bus clock
153 * @grf: the general register file will be used to do static set by software
154 * @regs: the base address of tsadc controller
155 * @tshut_temp: the hardware-controlled shutdown temperature value
156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
158 */
159 struct rockchip_thermal_data {
160 const struct rockchip_tsadc_chip *chip;
161 struct platform_device *pdev;
162 struct reset_control *reset;
163
164 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
165
166 struct clk *clk;
167 struct clk *pclk;
168
169 struct regmap *grf;
170 void __iomem *regs;
171
172 int tshut_temp;
173 enum tshut_mode tshut_mode;
174 enum tshut_polarity tshut_polarity;
175 };
176
177 /**
178 * TSADC Sensor Register description:
179 *
180 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
181 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
182 *
183 */
184 #define TSADCV2_USER_CON 0x00
185 #define TSADCV2_AUTO_CON 0x04
186 #define TSADCV2_INT_EN 0x08
187 #define TSADCV2_INT_PD 0x0c
188 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
189 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
190 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
191 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
192 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
193 #define TSADCV2_AUTO_PERIOD 0x68
194 #define TSADCV2_AUTO_PERIOD_HT 0x6c
195
196 #define TSADCV2_AUTO_EN BIT(0)
197 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
198 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
199
200 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
201
202 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
203 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
204 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
205
206 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
207 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
208
209 #define TSADCV2_DATA_MASK 0xfff
210 #define TSADCV3_DATA_MASK 0x3ff
211
212 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
213 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
214 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
215 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
216 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
217 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
218
219 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
220
221 #define GRF_SARADC_TESTBIT 0x0e644
222 #define GRF_TSADC_TESTBIT_L 0x0e648
223 #define GRF_TSADC_TESTBIT_H 0x0e64c
224
225 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
226 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
227 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
228 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
229
230 /**
231 * struct tsadc_table - code to temperature conversion table
232 * @code: the value of adc channel
233 * @temp: the temperature
234 * Note:
235 * code to temperature mapping of the temperature sensor is a piece wise linear
236 * curve.Any temperature, code faling between to 2 give temperatures can be
237 * linearly interpolated.
238 * Code to Temperature mapping should be updated based on manufacturer results.
239 */
240 struct tsadc_table {
241 u32 code;
242 int temp;
243 };
244
245 static const struct tsadc_table rk3228_code_table[] = {
246 {0, -40000},
247 {588, -40000},
248 {593, -35000},
249 {598, -30000},
250 {603, -25000},
251 {608, -20000},
252 {613, -15000},
253 {618, -10000},
254 {623, -5000},
255 {629, 0},
256 {634, 5000},
257 {639, 10000},
258 {644, 15000},
259 {649, 20000},
260 {654, 25000},
261 {660, 30000},
262 {665, 35000},
263 {670, 40000},
264 {675, 45000},
265 {681, 50000},
266 {686, 55000},
267 {691, 60000},
268 {696, 65000},
269 {702, 70000},
270 {707, 75000},
271 {712, 80000},
272 {717, 85000},
273 {723, 90000},
274 {728, 95000},
275 {733, 100000},
276 {738, 105000},
277 {744, 110000},
278 {749, 115000},
279 {754, 120000},
280 {760, 125000},
281 {TSADCV2_DATA_MASK, 125000},
282 };
283
284 static const struct tsadc_table rk3288_code_table[] = {
285 {TSADCV2_DATA_MASK, -40000},
286 {3800, -40000},
287 {3792, -35000},
288 {3783, -30000},
289 {3774, -25000},
290 {3765, -20000},
291 {3756, -15000},
292 {3747, -10000},
293 {3737, -5000},
294 {3728, 0},
295 {3718, 5000},
296 {3708, 10000},
297 {3698, 15000},
298 {3688, 20000},
299 {3678, 25000},
300 {3667, 30000},
301 {3656, 35000},
302 {3645, 40000},
303 {3634, 45000},
304 {3623, 50000},
305 {3611, 55000},
306 {3600, 60000},
307 {3588, 65000},
308 {3575, 70000},
309 {3563, 75000},
310 {3550, 80000},
311 {3537, 85000},
312 {3524, 90000},
313 {3510, 95000},
314 {3496, 100000},
315 {3482, 105000},
316 {3467, 110000},
317 {3452, 115000},
318 {3437, 120000},
319 {3421, 125000},
320 {0, 125000},
321 };
322
323 static const struct tsadc_table rk3328_code_table[] = {
324 {0, -40000},
325 {296, -40000},
326 {304, -35000},
327 {313, -30000},
328 {331, -20000},
329 {340, -15000},
330 {349, -10000},
331 {359, -5000},
332 {368, 0},
333 {378, 5000},
334 {388, 10000},
335 {398, 15000},
336 {408, 20000},
337 {418, 25000},
338 {429, 30000},
339 {440, 35000},
340 {451, 40000},
341 {462, 45000},
342 {473, 50000},
343 {485, 55000},
344 {496, 60000},
345 {508, 65000},
346 {521, 70000},
347 {533, 75000},
348 {546, 80000},
349 {559, 85000},
350 {572, 90000},
351 {586, 95000},
352 {600, 100000},
353 {614, 105000},
354 {629, 110000},
355 {644, 115000},
356 {659, 120000},
357 {675, 125000},
358 {TSADCV2_DATA_MASK, 125000},
359 };
360
361 static const struct tsadc_table rk3368_code_table[] = {
362 {0, -40000},
363 {106, -40000},
364 {108, -35000},
365 {110, -30000},
366 {112, -25000},
367 {114, -20000},
368 {116, -15000},
369 {118, -10000},
370 {120, -5000},
371 {122, 0},
372 {124, 5000},
373 {126, 10000},
374 {128, 15000},
375 {130, 20000},
376 {132, 25000},
377 {134, 30000},
378 {136, 35000},
379 {138, 40000},
380 {140, 45000},
381 {142, 50000},
382 {144, 55000},
383 {146, 60000},
384 {148, 65000},
385 {150, 70000},
386 {152, 75000},
387 {154, 80000},
388 {156, 85000},
389 {158, 90000},
390 {160, 95000},
391 {162, 100000},
392 {163, 105000},
393 {165, 110000},
394 {167, 115000},
395 {169, 120000},
396 {171, 125000},
397 {TSADCV3_DATA_MASK, 125000},
398 };
399
400 static const struct tsadc_table rk3399_code_table[] = {
401 {0, -40000},
402 {402, -40000},
403 {410, -35000},
404 {419, -30000},
405 {427, -25000},
406 {436, -20000},
407 {444, -15000},
408 {453, -10000},
409 {461, -5000},
410 {470, 0},
411 {478, 5000},
412 {487, 10000},
413 {496, 15000},
414 {504, 20000},
415 {513, 25000},
416 {521, 30000},
417 {530, 35000},
418 {538, 40000},
419 {547, 45000},
420 {555, 50000},
421 {564, 55000},
422 {573, 60000},
423 {581, 65000},
424 {590, 70000},
425 {599, 75000},
426 {607, 80000},
427 {616, 85000},
428 {624, 90000},
429 {633, 95000},
430 {642, 100000},
431 {650, 105000},
432 {659, 110000},
433 {668, 115000},
434 {677, 120000},
435 {685, 125000},
436 {TSADCV3_DATA_MASK, 125000},
437 };
438
439 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
440 int temp)
441 {
442 int high, low, mid;
443 unsigned long num;
444 unsigned int denom;
445 u32 error = table->data_mask;
446
447 low = 0;
448 high = (table->length - 1) - 1; /* ignore the last check for table */
449 mid = (high + low) / 2;
450
451 /* Return mask code data when the temp is over table range */
452 if (temp < table->id[low].temp || temp > table->id[high].temp)
453 goto exit;
454
455 while (low <= high) {
456 if (temp == table->id[mid].temp)
457 return table->id[mid].code;
458 else if (temp < table->id[mid].temp)
459 high = mid - 1;
460 else
461 low = mid + 1;
462 mid = (low + high) / 2;
463 }
464
465 /*
466 * The conversion code granularity provided by the table. Let's
467 * assume that the relationship between temperature and
468 * analog value between 2 table entries is linear and interpolate
469 * to produce less granular result.
470 */
471 num = abs(table->id[mid + 1].code - table->id[mid].code);
472 num *= temp - table->id[mid].temp;
473 denom = table->id[mid + 1].temp - table->id[mid].temp;
474
475 switch (table->mode) {
476 case ADC_DECREMENT:
477 return table->id[mid].code - (num / denom);
478 case ADC_INCREMENT:
479 return table->id[mid].code + (num / denom);
480 default:
481 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
482 return error;
483 }
484
485 exit:
486 pr_err("%s: invalid temperature, temp=%d error=%d\n",
487 __func__, temp, error);
488 return error;
489 }
490
491 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
492 u32 code, int *temp)
493 {
494 unsigned int low = 1;
495 unsigned int high = table->length - 1;
496 unsigned int mid = (low + high) / 2;
497 unsigned int num;
498 unsigned long denom;
499
500 WARN_ON(table->length < 2);
501
502 switch (table->mode) {
503 case ADC_DECREMENT:
504 code &= table->data_mask;
505 if (code <= table->id[high].code)
506 return -EAGAIN; /* Incorrect reading */
507
508 while (low <= high) {
509 if (code >= table->id[mid].code &&
510 code < table->id[mid - 1].code)
511 break;
512 else if (code < table->id[mid].code)
513 low = mid + 1;
514 else
515 high = mid - 1;
516
517 mid = (low + high) / 2;
518 }
519 break;
520 case ADC_INCREMENT:
521 code &= table->data_mask;
522 if (code < table->id[low].code)
523 return -EAGAIN; /* Incorrect reading */
524
525 while (low <= high) {
526 if (code <= table->id[mid].code &&
527 code > table->id[mid - 1].code)
528 break;
529 else if (code > table->id[mid].code)
530 low = mid + 1;
531 else
532 high = mid - 1;
533
534 mid = (low + high) / 2;
535 }
536 break;
537 default:
538 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
539 return -EINVAL;
540 }
541
542 /*
543 * The 5C granularity provided by the table is too much. Let's
544 * assume that the relationship between sensor readings and
545 * temperature between 2 table entries is linear and interpolate
546 * to produce less granular result.
547 */
548 num = table->id[mid].temp - table->id[mid - 1].temp;
549 num *= abs(table->id[mid - 1].code - code);
550 denom = abs(table->id[mid - 1].code - table->id[mid].code);
551 *temp = table->id[mid - 1].temp + (num / denom);
552
553 return 0;
554 }
555
556 /**
557 * rk_tsadcv2_initialize - initialize TASDC Controller.
558 *
559 * (1) Set TSADC_V2_AUTO_PERIOD:
560 * Configure the interleave between every two accessing of
561 * TSADC in normal operation.
562 *
563 * (2) Set TSADCV2_AUTO_PERIOD_HT:
564 * Configure the interleave between every two accessing of
565 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
566 *
567 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
568 * If the temperature is higher than COMP_INT or COMP_SHUT for
569 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
570 */
571 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
572 enum tshut_polarity tshut_polarity)
573 {
574 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
575 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
576 regs + TSADCV2_AUTO_CON);
577 else
578 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
579 regs + TSADCV2_AUTO_CON);
580
581 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
582 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
583 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
584 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
585 regs + TSADCV2_AUTO_PERIOD_HT);
586 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
587 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
588 }
589
590 /**
591 * rk_tsadcv3_initialize - initialize TASDC Controller.
592 *
593 * (1) The tsadc control power sequence.
594 *
595 * (2) Set TSADC_V2_AUTO_PERIOD:
596 * Configure the interleave between every two accessing of
597 * TSADC in normal operation.
598 *
599 * (2) Set TSADCV2_AUTO_PERIOD_HT:
600 * Configure the interleave between every two accessing of
601 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
602 *
603 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
604 * If the temperature is higher than COMP_INT or COMP_SHUT for
605 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
606 */
607 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
608 enum tshut_polarity tshut_polarity)
609 {
610 /* The tsadc control power sequence */
611 if (IS_ERR(grf)) {
612 /* Set interleave value to workround ic time sync issue */
613 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
614 TSADCV2_USER_CON);
615
616 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
617 regs + TSADCV2_AUTO_PERIOD);
618 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
619 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
620 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
621 regs + TSADCV2_AUTO_PERIOD_HT);
622 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
623 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
624
625 } else {
626 /* Enable the voltage common mode feature */
627 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
628 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
629
630 usleep_range(15, 100); /* The spec note says at least 15 us */
631 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
632 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
633 usleep_range(90, 200); /* The spec note says at least 90 us */
634
635 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
636 regs + TSADCV2_AUTO_PERIOD);
637 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
638 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
639 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
640 regs + TSADCV2_AUTO_PERIOD_HT);
641 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
642 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
643 }
644
645 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
646 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
647 regs + TSADCV2_AUTO_CON);
648 else
649 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
650 regs + TSADCV2_AUTO_CON);
651 }
652
653 static void rk_tsadcv2_irq_ack(void __iomem *regs)
654 {
655 u32 val;
656
657 val = readl_relaxed(regs + TSADCV2_INT_PD);
658 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
659 }
660
661 static void rk_tsadcv3_irq_ack(void __iomem *regs)
662 {
663 u32 val;
664
665 val = readl_relaxed(regs + TSADCV2_INT_PD);
666 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
667 }
668
669 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
670 {
671 u32 val;
672
673 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
674 if (enable)
675 val |= TSADCV2_AUTO_EN;
676 else
677 val &= ~TSADCV2_AUTO_EN;
678
679 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
680 }
681
682 /**
683 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
684 *
685 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
686 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
687 * adc value if setting this bit to enable.
688 */
689 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
690 {
691 u32 val;
692
693 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
694 if (enable)
695 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
696 else
697 val &= ~TSADCV2_AUTO_EN;
698
699 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
700 }
701
702 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
703 int chn, void __iomem *regs, int *temp)
704 {
705 u32 val;
706
707 val = readl_relaxed(regs + TSADCV2_DATA(chn));
708
709 return rk_tsadcv2_code_to_temp(table, val, temp);
710 }
711
712 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
713 int chn, void __iomem *regs, int temp)
714 {
715 u32 alarm_value;
716 u32 int_en, int_clr;
717
718 /*
719 * In some cases, some sensors didn't need the trip points, the
720 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
721 * in the end, ignore this case and disable the high temperature
722 * interrupt.
723 */
724 if (temp == INT_MAX) {
725 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
726 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
727 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
728 return 0;
729 }
730
731 /* Make sure the value is valid */
732 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
733 if (alarm_value == table->data_mask)
734 return -ERANGE;
735
736 writel_relaxed(alarm_value & table->data_mask,
737 regs + TSADCV2_COMP_INT(chn));
738
739 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
740 int_en |= TSADCV2_INT_SRC_EN(chn);
741 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
742
743 return 0;
744 }
745
746 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
747 int chn, void __iomem *regs, int temp)
748 {
749 u32 tshut_value, val;
750
751 /* Make sure the value is valid */
752 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
753 if (tshut_value == table->data_mask)
754 return -ERANGE;
755
756 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
757
758 /* TSHUT will be valid */
759 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
760 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
761
762 return 0;
763 }
764
765 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
766 enum tshut_mode mode)
767 {
768 u32 val;
769
770 val = readl_relaxed(regs + TSADCV2_INT_EN);
771 if (mode == TSHUT_MODE_GPIO) {
772 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
773 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
774 } else {
775 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
776 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
777 }
778
779 writel_relaxed(val, regs + TSADCV2_INT_EN);
780 }
781
782 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
783 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
784 .chn_num = 1, /* one channel for tsadc */
785
786 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
787 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
788 .tshut_temp = 95000,
789
790 .initialize = rk_tsadcv2_initialize,
791 .irq_ack = rk_tsadcv3_irq_ack,
792 .control = rk_tsadcv3_control,
793 .get_temp = rk_tsadcv2_get_temp,
794 .set_alarm_temp = rk_tsadcv2_alarm_temp,
795 .set_tshut_temp = rk_tsadcv2_tshut_temp,
796 .set_tshut_mode = rk_tsadcv2_tshut_mode,
797
798 .table = {
799 .id = rk3228_code_table,
800 .length = ARRAY_SIZE(rk3228_code_table),
801 .data_mask = TSADCV3_DATA_MASK,
802 .mode = ADC_INCREMENT,
803 },
804 };
805
806 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
807 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
808 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
809 .chn_num = 2, /* two channels for tsadc */
810
811 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
812 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
813 .tshut_temp = 95000,
814
815 .initialize = rk_tsadcv2_initialize,
816 .irq_ack = rk_tsadcv2_irq_ack,
817 .control = rk_tsadcv2_control,
818 .get_temp = rk_tsadcv2_get_temp,
819 .set_alarm_temp = rk_tsadcv2_alarm_temp,
820 .set_tshut_temp = rk_tsadcv2_tshut_temp,
821 .set_tshut_mode = rk_tsadcv2_tshut_mode,
822
823 .table = {
824 .id = rk3288_code_table,
825 .length = ARRAY_SIZE(rk3288_code_table),
826 .data_mask = TSADCV2_DATA_MASK,
827 .mode = ADC_DECREMENT,
828 },
829 };
830
831 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
832 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
833 .chn_num = 1, /* one channels for tsadc */
834
835 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
836 .tshut_temp = 95000,
837
838 .initialize = rk_tsadcv2_initialize,
839 .irq_ack = rk_tsadcv3_irq_ack,
840 .control = rk_tsadcv3_control,
841 .get_temp = rk_tsadcv2_get_temp,
842 .set_alarm_temp = rk_tsadcv2_alarm_temp,
843 .set_tshut_temp = rk_tsadcv2_tshut_temp,
844 .set_tshut_mode = rk_tsadcv2_tshut_mode,
845
846 .table = {
847 .id = rk3328_code_table,
848 .length = ARRAY_SIZE(rk3328_code_table),
849 .data_mask = TSADCV2_DATA_MASK,
850 .mode = ADC_INCREMENT,
851 },
852 };
853
854 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
855 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
856 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
857 .chn_num = 2, /* two channels for tsadc */
858
859 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
860 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
861 .tshut_temp = 95000,
862
863 .initialize = rk_tsadcv3_initialize,
864 .irq_ack = rk_tsadcv3_irq_ack,
865 .control = rk_tsadcv3_control,
866 .get_temp = rk_tsadcv2_get_temp,
867 .set_alarm_temp = rk_tsadcv2_alarm_temp,
868 .set_tshut_temp = rk_tsadcv2_tshut_temp,
869 .set_tshut_mode = rk_tsadcv2_tshut_mode,
870
871 .table = {
872 .id = rk3228_code_table,
873 .length = ARRAY_SIZE(rk3228_code_table),
874 .data_mask = TSADCV3_DATA_MASK,
875 .mode = ADC_INCREMENT,
876 },
877 };
878
879 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
880 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
881 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
882 .chn_num = 2, /* two channels for tsadc */
883
884 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
885 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
886 .tshut_temp = 95000,
887
888 .initialize = rk_tsadcv2_initialize,
889 .irq_ack = rk_tsadcv2_irq_ack,
890 .control = rk_tsadcv2_control,
891 .get_temp = rk_tsadcv2_get_temp,
892 .set_alarm_temp = rk_tsadcv2_alarm_temp,
893 .set_tshut_temp = rk_tsadcv2_tshut_temp,
894 .set_tshut_mode = rk_tsadcv2_tshut_mode,
895
896 .table = {
897 .id = rk3368_code_table,
898 .length = ARRAY_SIZE(rk3368_code_table),
899 .data_mask = TSADCV3_DATA_MASK,
900 .mode = ADC_INCREMENT,
901 },
902 };
903
904 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
905 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
906 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
907 .chn_num = 2, /* two channels for tsadc */
908
909 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
910 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
911 .tshut_temp = 95000,
912
913 .initialize = rk_tsadcv3_initialize,
914 .irq_ack = rk_tsadcv3_irq_ack,
915 .control = rk_tsadcv3_control,
916 .get_temp = rk_tsadcv2_get_temp,
917 .set_alarm_temp = rk_tsadcv2_alarm_temp,
918 .set_tshut_temp = rk_tsadcv2_tshut_temp,
919 .set_tshut_mode = rk_tsadcv2_tshut_mode,
920
921 .table = {
922 .id = rk3399_code_table,
923 .length = ARRAY_SIZE(rk3399_code_table),
924 .data_mask = TSADCV3_DATA_MASK,
925 .mode = ADC_INCREMENT,
926 },
927 };
928
929 static const struct of_device_id of_rockchip_thermal_match[] = {
930 {
931 .compatible = "rockchip,rk3228-tsadc",
932 .data = (void *)&rk3228_tsadc_data,
933 },
934 {
935 .compatible = "rockchip,rk3288-tsadc",
936 .data = (void *)&rk3288_tsadc_data,
937 },
938 {
939 .compatible = "rockchip,rk3328-tsadc",
940 .data = (void *)&rk3328_tsadc_data,
941 },
942 {
943 .compatible = "rockchip,rk3366-tsadc",
944 .data = (void *)&rk3366_tsadc_data,
945 },
946 {
947 .compatible = "rockchip,rk3368-tsadc",
948 .data = (void *)&rk3368_tsadc_data,
949 },
950 {
951 .compatible = "rockchip,rk3399-tsadc",
952 .data = (void *)&rk3399_tsadc_data,
953 },
954 { /* end */ },
955 };
956 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
957
958 static void
959 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
960 {
961 struct thermal_zone_device *tzd = sensor->tzd;
962
963 tzd->ops->set_mode(tzd,
964 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
965 }
966
967 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
968 {
969 struct rockchip_thermal_data *thermal = dev;
970 int i;
971
972 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
973
974 thermal->chip->irq_ack(thermal->regs);
975
976 for (i = 0; i < thermal->chip->chn_num; i++)
977 thermal_zone_device_update(thermal->sensors[i].tzd,
978 THERMAL_EVENT_UNSPECIFIED);
979
980 return IRQ_HANDLED;
981 }
982
983 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
984 {
985 struct rockchip_thermal_sensor *sensor = _sensor;
986 struct rockchip_thermal_data *thermal = sensor->thermal;
987 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
988
989 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
990 __func__, sensor->id, low, high);
991
992 return tsadc->set_alarm_temp(&tsadc->table,
993 sensor->id, thermal->regs, high);
994 }
995
996 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
997 {
998 struct rockchip_thermal_sensor *sensor = _sensor;
999 struct rockchip_thermal_data *thermal = sensor->thermal;
1000 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1001 int retval;
1002
1003 retval = tsadc->get_temp(&tsadc->table,
1004 sensor->id, thermal->regs, out_temp);
1005 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1006 sensor->id, *out_temp, retval);
1007
1008 return retval;
1009 }
1010
1011 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1012 .get_temp = rockchip_thermal_get_temp,
1013 .set_trips = rockchip_thermal_set_trips,
1014 };
1015
1016 static int rockchip_configure_from_dt(struct device *dev,
1017 struct device_node *np,
1018 struct rockchip_thermal_data *thermal)
1019 {
1020 u32 shut_temp, tshut_mode, tshut_polarity;
1021
1022 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1023 dev_warn(dev,
1024 "Missing tshut temp property, using default %d\n",
1025 thermal->chip->tshut_temp);
1026 thermal->tshut_temp = thermal->chip->tshut_temp;
1027 } else {
1028 if (shut_temp > INT_MAX) {
1029 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1030 shut_temp);
1031 return -ERANGE;
1032 }
1033 thermal->tshut_temp = shut_temp;
1034 }
1035
1036 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1037 dev_warn(dev,
1038 "Missing tshut mode property, using default (%s)\n",
1039 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1040 "gpio" : "cru");
1041 thermal->tshut_mode = thermal->chip->tshut_mode;
1042 } else {
1043 thermal->tshut_mode = tshut_mode;
1044 }
1045
1046 if (thermal->tshut_mode > 1) {
1047 dev_err(dev, "Invalid tshut mode specified: %d\n",
1048 thermal->tshut_mode);
1049 return -EINVAL;
1050 }
1051
1052 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1053 &tshut_polarity)) {
1054 dev_warn(dev,
1055 "Missing tshut-polarity property, using default (%s)\n",
1056 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1057 "low" : "high");
1058 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1059 } else {
1060 thermal->tshut_polarity = tshut_polarity;
1061 }
1062
1063 if (thermal->tshut_polarity > 1) {
1064 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1065 thermal->tshut_polarity);
1066 return -EINVAL;
1067 }
1068
1069 /* The tsadc wont to handle the error in here since some SoCs didn't
1070 * need this property.
1071 */
1072 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1073 if (IS_ERR(thermal->grf))
1074 dev_warn(dev, "Missing rockchip,grf property\n");
1075
1076 return 0;
1077 }
1078
1079 static int
1080 rockchip_thermal_register_sensor(struct platform_device *pdev,
1081 struct rockchip_thermal_data *thermal,
1082 struct rockchip_thermal_sensor *sensor,
1083 int id)
1084 {
1085 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1086 int error;
1087
1088 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1089
1090 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1091 thermal->tshut_temp);
1092 if (error)
1093 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1094 __func__, thermal->tshut_temp, error);
1095
1096 sensor->thermal = thermal;
1097 sensor->id = id;
1098 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1099 sensor, &rockchip_of_thermal_ops);
1100 if (IS_ERR(sensor->tzd)) {
1101 error = PTR_ERR(sensor->tzd);
1102 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1103 id, error);
1104 return error;
1105 }
1106
1107 return 0;
1108 }
1109
1110 /**
1111 * Reset TSADC Controller, reset all tsadc registers.
1112 */
1113 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1114 {
1115 reset_control_assert(reset);
1116 usleep_range(10, 20);
1117 reset_control_deassert(reset);
1118 }
1119
1120 static int rockchip_thermal_probe(struct platform_device *pdev)
1121 {
1122 struct device_node *np = pdev->dev.of_node;
1123 struct rockchip_thermal_data *thermal;
1124 const struct of_device_id *match;
1125 struct resource *res;
1126 int irq;
1127 int i;
1128 int error;
1129
1130 match = of_match_node(of_rockchip_thermal_match, np);
1131 if (!match)
1132 return -ENXIO;
1133
1134 irq = platform_get_irq(pdev, 0);
1135 if (irq < 0) {
1136 dev_err(&pdev->dev, "no irq resource?\n");
1137 return -EINVAL;
1138 }
1139
1140 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1141 GFP_KERNEL);
1142 if (!thermal)
1143 return -ENOMEM;
1144
1145 thermal->pdev = pdev;
1146
1147 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1148 if (!thermal->chip)
1149 return -EINVAL;
1150
1151 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1152 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1153 if (IS_ERR(thermal->regs))
1154 return PTR_ERR(thermal->regs);
1155
1156 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1157 if (IS_ERR(thermal->reset)) {
1158 error = PTR_ERR(thermal->reset);
1159 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1160 return error;
1161 }
1162
1163 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1164 if (IS_ERR(thermal->clk)) {
1165 error = PTR_ERR(thermal->clk);
1166 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1167 return error;
1168 }
1169
1170 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1171 if (IS_ERR(thermal->pclk)) {
1172 error = PTR_ERR(thermal->pclk);
1173 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1174 error);
1175 return error;
1176 }
1177
1178 error = clk_prepare_enable(thermal->clk);
1179 if (error) {
1180 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1181 error);
1182 return error;
1183 }
1184
1185 error = clk_prepare_enable(thermal->pclk);
1186 if (error) {
1187 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1188 goto err_disable_clk;
1189 }
1190
1191 rockchip_thermal_reset_controller(thermal->reset);
1192
1193 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1194 if (error) {
1195 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1196 error);
1197 goto err_disable_pclk;
1198 }
1199
1200 thermal->chip->initialize(thermal->grf, thermal->regs,
1201 thermal->tshut_polarity);
1202
1203 for (i = 0; i < thermal->chip->chn_num; i++) {
1204 error = rockchip_thermal_register_sensor(pdev, thermal,
1205 &thermal->sensors[i],
1206 thermal->chip->chn_id[i]);
1207 if (error) {
1208 dev_err(&pdev->dev,
1209 "failed to register sensor[%d] : error = %d\n",
1210 i, error);
1211 goto err_disable_pclk;
1212 }
1213 }
1214
1215 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1216 &rockchip_thermal_alarm_irq_thread,
1217 IRQF_ONESHOT,
1218 "rockchip_thermal", thermal);
1219 if (error) {
1220 dev_err(&pdev->dev,
1221 "failed to request tsadc irq: %d\n", error);
1222 goto err_disable_pclk;
1223 }
1224
1225 thermal->chip->control(thermal->regs, true);
1226
1227 for (i = 0; i < thermal->chip->chn_num; i++)
1228 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1229
1230 platform_set_drvdata(pdev, thermal);
1231
1232 return 0;
1233
1234 err_disable_pclk:
1235 clk_disable_unprepare(thermal->pclk);
1236 err_disable_clk:
1237 clk_disable_unprepare(thermal->clk);
1238
1239 return error;
1240 }
1241
1242 static int rockchip_thermal_remove(struct platform_device *pdev)
1243 {
1244 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1245 int i;
1246
1247 for (i = 0; i < thermal->chip->chn_num; i++) {
1248 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1249
1250 rockchip_thermal_toggle_sensor(sensor, false);
1251 }
1252
1253 thermal->chip->control(thermal->regs, false);
1254
1255 clk_disable_unprepare(thermal->pclk);
1256 clk_disable_unprepare(thermal->clk);
1257
1258 return 0;
1259 }
1260
1261 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1262 {
1263 struct platform_device *pdev = to_platform_device(dev);
1264 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1265 int i;
1266
1267 for (i = 0; i < thermal->chip->chn_num; i++)
1268 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1269
1270 thermal->chip->control(thermal->regs, false);
1271
1272 clk_disable(thermal->pclk);
1273 clk_disable(thermal->clk);
1274
1275 pinctrl_pm_select_sleep_state(dev);
1276
1277 return 0;
1278 }
1279
1280 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1281 {
1282 struct platform_device *pdev = to_platform_device(dev);
1283 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1284 int i;
1285 int error;
1286
1287 error = clk_enable(thermal->clk);
1288 if (error)
1289 return error;
1290
1291 error = clk_enable(thermal->pclk);
1292 if (error) {
1293 clk_disable(thermal->clk);
1294 return error;
1295 }
1296
1297 rockchip_thermal_reset_controller(thermal->reset);
1298
1299 thermal->chip->initialize(thermal->grf, thermal->regs,
1300 thermal->tshut_polarity);
1301
1302 for (i = 0; i < thermal->chip->chn_num; i++) {
1303 int id = thermal->sensors[i].id;
1304
1305 thermal->chip->set_tshut_mode(id, thermal->regs,
1306 thermal->tshut_mode);
1307
1308 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1309 id, thermal->regs,
1310 thermal->tshut_temp);
1311 if (error)
1312 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1313 __func__, thermal->tshut_temp, error);
1314 }
1315
1316 thermal->chip->control(thermal->regs, true);
1317
1318 for (i = 0; i < thermal->chip->chn_num; i++)
1319 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1320
1321 pinctrl_pm_select_default_state(dev);
1322
1323 return 0;
1324 }
1325
1326 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1327 rockchip_thermal_suspend, rockchip_thermal_resume);
1328
1329 static struct platform_driver rockchip_thermal_driver = {
1330 .driver = {
1331 .name = "rockchip-thermal",
1332 .pm = &rockchip_thermal_pm_ops,
1333 .of_match_table = of_rockchip_thermal_match,
1334 },
1335 .probe = rockchip_thermal_probe,
1336 .remove = rockchip_thermal_remove,
1337 };
1338
1339 module_platform_driver(rockchip_thermal_driver);
1340
1341 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1342 MODULE_AUTHOR("Rockchip, Inc.");
1343 MODULE_LICENSE("GPL v2");
1344 MODULE_ALIAS("platform:rockchip-thermal");
Motorola kernel-slsi