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Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / xgifb / vb_init.c
1 #include "osdef.h"
2 #include "vgatypes.h"
3
4
5 #ifdef LINUX_KERNEL
6 #include <linux/version.h>
7 #include <linux/types.h>
8 #include <linux/delay.h> /* udelay */
9 #include "XGIfb.h"
10 /*#if LINUX_VERSxION_CODE >= KERNEL_VERSION(2,5,0)
11 #include <video/XGIfb.h>
12 #else
13 #include <linux/XGIfb.h>
14 #endif */
15 #endif
16
17 #ifdef WIN2000
18 #include <dderror.h>
19 #include <devioctl.h>
20 #include <miniport.h>
21 #include <ntddvdeo.h>
22 #include <video.h>
23 #include "xgiv.h"
24 #include "dd_i2c.h"
25 #include "tools.h"
26 #endif
27
28 #include "vb_def.h"
29 #include "vb_struct.h"
30 #include "vb_util.h"
31 #include "vb_setmode.h"
32 #include "vb_init.h"
33 #include "vb_ext.h"
34
35 #ifdef LINUX_XF86
36 #include "xf86.h"
37 #include "xf86PciInfo.h"
38 #include "xgi.h"
39 #include "xgi_regs.h"
40 #endif
41
42 #ifdef LINUX_KERNEL
43 #include <asm/io.h>
44 #include <linux/types.h>
45 #endif
46
47
48
49
50 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
51
52 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
53 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
54 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
55 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
56 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
57 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
58 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
59 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
60 {0x09,0x08,0x01,0x01,0x00}};
61
62 USHORT XGINew_SDRDRAM_TYPE[13][5]=
63 {
64 { 2,12, 9,64,0x35},
65 { 1,13, 9,64,0x44},
66 { 2,12, 8,32,0x31},
67 { 2,11, 9,32,0x25},
68 { 1,12, 9,32,0x34},
69 { 1,13, 8,32,0x40},
70 { 2,11, 8,16,0x21},
71 { 1,12, 8,16,0x30},
72 { 1,11, 9,16,0x24},
73 { 1,11, 8, 8,0x20},
74 { 2, 9, 8, 4,0x01},
75 { 1,10, 8, 4,0x10},
76 { 1, 9, 8, 2,0x00}
77 };
78
79 USHORT XGINew_DDRDRAM_TYPE[4][5]=
80 {
81 { 2,12, 9,64,0x35},
82 { 2,12, 8,32,0x31},
83 { 2,11, 8,16,0x21},
84 { 2, 9, 8, 4,0x01}
85 };
86 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
87 {
88 { 2,13, 9,64,0x45},
89 { 2,12, 9,32,0x35},
90 { 2,12, 8,16,0x31},
91 { 2,11, 8, 8,0x21}
92 };
93 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
94 {
95 { 2,14,11,128,0x5D},
96 { 2,14,10,64,0x59},
97 { 2,13,11,64,0x4D},
98 { 2,14, 9,32,0x55},
99 { 2,13,10,32,0x49},
100 { 2,12,11,32,0x3D},
101 { 2,14, 8,16,0x51},
102 { 2,13, 9,16,0x45},
103 { 2,12,10,16,0x39},
104 { 2,13, 8, 8,0x41},
105 { 2,12, 9, 8,0x35},
106 { 2,12, 8, 4,0x31}
107 };
108
109 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
110 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
111 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
112 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
113 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
114 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
115 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
116 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
117
118 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
119 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
120 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
121 int XGINew_SDRSizing(PVB_DEVICE_INFO);
122 int XGINew_DDRSizing( PVB_DEVICE_INFO );
123 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
124 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
125 ULONG UNIROM; /* UNIROM */
126 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
127 void XGINew_Delay15us(ULONG);
128 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
129 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
130 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
131 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
132 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
133 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
134 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
135 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
136 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
137 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
138 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
139
140 #ifdef WIN2000
141 /* [Billy] 2007/05/20 For CH7007 */
142 extern UCHAR CH7007TVReg_UNTSC[][8],CH7007TVReg_ONTSC[][8],CH7007TVReg_UPAL[][8],CH7007TVReg_OPAL[][8];
143 extern UCHAR XGI7007_CHTVVCLKUNTSC[],XGI7007_CHTVVCLKONTSC[],XGI7007_CHTVVCLKUPAL[],XGI7007_CHTVVCLKOPAL[];
144 #endif
145
146 #ifdef LINUX_KERNEL
147 void DelayUS(ULONG MicroSeconds)
148 {
149 udelay(MicroSeconds);
150 }
151 #endif
152
153 /* --------------------------------------------------------------------- */
154 /* Function : XGIInitNew */
155 /* Input : */
156 /* Output : */
157 /* Description : */
158 /* --------------------------------------------------------------------- */
159 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
160 {
161
162 VB_DEVICE_INFO VBINF;
163 PVB_DEVICE_INFO pVBInfo = &VBINF;
164 UCHAR i , temp = 0 , temp1 ;
165 // VBIOSVersion[ 5 ] ;
166 PUCHAR volatile pVideoMemory;
167
168 /* ULONG j, k ; */
169
170 PXGI_DSReg pSR ;
171
172 ULONG Temp ;
173
174 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
175
176 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
177
178 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
179
180 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
181
182
183 // Newdebugcode( 0x99 ) ;
184
185
186 /* if ( pVBInfo->ROMAddr == 0 ) */
187 /* return( FALSE ) ; */
188
189 if ( pVBInfo->FBAddr == 0 )
190 {
191 printk("\n pVBInfo->FBAddr == 0 ");
192 return( FALSE ) ;
193 }
194 printk("1");
195 if ( pVBInfo->BaseAddr == 0 )
196 {
197 printk("\npVBInfo->BaseAddr == 0 ");
198 return( FALSE ) ;
199 }
200 printk("2");
201
202 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
203
204 pVBInfo->ISXPDOS = 0 ;
205 printk("3");
206
207 if ( !HwDeviceExtension->bIntegratedMMEnabled )
208 {
209 return( FALSE ) ; /* alan */
210 }
211 printk("4");
212
213 // XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ;
214
215 // VBIOSVersion[ 4 ] = 0x0 ;
216
217 /* 09/07/99 modify by domao */
218
219 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
220 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
221 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
222 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
223 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
224 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
225 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
226 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
227 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
228 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
229 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
230 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
231 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
232 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
233 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
234 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
235 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
236 printk("5");
237
238 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
239 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
240
241 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
242
243 /* ReadVBIOSData */
244 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
245
246 /* 1.Openkey */
247 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
248 printk("6");
249
250 /* GetXG21Sense (GPIO) */
251 if ( HwDeviceExtension->jChipType == XG21 )
252 {
253 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
254 }
255 if ( HwDeviceExtension->jChipType == XG27 )
256 {
257 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
258 }
259 printk("7");
260
261 /* 2.Reset Extended register */
262
263 for( i = 0x06 ; i < 0x20 ; i++ )
264 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
265
266 for( i = 0x21 ; i <= 0x27 ; i++ )
267 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
268
269 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
270 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
271
272 printk("8");
273
274 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
275 {
276 for( i = 0x31 ; i <= 0x3B ; i++ )
277 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
278 }
279 else
280 {
281 for( i = 0x31 ; i <= 0x3D ; i++ )
282 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
283 }
284 printk("9");
285
286 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
287 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
288
289 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
290 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
291
292 for( i = 0x79 ; i <= 0x7C ; i++ )
293 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
294
295 printk("10");
296
297 if ( HwDeviceExtension->jChipType >= XG20 )
298 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
299
300 /* 3.SetMemoryClock
301
302 if ( HwDeviceExtension->jChipType >= XG40 )
303 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
304
305 if ( HwDeviceExtension->jChipType < XG40 )
306 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
307
308 printk("11");
309
310 /* 4.SetDefExt1Regs begin */
311 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
312 if ( HwDeviceExtension->jChipType == XG27 )
313 {
314 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
315 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
316 }
317 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
318 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
319 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
320 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
321 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
322 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
323 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
324
325 /* SR11 = 0x0F ; */
326 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
327
328 printk("12");
329
330 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
331 {
332 // /* Set AGP Rate */
333 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
334 // temp1 &= 0x02 ;
335 // if ( temp1 == 0x02 )
336 // {
337 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
338 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
339 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
340 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
341 // VendorID &= 0x0000FFFF ;
342 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
343 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
344 // GraphicVendorID &= 0x0000FFFF;
345 //
346 // if ( ChipsetID == 0x7301039 )
347 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
348 //
349 // ChipsetID &= 0x0000FFFF ;
350 ///
351 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
352 // {
353 // if ( ChipsetID == 0x1106 )
354 // {
355 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
356 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
357 // else
358 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
359 // }
360 // else
361 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
362 // }
363 // }
364
365 printk("13");
366
367 if ( HwDeviceExtension->jChipType >= XG40 )
368 {
369 /* Set AGP customize registers (in SetDefAGPRegs) Start */
370 for( i = 0x47 ; i <= 0x4C ; i++ )
371 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
372
373 for( i = 0x70 ; i <= 0x71 ; i++ )
374 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
375
376 for( i = 0x74 ; i <= 0x77 ; i++ )
377 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
378 /* Set AGP customize registers (in SetDefAGPRegs) End */
379 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
380 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
381 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
382 // if ( ChipsetID == 0x25308086 )
383 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
384
385 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
386 Temp >>= 20 ;
387 Temp &= 0xF ;
388
389 if ( Temp == 1 )
390 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
391 }
392 printk("14");
393
394 if ( HwDeviceExtension->jChipType < XG40 )
395 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
396 } /* != XG20 */
397
398 /* Set PCI */
399 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
400 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
401 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
402 printk("15");
403
404 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
405 {
406 /* Set VB */
407 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
408 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
409 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
410 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
411 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
412
413
414 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
415
416 printk("16");
417
418 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
419 } /* != XG20 */
420
421
422 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
423
424 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
425 {
426 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
427 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
428 }
429 else
430 {
431 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
432 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
433 }
434 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
435 printk("17");
436
437 /*
438 if ( HwDeviceExtension->jChipType >= XG40 )
439 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
440
441 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
442 {
443 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
444 {
445 if ( pVBInfo->IF_DEF_LVDS == 0 )
446 {
447 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
448 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
449 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
450 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
451 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
452 }
453
454 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
455 }
456 } /* != XG20 */
457 printk("18");
458
459 if ( HwDeviceExtension->jChipType < XG40 )
460 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
461 printk("181");
462
463 if ( HwDeviceExtension->bSkipSense == FALSE )
464 {
465 printk("182");
466
467 XGI_SenseCRT1(pVBInfo) ;
468
469 printk("183");
470 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
471 pVBInfo->IF_DEF_CH7007 = 0;
472 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
473 {
474 printk("184");
475 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
476 printk("185");
477
478 }
479 if ( HwDeviceExtension->jChipType == XG21 )
480 {
481 printk("186");
482
483 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
484 temp = GetXG21FPBits( pVBInfo ) ;
485 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
486 printk("187");
487
488 }
489 if ( HwDeviceExtension->jChipType == XG27 )
490 {
491 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
492 temp = GetXG27FPBits( pVBInfo ) ;
493 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
494 }
495 }
496 printk("19");
497
498 if ( HwDeviceExtension->jChipType >= XG40 )
499 {
500 if ( HwDeviceExtension->jChipType >= XG40 )
501 {
502 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
503 }
504
505 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
506
507 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
508 {
509 pSR = HwDeviceExtension->pSR ;
510 if ( pSR!=NULL )
511 {
512 while( pSR->jIdx != 0xFF )
513 {
514 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
515 pSR++ ;
516 }
517 }
518 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
519 } /* SkipDramSizing */
520 else
521 {
522 #if 0
523 if ( HwDeviceExtension->jChipType == XG20 )
524 {
525 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
526 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
527 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
528 }
529 else
530 #endif
531 {
532 printk("20");
533
534 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
535 }
536 printk("21");
537
538 }
539 } /* XG40 */
540
541 printk("22");
542
543
544 /* SetDefExt2Regs begin */
545 /*
546 AGP = 1 ;
547 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
548 temp &= 0x30 ;
549 if ( temp == 0x30 )
550 AGP = 0 ;
551
552 if ( AGP == 0 )
553 *pVBInfo->pSR21 &= 0xEF ;
554
555 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
556 if ( AGP == 1 )
557 *pVBInfo->pSR22 &= 0x20 ;
558 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
559 */
560
561 // base = 0x80000000 ;
562 // OutPortLong( 0xcf8 , base ) ;
563 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
564 // if ( Temp == 0x1039 )
565 // {
566 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
567 // }
568 // else
569 // {
570 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
571 // }
572
573 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
574
575 printk("23");
576
577
578 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
579 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
580
581 printk("24");
582
583
584 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
585 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
586 printk("25");
587
588 return( TRUE ) ;
589 } /* end of init */
590
591
592
593
594
595 /* ============== alan ====================== */
596
597 /* --------------------------------------------------------------------- */
598 /* Function : XGINew_GetXG20DRAMType */
599 /* Input : */
600 /* Output : */
601 /* Description : */
602 /* --------------------------------------------------------------------- */
603 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
604 {
605 UCHAR data, temp ;
606
607 if ( HwDeviceExtension->jChipType < XG20 )
608 {
609 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
610 {
611 data = *pVBInfo->pSoftSetting & 0x07 ;
612 return( data ) ;
613 }
614 else
615 {
616 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
617
618 if ( data == 0 )
619 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
620
621 return( data ) ;
622 }
623 }
624 else if ( HwDeviceExtension->jChipType == XG27 )
625 {
626 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
627 {
628 data = *pVBInfo->pSoftSetting & 0x07 ;
629 return( data ) ;
630 }
631 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
632
633 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
634 data = 0 ; /*DDR*/
635 else
636 data = 1 ; /*DDRII*/
637 return( data ) ;
638 }
639 else if ( HwDeviceExtension->jChipType == XG21 )
640 {
641 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
642 DelayUS(800);
643 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
644 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
645 // HOTPLUG_SUPPORT
646 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
647 if ( temp & 0x01 ) /* DVI read GPIOH */
648 data = 1 ; /*DDRII*/
649 else
650 data = 0 ; /*DDR*/
651 //~HOTPLUG_SUPPORT
652 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
653 return( data ) ;
654 }
655 else
656 {
657 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
658
659 if ( data == 1 )
660 data ++ ;
661
662 return( data );
663 }
664 }
665
666
667 /* --------------------------------------------------------------------- */
668 /* Function : XGINew_Get310DRAMType */
669 /* Input : */
670 /* Output : */
671 /* Description : */
672 /* --------------------------------------------------------------------- */
673 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
674 {
675 UCHAR data ;
676
677 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
678 /* index &= 07 ; */
679
680 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
681 data = *pVBInfo->pSoftSetting & 0x03 ;
682 else
683 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
684
685 return( data ) ;
686 }
687
688
689
690 /* --------------------------------------------------------------------- */
691 /* Function : XGINew_Delay15us */
692 /* Input : */
693 /* Output : */
694 /* Description : */
695 /* --------------------------------------------------------------------- */
696 /*
697 void XGINew_Delay15us(ULONG ulMicrsoSec)
698 {
699 }
700 */
701
702
703 /* --------------------------------------------------------------------- */
704 /* Function : XGINew_SDR_MRS */
705 /* Input : */
706 /* Output : */
707 /* Description : */
708 /* --------------------------------------------------------------------- */
709 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
710 {
711 USHORT data ;
712
713 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
714 data &= 0x3F ; /* SR16 D7=0,D6=0 */
715 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
716 /* XGINew_Delay15us( 0x100 ) ; */
717 data |= 0x80 ; /* SR16 D7=1,D6=0 */
718 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
719 /* XGINew_Delay15us( 0x100 ) ; */
720 }
721
722
723 /* --------------------------------------------------------------------- */
724 /* Function : XGINew_DDR1x_MRS_340 */
725 /* Input : */
726 /* Output : */
727 /* Description : */
728 /* --------------------------------------------------------------------- */
729 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
730 {
731 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
732 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
733 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
734 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
735
736 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
737 {
738 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
739 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
740 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
741 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
742 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
743 }
744
745 DelayUS( 60 ) ;
746 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
747 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
748 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
749 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
750 DelayUS( 1000 ) ;
751 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
752 DelayUS( 500 ) ;
753 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
754 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
755 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
756 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
757 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
758 }
759
760
761 /* --------------------------------------------------------------------- */
762 /* Function : XGINew_DDR2x_MRS_340 */
763 /* Input : */
764 /* Output : */
765 /* Description : */
766 /* --------------------------------------------------------------------- */
767 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
768 {
769 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
770 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
771 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
772 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
773 DelayUS( 60 ) ;
774 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
775 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
776 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
777 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
778 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
779 DelayUS( 1000 ) ;
780 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
781 DelayUS( 500 ) ;
782 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
783 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
784 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
785 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
786 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
787 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
788 }
789
790 /* --------------------------------------------------------------------- */
791 /* Function : XGINew_DDRII_Bootup_XG27 */
792 /* Input : */
793 /* Output : */
794 /* Description : */
795 /* --------------------------------------------------------------------- */
796 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
797 {
798 ULONG P3d4 = P3c4 + 0x10 ;
799 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
800 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
801
802 /* Set Double Frequency */
803 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
804 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
805
806 DelayUS( 200 ) ;
807
808 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
809 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
810 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
811 DelayUS( 15 ) ;
812 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
813 DelayUS( 15 ) ;
814
815 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
816 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
817 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
818 DelayUS( 15 ) ;
819 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
820 DelayUS( 15) ;
821
822 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
823 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
824 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
825 DelayUS( 30 ) ;
826 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
827 DelayUS( 15 ) ;
828
829 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
830 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
831 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
832 DelayUS( 30 ) ;
833 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
834 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
835 /* DelayUS( 15 ) ; */
836
837 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
838 DelayUS( 60 ) ;
839 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
840
841 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
842 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
843 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
844
845 DelayUS( 30 ) ;
846 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
847 DelayUS( 15 ) ;
848
849 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
850 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
851 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
852 DelayUS( 30 ) ;
853 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
854 DelayUS( 15 ) ;
855
856 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
857 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
858 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
859 DelayUS( 30 ) ;
860 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
861 DelayUS( 15 ) ;
862
863 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
864 DelayUS( 200 ) ;
865
866
867 }
868 /* --------------------------------------------------------------------- */
869 /* Function : XGINew_DDR2_MRS_XG20 */
870 /* Input : */
871 /* Output : */
872 /* Description : */
873 /* --------------------------------------------------------------------- */
874 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
875 {
876 ULONG P3d4 = P3c4 + 0x10 ;
877
878 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
879 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
880
881 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
882
883 DelayUS( 200 ) ;
884 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
885 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
886 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
887 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
888
889 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
890 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
891 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
892 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
893
894 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
895 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
896 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
897 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
898
899 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
900 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
901 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
902 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
903 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
904
905 DelayUS( 15 ) ;
906 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
907 DelayUS( 30 ) ;
908 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
909 DelayUS( 100 ) ;
910
911 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
912 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
913 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
914 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
915 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
916
917 DelayUS( 200 ) ;
918 }
919
920 /* --------------------------------------------------------------------- */
921 /* Function : XGINew_DDR2_MRS_XG20 */
922 /* Input : */
923 /* Output : */
924 /* Description : */
925 /* --------------------------------------------------------------------- */
926 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
927 {
928 ULONG P3d4 = P3c4 + 0x10 ;
929
930 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
931 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
932
933 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
934 DelayUS( 200 ) ;
935 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
936 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
937
938 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
939 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
940 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
941
942 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
943 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
944
945 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
946 DelayUS( 15 ) ; ////06/11/22 XG27 A0
947 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
948
949
950 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
951 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
952
953 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
954 DelayUS( 15 ) ; ////06/11/22 XG27 A0
955 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
956
957 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
958 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
959
960 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
961 DelayUS( 15 ) ; ////06/11/23 XG27 A0
962 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
963
964 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
965 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
966 DelayUS( 60 ) ;
967 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
968
969
970 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
971 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
972
973 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
974 DelayUS( 30 ) ;
975 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
976
977 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
978 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
979
980 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
981 DelayUS( 30 ) ;
982 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
983
984 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
985 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
986
987 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
988 DelayUS( 30 ) ;
989 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
990
991 DelayUS( 15 ) ; ////Start Auto-PreCharge
992 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
993 DelayUS( 200 ) ;
994 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
995
996 }
997
998 /* --------------------------------------------------------------------- */
999 /* Function : XGINew_DDR1x_DefaultRegister */
1000 /* Input : */
1001 /* Output : */
1002 /* Description : */
1003 /* --------------------------------------------------------------------- */
1004 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1005 {
1006 ULONG P3d4 = Port ,
1007 P3c4 = Port - 0x10 ;
1008
1009 if ( HwDeviceExtension->jChipType >= XG20 )
1010 {
1011 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1012 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1013 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1014 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1015
1016 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1017 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1018
1019 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1020 }
1021 else
1022 {
1023 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1024
1025 switch( HwDeviceExtension->jChipType )
1026 {
1027 case XG41:
1028 case XG42:
1029 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1030 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1031 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1032 break ;
1033 default:
1034 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1035 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1036 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1037 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1038 XGINew_GetReg1( P3d4 , 0x86 ) ;
1039 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1040 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1041 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1042 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1043 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1044 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1045 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1046 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1047 break ;
1048 }
1049
1050 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1051 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1052 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1053 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1054 }
1055 }
1056
1057
1058 /* --------------------------------------------------------------------- */
1059 /* Function : XGINew_DDR2x_DefaultRegister */
1060 /* Input : */
1061 /* Output : */
1062 /* Description : */
1063 /* --------------------------------------------------------------------- */
1064 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1065 {
1066 ULONG P3d4 = Port ,
1067 P3c4 = Port - 0x10 ;
1068
1069 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1070
1071 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1072 switch( HwDeviceExtension->jChipType )
1073 {
1074 case XG41:
1075 case XG42:
1076 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1077 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1078 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1079 break ;
1080 default:
1081 /* keep following setting sequence, each setting in the same reg insert idle */
1082 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1083 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1084 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1085 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1086 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1087 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1088 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1089 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1090 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1091 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1092 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1093 }
1094 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1095 if ( HwDeviceExtension->jChipType == XG42 )
1096 {
1097 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1098 }
1099 else
1100 {
1101 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1102 }
1103 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1104
1105 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1106 }
1107
1108
1109 /* --------------------------------------------------------------------- */
1110 /* Function : XGINew_DDR2_DefaultRegister */
1111 /* Input : */
1112 /* Output : */
1113 /* Description : */
1114 /* --------------------------------------------------------------------- */
1115 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1116 {
1117 ULONG P3d4 = Port ,
1118 P3c4 = Port - 0x10 ;
1119
1120 /* keep following setting sequence, each setting in the same reg insert idle */
1121 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1122 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1123 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1124 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1125 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1126 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1127 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1128 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1129 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1130 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1131 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1132 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1133 if ( HwDeviceExtension->jChipType == XG27 )
1134 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1135 else
1136 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1137
1138 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1139 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1140 if ( HwDeviceExtension->jChipType == XG27 )
1141 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1142 else
1143 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1144 }
1145
1146
1147 /* --------------------------------------------------------------------- */
1148 /* Function : XGINew_SetDRAMDefaultRegister340 */
1149 /* Input : */
1150 /* Output : */
1151 /* Description : */
1152 /* --------------------------------------------------------------------- */
1153 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1154 {
1155 UCHAR temp , temp1 , temp2 , temp3 ,
1156 i , j , k ;
1157
1158 ULONG P3d4 = Port ,
1159 P3c4 = Port - 0x10 ;
1160
1161 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1162 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1163 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1164 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1165
1166 temp2 = 0 ;
1167 for( i = 0 ; i < 4 ; i++ )
1168 {
1169 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1170 for( j = 0 ; j < 4 ; j++ )
1171 {
1172 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1173 temp2 |= temp1 ;
1174 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1175 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1176 temp2 &= 0xF0 ;
1177 temp2 += 0x10 ;
1178 }
1179 }
1180
1181 temp2 = 0 ;
1182 for( i = 0 ; i < 4 ; i++ )
1183 {
1184 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1185 for( j = 0 ; j < 4 ; j++ )
1186 {
1187 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1188 temp2 |= temp1 ;
1189 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1190 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1191 temp2 &= 0xF0 ;
1192 temp2 += 0x10 ;
1193 }
1194 }
1195
1196 temp3 = 0 ;
1197 for( k = 0 ; k < 4 ; k++ )
1198 {
1199 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1200 temp2 = 0 ;
1201 for( i = 0 ; i < 8 ; i++ )
1202 {
1203 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1204 for( j = 0 ; j < 4 ; j++ )
1205 {
1206 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1207 temp2 |= temp1 ;
1208 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1209 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1210 temp2 &= 0xF8 ;
1211 temp2 += 0x08 ;
1212 }
1213 }
1214 temp3 += 0x01 ;
1215 }
1216
1217 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1218 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1219
1220 temp2 = 0x80 ;
1221 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1222 for( j = 0 ; j < 4 ; j++ )
1223 {
1224 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1225 temp2 |= temp1 ;
1226 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1227 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1228 temp2 &= 0xF0 ;
1229 temp2 += 0x10 ;
1230 }
1231
1232 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1233 temp1 = temp & 0x03 ;
1234 temp2 |= temp1 ;
1235 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1236
1237 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1238 temp1 = temp & 0x0F ;
1239 temp2 = ( temp >> 4 ) & 0x07 ;
1240 temp3 = temp & 0x80 ;
1241 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1242 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1243 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1244 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1245
1246 if ( HwDeviceExtension->jChipType == XG27 )
1247 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1248
1249 for( j = 0 ; j <= 6 ; j++ )
1250 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1251
1252 for( j = 0 ; j <= 2 ; j++ )
1253 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1254
1255 for( j = 0 ; j < 2 ; j++ )
1256 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1257
1258 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1259 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1260
1261 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1262
1263 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1264 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1265 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1266 if ( XGINew_RAMType )
1267 {
1268 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1269 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1270 if ( HwDeviceExtension->jChipType == XG27 )
1271 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1272
1273 }
1274 else
1275 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1276 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1277
1278 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1279 if( temp == 0 )
1280 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1281 else
1282 {
1283 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1284 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1285 }
1286 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1287 }
1288
1289
1290 /* --------------------------------------------------------------------- */
1291 /* Function : XGINew_DDR_MRS */
1292 /* Input : */
1293 /* Output : */
1294 /* Description : */
1295 /* --------------------------------------------------------------------- */
1296 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1297 {
1298 USHORT data ;
1299
1300 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1301
1302 /* SR16 <- 1F,DF,2F,AF */
1303 /* yriver modified SR16 <- 0F,DF,0F,AF */
1304 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1305 data = pVideoMemory[ 0xFB ] ;
1306 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1307
1308 data &= 0x0F ;
1309 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1310 data |= 0xC0 ;
1311 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1312 data &= 0x0F ;
1313 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1314 data |= 0x80 ;
1315 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1316 data &= 0x0F ;
1317 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1318 data |= 0xD0 ;
1319 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1320 data &= 0x0F ;
1321 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1322 data |= 0xA0 ;
1323 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1324 /*
1325 else {
1326 data &= 0x0F;
1327 data |= 0x10;
1328 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1329
1330 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1331 {
1332 data &= 0x0F;
1333 }
1334
1335 data |= 0xC0;
1336 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1337
1338
1339 data &= 0x0F;
1340 data |= 0x20;
1341 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1342 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1343 {
1344 data &= 0x0F;
1345 }
1346
1347 data |= 0x80;
1348 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1349 }
1350 */
1351 }
1352
1353
1354 /* check if read cache pointer is correct */
1355
1356
1357
1358 /* --------------------------------------------------------------------- */
1359 /* Function : XGINew_VerifyMclk */
1360 /* Input : */
1361 /* Output : */
1362 /* Description : */
1363 /* --------------------------------------------------------------------- */
1364 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1365 {
1366 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1367 UCHAR i , j ;
1368 USHORT Temp , SR21 ;
1369
1370 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1371 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1372
1373 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1374 {
1375 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1376 {
1377 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1378 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1379 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1380
1381 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1382 Temp |= 0x01 ; /* MCLK reset */
1383
1384
1385 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1386 Temp &= 0xFE ; /* MCLK normal operation */
1387
1388 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1389
1390 pVideoMemory[ 16 + j ] = j ;
1391 if ( pVideoMemory[ 16 + j ] == j )
1392 {
1393 pVideoMemory[ j ] = j ;
1394 break ;
1395 }
1396 }
1397 }
1398 }
1399
1400
1401
1402
1403
1404 /* --------------------------------------------------------------------- */
1405 /* Function : XGINew_SetDRAMSize_340 */
1406 /* Input : */
1407 /* Output : */
1408 /* Description : */
1409 /* --------------------------------------------------------------------- */
1410 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1411 {
1412 USHORT data ;
1413
1414 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1415 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1416
1417 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1418
1419
1420 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1421 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1422 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1423
1424 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1425 /*data |= 0x20 ;*/
1426 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1427 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1428 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1429 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1430
1431 }
1432
1433
1434 /* --------------------------------------------------------------------- */
1435 /* Function : */
1436 /* Input : */
1437 /* Output : */
1438 /* Description : */
1439 /* --------------------------------------------------------------------- */
1440 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1441 {
1442 USHORT data ;
1443 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1444 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1445 #ifdef XGI301
1446 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1447 #endif
1448
1449 #ifdef XGI302 /* alan,should change value */
1450 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1451 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1452 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1453 #endif
1454
1455 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1456
1457 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1458 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1459
1460 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1461 data |= 0x20 ;
1462 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1463
1464 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1465
1466
1467 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1468
1469 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1470 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1471 XGINew_CheckBusWidth_310( pVBInfo) ;
1472 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1473
1474
1475
1476 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1477 {
1478 XGINew_SDRSizing( pVBInfo ) ;
1479 }
1480 else
1481 {
1482 XGINew_DDRSizing( pVBInfo) ;
1483 }
1484
1485
1486
1487
1488 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1489
1490 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1491 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1492 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1493 }
1494
1495
1496
1497 /* --------------------------------------------------------------------- */
1498 /* Function : XGINew_SetDRAMModeRegister340 */
1499 /* Input : */
1500 /* Output : */
1501 /* Description : */
1502 /* --------------------------------------------------------------------- */
1503
1504 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1505 {
1506 UCHAR data ;
1507 VB_DEVICE_INFO VBINF;
1508 PVB_DEVICE_INFO pVBInfo = &VBINF;
1509 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1510 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1511 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1512 pVBInfo->ISXPDOS = 0 ;
1513
1514 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1515 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1516 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1517 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1518 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1519 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1520 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1521 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1522 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1523 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1524 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1525 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1526 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1527 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1528 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1529 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1530 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1531 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1532 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1533
1534 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1535
1536 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1537
1538 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1539 {
1540 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1541 if ( data == 0x01 )
1542 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1543 else
1544 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1545 }
1546 else
1547 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1548
1549 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1550 }
1551
1552 /* --------------------------------------------------------------------- */
1553 /* Function : XGINew_SetDRAMModeRegister */
1554 /* Input : */
1555 /* Output : */
1556 /* Description : */
1557 /* --------------------------------------------------------------------- */
1558 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1559 {
1560 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1561 {
1562 XGINew_SDR_MRS(pVBInfo ) ;
1563 }
1564 else
1565 {
1566 /* SR16 <- 0F,CF,0F,8F */
1567 XGINew_DDR_MRS( pVBInfo ) ;
1568 }
1569 }
1570
1571
1572 /* --------------------------------------------------------------------- */
1573 /* Function : XGINew_DisableRefresh */
1574 /* Input : */
1575 /* Output : */
1576 /* Description : */
1577 /* --------------------------------------------------------------------- */
1578 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1579 {
1580 USHORT data ;
1581
1582
1583 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1584 data &= 0xF8 ;
1585 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1586
1587 }
1588
1589
1590 /* --------------------------------------------------------------------- */
1591 /* Function : XGINew_EnableRefresh */
1592 /* Input : */
1593 /* Output : */
1594 /* Description : */
1595 /* --------------------------------------------------------------------- */
1596 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1597 {
1598
1599 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1600
1601
1602 }
1603
1604
1605 /* --------------------------------------------------------------------- */
1606 /* Function : XGINew_DisableChannelInterleaving */
1607 /* Input : */
1608 /* Output : */
1609 /* Description : */
1610 /* --------------------------------------------------------------------- */
1611 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1612 {
1613 USHORT data ;
1614
1615 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1616 data &= 0x1F ;
1617
1618 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1619 {
1620 case 64:
1621 data |= 0 ;
1622 break ;
1623 case 32:
1624 data |= 0x20 ;
1625 break ;
1626 case 16:
1627 data |= 0x40 ;
1628 break ;
1629 case 4:
1630 data |= 0x60 ;
1631 break ;
1632 default:
1633 break ;
1634 }
1635 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1636 }
1637
1638
1639 /* --------------------------------------------------------------------- */
1640 /* Function : XGINew_SetDRAMSizingType */
1641 /* Input : */
1642 /* Output : */
1643 /* Description : */
1644 /* --------------------------------------------------------------------- */
1645 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1646 {
1647 USHORT data ;
1648
1649 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1650 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1651 DelayUS( 15 ) ;
1652 /* should delay 50 ns */
1653 }
1654
1655
1656 /* --------------------------------------------------------------------- */
1657 /* Function : XGINew_CheckBusWidth_310 */
1658 /* Input : */
1659 /* Output : */
1660 /* Description : */
1661 /* --------------------------------------------------------------------- */
1662 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1663 {
1664 USHORT data ;
1665 PULONG volatile pVideoMemory ;
1666
1667 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1668
1669 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1670 {
1671 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1672 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1673 /* should delay */
1674 XGINew_SDR_MRS( pVBInfo ) ;
1675
1676 XGINew_ChannelAB = 0 ;
1677 XGINew_DataBusWidth = 128 ;
1678 pVideoMemory[ 0 ] = 0x01234567L ;
1679 pVideoMemory[ 1 ] = 0x456789ABL ;
1680 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1681 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1682 pVideoMemory[ 4 ] = 0x55555555L ;
1683 pVideoMemory[ 5 ] = 0x55555555L ;
1684 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1685 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1686
1687 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1688 {
1689 /* ChannelA64Bit */
1690 XGINew_DataBusWidth = 64 ;
1691 XGINew_ChannelAB = 0 ;
1692 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1693 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1694 }
1695
1696 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1697 {
1698 /* ChannelB64Bit */
1699 XGINew_DataBusWidth = 64 ;
1700 XGINew_ChannelAB = 1 ;
1701 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1702 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1703 }
1704
1705 return ;
1706 }
1707 else
1708 {
1709 /* DDR Dual channel */
1710 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1711 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1712 /* should delay */
1713 XGINew_DDR_MRS( pVBInfo ) ;
1714
1715 XGINew_ChannelAB = 0 ;
1716 XGINew_DataBusWidth = 64 ;
1717 pVideoMemory[ 0 ] = 0x01234567L ;
1718 pVideoMemory[ 1 ] = 0x456789ABL ;
1719 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1720 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1721 pVideoMemory[ 4 ] = 0x55555555L ;
1722 pVideoMemory[ 5 ] = 0x55555555L ;
1723 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1724 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1725
1726 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1727 {
1728 if ( pVideoMemory[ 0 ] == 0x01234567L )
1729 {
1730 /* Channel A 64bit */
1731 return ;
1732 }
1733 }
1734 else
1735 {
1736 if ( pVideoMemory[ 0 ] == 0x01234567L )
1737 {
1738 /* Channel A 32bit */
1739 XGINew_DataBusWidth = 32 ;
1740 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1741 return ;
1742 }
1743 }
1744
1745 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1746 XGINew_DDR_MRS( pVBInfo);
1747
1748 XGINew_ChannelAB = 1 ;
1749 XGINew_DataBusWidth = 64 ;
1750 pVideoMemory[ 0 ] = 0x01234567L ;
1751 pVideoMemory[ 1 ] = 0x456789ABL ;
1752 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1753 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1754 pVideoMemory[ 4 ] = 0x55555555L ;
1755 pVideoMemory[ 5 ] = 0x55555555L ;
1756 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1757 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1758
1759 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1760 {
1761 /* Channel B 64 */
1762 if ( pVideoMemory[ 0 ] == 0x01234567L )
1763 {
1764 /* Channel B 64bit */
1765 return ;
1766 }
1767 else
1768 {
1769 /* error */
1770 }
1771 }
1772 else
1773 {
1774 if ( pVideoMemory[ 0 ] == 0x01234567L )
1775 {
1776 /* Channel B 32 */
1777 XGINew_DataBusWidth = 32 ;
1778 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1779 }
1780 else
1781 {
1782 /* error */
1783 }
1784 }
1785 }
1786 }
1787
1788
1789 /* --------------------------------------------------------------------- */
1790 /* Function : XGINew_SetRank */
1791 /* Input : */
1792 /* Output : */
1793 /* Description : */
1794 /* --------------------------------------------------------------------- */
1795 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1796 {
1797 USHORT data ;
1798 int RankSize ;
1799
1800 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1801 return 0 ;
1802
1803 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1804
1805 if ( ( RankNo * RankSize ) <= 128 )
1806 {
1807 data = 0 ;
1808
1809 while( ( RankSize >>= 1 ) > 0 )
1810 {
1811 data += 0x10 ;
1812 }
1813 data |= ( RankNo - 1 ) << 2 ;
1814 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1815 data |= XGINew_ChannelAB ;
1816 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1817 /* should delay */
1818 XGINew_SDR_MRS( pVBInfo ) ;
1819 return( 1 ) ;
1820 }
1821 else
1822 return( 0 ) ;
1823 }
1824
1825
1826 /* --------------------------------------------------------------------- */
1827 /* Function : XGINew_SetDDRChannel */
1828 /* Input : */
1829 /* Output : */
1830 /* Description : */
1831 /* --------------------------------------------------------------------- */
1832 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1833 {
1834 USHORT data ;
1835 int RankSize ;
1836
1837 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1838 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1839 if ( ChannelNo * RankSize <= 128 )
1840 {
1841 data = 0 ;
1842 while( ( RankSize >>= 1 ) > 0 )
1843 {
1844 data += 0x10 ;
1845 }
1846
1847 if ( ChannelNo == 2 )
1848 data |= 0x0C ;
1849
1850 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1851 data |= XGINew_ChannelAB ;
1852 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1853 /* should delay */
1854 XGINew_DDR_MRS( pVBInfo ) ;
1855 return( 1 ) ;
1856 }
1857 else
1858 return( 0 ) ;
1859 }
1860
1861
1862 /* --------------------------------------------------------------------- */
1863 /* Function : XGINew_CheckColumn */
1864 /* Input : */
1865 /* Output : */
1866 /* Description : */
1867 /* --------------------------------------------------------------------- */
1868 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1869 {
1870 int i ;
1871 ULONG Increment , Position ;
1872
1873 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1874 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1875
1876 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1877 {
1878 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1879 Position += Increment ;
1880 }
1881
1882 #ifdef WIN2000 /* chiawen for linux solution */
1883 DelayUS( 100 ) ;
1884 #endif
1885
1886 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1887 {
1888 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1889 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1890 return( 0 ) ;
1891 Position += Increment ;
1892 }
1893 return( 1 ) ;
1894 }
1895
1896
1897 /* --------------------------------------------------------------------- */
1898 /* Function : XGINew_CheckBanks */
1899 /* Input : */
1900 /* Output : */
1901 /* Description : */
1902 /* --------------------------------------------------------------------- */
1903 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1904 {
1905 int i ;
1906 ULONG Increment , Position ;
1907
1908 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1909
1910 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1911 {
1912 /* pVBInfo->FBAddr[ Position ] = Position ; */
1913 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1914 Position += Increment ;
1915 }
1916
1917 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1918 {
1919 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1920 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1921 return( 0 ) ;
1922 Position += Increment ;
1923 }
1924 return( 1 ) ;
1925 }
1926
1927
1928 /* --------------------------------------------------------------------- */
1929 /* Function : XGINew_CheckRank */
1930 /* Input : */
1931 /* Output : */
1932 /* Description : */
1933 /* --------------------------------------------------------------------- */
1934 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1935 {
1936 int i ;
1937 ULONG Increment , Position ;
1938
1939 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1940 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1941
1942 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1943 {
1944 /* pVBInfo->FBAddr[ Position ] = Position ; */
1945 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1946 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1947 Position += Increment ;
1948 }
1949
1950 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1951 {
1952 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1953 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1954 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1955 return( 0 ) ;
1956 Position += Increment ;
1957 }
1958 return( 1 );
1959 }
1960
1961
1962 /* --------------------------------------------------------------------- */
1963 /* Function : XGINew_CheckDDRRank */
1964 /* Input : */
1965 /* Output : */
1966 /* Description : */
1967 /* --------------------------------------------------------------------- */
1968 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1969 {
1970 ULONG Increment , Position ;
1971 USHORT data ;
1972
1973 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1974 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1975
1976 Increment += Increment / 2 ;
1977
1978 Position = 0;
1979 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1980 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1981 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1982 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1983 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1984 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1985
1986 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1987 return( 1 ) ;
1988
1989 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1990 return( 0 ) ;
1991
1992 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1993 data &= 0xF3 ;
1994 data |= 0x0E ;
1995 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1996 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1997 data += 0x20 ;
1998 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1999
2000 return( 1 ) ;
2001 }
2002
2003
2004 /* --------------------------------------------------------------------- */
2005 /* Function : XGINew_CheckRanks */
2006 /* Input : */
2007 /* Output : */
2008 /* Description : */
2009 /* --------------------------------------------------------------------- */
2010 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2011 {
2012 int r ;
2013
2014 for( r = RankNo ; r >= 1 ; r-- )
2015 {
2016 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2017 return( 0 ) ;
2018 }
2019
2020 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2021 return( 0 ) ;
2022
2023 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2024 return( 0 ) ;
2025
2026 return( 1 ) ;
2027 }
2028
2029
2030 /* --------------------------------------------------------------------- */
2031 /* Function : XGINew_CheckDDRRanks */
2032 /* Input : */
2033 /* Output : */
2034 /* Description : */
2035 /* --------------------------------------------------------------------- */
2036 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2037 {
2038 int r ;
2039
2040 for( r = RankNo ; r >= 1 ; r-- )
2041 {
2042 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2043 return( 0 ) ;
2044 }
2045
2046 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2047 return( 0 ) ;
2048
2049 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2050 return( 0 ) ;
2051
2052 return( 1 ) ;
2053 }
2054
2055
2056 /* --------------------------------------------------------------------- */
2057 /* Function : */
2058 /* Input : */
2059 /* Output : */
2060 /* Description : */
2061 /* --------------------------------------------------------------------- */
2062 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2063 {
2064 int i ;
2065 UCHAR j ;
2066
2067 for( i = 0 ; i < 13 ; i++ )
2068 {
2069 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2070
2071 for( j = 2 ; j > 0 ; j-- )
2072 {
2073 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2074 continue ;
2075 else
2076 {
2077 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2078 return( 1 ) ;
2079 }
2080 }
2081 }
2082 return( 0 ) ;
2083 }
2084
2085
2086 /* --------------------------------------------------------------------- */
2087 /* Function : XGINew_SetDRAMSizeReg */
2088 /* Input : */
2089 /* Output : */
2090 /* Description : */
2091 /* --------------------------------------------------------------------- */
2092 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2093 {
2094 USHORT data = 0 , memsize = 0 ;
2095 int RankSize ;
2096 UCHAR ChannelNo ;
2097
2098 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2099 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2100 data &= 0x80 ;
2101
2102 if ( data == 0x80 )
2103 RankSize *= 2 ;
2104
2105 data = 0 ;
2106
2107 if( XGINew_ChannelAB == 3 )
2108 ChannelNo = 4 ;
2109 else
2110 ChannelNo = XGINew_ChannelAB ;
2111
2112 if ( ChannelNo * RankSize <= 256 )
2113 {
2114 while( ( RankSize >>= 1 ) > 0 )
2115 {
2116 data += 0x10 ;
2117 }
2118
2119 memsize = data >> 4 ;
2120
2121 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2122 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2123
2124 /* data |= XGINew_ChannelAB << 2 ; */
2125 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2126 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2127
2128 /* should delay */
2129 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2130 }
2131 return( memsize ) ;
2132 }
2133
2134
2135 /* --------------------------------------------------------------------- */
2136 /* Function : XGINew_SetDRAMSize20Reg */
2137 /* Input : */
2138 /* Output : */
2139 /* Description : */
2140 /* --------------------------------------------------------------------- */
2141 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2142 {
2143 USHORT data = 0 , memsize = 0 ;
2144 int RankSize ;
2145 UCHAR ChannelNo ;
2146
2147 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2148 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2149 data &= 0x80 ;
2150
2151 if ( data == 0x80 )
2152 RankSize *= 2 ;
2153
2154 data = 0 ;
2155
2156 if( XGINew_ChannelAB == 3 )
2157 ChannelNo = 4 ;
2158 else
2159 ChannelNo = XGINew_ChannelAB ;
2160
2161 if ( ChannelNo * RankSize <= 256 )
2162 {
2163 while( ( RankSize >>= 1 ) > 0 )
2164 {
2165 data += 0x10 ;
2166 }
2167
2168 memsize = data >> 4 ;
2169
2170 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2171 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2172 DelayUS( 15 ) ;
2173
2174 /* data |= XGINew_ChannelAB << 2 ; */
2175 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2176 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2177
2178 /* should delay */
2179 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2180 }
2181 return( memsize ) ;
2182 }
2183
2184
2185 /* --------------------------------------------------------------------- */
2186 /* Function : XGINew_ReadWriteRest */
2187 /* Input : */
2188 /* Output : */
2189 /* Description : */
2190 /* --------------------------------------------------------------------- */
2191 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2192 {
2193 int i ;
2194 ULONG Position = 0 ;
2195
2196 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2197
2198 for( i = StartAddr ; i <= StopAddr ; i++ )
2199 {
2200 Position = 1 << i ;
2201 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2202 }
2203
2204 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2205
2206 Position = 0 ;
2207
2208 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2209 return( 0 ) ;
2210
2211 for( i = StartAddr ; i <= StopAddr ; i++ )
2212 {
2213 Position = 1 << i ;
2214 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2215 return( 0 ) ;
2216 }
2217 return( 1 ) ;
2218 }
2219
2220
2221 /* --------------------------------------------------------------------- */
2222 /* Function : XGINew_CheckFrequence */
2223 /* Input : */
2224 /* Output : */
2225 /* Description : */
2226 /* --------------------------------------------------------------------- */
2227 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2228 {
2229 UCHAR data ;
2230
2231 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2232
2233 if ( ( data & 0x10 ) == 0 )
2234 {
2235 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2236 data = ( data & 0x02 ) >> 1 ;
2237 return( data ) ;
2238 }
2239 else
2240 return( data & 0x01 ) ;
2241 }
2242
2243
2244 /* --------------------------------------------------------------------- */
2245 /* Function : XGINew_CheckChannel */
2246 /* Input : */
2247 /* Output : */
2248 /* Description : */
2249 /* --------------------------------------------------------------------- */
2250 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2251 {
2252 UCHAR data;
2253
2254 switch( HwDeviceExtension->jChipType )
2255 {
2256 case XG20:
2257 case XG21:
2258 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2259 data = data & 0x01;
2260 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2261
2262 if ( data == 0 ) /* Single_32_16 */
2263 {
2264
2265 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2266 {
2267
2268 XGINew_DataBusWidth = 32 ; /* 32 bits */
2269 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2270 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2271 DelayUS( 15 ) ;
2272
2273 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2274 return ;
2275
2276 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2277 {
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2279 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2280 DelayUS( 15 ) ;
2281
2282 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2283 return ;
2284 }
2285 }
2286
2287 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2288 {
2289 XGINew_DataBusWidth = 16 ; /* 16 bits */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2291 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2292 DelayUS( 15 ) ;
2293
2294 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2295 return ;
2296 else
2297 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2298 DelayUS( 15 ) ;
2299 }
2300
2301 }
2302 else /* Dual_16_8 */
2303 {
2304 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2305 {
2306
2307 XGINew_DataBusWidth = 16 ; /* 16 bits */
2308 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2309 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2310 DelayUS( 15 ) ;
2311
2312 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2313 return ;
2314
2315 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2316 {
2317 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2319 DelayUS( 15 ) ;
2320
2321 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2322 return ;
2323 }
2324 }
2325
2326
2327 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2328 {
2329 XGINew_DataBusWidth = 8 ; /* 8 bits */
2330 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2331 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2332 DelayUS( 15 ) ;
2333
2334 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2335 return ;
2336 else
2337 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2338 DelayUS( 15 ) ;
2339 }
2340 }
2341 break ;
2342
2343 case XG27:
2344 XGINew_DataBusWidth = 16 ; /* 16 bits */
2345 XGINew_ChannelAB = 1 ; /* Single channel */
2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2347 break ;
2348 case XG41:
2349 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2350 {
2351 XGINew_DataBusWidth = 32 ; /* 32 bits */
2352 XGINew_ChannelAB = 3 ; /* Quad Channel */
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2354 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2355
2356 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2357 return ;
2358
2359 XGINew_ChannelAB = 2 ; /* Dual channels */
2360 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2361
2362 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2363 return ;
2364
2365 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2366
2367 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2368 return ;
2369
2370 XGINew_ChannelAB = 3 ;
2371 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2372 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2373
2374 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2375 return ;
2376
2377 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2378
2379 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2380 return ;
2381 else
2382 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2383 }
2384 else
2385 { /* DDR */
2386 XGINew_DataBusWidth = 64 ; /* 64 bits */
2387 XGINew_ChannelAB = 2 ; /* Dual channels */
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2389 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2390
2391 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2392 return ;
2393
2394 XGINew_ChannelAB = 1 ; /* Single channels */
2395 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2396
2397 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2398 return ;
2399
2400 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2401
2402 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2403 return ;
2404
2405 XGINew_ChannelAB = 2 ; /* Dual channels */
2406 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2407 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2408
2409 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2410 return ;
2411
2412 XGINew_ChannelAB = 1 ; /* Single channels */
2413 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2414
2415 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2416 return ;
2417 else
2418 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2419 }
2420
2421 break ;
2422
2423 case XG42:
2424 /*
2425 XG42 SR14 D[3] Reserve
2426 D[2] = 1, Dual Channel
2427 = 0, Single Channel
2428
2429 It's Different from Other XG40 Series.
2430 */
2431 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2432 {
2433 XGINew_DataBusWidth = 32 ; /* 32 bits */
2434 XGINew_ChannelAB = 2 ; /* 2 Channel */
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2437
2438 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2439 return ;
2440
2441 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2442 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2443 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2444 return ;
2445
2446 XGINew_ChannelAB = 1 ; /* Single Channel */
2447 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2448 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2449
2450 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2451 return ;
2452 else
2453 {
2454 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2455 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2456 }
2457 }
2458 else
2459 { /* DDR */
2460 XGINew_DataBusWidth = 64 ; /* 64 bits */
2461 XGINew_ChannelAB = 1 ; /* 1 channels */
2462 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2464
2465 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2466 return ;
2467 else
2468 {
2469 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2471 }
2472 }
2473
2474 break ;
2475
2476 default: /* XG40 */
2477
2478 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2479 {
2480 XGINew_DataBusWidth = 32 ; /* 32 bits */
2481 XGINew_ChannelAB = 3 ;
2482 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2484
2485 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2486 return ;
2487
2488 XGINew_ChannelAB = 2 ; /* 2 channels */
2489 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2490
2491 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2492 return ;
2493
2494 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2495 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2496
2497 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2498 XGINew_ChannelAB = 3 ; /* 4 channels */
2499 else
2500 {
2501 XGINew_ChannelAB = 2 ; /* 2 channels */
2502 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2503 }
2504 }
2505 else
2506 { /* DDR */
2507 XGINew_DataBusWidth = 64 ; /* 64 bits */
2508 XGINew_ChannelAB = 2 ; /* 2 channels */
2509 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2510 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2511
2512 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2513 return ;
2514 else
2515 {
2516 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2518 }
2519 }
2520 break ;
2521 }
2522 }
2523
2524
2525 /* --------------------------------------------------------------------- */
2526 /* Function : XGINew_DDRSizing340 */
2527 /* Input : */
2528 /* Output : */
2529 /* Description : */
2530 /* --------------------------------------------------------------------- */
2531 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2532 {
2533 int i ;
2534 USHORT memsize , addr ;
2535
2536 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2537 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2538 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2539
2540
2541 if ( HwDeviceExtension->jChipType >= XG20 )
2542 {
2543 for( i = 0 ; i < 12 ; i++ )
2544 {
2545 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2546 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2547 if ( memsize == 0 )
2548 continue ;
2549
2550 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2551 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2552 continue ;
2553
2554 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2555 return( 1 ) ;
2556 }
2557 }
2558 else
2559 {
2560 for( i = 0 ; i < 4 ; i++ )
2561 {
2562 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2563 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2564
2565 if ( memsize == 0 )
2566 continue ;
2567
2568 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2569 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2570 continue ;
2571
2572 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2573 return( 1 ) ;
2574 }
2575 }
2576 return( 0 ) ;
2577 }
2578
2579
2580 /* --------------------------------------------------------------------- */
2581 /* Function : XGINew_DDRSizing */
2582 /* Input : */
2583 /* Output : */
2584 /* Description : */
2585 /* --------------------------------------------------------------------- */
2586 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2587 {
2588 int i ;
2589 UCHAR j ;
2590
2591 for( i = 0 ; i < 4 ; i++ )
2592 {
2593 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2594 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2595 for( j = 2 ; j > 0 ; j-- )
2596 {
2597 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2598 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2599 continue ;
2600 else
2601 {
2602 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2603 return( 1 ) ;
2604 }
2605 }
2606 }
2607 return( 0 ) ;
2608 }
2609
2610 /* --------------------------------------------------------------------- */
2611 /* Function : XGINew_SetMemoryClock */
2612 /* Input : */
2613 /* Output : */
2614 /* Description : */
2615 /* --------------------------------------------------------------------- */
2616 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2617 {
2618
2619
2620 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2621 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2622 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2623
2624
2625
2626 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2627 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2628 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2629
2630 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2631 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2632 if ( HwDeviceExtension->jChipType == XG42 )
2633 {
2634 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2635 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2636 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2637 {
2638 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2639 }
2640 }
2641 }
2642
2643
2644 /* --------------------------------------------------------------------- */
2645 /* Function : ChkLFB */
2646 /* Input : */
2647 /* Output : */
2648 /* Description : */
2649 /* --------------------------------------------------------------------- */
2650 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2651 {
2652 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2653 return( TRUE ) ;
2654 else
2655 return( FALSE );
2656 }
2657
2658
2659 /* --------------------------------------------------------------------- */
2660 /* input : dx ,valid value : CR or second chip's CR */
2661 /* */
2662 /* SetPowerConsume : */
2663 /* Description: reduce 40/43 power consumption in first chip or */
2664 /* in second chip, assume CR A1 D[6]="1" in this case */
2665 /* output : none */
2666 /* --------------------------------------------------------------------- */
2667 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2668 {
2669 ULONG lTemp ;
2670 UCHAR bTemp;
2671
2672 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2673 if ((lTemp&0xFF)==0)
2674 {
2675 /* set CR58 D[5]=0 D[3]=0 */
2676 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2677 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2678 if (bTemp&0x20)
2679 {
2680 if (!(bTemp&0x10))
2681 {
2682 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2683 }
2684 else
2685 {
2686 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2687 }
2688
2689 }
2690
2691 }
2692 }
2693
2694
2695
2696 #if defined(LINUX_XF86)||defined(LINUX_KERNEL)
2697 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2698 {
2699
2700 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2701 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2702 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2703 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2704 pVBInfo->ISXPDOS = 0 ;
2705
2706 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2707 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2708 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2709 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2710 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2711 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2712 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2713 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2714 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2715 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2716 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2717 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2718 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2719 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2720 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2721 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2722 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2723 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2724 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2725
2726 switch(HwDeviceExtension->jChipType)
2727 {
2728 case XG40:
2729 case XG41:
2730 case XG42:
2731 case XG20:
2732 case XG21:
2733 default:
2734 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2735 return ;
2736 }
2737
2738 }
2739 #endif /* For Linux */
2740
2741 /* --------------------------------------------------------------------- */
2742 /* Function : ReadVBIOSTablData */
2743 /* Input : */
2744 /* Output : */
2745 /* Description : */
2746 /* --------------------------------------------------------------------- */
2747 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2748 {
2749 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2750 ULONG i ;
2751 UCHAR j , k ;
2752 #if 0
2753 ULONG ii , jj ;
2754 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2755 if ( i != 0 )
2756 UNIROM = 1 ;
2757
2758 ii = 0x90 ;
2759 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2760 {
2761 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2762 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2763 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2764 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2765 ii += 0x05 ;
2766 }
2767
2768 ii = 0xB8 ;
2769 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2770 {
2771 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2772 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2773 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2774 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2775 ii += 0x05 ;
2776 }
2777
2778 /* Volari customize data area start */
2779 /* if ( ChipType == XG40 ) */
2780 if ( ChipType >= XG40 )
2781 {
2782 ii = 0xE0 ;
2783 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2784 {
2785 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2786 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2787 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2788 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2789 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2790 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2791 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2792 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2793 ii += 0x08 ;
2794 }
2795 ii = 0x110 ;
2796 jj = 0x03 ;
2797 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2798 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2799 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2800 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2801 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2802 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2803 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2804 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2805
2806 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2807 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2808 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2809 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2810 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2811 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2812 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2813 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2814 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2815 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2816 ii = 0xF8 ;
2817
2818 for( jj = 0 ; jj < 3 ; jj++ )
2819 {
2820 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2821 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2822 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2823 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2824 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2825 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2826 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2827 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2828 ii += 0x08 ;
2829 }
2830
2831 ii = 0x118 ;
2832 for( j = 3 ; j < 24 ; j++ )
2833 {
2834 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2835 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2836 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2837 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2838 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2839 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2840 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2841 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2842 ii += 0x08 ;
2843 }
2844
2845 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2846
2847 for( j = 0 ; j < 8 ; j++ )
2848 {
2849 for( k = 0 ; k < 4 ; k++ )
2850 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2851 }
2852
2853 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2854
2855 for( j = 0 ; j < 8 ; j++ )
2856 {
2857 for( k = 0 ; k < 4 ; k++ )
2858 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2859 }
2860
2861 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2862 for( j = 0 ; j < 8 ; j++ )
2863 {
2864 for( k = 0 ; k < 32 ; k++ )
2865 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2866 }
2867
2868 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2869
2870 for( j = 0 ; j < 8 ; j++ )
2871 {
2872 for( k = 0 ; k < 2 ; k++ )
2873 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2874 }
2875
2876 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2877 for( j = 0 ; j < 12 ; j++ )
2878 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2879
2880 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2881 for( j = 0 ; j < 4 ; j++ )
2882 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2883
2884 if ( ChipType == XG21 )
2885 {
2886 if (pVideoMemory[ 0x67 ] & 0x80)
2887 {
2888 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2889 }
2890 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2891 {
2892 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2893 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2894 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2895 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2896 }
2897 }
2898
2899 if ( ChipType == XG27 )
2900 {
2901 jj = i+j;
2902 for( i = 0 ; i <= 0xB ; i++,jj++ )
2903 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2904 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2905 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2906
2907 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2908 jj++;
2909 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2910
2911 if (pVideoMemory[ 0x67 ] & 0x80)
2912 {
2913 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2914 }
2915 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2916 {
2917 jj++;
2918 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2919 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2920 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2921 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2922 }
2923
2924 }
2925
2926 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2927 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2928 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2929 if ( ChipType >= XG20 )
2930 {
2931 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2932 if ( ChipType == XG27 )
2933 {
2934 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2935 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2936 }
2937 }
2938
2939 }
2940 #endif
2941 /* Volari customize data area end */
2942
2943 if ( ChipType == XG21 )
2944 {
2945 pVBInfo->IF_DEF_LVDS = 0 ;
2946 if (pVideoMemory[ 0x65 ] & 0x1)
2947 {
2948 pVBInfo->IF_DEF_LVDS = 1 ;
2949 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2950 j = pVideoMemory[ i-1 ] ;
2951 if ( j != 0xff )
2952 {
2953 k = 0;
2954 do
2955 {
2956 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2957 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2958 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2959 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2960 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2961 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2962 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2963 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2964 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2965 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2966 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2967 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2968 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2969 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2970 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2971 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2972 i += 25;
2973 j--;
2974 k++;
2975 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2976 }
2977 else
2978 {
2979 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2980 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2981 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2982 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2983 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2984 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2985 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2986 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2987 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2988 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2989 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2990 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2991 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2992 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2993 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2994 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2995 }
2996 }
2997 }
2998 }
2999
3000 /* --------------------------------------------------------------------- */
3001 /* Function : XGINew_DDR1x_MRS_XG20 */
3002 /* Input : */
3003 /* Output : */
3004 /* Description : */
3005 /* --------------------------------------------------------------------- */
3006 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
3007 {
3008
3009 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
3010 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3011 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3012 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3013 DelayUS( 60 ) ;
3014
3015 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
3016 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3017 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3018 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3019 DelayUS( 60 ) ;
3020 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3021 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3022 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
3023 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3024 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3025 DelayUS( 1000 ) ;
3026 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
3027 DelayUS( 500 ) ;
3028 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3029 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3030 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
3031 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3032 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3033 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
3034 }
3035
3036 /* --------------------------------------------------------------------- */
3037 /* Function : XGINew_SetDRAMModeRegister_XG20 */
3038 /* Input : */
3039 /* Output : */
3040 /* Description : */
3041 /* --------------------------------------------------------------------- */
3042 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3043 {
3044 VB_DEVICE_INFO VBINF;
3045 PVB_DEVICE_INFO pVBInfo = &VBINF;
3046 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3047 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3048 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3049 pVBInfo->ISXPDOS = 0 ;
3050
3051 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3052 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3053 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3054 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3055 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3056 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3057 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3058 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3059 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3060 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3061 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3062 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3063 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3064 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3065 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3066 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3067 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3068
3069 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3070
3071 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3072
3073 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3074 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3075 else
3076 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3077
3078 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3079 }
3080
3081 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3082 {
3083 VB_DEVICE_INFO VBINF;
3084 PVB_DEVICE_INFO pVBInfo = &VBINF;
3085 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3086 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3087 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3088 pVBInfo->ISXPDOS = 0 ;
3089
3090 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3091 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3092 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3093 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3094 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3095 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3096 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3097 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3098 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3099 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3100 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3101 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3102 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3103 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3104 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3105 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3106 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3107
3108 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3109
3110 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3111
3112 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3113 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3114 else
3115 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3116 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3117
3118 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3119 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3120
3121 }
3122 /*
3123 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3124 {
3125 #ifndef LINUX_XF86
3126 UCHAR data ;
3127 #endif
3128 VB_DEVICE_INFO VBINF;
3129 PVB_DEVICE_INFO pVBInfo = &VBINF;
3130 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3131 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3132 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3133 pVBInfo->ISXPDOS = 0 ;
3134
3135 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3136 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3137 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3138 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3139 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3140 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3141 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3142 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3143 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3144 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3145 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3146 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3147 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3148 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3149 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3150 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3151 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3152
3153 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3154
3155 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3156
3157 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3158 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3159 else
3160 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3161
3162 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3163 }
3164 */
3165 /* -------------------------------------------------------- */
3166 /* Function : XGINew_ChkSenseStatus */
3167 /* Input : */
3168 /* Output : */
3169 /* Description : */
3170 /* -------------------------------------------------------- */
3171 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3172 {
3173 USHORT tempbx=0 , temp , tempcx , CR3CData;
3174
3175 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3176
3177 if ( temp & Monitor1Sense )
3178 tempbx |= ActiveCRT1 ;
3179 if ( temp & LCDSense )
3180 tempbx |= ActiveLCD ;
3181 if ( temp & Monitor2Sense )
3182 tempbx |= ActiveCRT2 ;
3183 if ( temp & TVSense )
3184 {
3185 tempbx |= ActiveTV ;
3186 if ( temp & AVIDEOSense )
3187 tempbx |= ( ActiveAVideo << 8 );
3188 if ( temp & SVIDEOSense )
3189 tempbx |= ( ActiveSVideo << 8 );
3190 if ( temp & SCARTSense )
3191 tempbx |= ( ActiveSCART << 8 );
3192 if ( temp & HiTVSense )
3193 tempbx |= ( ActiveHiTV << 8 );
3194 if ( temp & YPbPrSense )
3195 tempbx |= ( ActiveYPbPr << 8 );
3196 }
3197
3198 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3199 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3200
3201 if ( tempbx & tempcx )
3202 {
3203 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3204 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3205 {
3206 tempcx = 0x1FF0 ;
3207 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3208 {
3209 tempbx = 0x1FF0 ;
3210 }
3211 }
3212 }
3213 else
3214 {
3215 tempcx = 0x1FF0 ;
3216 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3217 {
3218 tempbx = 0x1FF0 ;
3219 }
3220 }
3221
3222 tempbx &= tempcx ;
3223 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3224 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3225 }
3226 /* -------------------------------------------------------- */
3227 /* Function : XGINew_SetModeScratch */
3228 /* Input : */
3229 /* Output : */
3230 /* Description : */
3231 /* -------------------------------------------------------- */
3232 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3233 {
3234 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3235
3236 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3237 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3238 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3239
3240 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3241 {
3242 if ( temp & ActiveCRT2 )
3243 tempcl = SetCRT2ToRAMDAC ;
3244 }
3245
3246 if ( temp & ActiveLCD )
3247 {
3248 tempcl |= SetCRT2ToLCD ;
3249 if ( temp & DriverMode )
3250 {
3251 if ( temp & ActiveTV )
3252 {
3253 tempch = SetToLCDA | EnableDualEdge ;
3254 temp ^= SetCRT2ToLCD ;
3255
3256 if ( ( temp >> 8 ) & ActiveAVideo )
3257 tempcl |= SetCRT2ToAVIDEO ;
3258 if ( ( temp >> 8 ) & ActiveSVideo )
3259 tempcl |= SetCRT2ToSVIDEO ;
3260 if ( ( temp >> 8 ) & ActiveSCART )
3261 tempcl |= SetCRT2ToSCART ;
3262
3263 if ( pVBInfo->IF_DEF_HiVision == 1 )
3264 {
3265 if ( ( temp >> 8 ) & ActiveHiTV )
3266 tempcl |= SetCRT2ToHiVisionTV ;
3267 }
3268
3269 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3270 {
3271 if ( ( temp >> 8 ) & ActiveYPbPr )
3272 tempch |= SetYPbPr ;
3273 }
3274 }
3275 }
3276 }
3277 else
3278 {
3279 if ( ( temp >> 8 ) & ActiveAVideo )
3280 tempcl |= SetCRT2ToAVIDEO ;
3281 if ( ( temp >> 8 ) & ActiveSVideo )
3282 tempcl |= SetCRT2ToSVIDEO ;
3283 if ( ( temp >> 8 ) & ActiveSCART )
3284 tempcl |= SetCRT2ToSCART ;
3285
3286 if ( pVBInfo->IF_DEF_HiVision == 1 )
3287 {
3288 if ( ( temp >> 8 ) & ActiveHiTV )
3289 tempcl |= SetCRT2ToHiVisionTV ;
3290 }
3291
3292 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3293 {
3294 if ( ( temp >> 8 ) & ActiveYPbPr )
3295 tempch |= SetYPbPr ;
3296 }
3297 }
3298
3299
3300 tempcl |= SetSimuScanMode ;
3301 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3302 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3303 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3304 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3305 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3306
3307 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3308 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3309 if ( !( temp & ActiveCRT1 ) )
3310 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3311 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3312 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3313 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3314 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3315
3316 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3317 CR38Data &= ~SetYPbPr ;
3318 CR38Data |= tempch ;
3319 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3320
3321 }
3322
3323 /* -------------------------------------------------------- */
3324 /* Function : XGINew_GetXG21Sense */
3325 /* Input : */
3326 /* Output : */
3327 /* Description : */
3328 /* -------------------------------------------------------- */
3329 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3330 {
3331 UCHAR Temp;
3332 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3333
3334 pVBInfo->IF_DEF_LVDS = 0 ;
3335
3336 #ifdef WIN2000
3337 pVBInfo->IF_DEF_CH7007 = 0 ;
3338 if ( ( pVideoMemory[ 0x65 ] & 0x02 ) ) /* For XG21 CH7007 */
3339 {
3340 /* VideoDebugPrint((0, "ReadVBIOSTablData: pVideoMemory[ 0x65 ] =%x\n",pVideoMemory[ 0x65 ])); */
3341 pVBInfo->IF_DEF_CH7007 = 1 ; /* [Billy] 07/05/03 */
3342 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x60 ) ; /* CH7007 on chip */
3343 }
3344 else
3345 #endif
3346 #if 1
3347 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3348 {
3349 pVBInfo->IF_DEF_LVDS = 1 ;
3350 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3351 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3352 }
3353 else
3354 {
3355 #endif
3356 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3357 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3358 if ( Temp == 0xC0 )
3359 { /* DVI & DVO GPIOA/B pull high */
3360 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3361 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3362 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3363 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3364 if ( !Temp )
3365 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3366 else
3367 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3368 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3369 }
3370 #if 1
3371 }
3372 #endif
3373 }
3374
3375 /* -------------------------------------------------------- */
3376 /* Function : XGINew_GetXG27Sense */
3377 /* Input : */
3378 /* Output : */
3379 /* Description : */
3380 /* -------------------------------------------------------- */
3381 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3382 {
3383 UCHAR Temp,bCR4A;
3384
3385 pVBInfo->IF_DEF_LVDS = 0 ;
3386 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3387 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3388 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3389 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3390
3391 if ( Temp <= 0x02 )
3392 {
3393 pVBInfo->IF_DEF_LVDS = 1 ;
3394 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3395 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3396 }
3397 else
3398 {
3399 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3400 }
3401 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3402
3403 }
3404
3405 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3406 {
3407 UCHAR CR38,CR4A,temp;
3408
3409 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3410 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3411 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3412 temp =0;
3413 if ( ( CR38 & 0xE0 ) > 0x80 )
3414 {
3415 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3416 temp &= 0x08;
3417 temp >>= 3;
3418 }
3419
3420 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3421
3422 return temp;
3423 }
3424
3425 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3426 {
3427 UCHAR CR4A,temp;
3428
3429 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3430 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3431 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3432 if ( temp <= 2 )
3433 {
3434 temp &= 0x03;
3435 }
3436 else
3437 {
3438 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3439 }
3440 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3441
3442 return temp;
3443 }
3444
kernel source for telekom puls (alcatel/mediatek)