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dfa047338513e67ffbaad071cf76971745e4277f
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / xgifb / vb_init.c
1 #include "osdef.h"
2 #include "vgatypes.h"
3
4
5 #ifdef LINUX_KERNEL
6 #include <linux/version.h>
7 #include <linux/types.h>
8 #include <linux/delay.h> /* udelay */
9 #include "XGIfb.h"
10 /*#if LINUX_VERSxION_CODE >= KERNEL_VERSION(2,5,0)
11 #include <video/XGIfb.h>
12 #else
13 #include <linux/XGIfb.h>
14 #endif */
15 #endif
16
17
18 #include "vb_def.h"
19 #include "vb_struct.h"
20 #include "vb_util.h"
21 #include "vb_setmode.h"
22 #include "vb_init.h"
23 #include "vb_ext.h"
24
25 #ifdef LINUX_XF86
26 #include "xf86.h"
27 #include "xf86PciInfo.h"
28 #include "xgi.h"
29 #include "xgi_regs.h"
30 #endif
31
32 #ifdef LINUX_KERNEL
33 #include <asm/io.h>
34 #endif
35
36
37
38
39 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
40
41 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
42 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
43 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
44 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
45 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
46 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
47 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
48 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
49 {0x09,0x08,0x01,0x01,0x00}};
50
51 USHORT XGINew_SDRDRAM_TYPE[13][5]=
52 {
53 { 2,12, 9,64,0x35},
54 { 1,13, 9,64,0x44},
55 { 2,12, 8,32,0x31},
56 { 2,11, 9,32,0x25},
57 { 1,12, 9,32,0x34},
58 { 1,13, 8,32,0x40},
59 { 2,11, 8,16,0x21},
60 { 1,12, 8,16,0x30},
61 { 1,11, 9,16,0x24},
62 { 1,11, 8, 8,0x20},
63 { 2, 9, 8, 4,0x01},
64 { 1,10, 8, 4,0x10},
65 { 1, 9, 8, 2,0x00}
66 };
67
68 USHORT XGINew_DDRDRAM_TYPE[4][5]=
69 {
70 { 2,12, 9,64,0x35},
71 { 2,12, 8,32,0x31},
72 { 2,11, 8,16,0x21},
73 { 2, 9, 8, 4,0x01}
74 };
75 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
76 {
77 { 2,13, 9,64,0x45},
78 { 2,12, 9,32,0x35},
79 { 2,12, 8,16,0x31},
80 { 2,11, 8, 8,0x21}
81 };
82 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
83 {
84 { 2,14,11,128,0x5D},
85 { 2,14,10,64,0x59},
86 { 2,13,11,64,0x4D},
87 { 2,14, 9,32,0x55},
88 { 2,13,10,32,0x49},
89 { 2,12,11,32,0x3D},
90 { 2,14, 8,16,0x51},
91 { 2,13, 9,16,0x45},
92 { 2,12,10,16,0x39},
93 { 2,13, 8, 8,0x41},
94 { 2,12, 9, 8,0x35},
95 { 2,12, 8, 4,0x31}
96 };
97
98 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
99 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
100 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
101 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
102 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
103 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
104 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
105 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
106
107 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
108 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
109 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
110 int XGINew_SDRSizing(PVB_DEVICE_INFO);
111 int XGINew_DDRSizing( PVB_DEVICE_INFO );
112 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
113 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
114 ULONG UNIROM; /* UNIROM */
115 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
116 void XGINew_Delay15us(ULONG);
117 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
118 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
119 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
120 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
121 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
122 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
123 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
124 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
125 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
126 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
127 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
128
129
130 #ifdef LINUX_KERNEL
131 void DelayUS(ULONG MicroSeconds)
132 {
133 udelay(MicroSeconds);
134 }
135 #endif
136
137 /* --------------------------------------------------------------------- */
138 /* Function : XGIInitNew */
139 /* Input : */
140 /* Output : */
141 /* Description : */
142 /* --------------------------------------------------------------------- */
143 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
144 {
145
146 VB_DEVICE_INFO VBINF;
147 PVB_DEVICE_INFO pVBInfo = &VBINF;
148 UCHAR i , temp = 0 , temp1 ;
149 // VBIOSVersion[ 5 ] ;
150 PUCHAR volatile pVideoMemory;
151
152 /* ULONG j, k ; */
153
154 PXGI_DSReg pSR ;
155
156 ULONG Temp ;
157
158 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
159
160 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
161
162 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
163
164 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
165
166
167 // Newdebugcode( 0x99 ) ;
168
169
170 /* if ( pVBInfo->ROMAddr == 0 ) */
171 /* return( FALSE ) ; */
172
173 if ( pVBInfo->FBAddr == 0 )
174 {
175 printk("\n pVBInfo->FBAddr == 0 ");
176 return( FALSE ) ;
177 }
178 printk("1");
179 if ( pVBInfo->BaseAddr == 0 )
180 {
181 printk("\npVBInfo->BaseAddr == 0 ");
182 return( FALSE ) ;
183 }
184 printk("2");
185
186 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
187
188 pVBInfo->ISXPDOS = 0 ;
189 printk("3");
190
191 if ( !HwDeviceExtension->bIntegratedMMEnabled )
192 {
193 return( FALSE ) ; /* alan */
194 }
195 printk("4");
196
197 // XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ;
198
199 // VBIOSVersion[ 4 ] = 0x0 ;
200
201 /* 09/07/99 modify by domao */
202
203 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
204 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
205 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
206 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
207 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
208 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
209 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
210 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
211 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
212 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
213 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
214 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
215 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
216 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
217 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
218 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
219 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
220 printk("5");
221
222 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
223 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
224
225 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
226
227 /* ReadVBIOSData */
228 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
229
230 /* 1.Openkey */
231 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
232 printk("6");
233
234 /* GetXG21Sense (GPIO) */
235 if ( HwDeviceExtension->jChipType == XG21 )
236 {
237 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
238 }
239 if ( HwDeviceExtension->jChipType == XG27 )
240 {
241 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
242 }
243 printk("7");
244
245 /* 2.Reset Extended register */
246
247 for( i = 0x06 ; i < 0x20 ; i++ )
248 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
249
250 for( i = 0x21 ; i <= 0x27 ; i++ )
251 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
252
253 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
254 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
255
256 printk("8");
257
258 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
259 {
260 for( i = 0x31 ; i <= 0x3B ; i++ )
261 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
262 }
263 else
264 {
265 for( i = 0x31 ; i <= 0x3D ; i++ )
266 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
267 }
268 printk("9");
269
270 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
271 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
272
273 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
274 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
275
276 for( i = 0x79 ; i <= 0x7C ; i++ )
277 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
278
279 printk("10");
280
281 if ( HwDeviceExtension->jChipType >= XG20 )
282 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
283
284 /* 3.SetMemoryClock
285
286 if ( HwDeviceExtension->jChipType >= XG40 )
287 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
288
289 if ( HwDeviceExtension->jChipType < XG40 )
290 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
291
292 printk("11");
293
294 /* 4.SetDefExt1Regs begin */
295 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
296 if ( HwDeviceExtension->jChipType == XG27 )
297 {
298 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
299 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
300 }
301 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
302 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
303 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
304 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
305 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
306 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
307 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
308
309 /* SR11 = 0x0F ; */
310 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
311
312 printk("12");
313
314 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
315 {
316 // /* Set AGP Rate */
317 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
318 // temp1 &= 0x02 ;
319 // if ( temp1 == 0x02 )
320 // {
321 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
322 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
323 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
324 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
325 // VendorID &= 0x0000FFFF ;
326 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
327 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
328 // GraphicVendorID &= 0x0000FFFF;
329 //
330 // if ( ChipsetID == 0x7301039 )
331 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
332 //
333 // ChipsetID &= 0x0000FFFF ;
334 ///
335 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
336 // {
337 // if ( ChipsetID == 0x1106 )
338 // {
339 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
340 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
341 // else
342 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
343 // }
344 // else
345 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
346 // }
347 // }
348
349 printk("13");
350
351 if ( HwDeviceExtension->jChipType >= XG40 )
352 {
353 /* Set AGP customize registers (in SetDefAGPRegs) Start */
354 for( i = 0x47 ; i <= 0x4C ; i++ )
355 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
356
357 for( i = 0x70 ; i <= 0x71 ; i++ )
358 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
359
360 for( i = 0x74 ; i <= 0x77 ; i++ )
361 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
362 /* Set AGP customize registers (in SetDefAGPRegs) End */
363 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
364 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
365 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
366 // if ( ChipsetID == 0x25308086 )
367 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
368
369 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
370 Temp >>= 20 ;
371 Temp &= 0xF ;
372
373 if ( Temp == 1 )
374 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
375 }
376 printk("14");
377
378 if ( HwDeviceExtension->jChipType < XG40 )
379 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
380 } /* != XG20 */
381
382 /* Set PCI */
383 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
384 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
385 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
386 printk("15");
387
388 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
389 {
390 /* Set VB */
391 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
392 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
393 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
394 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
395 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
396
397
398 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
399
400 printk("16");
401
402 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
403 } /* != XG20 */
404
405
406 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
407
408 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
409 {
410 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
411 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
412 }
413 else
414 {
415 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
416 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
417 }
418 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
419 printk("17");
420
421 /*
422 if ( HwDeviceExtension->jChipType >= XG40 )
423 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
424
425 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
426 {
427 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
428 {
429 if ( pVBInfo->IF_DEF_LVDS == 0 )
430 {
431 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
432 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
433 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
434 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
435 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
436 }
437
438 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
439 }
440 } /* != XG20 */
441 printk("18");
442
443 if ( HwDeviceExtension->jChipType < XG40 )
444 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
445 printk("181");
446
447 if ( HwDeviceExtension->bSkipSense == FALSE )
448 {
449 printk("182");
450
451 XGI_SenseCRT1(pVBInfo) ;
452
453 printk("183");
454 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
455 pVBInfo->IF_DEF_CH7007 = 0;
456 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
457 {
458 printk("184");
459 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
460 printk("185");
461
462 }
463 if ( HwDeviceExtension->jChipType == XG21 )
464 {
465 printk("186");
466
467 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
468 temp = GetXG21FPBits( pVBInfo ) ;
469 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
470 printk("187");
471
472 }
473 if ( HwDeviceExtension->jChipType == XG27 )
474 {
475 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
476 temp = GetXG27FPBits( pVBInfo ) ;
477 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
478 }
479 }
480 printk("19");
481
482 if ( HwDeviceExtension->jChipType >= XG40 )
483 {
484 if ( HwDeviceExtension->jChipType >= XG40 )
485 {
486 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
487 }
488
489 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
490
491 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
492 {
493 pSR = HwDeviceExtension->pSR ;
494 if ( pSR!=NULL )
495 {
496 while( pSR->jIdx != 0xFF )
497 {
498 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
499 pSR++ ;
500 }
501 }
502 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
503 } /* SkipDramSizing */
504 else
505 {
506 #if 0
507 if ( HwDeviceExtension->jChipType == XG20 )
508 {
509 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
510 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
511 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
512 }
513 else
514 #endif
515 {
516 printk("20");
517
518 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
519 }
520 printk("21");
521
522 }
523 } /* XG40 */
524
525 printk("22");
526
527
528 /* SetDefExt2Regs begin */
529 /*
530 AGP = 1 ;
531 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
532 temp &= 0x30 ;
533 if ( temp == 0x30 )
534 AGP = 0 ;
535
536 if ( AGP == 0 )
537 *pVBInfo->pSR21 &= 0xEF ;
538
539 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
540 if ( AGP == 1 )
541 *pVBInfo->pSR22 &= 0x20 ;
542 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
543 */
544
545 // base = 0x80000000 ;
546 // OutPortLong( 0xcf8 , base ) ;
547 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
548 // if ( Temp == 0x1039 )
549 // {
550 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
551 // }
552 // else
553 // {
554 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
555 // }
556
557 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
558
559 printk("23");
560
561
562 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
563 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
564
565 printk("24");
566
567
568 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
569 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
570 printk("25");
571
572 return( TRUE ) ;
573 } /* end of init */
574
575
576
577
578
579 /* ============== alan ====================== */
580
581 /* --------------------------------------------------------------------- */
582 /* Function : XGINew_GetXG20DRAMType */
583 /* Input : */
584 /* Output : */
585 /* Description : */
586 /* --------------------------------------------------------------------- */
587 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
588 {
589 UCHAR data, temp ;
590
591 if ( HwDeviceExtension->jChipType < XG20 )
592 {
593 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
594 {
595 data = *pVBInfo->pSoftSetting & 0x07 ;
596 return( data ) ;
597 }
598 else
599 {
600 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
601
602 if ( data == 0 )
603 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
604
605 return( data ) ;
606 }
607 }
608 else if ( HwDeviceExtension->jChipType == XG27 )
609 {
610 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
611 {
612 data = *pVBInfo->pSoftSetting & 0x07 ;
613 return( data ) ;
614 }
615 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
616
617 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
618 data = 0 ; /*DDR*/
619 else
620 data = 1 ; /*DDRII*/
621 return( data ) ;
622 }
623 else if ( HwDeviceExtension->jChipType == XG21 )
624 {
625 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
626 DelayUS(800);
627 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
628 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
629 // HOTPLUG_SUPPORT
630 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
631 if ( temp & 0x01 ) /* DVI read GPIOH */
632 data = 1 ; /*DDRII*/
633 else
634 data = 0 ; /*DDR*/
635 //~HOTPLUG_SUPPORT
636 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
637 return( data ) ;
638 }
639 else
640 {
641 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
642
643 if ( data == 1 )
644 data ++ ;
645
646 return( data );
647 }
648 }
649
650
651 /* --------------------------------------------------------------------- */
652 /* Function : XGINew_Get310DRAMType */
653 /* Input : */
654 /* Output : */
655 /* Description : */
656 /* --------------------------------------------------------------------- */
657 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
658 {
659 UCHAR data ;
660
661 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
662 /* index &= 07 ; */
663
664 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
665 data = *pVBInfo->pSoftSetting & 0x03 ;
666 else
667 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
668
669 return( data ) ;
670 }
671
672
673
674 /* --------------------------------------------------------------------- */
675 /* Function : XGINew_Delay15us */
676 /* Input : */
677 /* Output : */
678 /* Description : */
679 /* --------------------------------------------------------------------- */
680 /*
681 void XGINew_Delay15us(ULONG ulMicrsoSec)
682 {
683 }
684 */
685
686
687 /* --------------------------------------------------------------------- */
688 /* Function : XGINew_SDR_MRS */
689 /* Input : */
690 /* Output : */
691 /* Description : */
692 /* --------------------------------------------------------------------- */
693 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
694 {
695 USHORT data ;
696
697 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
698 data &= 0x3F ; /* SR16 D7=0,D6=0 */
699 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
700 /* XGINew_Delay15us( 0x100 ) ; */
701 data |= 0x80 ; /* SR16 D7=1,D6=0 */
702 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
703 /* XGINew_Delay15us( 0x100 ) ; */
704 }
705
706
707 /* --------------------------------------------------------------------- */
708 /* Function : XGINew_DDR1x_MRS_340 */
709 /* Input : */
710 /* Output : */
711 /* Description : */
712 /* --------------------------------------------------------------------- */
713 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
714 {
715 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
716 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
717 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
718 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
719
720 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
721 {
722 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
723 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
724 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
725 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
726 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
727 }
728
729 DelayUS( 60 ) ;
730 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
731 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
732 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
733 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
734 DelayUS( 1000 ) ;
735 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
736 DelayUS( 500 ) ;
737 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
738 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
739 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
740 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
741 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
742 }
743
744
745 /* --------------------------------------------------------------------- */
746 /* Function : XGINew_DDR2x_MRS_340 */
747 /* Input : */
748 /* Output : */
749 /* Description : */
750 /* --------------------------------------------------------------------- */
751 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
752 {
753 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
754 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
755 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
756 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
757 DelayUS( 60 ) ;
758 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
759 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
760 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
761 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
762 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
763 DelayUS( 1000 ) ;
764 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
765 DelayUS( 500 ) ;
766 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
767 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
768 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
769 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
770 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
771 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
772 }
773
774 /* --------------------------------------------------------------------- */
775 /* Function : XGINew_DDRII_Bootup_XG27 */
776 /* Input : */
777 /* Output : */
778 /* Description : */
779 /* --------------------------------------------------------------------- */
780 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
781 {
782 ULONG P3d4 = P3c4 + 0x10 ;
783 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
784 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
785
786 /* Set Double Frequency */
787 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
788 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
789
790 DelayUS( 200 ) ;
791
792 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
793 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
794 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
795 DelayUS( 15 ) ;
796 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
797 DelayUS( 15 ) ;
798
799 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
800 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
801 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
802 DelayUS( 15 ) ;
803 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
804 DelayUS( 15) ;
805
806 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
807 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
808 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
809 DelayUS( 30 ) ;
810 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
811 DelayUS( 15 ) ;
812
813 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
814 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
815 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
816 DelayUS( 30 ) ;
817 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
818 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
819 /* DelayUS( 15 ) ; */
820
821 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
822 DelayUS( 60 ) ;
823 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
824
825 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
826 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
827 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
828
829 DelayUS( 30 ) ;
830 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
831 DelayUS( 15 ) ;
832
833 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
834 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
835 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
836 DelayUS( 30 ) ;
837 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
838 DelayUS( 15 ) ;
839
840 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
841 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
842 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
843 DelayUS( 30 ) ;
844 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
845 DelayUS( 15 ) ;
846
847 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
848 DelayUS( 200 ) ;
849
850
851 }
852 /* --------------------------------------------------------------------- */
853 /* Function : XGINew_DDR2_MRS_XG20 */
854 /* Input : */
855 /* Output : */
856 /* Description : */
857 /* --------------------------------------------------------------------- */
858 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
859 {
860 ULONG P3d4 = P3c4 + 0x10 ;
861
862 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
863 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
864
865 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
866
867 DelayUS( 200 ) ;
868 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
869 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
870 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
871 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
872
873 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
874 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
875 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
876 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
877
878 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
879 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
880 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
881 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
882
883 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
884 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
885 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
886 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
887 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
888
889 DelayUS( 15 ) ;
890 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
891 DelayUS( 30 ) ;
892 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
893 DelayUS( 100 ) ;
894
895 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
896 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
897 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
898 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
899 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
900
901 DelayUS( 200 ) ;
902 }
903
904 /* --------------------------------------------------------------------- */
905 /* Function : XGINew_DDR2_MRS_XG20 */
906 /* Input : */
907 /* Output : */
908 /* Description : */
909 /* --------------------------------------------------------------------- */
910 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
911 {
912 ULONG P3d4 = P3c4 + 0x10 ;
913
914 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
915 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
916
917 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
918 DelayUS( 200 ) ;
919 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
920 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
921
922 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
923 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
924 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
925
926 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
927 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
928
929 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
930 DelayUS( 15 ) ; ////06/11/22 XG27 A0
931 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
932
933
934 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
935 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
936
937 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
938 DelayUS( 15 ) ; ////06/11/22 XG27 A0
939 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
940
941 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
942 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
943
944 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
945 DelayUS( 15 ) ; ////06/11/23 XG27 A0
946 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
947
948 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
949 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
950 DelayUS( 60 ) ;
951 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
952
953
954 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
955 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
956
957 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
958 DelayUS( 30 ) ;
959 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
960
961 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
962 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
963
964 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
965 DelayUS( 30 ) ;
966 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
967
968 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
969 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
970
971 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
972 DelayUS( 30 ) ;
973 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
974
975 DelayUS( 15 ) ; ////Start Auto-PreCharge
976 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
977 DelayUS( 200 ) ;
978 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
979
980 }
981
982 /* --------------------------------------------------------------------- */
983 /* Function : XGINew_DDR1x_DefaultRegister */
984 /* Input : */
985 /* Output : */
986 /* Description : */
987 /* --------------------------------------------------------------------- */
988 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
989 {
990 ULONG P3d4 = Port ,
991 P3c4 = Port - 0x10 ;
992
993 if ( HwDeviceExtension->jChipType >= XG20 )
994 {
995 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
996 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
997 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
998 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
999
1000 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1001 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1002
1003 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1004 }
1005 else
1006 {
1007 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1008
1009 switch( HwDeviceExtension->jChipType )
1010 {
1011 case XG41:
1012 case XG42:
1013 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1014 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1015 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1016 break ;
1017 default:
1018 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1019 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1020 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1021 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1022 XGINew_GetReg1( P3d4 , 0x86 ) ;
1023 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1024 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1025 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1026 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1027 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1028 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1029 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1030 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1031 break ;
1032 }
1033
1034 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1035 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1036 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1037 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1038 }
1039 }
1040
1041
1042 /* --------------------------------------------------------------------- */
1043 /* Function : XGINew_DDR2x_DefaultRegister */
1044 /* Input : */
1045 /* Output : */
1046 /* Description : */
1047 /* --------------------------------------------------------------------- */
1048 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1049 {
1050 ULONG P3d4 = Port ,
1051 P3c4 = Port - 0x10 ;
1052
1053 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1054
1055 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1056 switch( HwDeviceExtension->jChipType )
1057 {
1058 case XG41:
1059 case XG42:
1060 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1061 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1062 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1063 break ;
1064 default:
1065 /* keep following setting sequence, each setting in the same reg insert idle */
1066 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1067 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1068 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1069 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1070 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1071 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1072 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1073 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1074 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1075 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1076 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1077 }
1078 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1079 if ( HwDeviceExtension->jChipType == XG42 )
1080 {
1081 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1082 }
1083 else
1084 {
1085 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1086 }
1087 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1088
1089 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1090 }
1091
1092
1093 /* --------------------------------------------------------------------- */
1094 /* Function : XGINew_DDR2_DefaultRegister */
1095 /* Input : */
1096 /* Output : */
1097 /* Description : */
1098 /* --------------------------------------------------------------------- */
1099 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1100 {
1101 ULONG P3d4 = Port ,
1102 P3c4 = Port - 0x10 ;
1103
1104 /* keep following setting sequence, each setting in the same reg insert idle */
1105 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1106 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1107 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1108 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1109 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1110 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1111 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1112 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1113 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1114 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1115 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1116 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1117 if ( HwDeviceExtension->jChipType == XG27 )
1118 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1119 else
1120 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1121
1122 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1123 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1124 if ( HwDeviceExtension->jChipType == XG27 )
1125 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1126 else
1127 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1128 }
1129
1130
1131 /* --------------------------------------------------------------------- */
1132 /* Function : XGINew_SetDRAMDefaultRegister340 */
1133 /* Input : */
1134 /* Output : */
1135 /* Description : */
1136 /* --------------------------------------------------------------------- */
1137 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1138 {
1139 UCHAR temp , temp1 , temp2 , temp3 ,
1140 i , j , k ;
1141
1142 ULONG P3d4 = Port ,
1143 P3c4 = Port - 0x10 ;
1144
1145 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1146 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1147 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1148 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1149
1150 temp2 = 0 ;
1151 for( i = 0 ; i < 4 ; i++ )
1152 {
1153 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1154 for( j = 0 ; j < 4 ; j++ )
1155 {
1156 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1157 temp2 |= temp1 ;
1158 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1159 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1160 temp2 &= 0xF0 ;
1161 temp2 += 0x10 ;
1162 }
1163 }
1164
1165 temp2 = 0 ;
1166 for( i = 0 ; i < 4 ; i++ )
1167 {
1168 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1169 for( j = 0 ; j < 4 ; j++ )
1170 {
1171 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1172 temp2 |= temp1 ;
1173 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1174 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1175 temp2 &= 0xF0 ;
1176 temp2 += 0x10 ;
1177 }
1178 }
1179
1180 temp3 = 0 ;
1181 for( k = 0 ; k < 4 ; k++ )
1182 {
1183 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1184 temp2 = 0 ;
1185 for( i = 0 ; i < 8 ; i++ )
1186 {
1187 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1188 for( j = 0 ; j < 4 ; j++ )
1189 {
1190 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1191 temp2 |= temp1 ;
1192 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1193 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1194 temp2 &= 0xF8 ;
1195 temp2 += 0x08 ;
1196 }
1197 }
1198 temp3 += 0x01 ;
1199 }
1200
1201 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1202 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1203
1204 temp2 = 0x80 ;
1205 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1206 for( j = 0 ; j < 4 ; j++ )
1207 {
1208 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1209 temp2 |= temp1 ;
1210 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1211 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1212 temp2 &= 0xF0 ;
1213 temp2 += 0x10 ;
1214 }
1215
1216 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1217 temp1 = temp & 0x03 ;
1218 temp2 |= temp1 ;
1219 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1220
1221 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1222 temp1 = temp & 0x0F ;
1223 temp2 = ( temp >> 4 ) & 0x07 ;
1224 temp3 = temp & 0x80 ;
1225 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1226 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1227 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1228 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1229
1230 if ( HwDeviceExtension->jChipType == XG27 )
1231 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1232
1233 for( j = 0 ; j <= 6 ; j++ )
1234 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1235
1236 for( j = 0 ; j <= 2 ; j++ )
1237 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1238
1239 for( j = 0 ; j < 2 ; j++ )
1240 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1241
1242 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1243 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1244
1245 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1246
1247 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1248 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1249 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1250 if ( XGINew_RAMType )
1251 {
1252 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1253 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1254 if ( HwDeviceExtension->jChipType == XG27 )
1255 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1256
1257 }
1258 else
1259 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1260 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1261
1262 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1263 if( temp == 0 )
1264 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1265 else
1266 {
1267 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1268 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1269 }
1270 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1271 }
1272
1273
1274 /* --------------------------------------------------------------------- */
1275 /* Function : XGINew_DDR_MRS */
1276 /* Input : */
1277 /* Output : */
1278 /* Description : */
1279 /* --------------------------------------------------------------------- */
1280 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1281 {
1282 USHORT data ;
1283
1284 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1285
1286 /* SR16 <- 1F,DF,2F,AF */
1287 /* yriver modified SR16 <- 0F,DF,0F,AF */
1288 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1289 data = pVideoMemory[ 0xFB ] ;
1290 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1291
1292 data &= 0x0F ;
1293 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1294 data |= 0xC0 ;
1295 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1296 data &= 0x0F ;
1297 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1298 data |= 0x80 ;
1299 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1300 data &= 0x0F ;
1301 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1302 data |= 0xD0 ;
1303 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1304 data &= 0x0F ;
1305 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1306 data |= 0xA0 ;
1307 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1308 /*
1309 else {
1310 data &= 0x0F;
1311 data |= 0x10;
1312 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1313
1314 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1315 {
1316 data &= 0x0F;
1317 }
1318
1319 data |= 0xC0;
1320 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1321
1322
1323 data &= 0x0F;
1324 data |= 0x20;
1325 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1326 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1327 {
1328 data &= 0x0F;
1329 }
1330
1331 data |= 0x80;
1332 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1333 }
1334 */
1335 }
1336
1337
1338 /* check if read cache pointer is correct */
1339
1340
1341
1342 /* --------------------------------------------------------------------- */
1343 /* Function : XGINew_VerifyMclk */
1344 /* Input : */
1345 /* Output : */
1346 /* Description : */
1347 /* --------------------------------------------------------------------- */
1348 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1349 {
1350 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1351 UCHAR i , j ;
1352 USHORT Temp , SR21 ;
1353
1354 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1355 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1356
1357 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1358 {
1359 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1360 {
1361 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1362 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1363 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1364
1365 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1366 Temp |= 0x01 ; /* MCLK reset */
1367
1368
1369 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1370 Temp &= 0xFE ; /* MCLK normal operation */
1371
1372 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1373
1374 pVideoMemory[ 16 + j ] = j ;
1375 if ( pVideoMemory[ 16 + j ] == j )
1376 {
1377 pVideoMemory[ j ] = j ;
1378 break ;
1379 }
1380 }
1381 }
1382 }
1383
1384
1385
1386
1387
1388 /* --------------------------------------------------------------------- */
1389 /* Function : XGINew_SetDRAMSize_340 */
1390 /* Input : */
1391 /* Output : */
1392 /* Description : */
1393 /* --------------------------------------------------------------------- */
1394 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1395 {
1396 USHORT data ;
1397
1398 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1399 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1400
1401 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1402
1403
1404 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1405 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1406 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1407
1408 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1409 /*data |= 0x20 ;*/
1410 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1411 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1412 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1413 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1414
1415 }
1416
1417
1418 /* --------------------------------------------------------------------- */
1419 /* Function : */
1420 /* Input : */
1421 /* Output : */
1422 /* Description : */
1423 /* --------------------------------------------------------------------- */
1424 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1425 {
1426 USHORT data ;
1427 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1428 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1429 #ifdef XGI301
1430 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1431 #endif
1432
1433 #ifdef XGI302 /* alan,should change value */
1434 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1435 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1436 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1437 #endif
1438
1439 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1440
1441 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1442 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1443
1444 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1445 data |= 0x20 ;
1446 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1447
1448 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1449
1450
1451 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1452
1453 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1454 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1455 XGINew_CheckBusWidth_310( pVBInfo) ;
1456 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1457
1458
1459
1460 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1461 {
1462 XGINew_SDRSizing( pVBInfo ) ;
1463 }
1464 else
1465 {
1466 XGINew_DDRSizing( pVBInfo) ;
1467 }
1468
1469
1470
1471
1472 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1473
1474 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1475 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1476 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1477 }
1478
1479
1480
1481 /* --------------------------------------------------------------------- */
1482 /* Function : XGINew_SetDRAMModeRegister340 */
1483 /* Input : */
1484 /* Output : */
1485 /* Description : */
1486 /* --------------------------------------------------------------------- */
1487
1488 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1489 {
1490 UCHAR data ;
1491 VB_DEVICE_INFO VBINF;
1492 PVB_DEVICE_INFO pVBInfo = &VBINF;
1493 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1494 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1495 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1496 pVBInfo->ISXPDOS = 0 ;
1497
1498 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1499 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1500 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1501 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1502 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1503 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1504 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1505 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1506 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1507 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1508 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1509 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1510 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1511 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1512 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1513 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1514 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1515 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1516 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1517
1518 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1519
1520 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1521
1522 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1523 {
1524 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1525 if ( data == 0x01 )
1526 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1527 else
1528 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1529 }
1530 else
1531 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1532
1533 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1534 }
1535
1536 /* --------------------------------------------------------------------- */
1537 /* Function : XGINew_SetDRAMModeRegister */
1538 /* Input : */
1539 /* Output : */
1540 /* Description : */
1541 /* --------------------------------------------------------------------- */
1542 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1543 {
1544 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1545 {
1546 XGINew_SDR_MRS(pVBInfo ) ;
1547 }
1548 else
1549 {
1550 /* SR16 <- 0F,CF,0F,8F */
1551 XGINew_DDR_MRS( pVBInfo ) ;
1552 }
1553 }
1554
1555
1556 /* --------------------------------------------------------------------- */
1557 /* Function : XGINew_DisableRefresh */
1558 /* Input : */
1559 /* Output : */
1560 /* Description : */
1561 /* --------------------------------------------------------------------- */
1562 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1563 {
1564 USHORT data ;
1565
1566
1567 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1568 data &= 0xF8 ;
1569 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1570
1571 }
1572
1573
1574 /* --------------------------------------------------------------------- */
1575 /* Function : XGINew_EnableRefresh */
1576 /* Input : */
1577 /* Output : */
1578 /* Description : */
1579 /* --------------------------------------------------------------------- */
1580 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1581 {
1582
1583 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1584
1585
1586 }
1587
1588
1589 /* --------------------------------------------------------------------- */
1590 /* Function : XGINew_DisableChannelInterleaving */
1591 /* Input : */
1592 /* Output : */
1593 /* Description : */
1594 /* --------------------------------------------------------------------- */
1595 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1596 {
1597 USHORT data ;
1598
1599 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1600 data &= 0x1F ;
1601
1602 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1603 {
1604 case 64:
1605 data |= 0 ;
1606 break ;
1607 case 32:
1608 data |= 0x20 ;
1609 break ;
1610 case 16:
1611 data |= 0x40 ;
1612 break ;
1613 case 4:
1614 data |= 0x60 ;
1615 break ;
1616 default:
1617 break ;
1618 }
1619 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1620 }
1621
1622
1623 /* --------------------------------------------------------------------- */
1624 /* Function : XGINew_SetDRAMSizingType */
1625 /* Input : */
1626 /* Output : */
1627 /* Description : */
1628 /* --------------------------------------------------------------------- */
1629 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1630 {
1631 USHORT data ;
1632
1633 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1634 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1635 DelayUS( 15 ) ;
1636 /* should delay 50 ns */
1637 }
1638
1639
1640 /* --------------------------------------------------------------------- */
1641 /* Function : XGINew_CheckBusWidth_310 */
1642 /* Input : */
1643 /* Output : */
1644 /* Description : */
1645 /* --------------------------------------------------------------------- */
1646 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1647 {
1648 USHORT data ;
1649 PULONG volatile pVideoMemory ;
1650
1651 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1652
1653 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1654 {
1655 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1656 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1657 /* should delay */
1658 XGINew_SDR_MRS( pVBInfo ) ;
1659
1660 XGINew_ChannelAB = 0 ;
1661 XGINew_DataBusWidth = 128 ;
1662 pVideoMemory[ 0 ] = 0x01234567L ;
1663 pVideoMemory[ 1 ] = 0x456789ABL ;
1664 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1665 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1666 pVideoMemory[ 4 ] = 0x55555555L ;
1667 pVideoMemory[ 5 ] = 0x55555555L ;
1668 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1669 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1670
1671 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1672 {
1673 /* ChannelA64Bit */
1674 XGINew_DataBusWidth = 64 ;
1675 XGINew_ChannelAB = 0 ;
1676 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1677 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1678 }
1679
1680 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1681 {
1682 /* ChannelB64Bit */
1683 XGINew_DataBusWidth = 64 ;
1684 XGINew_ChannelAB = 1 ;
1685 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1686 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1687 }
1688
1689 return ;
1690 }
1691 else
1692 {
1693 /* DDR Dual channel */
1694 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1695 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1696 /* should delay */
1697 XGINew_DDR_MRS( pVBInfo ) ;
1698
1699 XGINew_ChannelAB = 0 ;
1700 XGINew_DataBusWidth = 64 ;
1701 pVideoMemory[ 0 ] = 0x01234567L ;
1702 pVideoMemory[ 1 ] = 0x456789ABL ;
1703 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1704 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1705 pVideoMemory[ 4 ] = 0x55555555L ;
1706 pVideoMemory[ 5 ] = 0x55555555L ;
1707 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1708 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1709
1710 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1711 {
1712 if ( pVideoMemory[ 0 ] == 0x01234567L )
1713 {
1714 /* Channel A 64bit */
1715 return ;
1716 }
1717 }
1718 else
1719 {
1720 if ( pVideoMemory[ 0 ] == 0x01234567L )
1721 {
1722 /* Channel A 32bit */
1723 XGINew_DataBusWidth = 32 ;
1724 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1725 return ;
1726 }
1727 }
1728
1729 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1730 XGINew_DDR_MRS( pVBInfo);
1731
1732 XGINew_ChannelAB = 1 ;
1733 XGINew_DataBusWidth = 64 ;
1734 pVideoMemory[ 0 ] = 0x01234567L ;
1735 pVideoMemory[ 1 ] = 0x456789ABL ;
1736 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1737 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1738 pVideoMemory[ 4 ] = 0x55555555L ;
1739 pVideoMemory[ 5 ] = 0x55555555L ;
1740 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1741 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1742
1743 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1744 {
1745 /* Channel B 64 */
1746 if ( pVideoMemory[ 0 ] == 0x01234567L )
1747 {
1748 /* Channel B 64bit */
1749 return ;
1750 }
1751 else
1752 {
1753 /* error */
1754 }
1755 }
1756 else
1757 {
1758 if ( pVideoMemory[ 0 ] == 0x01234567L )
1759 {
1760 /* Channel B 32 */
1761 XGINew_DataBusWidth = 32 ;
1762 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1763 }
1764 else
1765 {
1766 /* error */
1767 }
1768 }
1769 }
1770 }
1771
1772
1773 /* --------------------------------------------------------------------- */
1774 /* Function : XGINew_SetRank */
1775 /* Input : */
1776 /* Output : */
1777 /* Description : */
1778 /* --------------------------------------------------------------------- */
1779 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1780 {
1781 USHORT data ;
1782 int RankSize ;
1783
1784 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1785 return 0 ;
1786
1787 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1788
1789 if ( ( RankNo * RankSize ) <= 128 )
1790 {
1791 data = 0 ;
1792
1793 while( ( RankSize >>= 1 ) > 0 )
1794 {
1795 data += 0x10 ;
1796 }
1797 data |= ( RankNo - 1 ) << 2 ;
1798 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1799 data |= XGINew_ChannelAB ;
1800 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1801 /* should delay */
1802 XGINew_SDR_MRS( pVBInfo ) ;
1803 return( 1 ) ;
1804 }
1805 else
1806 return( 0 ) ;
1807 }
1808
1809
1810 /* --------------------------------------------------------------------- */
1811 /* Function : XGINew_SetDDRChannel */
1812 /* Input : */
1813 /* Output : */
1814 /* Description : */
1815 /* --------------------------------------------------------------------- */
1816 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1817 {
1818 USHORT data ;
1819 int RankSize ;
1820
1821 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1822 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1823 if ( ChannelNo * RankSize <= 128 )
1824 {
1825 data = 0 ;
1826 while( ( RankSize >>= 1 ) > 0 )
1827 {
1828 data += 0x10 ;
1829 }
1830
1831 if ( ChannelNo == 2 )
1832 data |= 0x0C ;
1833
1834 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1835 data |= XGINew_ChannelAB ;
1836 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1837 /* should delay */
1838 XGINew_DDR_MRS( pVBInfo ) ;
1839 return( 1 ) ;
1840 }
1841 else
1842 return( 0 ) ;
1843 }
1844
1845
1846 /* --------------------------------------------------------------------- */
1847 /* Function : XGINew_CheckColumn */
1848 /* Input : */
1849 /* Output : */
1850 /* Description : */
1851 /* --------------------------------------------------------------------- */
1852 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1853 {
1854 int i ;
1855 ULONG Increment , Position ;
1856
1857 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1858 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1859
1860 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1861 {
1862 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1863 Position += Increment ;
1864 }
1865
1866
1867 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1868 {
1869 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1870 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1871 return( 0 ) ;
1872 Position += Increment ;
1873 }
1874 return( 1 ) ;
1875 }
1876
1877
1878 /* --------------------------------------------------------------------- */
1879 /* Function : XGINew_CheckBanks */
1880 /* Input : */
1881 /* Output : */
1882 /* Description : */
1883 /* --------------------------------------------------------------------- */
1884 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1885 {
1886 int i ;
1887 ULONG Increment , Position ;
1888
1889 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1890
1891 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1892 {
1893 /* pVBInfo->FBAddr[ Position ] = Position ; */
1894 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1895 Position += Increment ;
1896 }
1897
1898 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1899 {
1900 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1901 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1902 return( 0 ) ;
1903 Position += Increment ;
1904 }
1905 return( 1 ) ;
1906 }
1907
1908
1909 /* --------------------------------------------------------------------- */
1910 /* Function : XGINew_CheckRank */
1911 /* Input : */
1912 /* Output : */
1913 /* Description : */
1914 /* --------------------------------------------------------------------- */
1915 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1916 {
1917 int i ;
1918 ULONG Increment , Position ;
1919
1920 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1921 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1922
1923 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1924 {
1925 /* pVBInfo->FBAddr[ Position ] = Position ; */
1926 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1927 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1928 Position += Increment ;
1929 }
1930
1931 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1932 {
1933 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1934 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1935 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1936 return( 0 ) ;
1937 Position += Increment ;
1938 }
1939 return( 1 );
1940 }
1941
1942
1943 /* --------------------------------------------------------------------- */
1944 /* Function : XGINew_CheckDDRRank */
1945 /* Input : */
1946 /* Output : */
1947 /* Description : */
1948 /* --------------------------------------------------------------------- */
1949 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1950 {
1951 ULONG Increment , Position ;
1952 USHORT data ;
1953
1954 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1955 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1956
1957 Increment += Increment / 2 ;
1958
1959 Position = 0;
1960 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1961 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1962 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1963 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1964 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1965 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1966
1967 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1968 return( 1 ) ;
1969
1970 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1971 return( 0 ) ;
1972
1973 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1974 data &= 0xF3 ;
1975 data |= 0x0E ;
1976 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1977 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1978 data += 0x20 ;
1979 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1980
1981 return( 1 ) ;
1982 }
1983
1984
1985 /* --------------------------------------------------------------------- */
1986 /* Function : XGINew_CheckRanks */
1987 /* Input : */
1988 /* Output : */
1989 /* Description : */
1990 /* --------------------------------------------------------------------- */
1991 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1992 {
1993 int r ;
1994
1995 for( r = RankNo ; r >= 1 ; r-- )
1996 {
1997 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
1998 return( 0 ) ;
1999 }
2000
2001 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2002 return( 0 ) ;
2003
2004 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2005 return( 0 ) ;
2006
2007 return( 1 ) ;
2008 }
2009
2010
2011 /* --------------------------------------------------------------------- */
2012 /* Function : XGINew_CheckDDRRanks */
2013 /* Input : */
2014 /* Output : */
2015 /* Description : */
2016 /* --------------------------------------------------------------------- */
2017 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2018 {
2019 int r ;
2020
2021 for( r = RankNo ; r >= 1 ; r-- )
2022 {
2023 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2024 return( 0 ) ;
2025 }
2026
2027 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2028 return( 0 ) ;
2029
2030 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2031 return( 0 ) ;
2032
2033 return( 1 ) ;
2034 }
2035
2036
2037 /* --------------------------------------------------------------------- */
2038 /* Function : */
2039 /* Input : */
2040 /* Output : */
2041 /* Description : */
2042 /* --------------------------------------------------------------------- */
2043 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2044 {
2045 int i ;
2046 UCHAR j ;
2047
2048 for( i = 0 ; i < 13 ; i++ )
2049 {
2050 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2051
2052 for( j = 2 ; j > 0 ; j-- )
2053 {
2054 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2055 continue ;
2056 else
2057 {
2058 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2059 return( 1 ) ;
2060 }
2061 }
2062 }
2063 return( 0 ) ;
2064 }
2065
2066
2067 /* --------------------------------------------------------------------- */
2068 /* Function : XGINew_SetDRAMSizeReg */
2069 /* Input : */
2070 /* Output : */
2071 /* Description : */
2072 /* --------------------------------------------------------------------- */
2073 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2074 {
2075 USHORT data = 0 , memsize = 0 ;
2076 int RankSize ;
2077 UCHAR ChannelNo ;
2078
2079 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2080 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2081 data &= 0x80 ;
2082
2083 if ( data == 0x80 )
2084 RankSize *= 2 ;
2085
2086 data = 0 ;
2087
2088 if( XGINew_ChannelAB == 3 )
2089 ChannelNo = 4 ;
2090 else
2091 ChannelNo = XGINew_ChannelAB ;
2092
2093 if ( ChannelNo * RankSize <= 256 )
2094 {
2095 while( ( RankSize >>= 1 ) > 0 )
2096 {
2097 data += 0x10 ;
2098 }
2099
2100 memsize = data >> 4 ;
2101
2102 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2103 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2104
2105 /* data |= XGINew_ChannelAB << 2 ; */
2106 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2107 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2108
2109 /* should delay */
2110 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2111 }
2112 return( memsize ) ;
2113 }
2114
2115
2116 /* --------------------------------------------------------------------- */
2117 /* Function : XGINew_SetDRAMSize20Reg */
2118 /* Input : */
2119 /* Output : */
2120 /* Description : */
2121 /* --------------------------------------------------------------------- */
2122 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2123 {
2124 USHORT data = 0 , memsize = 0 ;
2125 int RankSize ;
2126 UCHAR ChannelNo ;
2127
2128 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2129 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2130 data &= 0x80 ;
2131
2132 if ( data == 0x80 )
2133 RankSize *= 2 ;
2134
2135 data = 0 ;
2136
2137 if( XGINew_ChannelAB == 3 )
2138 ChannelNo = 4 ;
2139 else
2140 ChannelNo = XGINew_ChannelAB ;
2141
2142 if ( ChannelNo * RankSize <= 256 )
2143 {
2144 while( ( RankSize >>= 1 ) > 0 )
2145 {
2146 data += 0x10 ;
2147 }
2148
2149 memsize = data >> 4 ;
2150
2151 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2152 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2153 DelayUS( 15 ) ;
2154
2155 /* data |= XGINew_ChannelAB << 2 ; */
2156 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2157 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2158
2159 /* should delay */
2160 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2161 }
2162 return( memsize ) ;
2163 }
2164
2165
2166 /* --------------------------------------------------------------------- */
2167 /* Function : XGINew_ReadWriteRest */
2168 /* Input : */
2169 /* Output : */
2170 /* Description : */
2171 /* --------------------------------------------------------------------- */
2172 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2173 {
2174 int i ;
2175 ULONG Position = 0 ;
2176
2177 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2178
2179 for( i = StartAddr ; i <= StopAddr ; i++ )
2180 {
2181 Position = 1 << i ;
2182 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2183 }
2184
2185 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2186
2187 Position = 0 ;
2188
2189 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2190 return( 0 ) ;
2191
2192 for( i = StartAddr ; i <= StopAddr ; i++ )
2193 {
2194 Position = 1 << i ;
2195 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2196 return( 0 ) ;
2197 }
2198 return( 1 ) ;
2199 }
2200
2201
2202 /* --------------------------------------------------------------------- */
2203 /* Function : XGINew_CheckFrequence */
2204 /* Input : */
2205 /* Output : */
2206 /* Description : */
2207 /* --------------------------------------------------------------------- */
2208 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2209 {
2210 UCHAR data ;
2211
2212 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2213
2214 if ( ( data & 0x10 ) == 0 )
2215 {
2216 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2217 data = ( data & 0x02 ) >> 1 ;
2218 return( data ) ;
2219 }
2220 else
2221 return( data & 0x01 ) ;
2222 }
2223
2224
2225 /* --------------------------------------------------------------------- */
2226 /* Function : XGINew_CheckChannel */
2227 /* Input : */
2228 /* Output : */
2229 /* Description : */
2230 /* --------------------------------------------------------------------- */
2231 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2232 {
2233 UCHAR data;
2234
2235 switch( HwDeviceExtension->jChipType )
2236 {
2237 case XG20:
2238 case XG21:
2239 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2240 data = data & 0x01;
2241 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2242
2243 if ( data == 0 ) /* Single_32_16 */
2244 {
2245
2246 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2247 {
2248
2249 XGINew_DataBusWidth = 32 ; /* 32 bits */
2250 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2251 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2252 DelayUS( 15 ) ;
2253
2254 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2255 return ;
2256
2257 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2258 {
2259 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2260 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2261 DelayUS( 15 ) ;
2262
2263 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2264 return ;
2265 }
2266 }
2267
2268 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2269 {
2270 XGINew_DataBusWidth = 16 ; /* 16 bits */
2271 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2272 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2273 DelayUS( 15 ) ;
2274
2275 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2276 return ;
2277 else
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2279 DelayUS( 15 ) ;
2280 }
2281
2282 }
2283 else /* Dual_16_8 */
2284 {
2285 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2286 {
2287
2288 XGINew_DataBusWidth = 16 ; /* 16 bits */
2289 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2291 DelayUS( 15 ) ;
2292
2293 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2294 return ;
2295
2296 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2297 {
2298 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2299 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2300 DelayUS( 15 ) ;
2301
2302 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2303 return ;
2304 }
2305 }
2306
2307
2308 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2309 {
2310 XGINew_DataBusWidth = 8 ; /* 8 bits */
2311 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2312 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2313 DelayUS( 15 ) ;
2314
2315 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2316 return ;
2317 else
2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2319 DelayUS( 15 ) ;
2320 }
2321 }
2322 break ;
2323
2324 case XG27:
2325 XGINew_DataBusWidth = 16 ; /* 16 bits */
2326 XGINew_ChannelAB = 1 ; /* Single channel */
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2328 break ;
2329 case XG41:
2330 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2331 {
2332 XGINew_DataBusWidth = 32 ; /* 32 bits */
2333 XGINew_ChannelAB = 3 ; /* Quad Channel */
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2335 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2336
2337 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2338 return ;
2339
2340 XGINew_ChannelAB = 2 ; /* Dual channels */
2341 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2342
2343 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2344 return ;
2345
2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2347
2348 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2349 return ;
2350
2351 XGINew_ChannelAB = 3 ;
2352 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2354
2355 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2356 return ;
2357
2358 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2359
2360 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2361 return ;
2362 else
2363 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2364 }
2365 else
2366 { /* DDR */
2367 XGINew_DataBusWidth = 64 ; /* 64 bits */
2368 XGINew_ChannelAB = 2 ; /* Dual channels */
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2370 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2371
2372 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2373 return ;
2374
2375 XGINew_ChannelAB = 1 ; /* Single channels */
2376 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2377
2378 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2379 return ;
2380
2381 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2382
2383 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2384 return ;
2385
2386 XGINew_ChannelAB = 2 ; /* Dual channels */
2387 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2389
2390 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2391 return ;
2392
2393 XGINew_ChannelAB = 1 ; /* Single channels */
2394 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2395
2396 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2397 return ;
2398 else
2399 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2400 }
2401
2402 break ;
2403
2404 case XG42:
2405 /*
2406 XG42 SR14 D[3] Reserve
2407 D[2] = 1, Dual Channel
2408 = 0, Single Channel
2409
2410 It's Different from Other XG40 Series.
2411 */
2412 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2413 {
2414 XGINew_DataBusWidth = 32 ; /* 32 bits */
2415 XGINew_ChannelAB = 2 ; /* 2 Channel */
2416 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2418
2419 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2420 return ;
2421
2422 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2423 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2424 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2425 return ;
2426
2427 XGINew_ChannelAB = 1 ; /* Single Channel */
2428 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2429 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2430
2431 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2432 return ;
2433 else
2434 {
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2437 }
2438 }
2439 else
2440 { /* DDR */
2441 XGINew_DataBusWidth = 64 ; /* 64 bits */
2442 XGINew_ChannelAB = 1 ; /* 1 channels */
2443 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2445
2446 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2447 return ;
2448 else
2449 {
2450 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2452 }
2453 }
2454
2455 break ;
2456
2457 default: /* XG40 */
2458
2459 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2460 {
2461 XGINew_DataBusWidth = 32 ; /* 32 bits */
2462 XGINew_ChannelAB = 3 ;
2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2464 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2465
2466 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2467 return ;
2468
2469 XGINew_ChannelAB = 2 ; /* 2 channels */
2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2471
2472 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2473 return ;
2474
2475 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2476 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2477
2478 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2479 XGINew_ChannelAB = 3 ; /* 4 channels */
2480 else
2481 {
2482 XGINew_ChannelAB = 2 ; /* 2 channels */
2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2484 }
2485 }
2486 else
2487 { /* DDR */
2488 XGINew_DataBusWidth = 64 ; /* 64 bits */
2489 XGINew_ChannelAB = 2 ; /* 2 channels */
2490 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2492
2493 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2494 return ;
2495 else
2496 {
2497 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2498 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2499 }
2500 }
2501 break ;
2502 }
2503 }
2504
2505
2506 /* --------------------------------------------------------------------- */
2507 /* Function : XGINew_DDRSizing340 */
2508 /* Input : */
2509 /* Output : */
2510 /* Description : */
2511 /* --------------------------------------------------------------------- */
2512 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2513 {
2514 int i ;
2515 USHORT memsize , addr ;
2516
2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2518 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2519 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2520
2521
2522 if ( HwDeviceExtension->jChipType >= XG20 )
2523 {
2524 for( i = 0 ; i < 12 ; i++ )
2525 {
2526 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2527 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2528 if ( memsize == 0 )
2529 continue ;
2530
2531 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2532 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2533 continue ;
2534
2535 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2536 return( 1 ) ;
2537 }
2538 }
2539 else
2540 {
2541 for( i = 0 ; i < 4 ; i++ )
2542 {
2543 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2544 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2545
2546 if ( memsize == 0 )
2547 continue ;
2548
2549 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2550 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2551 continue ;
2552
2553 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2554 return( 1 ) ;
2555 }
2556 }
2557 return( 0 ) ;
2558 }
2559
2560
2561 /* --------------------------------------------------------------------- */
2562 /* Function : XGINew_DDRSizing */
2563 /* Input : */
2564 /* Output : */
2565 /* Description : */
2566 /* --------------------------------------------------------------------- */
2567 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2568 {
2569 int i ;
2570 UCHAR j ;
2571
2572 for( i = 0 ; i < 4 ; i++ )
2573 {
2574 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2575 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2576 for( j = 2 ; j > 0 ; j-- )
2577 {
2578 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2579 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2580 continue ;
2581 else
2582 {
2583 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2584 return( 1 ) ;
2585 }
2586 }
2587 }
2588 return( 0 ) ;
2589 }
2590
2591 /* --------------------------------------------------------------------- */
2592 /* Function : XGINew_SetMemoryClock */
2593 /* Input : */
2594 /* Output : */
2595 /* Description : */
2596 /* --------------------------------------------------------------------- */
2597 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2598 {
2599
2600
2601 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2602 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2603 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2604
2605
2606
2607 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2608 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2609 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2610
2611 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2612 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2613 if ( HwDeviceExtension->jChipType == XG42 )
2614 {
2615 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2616 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2617 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2618 {
2619 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2620 }
2621 }
2622 }
2623
2624
2625 /* --------------------------------------------------------------------- */
2626 /* Function : ChkLFB */
2627 /* Input : */
2628 /* Output : */
2629 /* Description : */
2630 /* --------------------------------------------------------------------- */
2631 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2632 {
2633 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2634 return( TRUE ) ;
2635 else
2636 return( FALSE );
2637 }
2638
2639
2640 /* --------------------------------------------------------------------- */
2641 /* input : dx ,valid value : CR or second chip's CR */
2642 /* */
2643 /* SetPowerConsume : */
2644 /* Description: reduce 40/43 power consumption in first chip or */
2645 /* in second chip, assume CR A1 D[6]="1" in this case */
2646 /* output : none */
2647 /* --------------------------------------------------------------------- */
2648 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2649 {
2650 ULONG lTemp ;
2651 UCHAR bTemp;
2652
2653 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2654 if ((lTemp&0xFF)==0)
2655 {
2656 /* set CR58 D[5]=0 D[3]=0 */
2657 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2658 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2659 if (bTemp&0x20)
2660 {
2661 if (!(bTemp&0x10))
2662 {
2663 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2664 }
2665 else
2666 {
2667 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2668 }
2669
2670 }
2671
2672 }
2673 }
2674
2675
2676
2677 #if defined(LINUX_XF86)||defined(LINUX_KERNEL)
2678 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2679 {
2680
2681 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2682 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2683 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2684 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2685 pVBInfo->ISXPDOS = 0 ;
2686
2687 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2688 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2689 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2690 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2691 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2692 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2693 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2694 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2695 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2696 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2697 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2698 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2699 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2700 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2701 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2702 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2703 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2704 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2705 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2706
2707 switch(HwDeviceExtension->jChipType)
2708 {
2709 case XG40:
2710 case XG41:
2711 case XG42:
2712 case XG20:
2713 case XG21:
2714 default:
2715 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2716 return ;
2717 }
2718
2719 }
2720 #endif /* For Linux */
2721
2722 /* --------------------------------------------------------------------- */
2723 /* Function : ReadVBIOSTablData */
2724 /* Input : */
2725 /* Output : */
2726 /* Description : */
2727 /* --------------------------------------------------------------------- */
2728 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2729 {
2730 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2731 ULONG i ;
2732 UCHAR j , k ;
2733 #if 0
2734 ULONG ii , jj ;
2735 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2736 if ( i != 0 )
2737 UNIROM = 1 ;
2738
2739 ii = 0x90 ;
2740 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2741 {
2742 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2743 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2744 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2745 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2746 ii += 0x05 ;
2747 }
2748
2749 ii = 0xB8 ;
2750 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2751 {
2752 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2753 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2754 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2755 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2756 ii += 0x05 ;
2757 }
2758
2759 /* Volari customize data area start */
2760 /* if ( ChipType == XG40 ) */
2761 if ( ChipType >= XG40 )
2762 {
2763 ii = 0xE0 ;
2764 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2765 {
2766 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2767 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2768 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2769 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2770 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2771 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2772 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2773 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2774 ii += 0x08 ;
2775 }
2776 ii = 0x110 ;
2777 jj = 0x03 ;
2778 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2779 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2780 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2781 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2782 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2783 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2784 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2785 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2786
2787 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2788 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2789 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2790 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2791 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2792 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2793 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2794 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2795 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2796 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2797 ii = 0xF8 ;
2798
2799 for( jj = 0 ; jj < 3 ; jj++ )
2800 {
2801 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2802 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2803 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2804 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2805 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2806 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2807 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2808 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2809 ii += 0x08 ;
2810 }
2811
2812 ii = 0x118 ;
2813 for( j = 3 ; j < 24 ; j++ )
2814 {
2815 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2816 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2817 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2818 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2819 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2820 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2821 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2822 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2823 ii += 0x08 ;
2824 }
2825
2826 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2827
2828 for( j = 0 ; j < 8 ; j++ )
2829 {
2830 for( k = 0 ; k < 4 ; k++ )
2831 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2832 }
2833
2834 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2835
2836 for( j = 0 ; j < 8 ; j++ )
2837 {
2838 for( k = 0 ; k < 4 ; k++ )
2839 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2840 }
2841
2842 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2843 for( j = 0 ; j < 8 ; j++ )
2844 {
2845 for( k = 0 ; k < 32 ; k++ )
2846 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2847 }
2848
2849 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2850
2851 for( j = 0 ; j < 8 ; j++ )
2852 {
2853 for( k = 0 ; k < 2 ; k++ )
2854 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2855 }
2856
2857 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2858 for( j = 0 ; j < 12 ; j++ )
2859 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2860
2861 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2862 for( j = 0 ; j < 4 ; j++ )
2863 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2864
2865 if ( ChipType == XG21 )
2866 {
2867 if (pVideoMemory[ 0x67 ] & 0x80)
2868 {
2869 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2870 }
2871 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2872 {
2873 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2874 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2875 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2876 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2877 }
2878 }
2879
2880 if ( ChipType == XG27 )
2881 {
2882 jj = i+j;
2883 for( i = 0 ; i <= 0xB ; i++,jj++ )
2884 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2885 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2886 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2887
2888 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2889 jj++;
2890 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2891
2892 if (pVideoMemory[ 0x67 ] & 0x80)
2893 {
2894 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2895 }
2896 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2897 {
2898 jj++;
2899 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2900 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2901 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2902 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2903 }
2904
2905 }
2906
2907 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2908 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2909 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2910 if ( ChipType >= XG20 )
2911 {
2912 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2913 if ( ChipType == XG27 )
2914 {
2915 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2916 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2917 }
2918 }
2919
2920 }
2921 #endif
2922 /* Volari customize data area end */
2923
2924 if ( ChipType == XG21 )
2925 {
2926 pVBInfo->IF_DEF_LVDS = 0 ;
2927 if (pVideoMemory[ 0x65 ] & 0x1)
2928 {
2929 pVBInfo->IF_DEF_LVDS = 1 ;
2930 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2931 j = pVideoMemory[ i-1 ] ;
2932 if ( j != 0xff )
2933 {
2934 k = 0;
2935 do
2936 {
2937 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2938 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2939 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2940 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2941 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2942 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2943 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2944 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2945 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2946 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2947 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2948 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2949 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2950 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2951 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2952 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2953 i += 25;
2954 j--;
2955 k++;
2956 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2957 }
2958 else
2959 {
2960 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2961 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2962 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2963 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2964 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2965 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2966 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2967 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2968 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2969 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2970 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2971 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2972 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2973 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2974 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2975 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2976 }
2977 }
2978 }
2979 }
2980
2981 /* --------------------------------------------------------------------- */
2982 /* Function : XGINew_DDR1x_MRS_XG20 */
2983 /* Input : */
2984 /* Output : */
2985 /* Description : */
2986 /* --------------------------------------------------------------------- */
2987 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
2988 {
2989
2990 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2991 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2992 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2993 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2994 DelayUS( 60 ) ;
2995
2996 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2997 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2998 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2999 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3000 DelayUS( 60 ) ;
3001 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3002 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3003 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
3004 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3005 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3006 DelayUS( 1000 ) ;
3007 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
3008 DelayUS( 500 ) ;
3009 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3010 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3011 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
3012 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3013 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3014 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
3015 }
3016
3017 /* --------------------------------------------------------------------- */
3018 /* Function : XGINew_SetDRAMModeRegister_XG20 */
3019 /* Input : */
3020 /* Output : */
3021 /* Description : */
3022 /* --------------------------------------------------------------------- */
3023 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3024 {
3025 VB_DEVICE_INFO VBINF;
3026 PVB_DEVICE_INFO pVBInfo = &VBINF;
3027 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3028 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3029 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3030 pVBInfo->ISXPDOS = 0 ;
3031
3032 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3033 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3034 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3035 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3036 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3037 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3038 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3039 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3040 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3041 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3042 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3043 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3044 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3045 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3046 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3047 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3048 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3049
3050 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3051
3052 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3053
3054 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3055 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3056 else
3057 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3058
3059 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3060 }
3061
3062 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3063 {
3064 VB_DEVICE_INFO VBINF;
3065 PVB_DEVICE_INFO pVBInfo = &VBINF;
3066 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3067 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3068 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3069 pVBInfo->ISXPDOS = 0 ;
3070
3071 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3072 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3073 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3074 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3075 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3076 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3077 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3078 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3079 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3080 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3081 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3082 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3083 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3084 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3085 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3086 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3087 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3088
3089 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3090
3091 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3092
3093 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3094 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3095 else
3096 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3097 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3098
3099 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3100 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3101
3102 }
3103 /*
3104 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3105 {
3106 #ifndef LINUX_XF86
3107 UCHAR data ;
3108 #endif
3109 VB_DEVICE_INFO VBINF;
3110 PVB_DEVICE_INFO pVBInfo = &VBINF;
3111 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3112 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3113 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3114 pVBInfo->ISXPDOS = 0 ;
3115
3116 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3117 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3118 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3119 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3120 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3121 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3122 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3123 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3124 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3125 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3126 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3127 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3128 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3129 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3130 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3131 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3132 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3133
3134 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3135
3136 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3137
3138 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3139 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3140 else
3141 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3142
3143 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3144 }
3145 */
3146 /* -------------------------------------------------------- */
3147 /* Function : XGINew_ChkSenseStatus */
3148 /* Input : */
3149 /* Output : */
3150 /* Description : */
3151 /* -------------------------------------------------------- */
3152 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3153 {
3154 USHORT tempbx=0 , temp , tempcx , CR3CData;
3155
3156 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3157
3158 if ( temp & Monitor1Sense )
3159 tempbx |= ActiveCRT1 ;
3160 if ( temp & LCDSense )
3161 tempbx |= ActiveLCD ;
3162 if ( temp & Monitor2Sense )
3163 tempbx |= ActiveCRT2 ;
3164 if ( temp & TVSense )
3165 {
3166 tempbx |= ActiveTV ;
3167 if ( temp & AVIDEOSense )
3168 tempbx |= ( ActiveAVideo << 8 );
3169 if ( temp & SVIDEOSense )
3170 tempbx |= ( ActiveSVideo << 8 );
3171 if ( temp & SCARTSense )
3172 tempbx |= ( ActiveSCART << 8 );
3173 if ( temp & HiTVSense )
3174 tempbx |= ( ActiveHiTV << 8 );
3175 if ( temp & YPbPrSense )
3176 tempbx |= ( ActiveYPbPr << 8 );
3177 }
3178
3179 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3180 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3181
3182 if ( tempbx & tempcx )
3183 {
3184 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3185 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3186 {
3187 tempcx = 0x1FF0 ;
3188 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3189 {
3190 tempbx = 0x1FF0 ;
3191 }
3192 }
3193 }
3194 else
3195 {
3196 tempcx = 0x1FF0 ;
3197 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3198 {
3199 tempbx = 0x1FF0 ;
3200 }
3201 }
3202
3203 tempbx &= tempcx ;
3204 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3205 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3206 }
3207 /* -------------------------------------------------------- */
3208 /* Function : XGINew_SetModeScratch */
3209 /* Input : */
3210 /* Output : */
3211 /* Description : */
3212 /* -------------------------------------------------------- */
3213 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3214 {
3215 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3216
3217 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3218 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3219 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3220
3221 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3222 {
3223 if ( temp & ActiveCRT2 )
3224 tempcl = SetCRT2ToRAMDAC ;
3225 }
3226
3227 if ( temp & ActiveLCD )
3228 {
3229 tempcl |= SetCRT2ToLCD ;
3230 if ( temp & DriverMode )
3231 {
3232 if ( temp & ActiveTV )
3233 {
3234 tempch = SetToLCDA | EnableDualEdge ;
3235 temp ^= SetCRT2ToLCD ;
3236
3237 if ( ( temp >> 8 ) & ActiveAVideo )
3238 tempcl |= SetCRT2ToAVIDEO ;
3239 if ( ( temp >> 8 ) & ActiveSVideo )
3240 tempcl |= SetCRT2ToSVIDEO ;
3241 if ( ( temp >> 8 ) & ActiveSCART )
3242 tempcl |= SetCRT2ToSCART ;
3243
3244 if ( pVBInfo->IF_DEF_HiVision == 1 )
3245 {
3246 if ( ( temp >> 8 ) & ActiveHiTV )
3247 tempcl |= SetCRT2ToHiVisionTV ;
3248 }
3249
3250 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3251 {
3252 if ( ( temp >> 8 ) & ActiveYPbPr )
3253 tempch |= SetYPbPr ;
3254 }
3255 }
3256 }
3257 }
3258 else
3259 {
3260 if ( ( temp >> 8 ) & ActiveAVideo )
3261 tempcl |= SetCRT2ToAVIDEO ;
3262 if ( ( temp >> 8 ) & ActiveSVideo )
3263 tempcl |= SetCRT2ToSVIDEO ;
3264 if ( ( temp >> 8 ) & ActiveSCART )
3265 tempcl |= SetCRT2ToSCART ;
3266
3267 if ( pVBInfo->IF_DEF_HiVision == 1 )
3268 {
3269 if ( ( temp >> 8 ) & ActiveHiTV )
3270 tempcl |= SetCRT2ToHiVisionTV ;
3271 }
3272
3273 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3274 {
3275 if ( ( temp >> 8 ) & ActiveYPbPr )
3276 tempch |= SetYPbPr ;
3277 }
3278 }
3279
3280
3281 tempcl |= SetSimuScanMode ;
3282 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3283 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3284 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3285 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3286 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3287
3288 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3289 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3290 if ( !( temp & ActiveCRT1 ) )
3291 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3292 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3293 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3294 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3295 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3296
3297 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3298 CR38Data &= ~SetYPbPr ;
3299 CR38Data |= tempch ;
3300 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3301
3302 }
3303
3304 /* -------------------------------------------------------- */
3305 /* Function : XGINew_GetXG21Sense */
3306 /* Input : */
3307 /* Output : */
3308 /* Description : */
3309 /* -------------------------------------------------------- */
3310 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3311 {
3312 UCHAR Temp;
3313 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3314
3315 pVBInfo->IF_DEF_LVDS = 0 ;
3316
3317 #if 1
3318 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3319 {
3320 pVBInfo->IF_DEF_LVDS = 1 ;
3321 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3322 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3323 }
3324 else
3325 {
3326 #endif
3327 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3328 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3329 if ( Temp == 0xC0 )
3330 { /* DVI & DVO GPIOA/B pull high */
3331 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3332 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3333 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3334 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3335 if ( !Temp )
3336 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3337 else
3338 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3339 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3340 }
3341 #if 1
3342 }
3343 #endif
3344 }
3345
3346 /* -------------------------------------------------------- */
3347 /* Function : XGINew_GetXG27Sense */
3348 /* Input : */
3349 /* Output : */
3350 /* Description : */
3351 /* -------------------------------------------------------- */
3352 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3353 {
3354 UCHAR Temp,bCR4A;
3355
3356 pVBInfo->IF_DEF_LVDS = 0 ;
3357 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3358 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3359 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3360 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3361
3362 if ( Temp <= 0x02 )
3363 {
3364 pVBInfo->IF_DEF_LVDS = 1 ;
3365 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3366 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3367 }
3368 else
3369 {
3370 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3371 }
3372 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3373
3374 }
3375
3376 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3377 {
3378 UCHAR CR38,CR4A,temp;
3379
3380 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3381 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3382 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3383 temp =0;
3384 if ( ( CR38 & 0xE0 ) > 0x80 )
3385 {
3386 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3387 temp &= 0x08;
3388 temp >>= 3;
3389 }
3390
3391 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3392
3393 return temp;
3394 }
3395
3396 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3397 {
3398 UCHAR CR4A,temp;
3399
3400 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3401 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3402 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3403 if ( temp <= 2 )
3404 {
3405 temp &= 0x03;
3406 }
3407 else
3408 {
3409 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3410 }
3411 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3412
3413 return temp;
3414 }
3415
kernel source for telekom puls (alcatel/mediatek)