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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / xgifb / vb_init.c
1 #include "osdef.h"
2 #include "vgatypes.h"
3
4
5 #ifdef LINUX_KERNEL
6 #include <linux/version.h>
7 #include <linux/types.h>
8 #include <linux/delay.h> /* udelay */
9 #include "XGIfb.h"
10 /*#if LINUX_VERSxION_CODE >= KERNEL_VERSION(2,5,0)
11 #include <video/XGIfb.h>
12 #else
13 #include <linux/XGIfb.h>
14 #endif */
15 #endif
16
17 #ifdef WIN2000
18 #include <dderror.h>
19 #include <devioctl.h>
20 #include <miniport.h>
21 #include <ntddvdeo.h>
22 #include <video.h>
23 #include "xgiv.h"
24 #include "dd_i2c.h"
25 #include "tools.h"
26 #endif
27
28 #include "vb_def.h"
29 #include "vb_struct.h"
30 #include "vb_util.h"
31 #include "vb_setmode.h"
32 #include "vb_init.h"
33 #include "vb_ext.h"
34
35 #ifdef LINUX_XF86
36 #include "xf86.h"
37 #include "xf86PciInfo.h"
38 #include "xgi.h"
39 #include "xgi_regs.h"
40 #endif
41
42 #ifdef LINUX_KERNEL
43 #include <asm/io.h>
44 #endif
45
46
47
48
49 UCHAR XGINew_ChannelAB,XGINew_DataBusWidth;
50
51 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
52 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44},
53 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40},
54 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32},
55 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30},
56 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28},
57 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24},
58 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10},
59 {0x09,0x08,0x01,0x01,0x00}};
60
61 USHORT XGINew_SDRDRAM_TYPE[13][5]=
62 {
63 { 2,12, 9,64,0x35},
64 { 1,13, 9,64,0x44},
65 { 2,12, 8,32,0x31},
66 { 2,11, 9,32,0x25},
67 { 1,12, 9,32,0x34},
68 { 1,13, 8,32,0x40},
69 { 2,11, 8,16,0x21},
70 { 1,12, 8,16,0x30},
71 { 1,11, 9,16,0x24},
72 { 1,11, 8, 8,0x20},
73 { 2, 9, 8, 4,0x01},
74 { 1,10, 8, 4,0x10},
75 { 1, 9, 8, 2,0x00}
76 };
77
78 USHORT XGINew_DDRDRAM_TYPE[4][5]=
79 {
80 { 2,12, 9,64,0x35},
81 { 2,12, 8,32,0x31},
82 { 2,11, 8,16,0x21},
83 { 2, 9, 8, 4,0x01}
84 };
85 USHORT XGINew_DDRDRAM_TYPE340[4][5]=
86 {
87 { 2,13, 9,64,0x45},
88 { 2,12, 9,32,0x35},
89 { 2,12, 8,16,0x31},
90 { 2,11, 8, 8,0x21}
91 };
92 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
93 {
94 { 2,14,11,128,0x5D},
95 { 2,14,10,64,0x59},
96 { 2,13,11,64,0x4D},
97 { 2,14, 9,32,0x55},
98 { 2,13,10,32,0x49},
99 { 2,12,11,32,0x3D},
100 { 2,14, 8,16,0x51},
101 { 2,13, 9,16,0x45},
102 { 2,12,10,16,0x39},
103 { 2,13, 8, 8,0x41},
104 { 2,12, 9, 8,0x35},
105 { 2,12, 8, 4,0x31}
106 };
107
108 void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
109 void XGINew_SetDRAMSize_310(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
110 void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO );
111 void XGINew_SetDRAMModeRegister(PVB_DEVICE_INFO );
112 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension );
113 void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG, PVB_DEVICE_INFO );
114 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo);
115 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension) ;
116
117 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO );
118 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO) ;
119 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO) ;
120 int XGINew_SDRSizing(PVB_DEVICE_INFO);
121 int XGINew_DDRSizing( PVB_DEVICE_INFO );
122 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO);
123 int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
124 ULONG UNIROM; /* UNIROM */
125 BOOLEAN ChkLFB( PVB_DEVICE_INFO );
126 void XGINew_Delay15us(ULONG);
127 void SetPowerConsume (PXGI_HW_DEVICE_INFO HwDeviceExtension,ULONG XGI_P3d4Port);
128 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo);
129 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo);
130 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension );
131 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension );
132 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
133 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) ;
134 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
135 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo);
136 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ;
137 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo);
138
139 #ifdef WIN2000
140 /* [Billy] 2007/05/20 For CH7007 */
141 extern UCHAR CH7007TVReg_UNTSC[][8],CH7007TVReg_ONTSC[][8],CH7007TVReg_UPAL[][8],CH7007TVReg_OPAL[][8];
142 extern UCHAR XGI7007_CHTVVCLKUNTSC[],XGI7007_CHTVVCLKONTSC[],XGI7007_CHTVVCLKUPAL[],XGI7007_CHTVVCLKOPAL[];
143 #endif
144
145 #ifdef LINUX_KERNEL
146 void DelayUS(ULONG MicroSeconds)
147 {
148 udelay(MicroSeconds);
149 }
150 #endif
151
152 /* --------------------------------------------------------------------- */
153 /* Function : XGIInitNew */
154 /* Input : */
155 /* Output : */
156 /* Description : */
157 /* --------------------------------------------------------------------- */
158 BOOLEAN XGIInitNew( PXGI_HW_DEVICE_INFO HwDeviceExtension )
159 {
160
161 VB_DEVICE_INFO VBINF;
162 PVB_DEVICE_INFO pVBInfo = &VBINF;
163 UCHAR i , temp = 0 , temp1 ;
164 // VBIOSVersion[ 5 ] ;
165 PUCHAR volatile pVideoMemory;
166
167 /* ULONG j, k ; */
168
169 PXGI_DSReg pSR ;
170
171 ULONG Temp ;
172
173 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
174
175 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
176
177 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
178
179 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr;
180
181
182 // Newdebugcode( 0x99 ) ;
183
184
185 /* if ( pVBInfo->ROMAddr == 0 ) */
186 /* return( FALSE ) ; */
187
188 if ( pVBInfo->FBAddr == 0 )
189 {
190 printk("\n pVBInfo->FBAddr == 0 ");
191 return( FALSE ) ;
192 }
193 printk("1");
194 if ( pVBInfo->BaseAddr == 0 )
195 {
196 printk("\npVBInfo->BaseAddr == 0 ");
197 return( FALSE ) ;
198 }
199 printk("2");
200
201 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
202
203 pVBInfo->ISXPDOS = 0 ;
204 printk("3");
205
206 if ( !HwDeviceExtension->bIntegratedMMEnabled )
207 {
208 return( FALSE ) ; /* alan */
209 }
210 printk("4");
211
212 // XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ;
213
214 // VBIOSVersion[ 4 ] = 0x0 ;
215
216 /* 09/07/99 modify by domao */
217
218 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
219 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
220 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
221 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
222 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
223 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
224 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
225 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
226 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
227 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
228 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
229 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
230 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
231 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
232 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
233 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
234 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
235 printk("5");
236
237 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
238 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
239
240 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
241
242 /* ReadVBIOSData */
243 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
244
245 /* 1.Openkey */
246 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
247 printk("6");
248
249 /* GetXG21Sense (GPIO) */
250 if ( HwDeviceExtension->jChipType == XG21 )
251 {
252 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
253 }
254 if ( HwDeviceExtension->jChipType == XG27 )
255 {
256 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
257 }
258 printk("7");
259
260 /* 2.Reset Extended register */
261
262 for( i = 0x06 ; i < 0x20 ; i++ )
263 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
264
265 for( i = 0x21 ; i <= 0x27 ; i++ )
266 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
267
268 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
269 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
270
271 printk("8");
272
273 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
274 {
275 for( i = 0x31 ; i <= 0x3B ; i++ )
276 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
277 }
278 else
279 {
280 for( i = 0x31 ; i <= 0x3D ; i++ )
281 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
282 }
283 printk("9");
284
285 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
286 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
287
288 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
289 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
290
291 for( i = 0x79 ; i <= 0x7C ; i++ )
292 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
293
294 printk("10");
295
296 if ( HwDeviceExtension->jChipType >= XG20 )
297 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
298
299 /* 3.SetMemoryClock
300
301 if ( HwDeviceExtension->jChipType >= XG40 )
302 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
303
304 if ( HwDeviceExtension->jChipType < XG40 )
305 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
306
307 printk("11");
308
309 /* 4.SetDefExt1Regs begin */
310 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
311 if ( HwDeviceExtension->jChipType == XG27 )
312 {
313 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
314 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
315 }
316 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
317 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
318 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
319 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
320 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
321 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
322 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
323
324 /* SR11 = 0x0F ; */
325 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
326
327 printk("12");
328
329 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
330 {
331 // /* Set AGP Rate */
332 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
333 // temp1 &= 0x02 ;
334 // if ( temp1 == 0x02 )
335 // {
336 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
337 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
338 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
339 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
340 // VendorID &= 0x0000FFFF ;
341 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
342 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
343 // GraphicVendorID &= 0x0000FFFF;
344 //
345 // if ( ChipsetID == 0x7301039 )
346 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
347 //
348 // ChipsetID &= 0x0000FFFF ;
349 ///
350 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
351 // {
352 // if ( ChipsetID == 0x1106 )
353 // {
354 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
355 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
356 // else
357 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
358 // }
359 // else
360 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
361 // }
362 // }
363
364 printk("13");
365
366 if ( HwDeviceExtension->jChipType >= XG40 )
367 {
368 /* Set AGP customize registers (in SetDefAGPRegs) Start */
369 for( i = 0x47 ; i <= 0x4C ; i++ )
370 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
371
372 for( i = 0x70 ; i <= 0x71 ; i++ )
373 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
374
375 for( i = 0x74 ; i <= 0x77 ; i++ )
376 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
377 /* Set AGP customize registers (in SetDefAGPRegs) End */
378 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
379 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
380 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
381 // if ( ChipsetID == 0x25308086 )
382 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
383
384 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
385 Temp >>= 20 ;
386 Temp &= 0xF ;
387
388 if ( Temp == 1 )
389 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
390 }
391 printk("14");
392
393 if ( HwDeviceExtension->jChipType < XG40 )
394 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
395 } /* != XG20 */
396
397 /* Set PCI */
398 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
399 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
400 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
401 printk("15");
402
403 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
404 {
405 /* Set VB */
406 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
407 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
408 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
409 temp1 = ( UCHAR )XGINew_GetReg1( pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
410 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ;
411
412
413 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
414
415 printk("16");
416
417 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
418 } /* != XG20 */
419
420
421 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
422
423 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
424 {
425 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
426 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
427 }
428 else
429 {
430 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
431 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
432 }
433 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
434 printk("17");
435
436 /*
437 if ( HwDeviceExtension->jChipType >= XG40 )
438 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
439
440 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
441 {
442 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
443 {
444 if ( pVBInfo->IF_DEF_LVDS == 0 )
445 {
446 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
447 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
448 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
449 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
450 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
451 }
452
453 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
454 }
455 } /* != XG20 */
456 printk("18");
457
458 if ( HwDeviceExtension->jChipType < XG40 )
459 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
460 printk("181");
461
462 if ( HwDeviceExtension->bSkipSense == FALSE )
463 {
464 printk("182");
465
466 XGI_SenseCRT1(pVBInfo) ;
467
468 printk("183");
469 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
470 pVBInfo->IF_DEF_CH7007 = 0;
471 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
472 {
473 printk("184");
474 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
475 printk("185");
476
477 }
478 if ( HwDeviceExtension->jChipType == XG21 )
479 {
480 printk("186");
481
482 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
483 temp = GetXG21FPBits( pVBInfo ) ;
484 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
485 printk("187");
486
487 }
488 if ( HwDeviceExtension->jChipType == XG27 )
489 {
490 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
491 temp = GetXG27FPBits( pVBInfo ) ;
492 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
493 }
494 }
495 printk("19");
496
497 if ( HwDeviceExtension->jChipType >= XG40 )
498 {
499 if ( HwDeviceExtension->jChipType >= XG40 )
500 {
501 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
502 }
503
504 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
505
506 if ( HwDeviceExtension->bSkipDramSizing == TRUE )
507 {
508 pSR = HwDeviceExtension->pSR ;
509 if ( pSR!=NULL )
510 {
511 while( pSR->jIdx != 0xFF )
512 {
513 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
514 pSR++ ;
515 }
516 }
517 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
518 } /* SkipDramSizing */
519 else
520 {
521 #if 0
522 if ( HwDeviceExtension->jChipType == XG20 )
523 {
524 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ;
525 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ;
526 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ;
527 }
528 else
529 #endif
530 {
531 printk("20");
532
533 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
534 }
535 printk("21");
536
537 }
538 } /* XG40 */
539
540 printk("22");
541
542
543 /* SetDefExt2Regs begin */
544 /*
545 AGP = 1 ;
546 temp =( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) ;
547 temp &= 0x30 ;
548 if ( temp == 0x30 )
549 AGP = 0 ;
550
551 if ( AGP == 0 )
552 *pVBInfo->pSR21 &= 0xEF ;
553
554 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
555 if ( AGP == 1 )
556 *pVBInfo->pSR22 &= 0x20 ;
557 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
558 */
559
560 // base = 0x80000000 ;
561 // OutPortLong( 0xcf8 , base ) ;
562 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
563 // if ( Temp == 0x1039 )
564 // {
565 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , ( UCHAR )( ( *pVBInfo->pSR22 ) & 0xFE ) ) ;
566 // }
567 // else
568 // {
569 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
570 // }
571
572 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
573
574 printk("23");
575
576
577 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
578 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
579
580 printk("24");
581
582
583 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
584 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
585 printk("25");
586
587 return( TRUE ) ;
588 } /* end of init */
589
590
591
592
593
594 /* ============== alan ====================== */
595
596 /* --------------------------------------------------------------------- */
597 /* Function : XGINew_GetXG20DRAMType */
598 /* Input : */
599 /* Output : */
600 /* Description : */
601 /* --------------------------------------------------------------------- */
602 UCHAR XGINew_GetXG20DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
603 {
604 UCHAR data, temp ;
605
606 if ( HwDeviceExtension->jChipType < XG20 )
607 {
608 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
609 {
610 data = *pVBInfo->pSoftSetting & 0x07 ;
611 return( data ) ;
612 }
613 else
614 {
615 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
616
617 if ( data == 0 )
618 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
619
620 return( data ) ;
621 }
622 }
623 else if ( HwDeviceExtension->jChipType == XG27 )
624 {
625 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
626 {
627 data = *pVBInfo->pSoftSetting & 0x07 ;
628 return( data ) ;
629 }
630 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
631
632 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
633 data = 0 ; /*DDR*/
634 else
635 data = 1 ; /*DDRII*/
636 return( data ) ;
637 }
638 else if ( HwDeviceExtension->jChipType == XG21 )
639 {
640 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
641 DelayUS(800);
642 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
643 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
644 // HOTPLUG_SUPPORT
645 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
646 if ( temp & 0x01 ) /* DVI read GPIOH */
647 data = 1 ; /*DDRII*/
648 else
649 data = 0 ; /*DDR*/
650 //~HOTPLUG_SUPPORT
651 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
652 return( data ) ;
653 }
654 else
655 {
656 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
657
658 if ( data == 1 )
659 data ++ ;
660
661 return( data );
662 }
663 }
664
665
666 /* --------------------------------------------------------------------- */
667 /* Function : XGINew_Get310DRAMType */
668 /* Input : */
669 /* Output : */
670 /* Description : */
671 /* --------------------------------------------------------------------- */
672 UCHAR XGINew_Get310DRAMType(PVB_DEVICE_INFO pVBInfo)
673 {
674 UCHAR data ;
675
676 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
677 /* index &= 07 ; */
678
679 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
680 data = *pVBInfo->pSoftSetting & 0x03 ;
681 else
682 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
683
684 return( data ) ;
685 }
686
687
688
689 /* --------------------------------------------------------------------- */
690 /* Function : XGINew_Delay15us */
691 /* Input : */
692 /* Output : */
693 /* Description : */
694 /* --------------------------------------------------------------------- */
695 /*
696 void XGINew_Delay15us(ULONG ulMicrsoSec)
697 {
698 }
699 */
700
701
702 /* --------------------------------------------------------------------- */
703 /* Function : XGINew_SDR_MRS */
704 /* Input : */
705 /* Output : */
706 /* Description : */
707 /* --------------------------------------------------------------------- */
708 void XGINew_SDR_MRS( PVB_DEVICE_INFO pVBInfo )
709 {
710 USHORT data ;
711
712 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
713 data &= 0x3F ; /* SR16 D7=0,D6=0 */
714 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
715 /* XGINew_Delay15us( 0x100 ) ; */
716 data |= 0x80 ; /* SR16 D7=1,D6=0 */
717 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
718 /* XGINew_Delay15us( 0x100 ) ; */
719 }
720
721
722 /* --------------------------------------------------------------------- */
723 /* Function : XGINew_DDR1x_MRS_340 */
724 /* Input : */
725 /* Output : */
726 /* Description : */
727 /* --------------------------------------------------------------------- */
728 void XGINew_DDR1x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
729 {
730 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
731 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
732 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
733 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
734
735 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
736 {
737 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
738 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
739 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
740 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
741 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
742 }
743
744 DelayUS( 60 ) ;
745 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
746 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
747 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
748 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
749 DelayUS( 1000 ) ;
750 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
751 DelayUS( 500 ) ;
752 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
753 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
754 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
755 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
756 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
757 }
758
759
760 /* --------------------------------------------------------------------- */
761 /* Function : XGINew_DDR2x_MRS_340 */
762 /* Input : */
763 /* Output : */
764 /* Description : */
765 /* --------------------------------------------------------------------- */
766 void XGINew_DDR2x_MRS_340( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
767 {
768 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
769 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
770 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
771 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
772 DelayUS( 60 ) ;
773 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
774 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
775 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
776 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
777 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
778 DelayUS( 1000 ) ;
779 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
780 DelayUS( 500 ) ;
781 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
782 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
783 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
784 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
785 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
786 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
787 }
788
789 /* --------------------------------------------------------------------- */
790 /* Function : XGINew_DDRII_Bootup_XG27 */
791 /* Input : */
792 /* Output : */
793 /* Description : */
794 /* --------------------------------------------------------------------- */
795 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
796 {
797 ULONG P3d4 = P3c4 + 0x10 ;
798 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
799 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
800
801 /* Set Double Frequency */
802 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
803 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
804
805 DelayUS( 200 ) ;
806
807 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
808 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
809 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
810 DelayUS( 15 ) ;
811 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
812 DelayUS( 15 ) ;
813
814 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
815 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
816 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
817 DelayUS( 15 ) ;
818 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
819 DelayUS( 15) ;
820
821 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
822 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
823 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
824 DelayUS( 30 ) ;
825 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
826 DelayUS( 15 ) ;
827
828 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
829 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
830 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
831 DelayUS( 30 ) ;
832 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
833 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
834 /* DelayUS( 15 ) ; */
835
836 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
837 DelayUS( 60 ) ;
838 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
839
840 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
841 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
842 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
843
844 DelayUS( 30 ) ;
845 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
846 DelayUS( 15 ) ;
847
848 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
849 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
850 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
851 DelayUS( 30 ) ;
852 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
853 DelayUS( 15 ) ;
854
855 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
856 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
857 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
858 DelayUS( 30 ) ;
859 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
860 DelayUS( 15 ) ;
861
862 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
863 DelayUS( 200 ) ;
864
865
866 }
867 /* --------------------------------------------------------------------- */
868 /* Function : XGINew_DDR2_MRS_XG20 */
869 /* Input : */
870 /* Output : */
871 /* Description : */
872 /* --------------------------------------------------------------------- */
873 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
874 {
875 ULONG P3d4 = P3c4 + 0x10 ;
876
877 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
878 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
879
880 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
881
882 DelayUS( 200 ) ;
883 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
884 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
885 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
886 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
887
888 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
889 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
890 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
891 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
892
893 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
894 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
895 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
896 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
897
898 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
899 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
900 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
901 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
902 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
903
904 DelayUS( 15 ) ;
905 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
906 DelayUS( 30 ) ;
907 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
908 DelayUS( 100 ) ;
909
910 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
911 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
912 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
913 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
914 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
915
916 DelayUS( 200 ) ;
917 }
918
919 /* --------------------------------------------------------------------- */
920 /* Function : XGINew_DDR2_MRS_XG20 */
921 /* Input : */
922 /* Output : */
923 /* Description : */
924 /* --------------------------------------------------------------------- */
925 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
926 {
927 ULONG P3d4 = P3c4 + 0x10 ;
928
929 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
930 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
931
932 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
933 DelayUS( 200 ) ;
934 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
935 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
936
937 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
938 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
939 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
940
941 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
942 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
943
944 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
945 DelayUS( 15 ) ; ////06/11/22 XG27 A0
946 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
947
948
949 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
950 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
951
952 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
953 DelayUS( 15 ) ; ////06/11/22 XG27 A0
954 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
955
956 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
957 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
958
959 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
960 DelayUS( 15 ) ; ////06/11/23 XG27 A0
961 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
962
963 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
964 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
965 DelayUS( 60 ) ;
966 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
967
968
969 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
970 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
971
972 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
973 DelayUS( 30 ) ;
974 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
975
976 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
977 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
978
979 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
980 DelayUS( 30 ) ;
981 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
982
983 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
984 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
985
986 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
987 DelayUS( 30 ) ;
988 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
989
990 DelayUS( 15 ) ; ////Start Auto-PreCharge
991 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
992 DelayUS( 200 ) ;
993 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
994
995 }
996
997 /* --------------------------------------------------------------------- */
998 /* Function : XGINew_DDR1x_DefaultRegister */
999 /* Input : */
1000 /* Output : */
1001 /* Description : */
1002 /* --------------------------------------------------------------------- */
1003 void XGINew_DDR1x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1004 {
1005 ULONG P3d4 = Port ,
1006 P3c4 = Port - 0x10 ;
1007
1008 if ( HwDeviceExtension->jChipType >= XG20 )
1009 {
1010 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1011 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1012 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1013 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1014
1015 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1016 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1017
1018 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
1019 }
1020 else
1021 {
1022 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1023
1024 switch( HwDeviceExtension->jChipType )
1025 {
1026 case XG41:
1027 case XG42:
1028 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1029 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1030 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1031 break ;
1032 default:
1033 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1034 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1035 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1036 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1037 XGINew_GetReg1( P3d4 , 0x86 ) ;
1038 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1039 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1040 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1041 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1042 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1043 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1044 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1045 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1046 break ;
1047 }
1048
1049 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1050 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1051 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1052 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1053 }
1054 }
1055
1056
1057 /* --------------------------------------------------------------------- */
1058 /* Function : XGINew_DDR2x_DefaultRegister */
1059 /* Input : */
1060 /* Output : */
1061 /* Description : */
1062 /* --------------------------------------------------------------------- */
1063 void XGINew_DDR2x_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port ,PVB_DEVICE_INFO pVBInfo)
1064 {
1065 ULONG P3d4 = Port ,
1066 P3c4 = Port - 0x10 ;
1067
1068 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1069
1070 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1071 switch( HwDeviceExtension->jChipType )
1072 {
1073 case XG41:
1074 case XG42:
1075 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1076 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1077 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1078 break ;
1079 default:
1080 /* keep following setting sequence, each setting in the same reg insert idle */
1081 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1082 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1083 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1084 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1085 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1086 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1087 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1088 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1089 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1090 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1091 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1092 }
1093 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1094 if ( HwDeviceExtension->jChipType == XG42 )
1095 {
1096 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1097 }
1098 else
1099 {
1100 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1101 }
1102 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1103
1104 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1105 }
1106
1107
1108 /* --------------------------------------------------------------------- */
1109 /* Function : XGINew_DDR2_DefaultRegister */
1110 /* Input : */
1111 /* Output : */
1112 /* Description : */
1113 /* --------------------------------------------------------------------- */
1114 void XGINew_DDR2_DefaultRegister( PXGI_HW_DEVICE_INFO HwDeviceExtension, ULONG Port , PVB_DEVICE_INFO pVBInfo)
1115 {
1116 ULONG P3d4 = Port ,
1117 P3c4 = Port - 0x10 ;
1118
1119 /* keep following setting sequence, each setting in the same reg insert idle */
1120 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1121 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1122 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1123 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1124 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1125 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1126 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1127 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1128 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1129 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1130 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1131 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1132 if ( HwDeviceExtension->jChipType == XG27 )
1133 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1134 else
1135 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1136
1137 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1138 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1139 if ( HwDeviceExtension->jChipType == XG27 )
1140 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1141 else
1142 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1143 }
1144
1145
1146 /* --------------------------------------------------------------------- */
1147 /* Function : XGINew_SetDRAMDefaultRegister340 */
1148 /* Input : */
1149 /* Output : */
1150 /* Description : */
1151 /* --------------------------------------------------------------------- */
1152 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG Port , PVB_DEVICE_INFO pVBInfo)
1153 {
1154 UCHAR temp , temp1 , temp2 , temp3 ,
1155 i , j , k ;
1156
1157 ULONG P3d4 = Port ,
1158 P3c4 = Port - 0x10 ;
1159
1160 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1161 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1162 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1163 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1164
1165 temp2 = 0 ;
1166 for( i = 0 ; i < 4 ; i++ )
1167 {
1168 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1169 for( j = 0 ; j < 4 ; j++ )
1170 {
1171 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1172 temp2 |= temp1 ;
1173 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1174 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1175 temp2 &= 0xF0 ;
1176 temp2 += 0x10 ;
1177 }
1178 }
1179
1180 temp2 = 0 ;
1181 for( i = 0 ; i < 4 ; i++ )
1182 {
1183 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1184 for( j = 0 ; j < 4 ; j++ )
1185 {
1186 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1187 temp2 |= temp1 ;
1188 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1189 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1190 temp2 &= 0xF0 ;
1191 temp2 += 0x10 ;
1192 }
1193 }
1194
1195 temp3 = 0 ;
1196 for( k = 0 ; k < 4 ; k++ )
1197 {
1198 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1199 temp2 = 0 ;
1200 for( i = 0 ; i < 8 ; i++ )
1201 {
1202 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1203 for( j = 0 ; j < 4 ; j++ )
1204 {
1205 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1206 temp2 |= temp1 ;
1207 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1208 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1209 temp2 &= 0xF8 ;
1210 temp2 += 0x08 ;
1211 }
1212 }
1213 temp3 += 0x01 ;
1214 }
1215
1216 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1217 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1218
1219 temp2 = 0x80 ;
1220 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1221 for( j = 0 ; j < 4 ; j++ )
1222 {
1223 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1224 temp2 |= temp1 ;
1225 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1226 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1227 temp2 &= 0xF0 ;
1228 temp2 += 0x10 ;
1229 }
1230
1231 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1232 temp1 = temp & 0x03 ;
1233 temp2 |= temp1 ;
1234 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1235
1236 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1237 temp1 = temp & 0x0F ;
1238 temp2 = ( temp >> 4 ) & 0x07 ;
1239 temp3 = temp & 0x80 ;
1240 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1241 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1242 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1243 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1244
1245 if ( HwDeviceExtension->jChipType == XG27 )
1246 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1247
1248 for( j = 0 ; j <= 6 ; j++ )
1249 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1250
1251 for( j = 0 ; j <= 2 ; j++ )
1252 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1253
1254 for( j = 0 ; j < 2 ; j++ )
1255 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1256
1257 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1258 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1259
1260 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1261
1262 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1263 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1264 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1265 if ( XGINew_RAMType )
1266 {
1267 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1268 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1269 if ( HwDeviceExtension->jChipType == XG27 )
1270 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1271
1272 }
1273 else
1274 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1275 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1276
1277 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1278 if( temp == 0 )
1279 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1280 else
1281 {
1282 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1283 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1284 }
1285 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1286 }
1287
1288
1289 /* --------------------------------------------------------------------- */
1290 /* Function : XGINew_DDR_MRS */
1291 /* Input : */
1292 /* Output : */
1293 /* Description : */
1294 /* --------------------------------------------------------------------- */
1295 void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo)
1296 {
1297 USHORT data ;
1298
1299 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
1300
1301 /* SR16 <- 1F,DF,2F,AF */
1302 /* yriver modified SR16 <- 0F,DF,0F,AF */
1303 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1304 data = pVideoMemory[ 0xFB ] ;
1305 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1306
1307 data &= 0x0F ;
1308 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1309 data |= 0xC0 ;
1310 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1311 data &= 0x0F ;
1312 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1313 data |= 0x80 ;
1314 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1315 data &= 0x0F ;
1316 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1317 data |= 0xD0 ;
1318 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1319 data &= 0x0F ;
1320 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1321 data |= 0xA0 ;
1322 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1323 /*
1324 else {
1325 data &= 0x0F;
1326 data |= 0x10;
1327 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1328
1329 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1330 {
1331 data &= 0x0F;
1332 }
1333
1334 data |= 0xC0;
1335 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1336
1337
1338 data &= 0x0F;
1339 data |= 0x20;
1340 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1341 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1342 {
1343 data &= 0x0F;
1344 }
1345
1346 data |= 0x80;
1347 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1348 }
1349 */
1350 }
1351
1352
1353 /* check if read cache pointer is correct */
1354
1355
1356
1357 /* --------------------------------------------------------------------- */
1358 /* Function : XGINew_VerifyMclk */
1359 /* Input : */
1360 /* Output : */
1361 /* Description : */
1362 /* --------------------------------------------------------------------- */
1363 void XGINew_VerifyMclk( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1364 {
1365 PUCHAR pVideoMemory = pVBInfo->FBAddr ;
1366 UCHAR i , j ;
1367 USHORT Temp , SR21 ;
1368
1369 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1370 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1371
1372 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1373 {
1374 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1375 {
1376 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1377 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1378 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1379
1380 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1381 Temp |= 0x01 ; /* MCLK reset */
1382
1383
1384 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1385 Temp &= 0xFE ; /* MCLK normal operation */
1386
1387 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1388
1389 pVideoMemory[ 16 + j ] = j ;
1390 if ( pVideoMemory[ 16 + j ] == j )
1391 {
1392 pVideoMemory[ j ] = j ;
1393 break ;
1394 }
1395 }
1396 }
1397 }
1398
1399
1400
1401
1402
1403 /* --------------------------------------------------------------------- */
1404 /* Function : XGINew_SetDRAMSize_340 */
1405 /* Input : */
1406 /* Output : */
1407 /* Description : */
1408 /* --------------------------------------------------------------------- */
1409 void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1410 {
1411 USHORT data ;
1412
1413 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1414 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1415
1416 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1417
1418
1419 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1420 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1421 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1422
1423 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1424 /*data |= 0x20 ;*/
1425 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1426 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1427 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1428 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1429
1430 }
1431
1432
1433 /* --------------------------------------------------------------------- */
1434 /* Function : */
1435 /* Input : */
1436 /* Output : */
1437 /* Description : */
1438 /* --------------------------------------------------------------------- */
1439 void XGINew_SetDRAMSize_310( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1440 {
1441 USHORT data ;
1442 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1443 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1444 #ifdef XGI301
1445 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1446 #endif
1447
1448 #ifdef XGI302 /* alan,should change value */
1449 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1450 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1451 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1452 #endif
1453
1454 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1455
1456 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1457 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1458
1459 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1460 data |= 0x20 ;
1461 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1462
1463 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1464
1465
1466 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , ( USHORT )( data | 0x0F ) ) ; /* assume lowest speed DRAM */
1467
1468 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1469 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1470 XGINew_CheckBusWidth_310( pVBInfo) ;
1471 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1472
1473
1474
1475 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1476 {
1477 XGINew_SDRSizing( pVBInfo ) ;
1478 }
1479 else
1480 {
1481 XGINew_DDRSizing( pVBInfo) ;
1482 }
1483
1484
1485
1486
1487 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , pVBInfo->SR15[ 1 ][ XGINew_RAMType ] ) ; /* restore SR16 */
1488
1489 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1490 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1491 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1492 }
1493
1494
1495
1496 /* --------------------------------------------------------------------- */
1497 /* Function : XGINew_SetDRAMModeRegister340 */
1498 /* Input : */
1499 /* Output : */
1500 /* Description : */
1501 /* --------------------------------------------------------------------- */
1502
1503 void XGINew_SetDRAMModeRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension )
1504 {
1505 UCHAR data ;
1506 VB_DEVICE_INFO VBINF;
1507 PVB_DEVICE_INFO pVBInfo = &VBINF;
1508 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1509 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1510 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
1511 pVBInfo->ISXPDOS = 0 ;
1512
1513 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1514 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1515 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1516 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1517 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1518 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1519 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1520 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1521 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1522 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1523 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1524 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1525 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1526 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1527 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1528 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1529 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1530 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1531 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1532
1533 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1534
1535 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1536
1537 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1538 {
1539 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1540 if ( data == 0x01 )
1541 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1542 else
1543 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1544 }
1545 else
1546 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1547
1548 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1549 }
1550
1551 /* --------------------------------------------------------------------- */
1552 /* Function : XGINew_SetDRAMModeRegister */
1553 /* Input : */
1554 /* Output : */
1555 /* Description : */
1556 /* --------------------------------------------------------------------- */
1557 void XGINew_SetDRAMModeRegister( PVB_DEVICE_INFO pVBInfo)
1558 {
1559 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1560 {
1561 XGINew_SDR_MRS(pVBInfo ) ;
1562 }
1563 else
1564 {
1565 /* SR16 <- 0F,CF,0F,8F */
1566 XGINew_DDR_MRS( pVBInfo ) ;
1567 }
1568 }
1569
1570
1571 /* --------------------------------------------------------------------- */
1572 /* Function : XGINew_DisableRefresh */
1573 /* Input : */
1574 /* Output : */
1575 /* Description : */
1576 /* --------------------------------------------------------------------- */
1577 void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1578 {
1579 USHORT data ;
1580
1581
1582 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1583 data &= 0xF8 ;
1584 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1585
1586 }
1587
1588
1589 /* --------------------------------------------------------------------- */
1590 /* Function : XGINew_EnableRefresh */
1591 /* Input : */
1592 /* Output : */
1593 /* Description : */
1594 /* --------------------------------------------------------------------- */
1595 void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
1596 {
1597
1598 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1599
1600
1601 }
1602
1603
1604 /* --------------------------------------------------------------------- */
1605 /* Function : XGINew_DisableChannelInterleaving */
1606 /* Input : */
1607 /* Output : */
1608 /* Description : */
1609 /* --------------------------------------------------------------------- */
1610 void XGINew_DisableChannelInterleaving( int index , USHORT XGINew_DDRDRAM_TYPE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1611 {
1612 USHORT data ;
1613
1614 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1615 data &= 0x1F ;
1616
1617 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1618 {
1619 case 64:
1620 data |= 0 ;
1621 break ;
1622 case 32:
1623 data |= 0x20 ;
1624 break ;
1625 case 16:
1626 data |= 0x40 ;
1627 break ;
1628 case 4:
1629 data |= 0x60 ;
1630 break ;
1631 default:
1632 break ;
1633 }
1634 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1635 }
1636
1637
1638 /* --------------------------------------------------------------------- */
1639 /* Function : XGINew_SetDRAMSizingType */
1640 /* Input : */
1641 /* Output : */
1642 /* Description : */
1643 /* --------------------------------------------------------------------- */
1644 void XGINew_SetDRAMSizingType( int index , USHORT DRAMTYPE_TABLE[][ 5 ] ,PVB_DEVICE_INFO pVBInfo)
1645 {
1646 USHORT data ;
1647
1648 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1649 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1650 DelayUS( 15 ) ;
1651 /* should delay 50 ns */
1652 }
1653
1654
1655 /* --------------------------------------------------------------------- */
1656 /* Function : XGINew_CheckBusWidth_310 */
1657 /* Input : */
1658 /* Output : */
1659 /* Description : */
1660 /* --------------------------------------------------------------------- */
1661 void XGINew_CheckBusWidth_310( PVB_DEVICE_INFO pVBInfo)
1662 {
1663 USHORT data ;
1664 PULONG volatile pVideoMemory ;
1665
1666 pVideoMemory = (PULONG) pVBInfo->FBAddr;
1667
1668 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1669 {
1670 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1671 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1672 /* should delay */
1673 XGINew_SDR_MRS( pVBInfo ) ;
1674
1675 XGINew_ChannelAB = 0 ;
1676 XGINew_DataBusWidth = 128 ;
1677 pVideoMemory[ 0 ] = 0x01234567L ;
1678 pVideoMemory[ 1 ] = 0x456789ABL ;
1679 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1680 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1681 pVideoMemory[ 4 ] = 0x55555555L ;
1682 pVideoMemory[ 5 ] = 0x55555555L ;
1683 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1684 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1685
1686 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1687 {
1688 /* ChannelA64Bit */
1689 XGINew_DataBusWidth = 64 ;
1690 XGINew_ChannelAB = 0 ;
1691 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1692 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( data & 0xFD ) ) ;
1693 }
1694
1695 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1696 {
1697 /* ChannelB64Bit */
1698 XGINew_DataBusWidth = 64 ;
1699 XGINew_ChannelAB = 1 ;
1700 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1701 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( USHORT )( ( data & 0xFD ) | 0x01 ) ) ;
1702 }
1703
1704 return ;
1705 }
1706 else
1707 {
1708 /* DDR Dual channel */
1709 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1710 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1711 /* should delay */
1712 XGINew_DDR_MRS( pVBInfo ) ;
1713
1714 XGINew_ChannelAB = 0 ;
1715 XGINew_DataBusWidth = 64 ;
1716 pVideoMemory[ 0 ] = 0x01234567L ;
1717 pVideoMemory[ 1 ] = 0x456789ABL ;
1718 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1719 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1720 pVideoMemory[ 4 ] = 0x55555555L ;
1721 pVideoMemory[ 5 ] = 0x55555555L ;
1722 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1723 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1724
1725 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1726 {
1727 if ( pVideoMemory[ 0 ] == 0x01234567L )
1728 {
1729 /* Channel A 64bit */
1730 return ;
1731 }
1732 }
1733 else
1734 {
1735 if ( pVideoMemory[ 0 ] == 0x01234567L )
1736 {
1737 /* Channel A 32bit */
1738 XGINew_DataBusWidth = 32 ;
1739 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1740 return ;
1741 }
1742 }
1743
1744 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1745 XGINew_DDR_MRS( pVBInfo);
1746
1747 XGINew_ChannelAB = 1 ;
1748 XGINew_DataBusWidth = 64 ;
1749 pVideoMemory[ 0 ] = 0x01234567L ;
1750 pVideoMemory[ 1 ] = 0x456789ABL ;
1751 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1752 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1753 pVideoMemory[ 4 ] = 0x55555555L ;
1754 pVideoMemory[ 5 ] = 0x55555555L ;
1755 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1756 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1757
1758 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1759 {
1760 /* Channel B 64 */
1761 if ( pVideoMemory[ 0 ] == 0x01234567L )
1762 {
1763 /* Channel B 64bit */
1764 return ;
1765 }
1766 else
1767 {
1768 /* error */
1769 }
1770 }
1771 else
1772 {
1773 if ( pVideoMemory[ 0 ] == 0x01234567L )
1774 {
1775 /* Channel B 32 */
1776 XGINew_DataBusWidth = 32 ;
1777 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1778 }
1779 else
1780 {
1781 /* error */
1782 }
1783 }
1784 }
1785 }
1786
1787
1788 /* --------------------------------------------------------------------- */
1789 /* Function : XGINew_SetRank */
1790 /* Input : */
1791 /* Output : */
1792 /* Description : */
1793 /* --------------------------------------------------------------------- */
1794 int XGINew_SetRank( int index , UCHAR RankNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1795 {
1796 USHORT data ;
1797 int RankSize ;
1798
1799 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1800 return 0 ;
1801
1802 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1803
1804 if ( ( RankNo * RankSize ) <= 128 )
1805 {
1806 data = 0 ;
1807
1808 while( ( RankSize >>= 1 ) > 0 )
1809 {
1810 data += 0x10 ;
1811 }
1812 data |= ( RankNo - 1 ) << 2 ;
1813 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1814 data |= XGINew_ChannelAB ;
1815 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1816 /* should delay */
1817 XGINew_SDR_MRS( pVBInfo ) ;
1818 return( 1 ) ;
1819 }
1820 else
1821 return( 0 ) ;
1822 }
1823
1824
1825 /* --------------------------------------------------------------------- */
1826 /* Function : XGINew_SetDDRChannel */
1827 /* Input : */
1828 /* Output : */
1829 /* Description : */
1830 /* --------------------------------------------------------------------- */
1831 int XGINew_SetDDRChannel( int index , UCHAR ChannelNo , UCHAR XGINew_ChannelAB , USHORT DRAMTYPE_TABLE[][ 5 ] , PVB_DEVICE_INFO pVBInfo)
1832 {
1833 USHORT data ;
1834 int RankSize ;
1835
1836 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1837 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1838 if ( ChannelNo * RankSize <= 128 )
1839 {
1840 data = 0 ;
1841 while( ( RankSize >>= 1 ) > 0 )
1842 {
1843 data += 0x10 ;
1844 }
1845
1846 if ( ChannelNo == 2 )
1847 data |= 0x0C ;
1848
1849 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1850 data |= XGINew_ChannelAB ;
1851 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1852 /* should delay */
1853 XGINew_DDR_MRS( pVBInfo ) ;
1854 return( 1 ) ;
1855 }
1856 else
1857 return( 0 ) ;
1858 }
1859
1860
1861 /* --------------------------------------------------------------------- */
1862 /* Function : XGINew_CheckColumn */
1863 /* Input : */
1864 /* Output : */
1865 /* Description : */
1866 /* --------------------------------------------------------------------- */
1867 int XGINew_CheckColumn( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1868 {
1869 int i ;
1870 ULONG Increment , Position ;
1871
1872 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1873 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1874
1875 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1876 {
1877 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1878 Position += Increment ;
1879 }
1880
1881 #ifdef WIN2000 /* chiawen for linux solution */
1882 DelayUS( 100 ) ;
1883 #endif
1884
1885 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1886 {
1887 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1888 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1889 return( 0 ) ;
1890 Position += Increment ;
1891 }
1892 return( 1 ) ;
1893 }
1894
1895
1896 /* --------------------------------------------------------------------- */
1897 /* Function : XGINew_CheckBanks */
1898 /* Input : */
1899 /* Output : */
1900 /* Description : */
1901 /* --------------------------------------------------------------------- */
1902 int XGINew_CheckBanks( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1903 {
1904 int i ;
1905 ULONG Increment , Position ;
1906
1907 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1908
1909 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1910 {
1911 /* pVBInfo->FBAddr[ Position ] = Position ; */
1912 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1913 Position += Increment ;
1914 }
1915
1916 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1917 {
1918 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1919 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1920 return( 0 ) ;
1921 Position += Increment ;
1922 }
1923 return( 1 ) ;
1924 }
1925
1926
1927 /* --------------------------------------------------------------------- */
1928 /* Function : XGINew_CheckRank */
1929 /* Input : */
1930 /* Output : */
1931 /* Description : */
1932 /* --------------------------------------------------------------------- */
1933 int XGINew_CheckRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1934 {
1935 int i ;
1936 ULONG Increment , Position ;
1937
1938 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1939 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1940
1941 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1942 {
1943 /* pVBInfo->FBAddr[ Position ] = Position ; */
1944 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */
1945 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
1946 Position += Increment ;
1947 }
1948
1949 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1950 {
1951 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1952 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */
1953 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
1954 return( 0 ) ;
1955 Position += Increment ;
1956 }
1957 return( 1 );
1958 }
1959
1960
1961 /* --------------------------------------------------------------------- */
1962 /* Function : XGINew_CheckDDRRank */
1963 /* Input : */
1964 /* Output : */
1965 /* Description : */
1966 /* --------------------------------------------------------------------- */
1967 int XGINew_CheckDDRRank( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
1968 {
1969 ULONG Increment , Position ;
1970 USHORT data ;
1971
1972 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1973 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1974
1975 Increment += Increment / 2 ;
1976
1977 Position = 0;
1978 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ;
1979 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ;
1980 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ;
1981 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ;
1982 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ;
1983 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ;
1984
1985 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB )
1986 return( 1 ) ;
1987
1988 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 )
1989 return( 0 ) ;
1990
1991 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1992 data &= 0xF3 ;
1993 data |= 0x0E ;
1994 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1995 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1996 data += 0x20 ;
1997 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1998
1999 return( 1 ) ;
2000 }
2001
2002
2003 /* --------------------------------------------------------------------- */
2004 /* Function : XGINew_CheckRanks */
2005 /* Input : */
2006 /* Output : */
2007 /* Description : */
2008 /* --------------------------------------------------------------------- */
2009 int XGINew_CheckRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2010 {
2011 int r ;
2012
2013 for( r = RankNo ; r >= 1 ; r-- )
2014 {
2015 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2016 return( 0 ) ;
2017 }
2018
2019 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2020 return( 0 ) ;
2021
2022 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2023 return( 0 ) ;
2024
2025 return( 1 ) ;
2026 }
2027
2028
2029 /* --------------------------------------------------------------------- */
2030 /* Function : XGINew_CheckDDRRanks */
2031 /* Input : */
2032 /* Output : */
2033 /* Description : */
2034 /* --------------------------------------------------------------------- */
2035 int XGINew_CheckDDRRanks( int RankNo , int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2036 {
2037 int r ;
2038
2039 for( r = RankNo ; r >= 1 ; r-- )
2040 {
2041 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2042 return( 0 ) ;
2043 }
2044
2045 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2046 return( 0 ) ;
2047
2048 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2049 return( 0 ) ;
2050
2051 return( 1 ) ;
2052 }
2053
2054
2055 /* --------------------------------------------------------------------- */
2056 /* Function : */
2057 /* Input : */
2058 /* Output : */
2059 /* Description : */
2060 /* --------------------------------------------------------------------- */
2061 int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo)
2062 {
2063 int i ;
2064 UCHAR j ;
2065
2066 for( i = 0 ; i < 13 ; i++ )
2067 {
2068 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2069
2070 for( j = 2 ; j > 0 ; j-- )
2071 {
2072 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) )
2073 continue ;
2074 else
2075 {
2076 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2077 return( 1 ) ;
2078 }
2079 }
2080 }
2081 return( 0 ) ;
2082 }
2083
2084
2085 /* --------------------------------------------------------------------- */
2086 /* Function : XGINew_SetDRAMSizeReg */
2087 /* Input : */
2088 /* Output : */
2089 /* Description : */
2090 /* --------------------------------------------------------------------- */
2091 USHORT XGINew_SetDRAMSizeReg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2092 {
2093 USHORT data = 0 , memsize = 0 ;
2094 int RankSize ;
2095 UCHAR ChannelNo ;
2096
2097 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2098 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2099 data &= 0x80 ;
2100
2101 if ( data == 0x80 )
2102 RankSize *= 2 ;
2103
2104 data = 0 ;
2105
2106 if( XGINew_ChannelAB == 3 )
2107 ChannelNo = 4 ;
2108 else
2109 ChannelNo = XGINew_ChannelAB ;
2110
2111 if ( ChannelNo * RankSize <= 256 )
2112 {
2113 while( ( RankSize >>= 1 ) > 0 )
2114 {
2115 data += 0x10 ;
2116 }
2117
2118 memsize = data >> 4 ;
2119
2120 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2121 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2122
2123 /* data |= XGINew_ChannelAB << 2 ; */
2124 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2125 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2126
2127 /* should delay */
2128 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2129 }
2130 return( memsize ) ;
2131 }
2132
2133
2134 /* --------------------------------------------------------------------- */
2135 /* Function : XGINew_SetDRAMSize20Reg */
2136 /* Input : */
2137 /* Output : */
2138 /* Description : */
2139 /* --------------------------------------------------------------------- */
2140 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2141 {
2142 USHORT data = 0 , memsize = 0 ;
2143 int RankSize ;
2144 UCHAR ChannelNo ;
2145
2146 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2147 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2148 data &= 0x80 ;
2149
2150 if ( data == 0x80 )
2151 RankSize *= 2 ;
2152
2153 data = 0 ;
2154
2155 if( XGINew_ChannelAB == 3 )
2156 ChannelNo = 4 ;
2157 else
2158 ChannelNo = XGINew_ChannelAB ;
2159
2160 if ( ChannelNo * RankSize <= 256 )
2161 {
2162 while( ( RankSize >>= 1 ) > 0 )
2163 {
2164 data += 0x10 ;
2165 }
2166
2167 memsize = data >> 4 ;
2168
2169 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2170 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2171 DelayUS( 15 ) ;
2172
2173 /* data |= XGINew_ChannelAB << 2 ; */
2174 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2175 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2176
2177 /* should delay */
2178 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2179 }
2180 return( memsize ) ;
2181 }
2182
2183
2184 /* --------------------------------------------------------------------- */
2185 /* Function : XGINew_ReadWriteRest */
2186 /* Input : */
2187 /* Output : */
2188 /* Description : */
2189 /* --------------------------------------------------------------------- */
2190 int XGINew_ReadWriteRest( USHORT StopAddr , USHORT StartAddr, PVB_DEVICE_INFO pVBInfo)
2191 {
2192 int i ;
2193 ULONG Position = 0 ;
2194
2195 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2196
2197 for( i = StartAddr ; i <= StopAddr ; i++ )
2198 {
2199 Position = 1 << i ;
2200 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ;
2201 }
2202
2203 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2204
2205 Position = 0 ;
2206
2207 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2208 return( 0 ) ;
2209
2210 for( i = StartAddr ; i <= StopAddr ; i++ )
2211 {
2212 Position = 1 << i ;
2213 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position )
2214 return( 0 ) ;
2215 }
2216 return( 1 ) ;
2217 }
2218
2219
2220 /* --------------------------------------------------------------------- */
2221 /* Function : XGINew_CheckFrequence */
2222 /* Input : */
2223 /* Output : */
2224 /* Description : */
2225 /* --------------------------------------------------------------------- */
2226 UCHAR XGINew_CheckFrequence( PVB_DEVICE_INFO pVBInfo )
2227 {
2228 UCHAR data ;
2229
2230 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2231
2232 if ( ( data & 0x10 ) == 0 )
2233 {
2234 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2235 data = ( data & 0x02 ) >> 1 ;
2236 return( data ) ;
2237 }
2238 else
2239 return( data & 0x01 ) ;
2240 }
2241
2242
2243 /* --------------------------------------------------------------------- */
2244 /* Function : XGINew_CheckChannel */
2245 /* Input : */
2246 /* Output : */
2247 /* Description : */
2248 /* --------------------------------------------------------------------- */
2249 void XGINew_CheckChannel( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2250 {
2251 UCHAR data;
2252
2253 switch( HwDeviceExtension->jChipType )
2254 {
2255 case XG20:
2256 case XG21:
2257 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2258 data = data & 0x01;
2259 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2260
2261 if ( data == 0 ) /* Single_32_16 */
2262 {
2263
2264 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2265 {
2266
2267 XGINew_DataBusWidth = 32 ; /* 32 bits */
2268 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2269 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2270 DelayUS( 15 ) ;
2271
2272 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2273 return ;
2274
2275 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2276 {
2277 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2279 DelayUS( 15 ) ;
2280
2281 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2282 return ;
2283 }
2284 }
2285
2286 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2287 {
2288 XGINew_DataBusWidth = 16 ; /* 16 bits */
2289 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2291 DelayUS( 15 ) ;
2292
2293 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2294 return ;
2295 else
2296 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2297 DelayUS( 15 ) ;
2298 }
2299
2300 }
2301 else /* Dual_16_8 */
2302 {
2303 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2304 {
2305
2306 XGINew_DataBusWidth = 16 ; /* 16 bits */
2307 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2308 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2309 DelayUS( 15 ) ;
2310
2311 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2312 return ;
2313
2314 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2315 {
2316 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2317 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2318 DelayUS( 15 ) ;
2319
2320 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2321 return ;
2322 }
2323 }
2324
2325
2326 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2327 {
2328 XGINew_DataBusWidth = 8 ; /* 8 bits */
2329 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2330 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2331 DelayUS( 15 ) ;
2332
2333 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2334 return ;
2335 else
2336 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2337 DelayUS( 15 ) ;
2338 }
2339 }
2340 break ;
2341
2342 case XG27:
2343 XGINew_DataBusWidth = 16 ; /* 16 bits */
2344 XGINew_ChannelAB = 1 ; /* Single channel */
2345 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2346 break ;
2347 case XG41:
2348 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2349 {
2350 XGINew_DataBusWidth = 32 ; /* 32 bits */
2351 XGINew_ChannelAB = 3 ; /* Quad Channel */
2352 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2354
2355 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2356 return ;
2357
2358 XGINew_ChannelAB = 2 ; /* Dual channels */
2359 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2360
2361 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2362 return ;
2363
2364 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2365
2366 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2367 return ;
2368
2369 XGINew_ChannelAB = 3 ;
2370 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2371 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2372
2373 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2374 return ;
2375
2376 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2377
2378 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2379 return ;
2380 else
2381 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2382 }
2383 else
2384 { /* DDR */
2385 XGINew_DataBusWidth = 64 ; /* 64 bits */
2386 XGINew_ChannelAB = 2 ; /* Dual channels */
2387 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2389
2390 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2391 return ;
2392
2393 XGINew_ChannelAB = 1 ; /* Single channels */
2394 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2395
2396 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2397 return ;
2398
2399 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2400
2401 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2402 return ;
2403
2404 XGINew_ChannelAB = 2 ; /* Dual channels */
2405 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2406 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2407
2408 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2409 return ;
2410
2411 XGINew_ChannelAB = 1 ; /* Single channels */
2412 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2413
2414 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2415 return ;
2416 else
2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2418 }
2419
2420 break ;
2421
2422 case XG42:
2423 /*
2424 XG42 SR14 D[3] Reserve
2425 D[2] = 1, Dual Channel
2426 = 0, Single Channel
2427
2428 It's Different from Other XG40 Series.
2429 */
2430 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2431 {
2432 XGINew_DataBusWidth = 32 ; /* 32 bits */
2433 XGINew_ChannelAB = 2 ; /* 2 Channel */
2434 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2436
2437 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2438 return ;
2439
2440 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2441 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2442 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2443 return ;
2444
2445 XGINew_ChannelAB = 1 ; /* Single Channel */
2446 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2447 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2448
2449 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2450 return ;
2451 else
2452 {
2453 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2454 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2455 }
2456 }
2457 else
2458 { /* DDR */
2459 XGINew_DataBusWidth = 64 ; /* 64 bits */
2460 XGINew_ChannelAB = 1 ; /* 1 channels */
2461 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2462 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2463
2464 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2465 return ;
2466 else
2467 {
2468 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2469 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2470 }
2471 }
2472
2473 break ;
2474
2475 default: /* XG40 */
2476
2477 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2478 {
2479 XGINew_DataBusWidth = 32 ; /* 32 bits */
2480 XGINew_ChannelAB = 3 ;
2481 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2482 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2483
2484 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2485 return ;
2486
2487 XGINew_ChannelAB = 2 ; /* 2 channels */
2488 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2489
2490 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2491 return ;
2492
2493 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2494 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2495
2496 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2497 XGINew_ChannelAB = 3 ; /* 4 channels */
2498 else
2499 {
2500 XGINew_ChannelAB = 2 ; /* 2 channels */
2501 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2502 }
2503 }
2504 else
2505 { /* DDR */
2506 XGINew_DataBusWidth = 64 ; /* 64 bits */
2507 XGINew_ChannelAB = 2 ; /* 2 channels */
2508 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2509 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2510
2511 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2512 return ;
2513 else
2514 {
2515 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2516 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2517 }
2518 }
2519 break ;
2520 }
2521 }
2522
2523
2524 /* --------------------------------------------------------------------- */
2525 /* Function : XGINew_DDRSizing340 */
2526 /* Input : */
2527 /* Output : */
2528 /* Description : */
2529 /* --------------------------------------------------------------------- */
2530 int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2531 {
2532 int i ;
2533 USHORT memsize , addr ;
2534
2535 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2536 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2537 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2538
2539
2540 if ( HwDeviceExtension->jChipType >= XG20 )
2541 {
2542 for( i = 0 ; i < 12 ; i++ )
2543 {
2544 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2545 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2546 if ( memsize == 0 )
2547 continue ;
2548
2549 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2550 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2551 continue ;
2552
2553 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2554 return( 1 ) ;
2555 }
2556 }
2557 else
2558 {
2559 for( i = 0 ; i < 4 ; i++ )
2560 {
2561 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2562 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2563
2564 if ( memsize == 0 )
2565 continue ;
2566
2567 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2568 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) )
2569 continue ;
2570
2571 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2572 return( 1 ) ;
2573 }
2574 }
2575 return( 0 ) ;
2576 }
2577
2578
2579 /* --------------------------------------------------------------------- */
2580 /* Function : XGINew_DDRSizing */
2581 /* Input : */
2582 /* Output : */
2583 /* Description : */
2584 /* --------------------------------------------------------------------- */
2585 int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo)
2586 {
2587 int i ;
2588 UCHAR j ;
2589
2590 for( i = 0 ; i < 4 ; i++ )
2591 {
2592 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2593 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2594 for( j = 2 ; j > 0 ; j-- )
2595 {
2596 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2597 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2598 continue ;
2599 else
2600 {
2601 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2602 return( 1 ) ;
2603 }
2604 }
2605 }
2606 return( 0 ) ;
2607 }
2608
2609 /* --------------------------------------------------------------------- */
2610 /* Function : XGINew_SetMemoryClock */
2611 /* Input : */
2612 /* Output : */
2613 /* Description : */
2614 /* --------------------------------------------------------------------- */
2615 void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2616 {
2617
2618
2619 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2620 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2621 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2622
2623
2624
2625 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2626 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2627 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2628
2629 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2630 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2631 if ( HwDeviceExtension->jChipType == XG42 )
2632 {
2633 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2634 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2635 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2636 {
2637 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGINew_GetReg1( pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ;
2638 }
2639 }
2640 }
2641
2642
2643 /* --------------------------------------------------------------------- */
2644 /* Function : ChkLFB */
2645 /* Input : */
2646 /* Output : */
2647 /* Description : */
2648 /* --------------------------------------------------------------------- */
2649 BOOLEAN ChkLFB( PVB_DEVICE_INFO pVBInfo )
2650 {
2651 if ( LFBDRAMTrap & XGINew_GetReg1( pVBInfo->P3d4 , 0x78 ) )
2652 return( TRUE ) ;
2653 else
2654 return( FALSE );
2655 }
2656
2657
2658 /* --------------------------------------------------------------------- */
2659 /* input : dx ,valid value : CR or second chip's CR */
2660 /* */
2661 /* SetPowerConsume : */
2662 /* Description: reduce 40/43 power consumption in first chip or */
2663 /* in second chip, assume CR A1 D[6]="1" in this case */
2664 /* output : none */
2665 /* --------------------------------------------------------------------- */
2666 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , ULONG XGI_P3d4Port )
2667 {
2668 ULONG lTemp ;
2669 UCHAR bTemp;
2670
2671 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2672 if ((lTemp&0xFF)==0)
2673 {
2674 /* set CR58 D[5]=0 D[3]=0 */
2675 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2676 bTemp = (UCHAR) XGINew_GetReg1( XGI_P3d4Port , 0xCB ) ;
2677 if (bTemp&0x20)
2678 {
2679 if (!(bTemp&0x10))
2680 {
2681 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2682 }
2683 else
2684 {
2685 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2686 }
2687
2688 }
2689
2690 }
2691 }
2692
2693
2694
2695 #if defined(LINUX_XF86)||defined(LINUX_KERNEL)
2696 void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
2697 {
2698
2699 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
2700 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2701 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2702 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
2703 pVBInfo->ISXPDOS = 0 ;
2704
2705 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2706 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2707 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2708 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2709 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2710 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2711 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2712 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2713 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2714 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2715 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2716 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2717 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2718 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2719 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2720 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2721 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2722 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2723 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2724
2725 switch(HwDeviceExtension->jChipType)
2726 {
2727 case XG40:
2728 case XG41:
2729 case XG42:
2730 case XG20:
2731 case XG21:
2732 default:
2733 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2734 return ;
2735 }
2736
2737 }
2738 #endif /* For Linux */
2739
2740 /* --------------------------------------------------------------------- */
2741 /* Function : ReadVBIOSTablData */
2742 /* Input : */
2743 /* Output : */
2744 /* Description : */
2745 /* --------------------------------------------------------------------- */
2746 void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo)
2747 {
2748 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
2749 ULONG i ;
2750 UCHAR j , k ;
2751 #if 0
2752 ULONG ii , jj ;
2753 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */
2754 if ( i != 0 )
2755 UNIROM = 1 ;
2756
2757 ii = 0x90 ;
2758 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2759 {
2760 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ;
2761 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ;
2762 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ;
2763 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2764 ii += 0x05 ;
2765 }
2766
2767 ii = 0xB8 ;
2768 for( jj = 0x00 ; jj < 0x08 ; jj++ )
2769 {
2770 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ;
2771 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ;
2772 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ;
2773 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ;
2774 ii += 0x05 ;
2775 }
2776
2777 /* Volari customize data area start */
2778 /* if ( ChipType == XG40 ) */
2779 if ( ChipType >= XG40 )
2780 {
2781 ii = 0xE0 ;
2782 for( jj = 0x00 ; jj < 0x03 ; jj++ )
2783 {
2784 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */
2785 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2786 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2787 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2788 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2789 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2790 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2791 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2792 ii += 0x08 ;
2793 }
2794 ii = 0x110 ;
2795 jj = 0x03 ;
2796 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */
2797 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2798 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2799 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2800 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2801 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2802 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2803 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2804
2805 *pVBInfo->pSR07 = pVideoMemory[ 0x74 ] ;
2806 *pVBInfo->pSR1F = pVideoMemory[ 0x75 ] ;
2807 *pVBInfo->pSR21 = pVideoMemory[ 0x76 ] ;
2808 *pVBInfo->pSR22 = pVideoMemory[ 0x77 ] ;
2809 *pVBInfo->pSR23 = pVideoMemory[ 0x78 ] ;
2810 *pVBInfo->pSR24 = pVideoMemory[ 0x79 ] ;
2811 pVBInfo->SR25[ 0 ] = pVideoMemory[ 0x7A ] ;
2812 *pVBInfo->pSR31 = pVideoMemory[ 0x7B ] ;
2813 *pVBInfo->pSR32 = pVideoMemory[ 0x7C ] ;
2814 *pVBInfo->pSR33 = pVideoMemory[ 0x7D ] ;
2815 ii = 0xF8 ;
2816
2817 for( jj = 0 ; jj < 3 ; jj++ )
2818 {
2819 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ;
2820 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2821 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2822 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2823 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2824 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2825 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2826 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2827 ii += 0x08 ;
2828 }
2829
2830 ii = 0x118 ;
2831 for( j = 3 ; j < 24 ; j++ )
2832 {
2833 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ;
2834 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ;
2835 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ;
2836 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ;
2837 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ;
2838 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ;
2839 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ;
2840 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ;
2841 ii += 0x08 ;
2842 }
2843
2844 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ;
2845
2846 for( j = 0 ; j < 8 ; j++ )
2847 {
2848 for( k = 0 ; k < 4 ; k++ )
2849 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2850 }
2851
2852 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ;
2853
2854 for( j = 0 ; j < 8 ; j++ )
2855 {
2856 for( k = 0 ; k < 4 ; k++ )
2857 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ;
2858 }
2859
2860 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ;
2861 for( j = 0 ; j < 8 ; j++ )
2862 {
2863 for( k = 0 ; k < 32 ; k++ )
2864 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ;
2865 }
2866
2867 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ;
2868
2869 for( j = 0 ; j < 8 ; j++ )
2870 {
2871 for( k = 0 ; k < 2 ; k++ )
2872 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ;
2873 }
2874
2875 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ;
2876 for( j = 0 ; j < 12 ; j++ )
2877 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ;
2878
2879 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ;
2880 for( j = 0 ; j < 4 ; j++ )
2881 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ;
2882
2883 if ( ChipType == XG21 )
2884 {
2885 if (pVideoMemory[ 0x67 ] & 0x80)
2886 {
2887 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2888 }
2889 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2890 {
2891 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ;
2892 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ;
2893 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ;
2894 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ;
2895 }
2896 }
2897
2898 if ( ChipType == XG27 )
2899 {
2900 jj = i+j;
2901 for( i = 0 ; i <= 0xB ; i++,jj++ )
2902 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ;
2903 for( i = 0x0 ; i <= 0x1 ; i++,jj++ )
2904 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ;
2905
2906 *pVBInfo->pSR40 = pVideoMemory[ jj ] ;
2907 jj++;
2908 *pVBInfo->pSR41 = pVideoMemory[ jj ] ;
2909
2910 if (pVideoMemory[ 0x67 ] & 0x80)
2911 {
2912 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ];
2913 }
2914 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 )
2915 {
2916 jj++;
2917 *pVBInfo->pCR2E = pVideoMemory[ jj ] ;
2918 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ;
2919 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ;
2920 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ;
2921 }
2922
2923 }
2924
2925 *pVBInfo->pCRCF = pVideoMemory[ 0x1CA ] ;
2926 *pVBInfo->pXGINew_DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ;
2927 *pVBInfo->pXGINew_I2CDefinition = pVideoMemory[ 0x1D1 ] ;
2928 if ( ChipType >= XG20 )
2929 {
2930 *pVBInfo->pXGINew_CR97 = pVideoMemory[ 0x1D2 ] ;
2931 if ( ChipType == XG27 )
2932 {
2933 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ;
2934 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ;
2935 }
2936 }
2937
2938 }
2939 #endif
2940 /* Volari customize data area end */
2941
2942 if ( ChipType == XG21 )
2943 {
2944 pVBInfo->IF_DEF_LVDS = 0 ;
2945 if (pVideoMemory[ 0x65 ] & 0x1)
2946 {
2947 pVBInfo->IF_DEF_LVDS = 1 ;
2948 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2949 j = pVideoMemory[ i-1 ] ;
2950 if ( j != 0xff )
2951 {
2952 k = 0;
2953 do
2954 {
2955 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2956 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2957 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2958 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2959 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2960 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2961 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2962 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2963 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2964 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2965 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2966 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2967 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2968 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2969 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2970 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2971 i += 25;
2972 j--;
2973 k++;
2974 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) );
2975 }
2976 else
2977 {
2978 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2979 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2980 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2981 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2982 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2983 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2984 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2985 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2986 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2987 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2988 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2989 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2990 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2991 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2992 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2993 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2994 }
2995 }
2996 }
2997 }
2998
2999 /* --------------------------------------------------------------------- */
3000 /* Function : XGINew_DDR1x_MRS_XG20 */
3001 /* Input : */
3002 /* Output : */
3003 /* Description : */
3004 /* --------------------------------------------------------------------- */
3005 void XGINew_DDR1x_MRS_XG20( ULONG P3c4 , PVB_DEVICE_INFO pVBInfo)
3006 {
3007
3008 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
3009 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3010 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3011 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3012 DelayUS( 60 ) ;
3013
3014 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
3015 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
3016 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
3017 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
3018 DelayUS( 60 ) ;
3019 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3020 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3021 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
3022 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3023 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3024 DelayUS( 1000 ) ;
3025 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
3026 DelayUS( 500 ) ;
3027 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
3028 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
3029 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
3030 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
3031 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
3032 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
3033 }
3034
3035 /* --------------------------------------------------------------------- */
3036 /* Function : XGINew_SetDRAMModeRegister_XG20 */
3037 /* Input : */
3038 /* Output : */
3039 /* Description : */
3040 /* --------------------------------------------------------------------- */
3041 void XGINew_SetDRAMModeRegister_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3042 {
3043 VB_DEVICE_INFO VBINF;
3044 PVB_DEVICE_INFO pVBInfo = &VBINF;
3045 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3046 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3047 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3048 pVBInfo->ISXPDOS = 0 ;
3049
3050 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3051 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3052 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3053 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3054 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3055 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3056 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3057 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3058 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3059 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3060 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3061 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3062 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3063 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3064 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3065 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3066 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3067
3068 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3069
3070 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3071
3072 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3073 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3074 else
3075 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3076
3077 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3078 }
3079
3080 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3081 {
3082 VB_DEVICE_INFO VBINF;
3083 PVB_DEVICE_INFO pVBInfo = &VBINF;
3084 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3085 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3086 pVBInfo->BaseAddr = (ULONG)HwDeviceExtension->pjIOAddress ;
3087 pVBInfo->ISXPDOS = 0 ;
3088
3089 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3090 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3091 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3092 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3093 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3094 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3095 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3096 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3097 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3098 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3099 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3100 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3101 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3102 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3103 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3104 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3105 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3106
3107 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3108
3109 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3110
3111 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3112 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3113 else
3114 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3115 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
3116
3117 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3118 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
3119
3120 }
3121 /*
3122 void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension )
3123 {
3124 #ifndef LINUX_XF86
3125 UCHAR data ;
3126 #endif
3127 VB_DEVICE_INFO VBINF;
3128 PVB_DEVICE_INFO pVBInfo = &VBINF;
3129 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
3130 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
3131 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
3132 pVBInfo->ISXPDOS = 0 ;
3133
3134 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
3135 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3136 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
3137 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
3138 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
3139 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
3140 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
3141 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
3142 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
3143 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
3144 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
3145 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
3146 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
3147 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
3148 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
3149 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
3150 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
3151
3152 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
3153
3154 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
3155
3156 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
3157 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
3158 else
3159 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
3160
3161 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
3162 }
3163 */
3164 /* -------------------------------------------------------- */
3165 /* Function : XGINew_ChkSenseStatus */
3166 /* Input : */
3167 /* Output : */
3168 /* Description : */
3169 /* -------------------------------------------------------- */
3170 void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo)
3171 {
3172 USHORT tempbx=0 , temp , tempcx , CR3CData;
3173
3174 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
3175
3176 if ( temp & Monitor1Sense )
3177 tempbx |= ActiveCRT1 ;
3178 if ( temp & LCDSense )
3179 tempbx |= ActiveLCD ;
3180 if ( temp & Monitor2Sense )
3181 tempbx |= ActiveCRT2 ;
3182 if ( temp & TVSense )
3183 {
3184 tempbx |= ActiveTV ;
3185 if ( temp & AVIDEOSense )
3186 tempbx |= ( ActiveAVideo << 8 );
3187 if ( temp & SVIDEOSense )
3188 tempbx |= ( ActiveSVideo << 8 );
3189 if ( temp & SCARTSense )
3190 tempbx |= ( ActiveSCART << 8 );
3191 if ( temp & HiTVSense )
3192 tempbx |= ( ActiveHiTV << 8 );
3193 if ( temp & YPbPrSense )
3194 tempbx |= ( ActiveYPbPr << 8 );
3195 }
3196
3197 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3198 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3199
3200 if ( tempbx & tempcx )
3201 {
3202 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3203 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3204 {
3205 tempcx = 0x1FF0 ;
3206 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3207 {
3208 tempbx = 0x1FF0 ;
3209 }
3210 }
3211 }
3212 else
3213 {
3214 tempcx = 0x1FF0 ;
3215 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3216 {
3217 tempbx = 0x1FF0 ;
3218 }
3219 }
3220
3221 tempbx &= tempcx ;
3222 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3223 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3224 }
3225 /* -------------------------------------------------------- */
3226 /* Function : XGINew_SetModeScratch */
3227 /* Input : */
3228 /* Output : */
3229 /* Description : */
3230 /* -------------------------------------------------------- */
3231 void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo )
3232 {
3233 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3234
3235 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3236 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3237 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3238
3239 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3240 {
3241 if ( temp & ActiveCRT2 )
3242 tempcl = SetCRT2ToRAMDAC ;
3243 }
3244
3245 if ( temp & ActiveLCD )
3246 {
3247 tempcl |= SetCRT2ToLCD ;
3248 if ( temp & DriverMode )
3249 {
3250 if ( temp & ActiveTV )
3251 {
3252 tempch = SetToLCDA | EnableDualEdge ;
3253 temp ^= SetCRT2ToLCD ;
3254
3255 if ( ( temp >> 8 ) & ActiveAVideo )
3256 tempcl |= SetCRT2ToAVIDEO ;
3257 if ( ( temp >> 8 ) & ActiveSVideo )
3258 tempcl |= SetCRT2ToSVIDEO ;
3259 if ( ( temp >> 8 ) & ActiveSCART )
3260 tempcl |= SetCRT2ToSCART ;
3261
3262 if ( pVBInfo->IF_DEF_HiVision == 1 )
3263 {
3264 if ( ( temp >> 8 ) & ActiveHiTV )
3265 tempcl |= SetCRT2ToHiVisionTV ;
3266 }
3267
3268 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3269 {
3270 if ( ( temp >> 8 ) & ActiveYPbPr )
3271 tempch |= SetYPbPr ;
3272 }
3273 }
3274 }
3275 }
3276 else
3277 {
3278 if ( ( temp >> 8 ) & ActiveAVideo )
3279 tempcl |= SetCRT2ToAVIDEO ;
3280 if ( ( temp >> 8 ) & ActiveSVideo )
3281 tempcl |= SetCRT2ToSVIDEO ;
3282 if ( ( temp >> 8 ) & ActiveSCART )
3283 tempcl |= SetCRT2ToSCART ;
3284
3285 if ( pVBInfo->IF_DEF_HiVision == 1 )
3286 {
3287 if ( ( temp >> 8 ) & ActiveHiTV )
3288 tempcl |= SetCRT2ToHiVisionTV ;
3289 }
3290
3291 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3292 {
3293 if ( ( temp >> 8 ) & ActiveYPbPr )
3294 tempch |= SetYPbPr ;
3295 }
3296 }
3297
3298
3299 tempcl |= SetSimuScanMode ;
3300 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3301 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3302 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3303 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3304 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3305
3306 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3307 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3308 if ( !( temp & ActiveCRT1 ) )
3309 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3310 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3311 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3312 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3313 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3314
3315 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3316 CR38Data &= ~SetYPbPr ;
3317 CR38Data |= tempch ;
3318 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3319
3320 }
3321
3322 /* -------------------------------------------------------- */
3323 /* Function : XGINew_GetXG21Sense */
3324 /* Input : */
3325 /* Output : */
3326 /* Description : */
3327 /* -------------------------------------------------------- */
3328 void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3329 {
3330 UCHAR Temp;
3331 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ;
3332
3333 pVBInfo->IF_DEF_LVDS = 0 ;
3334
3335 #ifdef WIN2000
3336 pVBInfo->IF_DEF_CH7007 = 0 ;
3337 if ( ( pVideoMemory[ 0x65 ] & 0x02 ) ) /* For XG21 CH7007 */
3338 {
3339 /* VideoDebugPrint((0, "ReadVBIOSTablData: pVideoMemory[ 0x65 ] =%x\n",pVideoMemory[ 0x65 ])); */
3340 pVBInfo->IF_DEF_CH7007 = 1 ; /* [Billy] 07/05/03 */
3341 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x60 ) ; /* CH7007 on chip */
3342 }
3343 else
3344 #endif
3345 #if 1
3346 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3347 {
3348 pVBInfo->IF_DEF_LVDS = 1 ;
3349 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3350 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3351 }
3352 else
3353 {
3354 #endif
3355 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3356 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3357 if ( Temp == 0xC0 )
3358 { /* DVI & DVO GPIOA/B pull high */
3359 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3360 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3361 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3362 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3363 if ( !Temp )
3364 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3365 else
3366 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3367 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3368 }
3369 #if 1
3370 }
3371 #endif
3372 }
3373
3374 /* -------------------------------------------------------- */
3375 /* Function : XGINew_GetXG27Sense */
3376 /* Input : */
3377 /* Output : */
3378 /* Description : */
3379 /* -------------------------------------------------------- */
3380 void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo)
3381 {
3382 UCHAR Temp,bCR4A;
3383
3384 pVBInfo->IF_DEF_LVDS = 0 ;
3385 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3386 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3387 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3388 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3389
3390 if ( Temp <= 0x02 )
3391 {
3392 pVBInfo->IF_DEF_LVDS = 1 ;
3393 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3394 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3395 }
3396 else
3397 {
3398 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3399 }
3400 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3401
3402 }
3403
3404 UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo)
3405 {
3406 UCHAR CR38,CR4A,temp;
3407
3408 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3409 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3410 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3411 temp =0;
3412 if ( ( CR38 & 0xE0 ) > 0x80 )
3413 {
3414 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3415 temp &= 0x08;
3416 temp >>= 3;
3417 }
3418
3419 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3420
3421 return temp;
3422 }
3423
3424 UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo)
3425 {
3426 UCHAR CR4A,temp;
3427
3428 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3429 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3430 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3431 if ( temp <= 2 )
3432 {
3433 temp &= 0x03;
3434 }
3435 else
3436 {
3437 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3438 }
3439 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3440
3441 return temp;
3442 }
3443
kernel source for telekom puls (alcatel/mediatek)