5 * ====================================================
7 * ====================================================
11 * ====================================================
12 * For MAXIM2825/6/7 Ver. 331 or more
19 * channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
20 * channe1 02 ; 0x03 0x32141 ; 0x04 0x08444;
21 * channe1 03 ; 0x03 0x32143 ; 0x04 0x0aeee;
22 * channe1 04 ; 0x03 0x32142 ; 0x04 0x0b333;
23 * channe1 05 ; 0x03 0x31141 ; 0x04 0x08444;
24 * channe1 06 ; 0x03 0x31143 ; 0x04 0x0aeee;
25 * channe1 07 ; 0x03 0x31142 ; 0x04 0x0b333;
26 * channe1 08 ; 0x03 0x33141 ; 0x04 0x08444;
27 * channe1 09 ; 0x03 0x33143 ; 0x04 0x0aeee;
28 * channe1 10 ; 0x03 0x33142 ; 0x04 0x0b333;
29 * channe1 11 ; 0x03 0x30941 ; 0x04 0x08444;
30 * channe1 12 ; 0x03 0x30943 ; 0x04 0x0aeee;
31 * channe1 13 ; 0x03 0x30942 ; 0x04 0x0b333;
36 * 0x08 0x05100; 100 Hz DC
37 * 0x08 0x05900; 30 KHz DC
39 * 0x0a 0x17e00, 0x17ea0
41 * 0x0c 0x0c900 -- 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
44 /* MAX2825 (pure b/g) */
45 u32 max2825_rf_data
[] = {
58 (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
61 u32 max2825_channel_data_24
[][3] = {
62 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */
63 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */
64 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */
65 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 04 */
66 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 05 */
67 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 06 */
68 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 07 */
69 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 08 */
70 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 09 */
71 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 10 */
72 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 11 */
73 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 12 */
74 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 13 */
75 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
78 u32 max2825_power_data_24
[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
80 /* ========================================== */
82 u32 max2827_rf_data
[] = {
83 (0x00 << 18) | 0x000a2,
84 (0x01 << 18) | 0x21cc0,
85 (0x02 << 18) | 0x13806,
86 (0x03 << 18) | 0x30142,
87 (0x04 << 18) | 0x0b333,
88 (0x05 << 18) | 0x289A6,
89 (0x06 << 18) | 0x18008,
90 (0x07 << 18) | 0x38000,
91 (0x08 << 18) | 0x05100,
92 (0x09 << 18) | 0x24f08,
93 (0x0A << 18) | 0x14000,
94 (0x0B << 18) | 0x37d80,
95 (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
98 u32 max2827_channel_data_24
[][3] = {
99 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
100 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
101 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
102 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
103 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
104 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
105 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
106 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
107 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
108 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
109 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
110 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
111 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
112 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
115 u32 max2827_channel_data_50
[][3] = {
116 {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */
117 {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */
118 {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */
119 {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2A9A6}, /* channel 48 */
120 {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x2A9A6}, /* channel 52 */
121 {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 56 */
122 {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 60 */
123 {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */
126 u32 max2827_power_data_24
[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100};
127 u32 max2827_power_data_50
[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300};
129 /* ======================================================= */
130 /* MAX2828 (a/b/g) */
131 u32 max2828_rf_data
[] = {
132 (0x00 << 18) | 0x000a2,
133 (0x01 << 18) | 0x21cc0,
134 (0x02 << 18) | 0x13806,
135 (0x03 << 18) | 0x30142,
136 (0x04 << 18) | 0x0b333,
137 (0x05 << 18) | 0x289A6,
138 (0x06 << 18) | 0x18008,
139 (0x07 << 18) | 0x38000,
140 (0x08 << 18) | 0x05100,
141 (0x09 << 18) | 0x24f08,
142 (0x0A << 18) | 0x14000,
143 (0x0B << 18) | 0x37d80,
144 (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
147 u32 max2828_channel_data_24
[][3] = {
148 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
149 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
150 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
151 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
152 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
153 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
154 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
155 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
156 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
157 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
158 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
159 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
160 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
161 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
164 u32 max2828_channel_data_50
[][3] = {
165 {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */
166 {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */
167 {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */
168 {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}, /* channel 48 */
169 {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x289A6}, /* channel 52 */
170 {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 56 */
171 {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 60 */
172 {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */
175 u32 max2828_power_data_24
[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
176 u32 max2828_power_data_50
[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
178 /* ========================================================== */
179 /* MAX2829 (a/b/g) */
180 u32 max2829_rf_data
[] = {
181 (0x00 << 18) | 0x000a2,
182 (0x01 << 18) | 0x23520,
183 (0x02 << 18) | 0x13802,
184 (0x03 << 18) | 0x30142,
185 (0x04 << 18) | 0x0b333,
186 (0x05 << 18) | 0x28906,
187 (0x06 << 18) | 0x18008,
188 (0x07 << 18) | 0x3B500,
189 (0x08 << 18) | 0x05100,
190 (0x09 << 18) | 0x24f08,
191 (0x0A << 18) | 0x14000,
192 (0x0B << 18) | 0x37d80,
193 (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */
196 u32 max2829_channel_data_24
[][3] = {
197 {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */
198 {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */
199 {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */
200 {(3 << 18) | 0x32142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 04 (2427MHz) */
201 {(3 << 18) | 0x31141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 05 (2432MHz) */
202 {(3 << 18) | 0x31143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 06 (2437MHz) */
203 {(3 << 18) | 0x31142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 07 (2442MHz) */
204 {(3 << 18) | 0x33141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 08 (2447MHz) */
205 {(3 << 18) | 0x33143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 09 (2452MHz) */
206 {(3 << 18) | 0x33142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 10 (2457MHz) */
207 {(3 << 18) | 0x30941, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 11 (2462MHz) */
208 {(3 << 18) | 0x30943, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 12 (2467MHz) */
209 {(3 << 18) | 0x30942, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 13 (2472MHz) */
210 {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */
213 u32 max2829_channel_data_50
[][4] = {
214 {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */
215 {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */
216 {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */
217 {48, (3 << 18) | 0x322c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 48 (5.240GHz) */
218 {52, (3 << 18) | 0x312c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 52 (5.260GHz) */
219 {56, (3 << 18) | 0x332c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 56 (5.280GHz) */
220 {60, (3 << 18) | 0x30ac0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 60 (5.300GHz) */
221 {64, (3 << 18) | 0x30ac2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 64 (5.320GHz) */
223 {100, (3 << 18) | 0x30ec0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 100 (5.500GHz) */
224 {104, (3 << 18) | 0x30ec2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 104 (5.520GHz) */
225 {108, (3 << 18) | 0x32ec1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 108 (5.540GHz) */
226 {112, (3 << 18) | 0x31ec1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 112 (5.560GHz) */
227 {116, (3 << 18) | 0x33ec3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 116 (5.580GHz) */
228 {120, (3 << 18) | 0x301c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 120 (5.600GHz) */
229 {124, (3 << 18) | 0x301c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 124 (5.620GHz) */
230 {128, (3 << 18) | 0x321c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 128 (5.640GHz) */
231 {132, (3 << 18) | 0x311c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 132 (5.660GHz) */
232 {136, (3 << 18) | 0x331c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 136 (5.680GHz) */
233 {140, (3 << 18) | 0x309c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 140 (5.700GHz) */
235 {149, (3 << 18) | 0x329c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 149 (5.745GHz) */
236 {153, (3 << 18) | 0x319c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 153 (5.765GHz) */
237 {157, (3 << 18) | 0x339c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 157 (5.785GHz) */
238 {161, (3 << 18) | 0x305c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 161 (5.805GHz) */
241 { 184, (3 << 18) | 0x308c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 184 (4.920GHz) */
242 { 188, (3 << 18) | 0x328c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 188 (4.940GHz) */
243 { 192, (3 << 18) | 0x318c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 192 (4.960GHz) */
244 { 196, (3 << 18) | 0x338c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 196 (4.980GHz) */
245 { 8, (3 << 18) | 0x324c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 8 (5.040GHz) */
246 { 12, (3 << 18) | 0x314c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 12 (5.060GHz) */
247 { 16, (3 << 18) | 0x334c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 16 (5.080GHz) */
248 { 34, (3 << 18) | 0x31cc2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 34 (5.170GHz) */
249 { 38, (3 << 18) | 0x33cc1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 38 (5.190GHz) */
250 { 42, (3 << 18) | 0x302c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 42 (5.210GHz) */
251 { 46, (3 << 18) | 0x322c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 46 (5.230GHz) */
255 * ====================================================================
256 * For MAXIM2825/6/7 Ver. 317 or less
263 * channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
264 * channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
265 * channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
266 * channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
267 * channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
268 * channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
269 * channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
270 * channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
271 * channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
272 * channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
273 * channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
274 * channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
275 * channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
278 * channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
279 * channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
280 * channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
281 * channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
282 * channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
283 * channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
284 * channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
285 * channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
287 * 2.4GHz band ; 0x05 0x28986;
288 * 5.0GHz band ; 0x05 0x2a986
296 * ====================================================================
298 u32 maxim_317_rf_data
[] = {
299 (0x00 << 18) | 0x000a2,
300 (0x01 << 18) | 0x214c0,
301 (0x02 << 18) | 0x13802,
302 (0x03 << 18) | 0x30143,
303 (0x04 << 18) | 0x0accc,
304 (0x05 << 18) | 0x28986,
305 (0x06 << 18) | 0x18008,
306 (0x07 << 18) | 0x38400,
307 (0x08 << 18) | 0x05108,
308 (0x09 << 18) | 0x27ff8,
309 (0x0A << 18) | 0x14000,
310 (0x0B << 18) | 0x37f99,
311 (0x0C << 18) | 0x0c000
314 u32 maxim_317_channel_data_24
[][3] = {
315 {(0x03 << 18) | 0x30143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 01 */
316 {(0x03 << 18) | 0x32140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 02 */
317 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 03 */
318 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 04 */
319 {(0x03 << 18) | 0x31140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 05 */
320 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 06 */
321 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 07 */
322 {(0x03 << 18) | 0x33140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 08 */
323 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 09 */
324 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 10 */
325 {(0x03 << 18) | 0x30940, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 11 */
326 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 12 */
327 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986} /* channe1 13 */
330 u32 maxim_317_channel_data_50
[][3] = {
331 {(0x03 << 18) | 0x33cc0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a986}, /* channel 36 */
332 {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a986}, /* channel 40 */
333 {(0x03 << 18) | 0x302c3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a986}, /* channel 44 */
334 {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09666, (0x05 << 18) | 0x2a986}, /* channel 48 */
335 {(0x03 << 18) | 0x312c2, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2a986}, /* channel 52 */
336 {(0x03 << 18) | 0x332c0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a99e}, /* channel 56 */
337 {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a99e}, /* channel 60 */
338 {(0x03 << 18) | 0x30ac3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a99e} /* channel 64 */
341 u32 maxim_317_power_data_24
[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
342 u32 maxim_317_power_data_50
[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
345 * ===================================================================
346 * AL2230 MP (Mass Production Version)
347 * RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
348 * 20-bit length and LSB first
350 * Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
351 * Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
352 * Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
353 * Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
354 * Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
355 * Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
356 * Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
357 * Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
358 * Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
359 * Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
360 * Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
361 * Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
362 * Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
363 * Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
365 * 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
366 * 0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
381 * RF Calibration for Airoha AL2230
383 * 0x0f 0xf00a0 ; Initial Setting
384 * 0x0f 0xf00b0 ; Activate TX DCC
385 * 0x0f 0xf02a0 ; Activate Phase Calibration
386 * 0x0f 0xf00e0 ; Activate Filter RC Calibration
387 * 0x0f 0xf00a0 ; Restore Initial Setting
388 * ==================================================================
390 u32 al2230_rf_data
[] = {
391 (0x00 << 20) | 0x09EFC,
392 (0x01 << 20) | 0x8CCCC,
393 (0x02 << 20) | 0x40058,
394 (0x03 << 20) | 0xCFFF0,
395 (0x04 << 20) | 0x24100,
396 (0x05 << 20) | 0xA3B2F,
397 (0x06 << 20) | 0x6DA01,
398 (0x07 << 20) | 0xE3628,
399 (0x08 << 20) | 0x11600,
400 (0x09 << 20) | 0x9DC02,
401 (0x0A << 20) | 0x5ddb0,
402 (0x0B << 20) | 0xD9900,
403 (0x0C << 20) | 0x3FFBD,
404 (0x0D << 20) | 0xB0000,
405 (0x0F << 20) | 0xF01A0
408 u32 al2230s_rf_data
[] = {
409 (0x00 << 20) | 0x09EFC,
410 (0x01 << 20) | 0x8CCCC,
411 (0x02 << 20) | 0x40058,
412 (0x03 << 20) | 0xCFFF0,
413 (0x04 << 20) | 0x24100,
414 (0x05 << 20) | 0xA3B2F,
415 (0x06 << 20) | 0x6DA01,
416 (0x07 << 20) | 0xE3628,
417 (0x08 << 20) | 0x11600,
418 (0x09 << 20) | 0x9DC02,
419 (0x0A << 20) | 0x5DDB0,
420 (0x0B << 20) | 0xD9900,
421 (0x0C << 20) | 0x3FFBD,
422 (0x0D << 20) | 0xB0000,
423 (0x0F << 20) | 0xF01A0
426 u32 al2230_channel_data_24
[][2] = {
427 {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */
428 {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */
429 {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */
430 {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 04 */
431 {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 05 */
432 {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 06 */
433 {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 07 */
434 {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 08 */
435 {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCC}, /* channe1 09 */
436 {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCD}, /* channe1 10 */
437 {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCC}, /* channe1 11 */
438 {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCD}, /* channe1 12 */
439 {(0x00 << 20) | 0x03EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 13 */
440 {(0x00 << 20) | 0x03E7C, (0x01 << 20) | 0x86666} /* channe1 14 */
443 /* Current setting. u32 airoha_power_data_24[] = {(0x09 << 20) | 0x90202, (0x09 << 20) | 0x96602, (0x09 << 20) | 0x97602}; */
444 #define AIROHA_TXVGA_LOW_INDEX 31 /* Index for 0x90202 */
445 #define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */
446 #define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */
448 u32 al2230_txvga_data
[][2] = {
493 * ==========================================
494 * For Airoha AL7230, 2.4Ghz band
498 /* channel independent registers: */
499 u32 al7230_rf_data_24
[] = {
500 (0x00 << 24) | 0x003790,
501 (0x01 << 24) | 0x133331,
502 (0x02 << 24) | 0x841FF2,
503 (0x03 << 24) | 0x3FDFA3,
504 (0x04 << 24) | 0x7FD784,
505 (0x05 << 24) | 0x802B55,
506 (0x06 << 24) | 0x56AF36,
507 (0x07 << 24) | 0xCE0207,
508 (0x08 << 24) | 0x6EBC08,
509 (0x09 << 24) | 0x221BB9,
510 (0x0A << 24) | 0xE0000A,
511 (0x0B << 24) | 0x08071B,
512 (0x0C << 24) | 0x000A3C,
513 (0x0D << 24) | 0xFFFFFD,
514 (0x0E << 24) | 0x00000E,
515 (0x0F << 24) | 0x1ABA8F
518 u32 al7230_channel_data_24
[][2] = {
519 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */
520 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */
521 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */
522 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x0B3331}, /* channe1 04 */
523 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x133331}, /* channe1 05 */
524 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x1B3331}, /* channe1 06 */
525 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x033331}, /* channe1 07 */
526 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x0B3331}, /* channe1 08 */
527 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x133331}, /* channe1 09 */
528 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x1B3331}, /* channe1 10 */
529 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x033331}, /* channe1 11 */
530 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x0B3331}, /* channe1 12 */
531 {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x133331}, /* channe1 13 */
532 {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x066661} /* channel 14 */
535 /* channel independent registers: */
536 u32 al7230_rf_data_50
[] = {
537 (0x00 << 24) | 0x0FF520,
538 (0x01 << 24) | 0x000001,
539 (0x02 << 24) | 0x451FE2,
540 (0x03 << 24) | 0x5FDFA3,
541 (0x04 << 24) | 0x6FD784,
542 (0x05 << 24) | 0x853F55,
543 (0x06 << 24) | 0x56AF36,
544 (0x07 << 24) | 0xCE0207,
545 (0x08 << 24) | 0x6EBC08,
546 (0x09 << 24) | 0x221BB9,
547 (0x0A << 24) | 0xE0600A,
548 (0x0B << 24) | 0x08044B,
549 (0x0C << 24) | 0x00143C,
550 (0x0D << 24) | 0xFFFFFD,
551 (0x0E << 24) | 0x00000E,
552 (0x0F << 24) | 0x12BACF /* 5Ghz default state */
555 u32 al7230_channel_data_5
[][4] = {
556 /* channel dependent registers: 0x00, 0x01 and 0x04 */
557 /* 11J =========== */
558 {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */
559 {188, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 188 */
560 {192, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 192 */
561 {196, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 196 */
562 {8, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 008 */
563 {12, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 012 */
564 {16, (0x00 << 24) | 0x0FF550, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 016 */
565 {34, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 034 */
566 {38, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x100001, (0x04 << 24) | 0x77F784}, /* channel 038 */
567 {42, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x1AAAA1, (0x04 << 24) | 0x77F784}, /* channel 042 */
568 {46, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 046 */
569 /* 11 A/H ========= */
570 {36, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 036 */
571 {40, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 040 */
572 {44, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 044 */
573 {48, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 048 */
574 {52, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 052 */
575 {56, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 056 */
576 {60, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 060 */
577 {64, (0x00 << 24) | 0x0FF590, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 064 */
578 {100, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 100 */
579 {104, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 104 */
580 {108, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 108 */
581 {112, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 112 */
582 {116, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 116 */
583 {120, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 120 */
584 {124, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 124 */
585 {128, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 128 */
586 {132, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 132 */
587 {136, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 136 */
588 {140, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 140 */
589 {149, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 149 */
590 {153, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784}, /* channel 153 */
591 {157, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x0D5551, (0x04 << 24) | 0x77F784}, /* channel 157 */
592 {161, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 161 */
593 {165, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784} /* channel 165 */
597 * RF Calibration <=== Register 0x0F
598 * 0x0F 0x1ABA8F; start from 2.4Ghz default state
599 * 0x0F 0x9ABA8F; TXDC compensation
600 * 0x0F 0x3ABA8F; RXFIL adjustment
601 * 0x0F 0x1ABA8F; restore 2.4Ghz default state
604 /* TXVGA Mapping Table <=== Register 0x0B */
605 u32 al7230_txvga_data
[][2] = {
606 {0x08040B, 0}, /* TXVGA = 0; */
607 {0x08041B, 1}, /* TXVGA = 1; */
608 {0x08042B, 2}, /* TXVGA = 2; */
609 {0x08043B, 3}, /* TXVGA = 3; */
610 {0x08044B, 4}, /* TXVGA = 4; */
611 {0x08045B, 5}, /* TXVGA = 5; */
612 {0x08046B, 6}, /* TXVGA = 6; */
613 {0x08047B, 7}, /* TXVGA = 7; */
614 {0x08048B, 8}, /* TXVGA = 8; */
615 {0x08049B, 9}, /* TXVGA = 9; */
616 {0x0804AB, 10}, /* TXVGA = 10; */
617 {0x0804BB, 11}, /* TXVGA = 11; */
618 {0x0804CB, 12}, /* TXVGA = 12; */
619 {0x0804DB, 13}, /* TXVGA = 13; */
620 {0x0804EB, 14}, /* TXVGA = 14; */
621 {0x0804FB, 15}, /* TXVGA = 15; */
622 {0x08050B, 16}, /* TXVGA = 16; */
623 {0x08051B, 17}, /* TXVGA = 17; */
624 {0x08052B, 18}, /* TXVGA = 18; */
625 {0x08053B, 19}, /* TXVGA = 19; */
626 {0x08054B, 20}, /* TXVGA = 20; */
627 {0x08055B, 21}, /* TXVGA = 21; */
628 {0x08056B, 22}, /* TXVGA = 22; */
629 {0x08057B, 23}, /* TXVGA = 23; */
630 {0x08058B, 24}, /* TXVGA = 24; */
631 {0x08059B, 25}, /* TXVGA = 25; */
632 {0x0805AB, 26}, /* TXVGA = 26; */
633 {0x0805BB, 27}, /* TXVGA = 27; */
634 {0x0805CB, 28}, /* TXVGA = 28; */
635 {0x0805DB, 29}, /* TXVGA = 29; */
636 {0x0805EB, 30}, /* TXVGA = 30; */
637 {0x0805FB, 31}, /* TXVGA = 31; */
638 {0x08060B, 32}, /* TXVGA = 32; */
639 {0x08061B, 33}, /* TXVGA = 33; */
640 {0x08062B, 34}, /* TXVGA = 34; */
641 {0x08063B, 35}, /* TXVGA = 35; */
642 {0x08064B, 36}, /* TXVGA = 36; */
643 {0x08065B, 37}, /* TXVGA = 37; */
644 {0x08066B, 38}, /* TXVGA = 38; */
645 {0x08067B, 39}, /* TXVGA = 39; */
646 {0x08068B, 40}, /* TXVGA = 40; */
647 {0x08069B, 41}, /* TXVGA = 41; */
648 {0x0806AB, 42}, /* TXVGA = 42; */
649 {0x0806BB, 43}, /* TXVGA = 43; */
650 {0x0806CB, 44}, /* TXVGA = 44; */
651 {0x0806DB, 45}, /* TXVGA = 45; */
652 {0x0806EB, 46}, /* TXVGA = 46; */
653 {0x0806FB, 47}, /* TXVGA = 47; */
654 {0x08070B, 48}, /* TXVGA = 48; */
655 {0x08071B, 49}, /* TXVGA = 49; */
656 {0x08072B, 50}, /* TXVGA = 50; */
657 {0x08073B, 51}, /* TXVGA = 51; */
658 {0x08074B, 52}, /* TXVGA = 52; */
659 {0x08075B, 53}, /* TXVGA = 53; */
660 {0x08076B, 54}, /* TXVGA = 54; */
661 {0x08077B, 55}, /* TXVGA = 55; */
662 {0x08078B, 56}, /* TXVGA = 56; */
663 {0x08079B, 57}, /* TXVGA = 57; */
664 {0x0807AB, 58}, /* TXVGA = 58; */
665 {0x0807BB, 59}, /* TXVGA = 59; */
666 {0x0807CB, 60}, /* TXVGA = 60; */
667 {0x0807DB, 61}, /* TXVGA = 61; */
668 {0x0807EB, 62}, /* TXVGA = 62; */
669 {0x0807FB, 63}, /* TXVGA = 63; */
671 /* ============================================= */
674 * W89RF242 RFIC SPI programming initial data
675 * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
677 u32 w89rf242_rf_data
[] = {
678 (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */
679 (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */
680 (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */
681 (0x03 << 24) | 0x026286, /* 0098A; FCHN (0x03) -- default CH7, 2442MHz */
682 (0x04 << 24) | 0x000208, /* 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C */
683 (0x05 << 24) | 0x24C60A, /* 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D */
684 (0x06 << 24) | 0x3432CC, /* 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input */
685 (0x07 << 24) | 0x0C68CE, /* 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 */
686 (0x08 << 24) | 0x100010, /* 04000; TCAL (0x08) -- for LO */
687 (0x09 << 24) | 0x004012, /* 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) */
688 (0x0A << 24) | 0x704014, /* 1C100; RCALB (0x0A) */
689 (0x0B << 24) | 0x18BDD6, /* 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B */
690 (0x0C << 24) | 0x575558, /* 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner */
691 (0x0D << 24) | 0x55545A, /* 15555 ; IBSB (0x0D) */
692 (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */
693 (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */
694 (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */
695 (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Tempearure sensor */
698 u32 w89rf242_channel_data_24
[][2] = {
699 {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */
700 {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */
701 {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */
702 {(0x03 << 24) | 0x025EC6, (0x04 << 24) | 0x080408}, /* channe1 04 */
703 {(0x03 << 24) | 0x026006, (0x04 << 24) | 0x080408}, /* channe1 05 */
704 {(0x03 << 24) | 0x026146, (0x04 << 24) | 0x080408}, /* channe1 06 */
705 {(0x03 << 24) | 0x026286, (0x04 << 24) | 0x080408}, /* channe1 07 */
706 {(0x03 << 24) | 0x0263C6, (0x04 << 24) | 0x080408}, /* channe1 08 */
707 {(0x03 << 24) | 0x026506, (0x04 << 24) | 0x080408}, /* channe1 09 */
708 {(0x03 << 24) | 0x026646, (0x04 << 24) | 0x080408}, /* channe1 10 */
709 {(0x03 << 24) | 0x026786, (0x04 << 24) | 0x080408}, /* channe1 11 */
710 {(0x03 << 24) | 0x0268C6, (0x04 << 24) | 0x080408}, /* channe1 12 */
711 {(0x03 << 24) | 0x026A06, (0x04 << 24) | 0x080408}, /* channe1 13 */
712 {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */
715 u32 w89rf242_power_data_24
[] = {(0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A};
717 u32 w89rf242_txvga_old_mapping
[][2] = {
718 {0, 0} , /* New <-> Old */
740 u32 w89rf242_txvga_data
[][5] = {
742 {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */
743 {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131},
744 {(0x05 << 24) | 0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131}, /* (default) +14dBm (ANT) */
745 {(0x05 << 24) | 0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131},
748 {(0x05 << 24) | 0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838},
749 {(0x05 << 24) | 0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B},
752 { (0x05 << 24) | 0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333},
753 { (0x05 << 24) | 0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737},
756 {(0x05 << 24) | 0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030},
757 {(0x05 << 24) | 0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434},
760 {(0x05 << 24) | 0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030},
761 {(0x05 << 24) | 0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232},
764 {(0x05 << 24) | 0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131},
765 {(0x05 << 24) | 0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434},
768 {(0x05 << 24) | 0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131},
769 {(0x05 << 24) | 0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434},
772 {(0x05 << 24) | 0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131},
773 {(0x05 << 24) | 0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535},
776 {(0x05 << 24) | 0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F},
777 {(0x05 << 24) | 0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131},
780 {(0x05 << 24) | 0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E},
781 {(0x05 << 24) | 0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030},
784 {(0x05 << 24) | 0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D},
785 {(0x05 << 24) | 0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030},
788 {(0x05 << 24) | 0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E},
789 {(0x05 << 24) | 0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131},
792 {(0x05 << 24) | 0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030},
793 {(0x05 << 24) | 0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434},
796 {(0x05 << 24) | 0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131},
797 {(0x05 << 24) | 0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636},
800 {(0x05 << 24) | 0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737},
801 {(0x05 << 24) | 0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B},
804 {(0x05 << 24) | 0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B},
805 {(0x05 << 24) | 0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141},
808 {(0x05 << 24) | 0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242}
811 /* ================================================================================================== */
816 * =============================================================================================================
817 * Uxx_ReadEthernetAddress --
819 * Routine Description:
820 * Reads in the Ethernet address from the IC.
823 * pHwData - The pHwData structure
827 * The address is stored in EthernetIDAddr.
828 * =============================================================================================================
830 void Uxx_ReadEthernetAddress(struct hw_data
*pHwData
)
835 * Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
836 * Only unplug and plug again can make hardware read EEPROM again.
838 Wb35Reg_WriteSync(pHwData
, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */
839 Wb35Reg_ReadSync(pHwData
, 0x03b4, <mp
);
840 *(u16
*)pHwData
->PermanentMacAddress
= cpu_to_le16((u16
) ltmp
);
841 Wb35Reg_WriteSync(pHwData
, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */
842 Wb35Reg_ReadSync(pHwData
, 0x03b4, <mp
);
843 *(u16
*)(pHwData
->PermanentMacAddress
+ 2) = cpu_to_le16((u16
) ltmp
);
844 Wb35Reg_WriteSync(pHwData
, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */
845 Wb35Reg_ReadSync(pHwData
, 0x03b4, <mp
);
846 *(u16
*)(pHwData
->PermanentMacAddress
+ 4) = cpu_to_le16((u16
) ltmp
);
847 *(u16
*)(pHwData
->PermanentMacAddress
+ 6) = 0;
848 Wb35Reg_WriteSync(pHwData
, 0x03e8, cpu_to_le32(*(u32
*)pHwData
->PermanentMacAddress
));
849 Wb35Reg_WriteSync(pHwData
, 0x03ec, cpu_to_le32(*(u32
*)(pHwData
->PermanentMacAddress
+ 4)));
854 * ===============================================================================================================
855 * CardGetMulticastBit --
857 * For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
858 * Calls CardComputeCrc() to determine the CRC value.
860 * Address - the address
861 * Byte - the byte that it hashes to
862 * Value - will have a 1 in the relevant bit
865 * ==============================================================================================================
867 void CardGetMulticastBit(u8 Address
[ETH_ALEN
], u8
*Byte
, u8
*Value
)
872 /* First compute the CRC. */
873 Crc
= CardComputeCrc(Address
, ETH_ALEN
);
875 /* The computed CRC is bit0~31 from left to right */
876 /* At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 */
877 BitNumber
= (u32
) ((Crc
>> 26) & 0x3f);
879 *Byte
= (u8
) (BitNumber
>> 3); /* 900514 original (BitNumber / 8) */
880 *Value
= (u8
) ((u8
) 1 << (BitNumber
% 8));
883 void Uxx_power_on_procedure(struct hw_data
*pHwData
)
887 if (pHwData
->phy_type
<= RF_MAXIM_V1
)
888 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xffffff38);
890 Wb35Reg_WriteSync(pHwData
, 0x03f4, 0xFF5807FF);
891 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0x80); /* regulator on only */
893 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */
896 if ((pHwData
->phy_type
== RF_WB_242
) ||
897 (RF_WB_242_1
== pHwData
->phy_type
))
900 Wb35Reg_WriteSync(pHwData
, 0x03d0, ltmp
);
901 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
904 Wb35Reg_ReadSync(pHwData
, 0x03d0, <mp
);
905 loop
= 500; /* Wait for 5 second */
906 while (!(ltmp
& 0x20) && loop
--) {
908 if (!Wb35Reg_ReadSync(pHwData
, 0x03d0, <mp
))
912 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xe0); /* MLK_EN */
915 Wb35Reg_WriteSync(pHwData
, 0x03b0, 1); /* Reset hardware first */
918 /* Set burst write delay */
919 Wb35Reg_WriteSync(pHwData
, 0x03f8, 0x7ff);
922 void Set_ChanIndep_RfData_al7230_24(struct hw_data
*pHwData
, u32
*pltmp
, char number
)
926 for (i
= 0; i
< number
; i
++) {
927 pHwData
->phy_para
[i
] = al7230_rf_data_24
[i
];
928 pltmp
[i
] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24
[i
] & 0xffffff);
932 void Set_ChanIndep_RfData_al7230_50(struct hw_data
*pHwData
, u32
*pltmp
, char number
)
936 for (i
= 0; i
< number
; i
++) {
937 pHwData
->phy_para
[i
] = al7230_rf_data_50
[i
];
938 pltmp
[i
] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50
[i
] & 0xffffff);
944 * =============================================================================================================
945 * RFSynthesizer_initial --
946 * =============================================================================================================
948 void RFSynthesizer_initial(struct hw_data
*pHwData
)
953 u8 number
= 0x00; /* The number of register vale */
957 * bit[31] SPI Enable.
958 * 1=perform synthesizer program operation. This bit will
959 * cleared automatically after the operation is completed.
960 * bit[30] SPI R/W Control
962 * bit[29:24] SPI Data Format Length
963 * bit[17:4 ] RF Data bits.
964 * bit[3 :0 ] RF address.
966 switch (pHwData
->phy_type
) {
968 case RF_MAXIM_V1
: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
969 number
= ARRAY_SIZE(max2825_rf_data
);
970 for (i
= 0; i
< number
; i
++) {
971 pHwData
->phy_para
[i
] = max2825_rf_data
[i
]; /* Backup Rf parameter */
972 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data
[i
], 18);
976 number
= ARRAY_SIZE(max2827_rf_data
);
977 for (i
= 0; i
< number
; i
++) {
978 pHwData
->phy_para
[i
] = max2827_rf_data
[i
];
979 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data
[i
], 18);
983 number
= ARRAY_SIZE(max2828_rf_data
);
984 for (i
= 0; i
< number
; i
++) {
985 pHwData
->phy_para
[i
] = max2828_rf_data
[i
];
986 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data
[i
], 18);
990 number
= ARRAY_SIZE(max2829_rf_data
);
991 for (i
= 0; i
< number
; i
++) {
992 pHwData
->phy_para
[i
] = max2829_rf_data
[i
];
993 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data
[i
], 18);
997 number
= ARRAY_SIZE(al2230_rf_data
);
998 for (i
= 0; i
< number
; i
++) {
999 pHwData
->phy_para
[i
] = al2230_rf_data
[i
];
1000 pltmp
[i
] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data
[i
], 20);
1003 case RF_AIROHA_2230S
:
1004 number
= ARRAY_SIZE(al2230s_rf_data
);
1005 for (i
= 0; i
< number
; i
++) {
1006 pHwData
->phy_para
[i
] = al2230s_rf_data
[i
];
1007 pltmp
[i
] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data
[i
], 20);
1010 case RF_AIROHA_7230
:
1011 /* Start to fill RF parameters, PLL_ON should be pulled low. */
1012 Wb35Reg_WriteSync(pHwData
, 0x03dc, 0x00000000);
1013 #ifdef _PE_STATE_DUMP_
1014 printk("* PLL_ON low\n");
1016 number
= ARRAY_SIZE(al7230_rf_data_24
);
1017 Set_ChanIndep_RfData_al7230_24(pHwData
, pltmp
, number
);
1021 number
= ARRAY_SIZE(w89rf242_rf_data
);
1022 for (i
= 0; i
< number
; i
++) {
1023 ltmp
= w89rf242_rf_data
[i
];
1024 if (i
== 4) { /* Update the VCO trim from EEPROM */
1025 ltmp
&= ~0xff0; /* Mask bit4 ~bit11 */
1026 ltmp
|= pHwData
->VCO_trim
<< 4;
1029 pHwData
->phy_para
[i
] = ltmp
;
1030 pltmp
[i
] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(ltmp
, 24);
1035 pHwData
->phy_number
= number
;
1037 /* The 16 is the maximum capability of hardware. Here use 12 */
1039 for (i
= 0; i
< 12; i
++) /* For Al2230 */
1040 Wb35Reg_WriteSync(pHwData
, 0x0864, pltmp
[i
]);
1046 /* Write to register. number must less and equal than 16 */
1047 for (i
= 0; i
< number
; i
++)
1048 Wb35Reg_WriteSync(pHwData
, 0x864, pltmp
[i
]);
1050 /* Calibration only 1 time */
1051 if (pHwData
->CalOneTime
)
1053 pHwData
->CalOneTime
= 1;
1055 switch (pHwData
->phy_type
) {
1056 case RF_AIROHA_2230
:
1057 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x07 << 20) | 0xE168E, 20);
1058 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1060 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data
[7], 20);
1061 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1063 case RF_AIROHA_2230S
:
1064 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0x80); /* regulator on only */
1066 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
1068 Wb35Reg_WriteSync(pHwData
, 0x03d4, 0xe0); /* MLK_EN */
1069 Wb35Reg_WriteSync(pHwData
, 0x03b0, 1); /* Reset hardware first */
1071 /* ========================================================= */
1073 /* The follow code doesn't use the burst-write mode */
1074 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F<<20) | 0xF01A0, 20);
1075 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1077 ltmp
= pHwData
->reg
.BB5C
& 0xfffff000;
1078 Wb35Reg_WriteSync(pHwData
, 0x105c, ltmp
);
1079 pHwData
->reg
.BB50
|= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */
1080 Wb35Reg_WriteSync(pHwData
, 0x1050, pHwData
->reg
.BB50
);
1083 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01B0, 20);
1084 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1087 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01E0, 20);
1088 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1091 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
1092 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
) ;
1094 Wb35Reg_WriteSync(pHwData
, 0x105c, pHwData
->reg
.BB5C
);
1095 pHwData
->reg
.BB50
&= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1096 Wb35Reg_WriteSync(pHwData
, 0x1050, pHwData
->reg
.BB50
);
1098 case RF_AIROHA_7230
:
1099 /* RF parameters have filled completely, PLL_ON should be pulled high */
1100 Wb35Reg_WriteSync(pHwData
, 0x03dc, 0x00000080);
1101 #ifdef _PE_STATE_DUMP_
1102 printk("* PLL_ON high\n");
1106 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1107 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1109 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1110 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1112 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1113 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1117 Wb35Reg_WriteSync(pHwData
, 0x03dc, 0x00000000);
1118 #ifdef _PE_STATE_DUMP_
1119 printk("* PLL_ON low\n");
1122 number
= ARRAY_SIZE(al7230_rf_data_50
);
1123 Set_ChanIndep_RfData_al7230_50(pHwData
, pltmp
, number
);
1124 /* Write to register. number must less and equal than 16 */
1125 for (i
= 0; i
< number
; i
++)
1126 Wb35Reg_WriteSync(pHwData
, 0x0864, pltmp
[i
]);
1129 Wb35Reg_WriteSync(pHwData
, 0x03dc, 0x00000080);
1130 #ifdef _PE_STATE_DUMP_
1131 printk("* PLL_ON high\n");
1134 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1135 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1137 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1138 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1140 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1141 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1147 ltmp
= pHwData
->reg
.BB5C
& 0xfffff000;
1148 Wb35Reg_WriteSync(pHwData
, 0x105c, ltmp
);
1149 Wb35Reg_WriteSync(pHwData
, 0x1058, 0);
1150 pHwData
->reg
.BB50
|= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1151 Wb35Reg_WriteSync(pHwData
, 0x1050, pHwData
->reg
.BB50
);
1153 /* ----- Calibration (1). VCO frequency calibration */
1154 /* Calibration (1a.0). Synthesizer reset */
1155 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00101E, 24);
1156 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1158 /* Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time */
1159 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFE69c0, 24);
1160 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1163 /* ----- Calibration (2). TX baseband Gm-C filter auto-tuning */
1164 /* Calibration (2a). turn off ENCAL signal */
1165 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1166 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1167 /* Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) */
1168 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1169 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1170 /* Calibration (2b). send TX reset signal */
1171 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00201E, 24);
1172 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1173 /* Calibration (2c). turn-on TX Gm-C filter auto-tuning */
1174 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFCEBC0, 24);
1175 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1176 udelay(150); /* Sleep 150 us */
1177 /* turn off ENCAL signal */
1178 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1179 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1181 /* ----- Calibration (3). RX baseband Gm-C filter auto-tuning */
1182 /* Calibration (3a). turn off ENCAL signal */
1183 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1184 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1185 /* Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default;) */
1186 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1187 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1188 /* Calibration (3b). send RX reset signal */
1189 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00401E, 24);
1190 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1191 /* Calibration (3c). turn-on RX Gm-C filter auto-tuning */
1192 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFEEDC0, 24);
1193 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1194 udelay(150); /* Sleep 150 us */
1195 /* Calibration (3e). turn off ENCAL signal */
1196 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1197 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1199 /* ----- Calibration (4). TX LO leakage calibration */
1200 /* Calibration (4a). TX LO leakage calibration */
1201 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFD6BC0, 24);
1202 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1203 udelay(150); /* Sleep 150 us */
1205 /* ----- Calibration (5). RX DC offset calibration */
1206 /* Calibration (5a). turn off ENCAL signal and set to RX SW DC calibration mode */
1207 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1208 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1209 /* Calibration (5b). turn off AGC servo-loop & RSSI */
1210 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEBFFC2, 24);
1211 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1213 /* for LNA=11 -------- */
1214 /* Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 */
1215 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x343FCC, 24);
1216 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1217 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1218 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1219 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1221 /* Calibration (5f). turn off ENCAL signal */
1222 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1223 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1225 /* for LNA=10 -------- */
1226 /* Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 */
1227 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x342FCC, 24);
1228 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1229 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1230 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1231 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1233 /* Calibration (5f). turn off ENCAL signal */
1234 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1235 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1237 /* for LNA=01 -------- */
1238 /* Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 */
1239 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x341FCC, 24);
1240 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1241 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1242 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1243 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1245 /* Calibration (5f). turn off ENCAL signal */
1246 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1247 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1249 /* for LNA=00 -------- */
1250 /* Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 */
1251 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x340FCC, 24);
1252 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1253 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1254 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1255 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1257 /* Calibration (5f). turn off ENCAL signal */
1258 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1259 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1260 /* Calibration (5g). turn on AGC servo-loop */
1261 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEFFFC2, 24);
1262 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1264 /* ----- Calibration (7). Switch RF chip to normal mode */
1265 /* 0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode */
1266 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF86100, 24);
1267 Wb35Reg_WriteSync(pHwData
, 0x0864, ltmp
);
1273 void BBProcessor_AL7230_2400(struct hw_data
*pHwData
)
1275 struct wb35_reg
*reg
= &pHwData
->reg
;
1278 pltmp
[0] = 0x16A8337A; /* 0x1000 AGC_Ctrl1 */
1279 pltmp
[1] = 0x9AFF9AA6; /* 0x1004 AGC_Ctrl2 */
1280 pltmp
[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1281 pltmp
[3] = 0xFFF72031; /* 0x100c AGC_Ctrl4 */
1282 reg
->BB0C
= 0xFFF72031;
1283 pltmp
[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1284 pltmp
[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1285 pltmp
[6] = 0xF2211111; /* 0x1018 AGC_Ctrl7 */
1286 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1287 pltmp
[8] = 0x06443440; /* 0x1020 AGC_Ctrl9 */
1288 pltmp
[9] = 0xA8002A79; /* 0x1024 AGC_Ctrl10 */
1289 pltmp
[10] = 0x40000528;
1290 pltmp
[11] = 0x232D7F30; /* 0x102c A_ACQ_Ctrl */
1291 reg
->BB2C
= 0x232D7F30;
1292 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1294 pltmp
[0] = 0x00002c54; /* 0x1030 B_ACQ_Ctrl */
1295 reg
->BB30
= 0x00002c54;
1296 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1297 pltmp
[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1298 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1299 reg
->BB3C
= 0x00000000;
1300 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1301 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1302 pltmp
[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1303 pltmp
[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1304 pltmp
[8] = 0x2B106208; /* 0x1050 MODE_Ctrl */
1305 reg
->BB50
= 0x2B106208;
1306 pltmp
[9] = 0; /* 0x1054 */
1307 reg
->BB54
= 0x00000000;
1308 pltmp
[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1309 reg
->BB58
= 0x52524242;
1310 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1311 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1314 void BBProcessor_AL7230_5000(struct hw_data
*pHwData
)
1316 struct wb35_reg
*reg
= &pHwData
->reg
;
1319 pltmp
[0] = 0x16AA6678; /* 0x1000 AGC_Ctrl1 */
1320 pltmp
[1] = 0x9AFFA0B2; /* 0x1004 AGC_Ctrl2 */
1321 pltmp
[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1322 pltmp
[3] = 0xEFFF233E; /* 0x100c AGC_Ctrl4 */
1323 reg
->BB0C
= 0xEFFF233E;
1324 pltmp
[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1325 pltmp
[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1326 pltmp
[6] = 0xF2432111; /* 0x1018 AGC_Ctrl7 */
1327 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1328 pltmp
[8] = 0x05C43440; /* 0x1020 AGC_Ctrl9 */
1329 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1330 pltmp
[10] = 0x40000528;
1331 pltmp
[11] = 0x232FDF30;/* 0x102c A_ACQ_Ctrl */
1332 reg
->BB2C
= 0x232FDF30;
1333 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1335 pltmp
[0] = 0x80002C7C; /* 0x1030 B_ACQ_Ctrl */
1336 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1337 pltmp
[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1338 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1339 reg
->BB3C
= 0x00000000;
1340 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1341 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1342 pltmp
[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1343 pltmp
[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1344 pltmp
[8] = 0x2B107208; /* 0x1050 MODE_Ctrl */
1345 reg
->BB50
= 0x2B107208;
1346 pltmp
[9] = 0; /* 0x1054 */
1347 reg
->BB54
= 0x00000000;
1348 pltmp
[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1349 reg
->BB58
= 0x52524242;
1350 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1351 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1355 * ===========================================================================
1356 * BBProcessorPowerupInit --
1359 * Initialize the Baseband processor.
1362 * pHwData - Handle of the USB Device.
1366 *============================================================================
1368 void BBProcessor_initial(struct hw_data
*pHwData
)
1370 struct wb35_reg
*reg
= &pHwData
->reg
;
1373 switch (pHwData
->phy_type
) {
1374 case RF_MAXIM_V1
: /* Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1375 pltmp
[0] = 0x16F47E77; /* 0x1000 AGC_Ctrl1 */
1376 pltmp
[1] = 0x9AFFAEA4; /* 0x1004 AGC_Ctrl2 */
1377 pltmp
[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1378 pltmp
[3] = 0xEFFF1A34; /* 0x100c AGC_Ctrl4 */
1379 reg
->BB0C
= 0xEFFF1A34;
1380 pltmp
[4] = 0x0FABE0B7; /* 0x1010 AGC_Ctrl5 */
1381 pltmp
[5] = 0x00CAA332; /* 0x1014 AGC_Ctrl6 */
1382 pltmp
[6] = 0xF6632111; /* 0x1018 AGC_Ctrl7 */
1383 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1384 pltmp
[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1385 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1386 pltmp
[10] = (pHwData
->phy_type
== 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */
1387 pltmp
[11] = 0x232FDF30; /* 0x102c A_ACQ_Ctrl */
1388 reg
->BB2C
= 0x232FDF30; /* Modify for 33's 1.0.95.xxx version, antenna 1 */
1389 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1391 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1392 reg
->BB30
= 0x00002C54;
1393 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1394 pltmp
[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1395 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1396 reg
->BB3C
= 0x00000000;
1397 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1398 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1399 pltmp
[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1400 pltmp
[7] = 0x0E00FEFF; /* 0x104c 11b TX RC filter */
1401 pltmp
[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1402 reg
->BB50
= 0x27106208;
1403 pltmp
[9] = 0; /* 0x1054 */
1404 reg
->BB54
= 0x00000000;
1405 pltmp
[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1406 reg
->BB58
= 0x64646464;
1407 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1408 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1410 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1416 pltmp
[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1417 pltmp
[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1418 pltmp
[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1419 pltmp
[3] = 0xefff1a34; /* 0x100c AGC_Ctrl4 */
1420 reg
->BB0C
= 0xefff1a34;
1421 pltmp
[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1422 pltmp
[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1423 pltmp
[6] = 0xf6632111; /* 0x1018 AGC_Ctrl7 */
1424 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1425 pltmp
[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1426 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1427 pltmp
[10] = 0x40000528;
1428 pltmp
[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1429 reg
->BB2C
= 0x232fdf30; /* antenna 1 */
1430 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1432 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1433 reg
->BB30
= 0x00002C54;
1434 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1435 pltmp
[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1436 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1437 reg
->BB3C
= 0x00000000;
1438 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1439 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1440 pltmp
[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1441 pltmp
[7] = 0x0D00FDFF; /* 0x104c 11b TX RC filter */
1442 pltmp
[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1443 reg
->BB50
= 0x27106208;
1444 pltmp
[9] = 0; /* 0x1054 */
1445 reg
->BB54
= 0x00000000;
1446 pltmp
[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1447 reg
->BB58
= 0x64646464;
1448 pltmp
[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1449 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1451 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1455 pltmp
[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1456 pltmp
[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1457 pltmp
[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1458 pltmp
[3] = 0xf4ff1632; /* 0x100c AGC_Ctrl4 */
1459 reg
->BB0C
= 0xf4ff1632;
1460 pltmp
[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1461 pltmp
[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1462 pltmp
[6] = 0xf8632112; /* 0x1018 AGC_Ctrl7 */
1463 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1464 pltmp
[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1465 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1466 pltmp
[10] = 0x40000528;
1467 pltmp
[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1468 reg
->BB2C
= 0x232fdf30; /* antenna 1 */
1469 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1471 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1472 reg
->BB30
= 0x00002C54;
1473 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1474 pltmp
[2] = 0x5b2c8769; /* 0x1038 B_TXRX_Ctrl */
1475 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1476 reg
->BB3C
= 0x00000000;
1477 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1478 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1479 pltmp
[6] = 0x002c2617; /* 0x1048 11b TX RC filter */
1480 pltmp
[7] = 0x0800feff; /* 0x104c 11b TX RC filter */
1481 pltmp
[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1482 reg
->BB50
= 0x27106208;
1483 pltmp
[9] = 0; /* 0x1054 */
1484 reg
->BB54
= 0x00000000;
1485 pltmp
[10] = 0x64644a4a; /* 0x1058 IQ_Alpha */
1486 reg
->BB58
= 0x64646464;
1487 pltmp
[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1488 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1489 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1491 case RF_AIROHA_2230
:
1492 pltmp
[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1493 pltmp
[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1494 pltmp
[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1495 pltmp
[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1496 reg
->BB0C
= 0xFFFd203c;
1497 pltmp
[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1498 pltmp
[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1499 pltmp
[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1500 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1501 pltmp
[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1502 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1503 pltmp
[10] = 0X40000528;
1504 pltmp
[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1505 reg
->BB2C
= 0x232dfF30; /* antenna 1 */
1506 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1508 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1509 reg
->BB30
= 0x00002C54;
1510 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1511 pltmp
[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1512 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1513 reg
->BB3C
= 0x00000000;
1514 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1515 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1516 pltmp
[6] = BB48_DEFAULT_AL2230_11G
; /* 0x1048 11b TX RC filter */
1517 reg
->BB48
= BB48_DEFAULT_AL2230_11G
; /* 20051221 ch14 */
1518 pltmp
[7] = BB4C_DEFAULT_AL2230_11G
; /* 0x104c 11b TX RC filter */
1519 reg
->BB4C
= BB4C_DEFAULT_AL2230_11G
;
1520 pltmp
[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1521 reg
->BB50
= 0x27106200;
1522 pltmp
[9] = 0; /* 0x1054 */
1523 reg
->BB54
= 0x00000000;
1524 pltmp
[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1525 reg
->BB58
= 0x52524242;
1526 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1527 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1529 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1531 case RF_AIROHA_2230S
:
1532 pltmp
[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1533 pltmp
[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1534 pltmp
[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1535 pltmp
[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1536 reg
->BB0C
= 0xFFFd203c;
1537 pltmp
[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1538 pltmp
[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1539 pltmp
[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1540 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1541 pltmp
[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1542 pltmp
[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1543 pltmp
[10] = 0X40000528;
1544 pltmp
[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1545 reg
->BB2C
= 0x232dfF30; /* antenna 1 */
1546 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1548 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1549 reg
->BB30
= 0x00002C54;
1550 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1551 pltmp
[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1552 pltmp
[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1553 reg
->BB3C
= 0x00000000;
1554 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1555 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1556 pltmp
[6] = BB48_DEFAULT_AL2230_11G
; /* 0x1048 11b TX RC filter */
1557 reg
->BB48
= BB48_DEFAULT_AL2230_11G
; /* ch14 */
1558 pltmp
[7] = BB4C_DEFAULT_AL2230_11G
; /* 0x104c 11b TX RC filter */
1559 reg
->BB4C
= BB4C_DEFAULT_AL2230_11G
;
1560 pltmp
[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1561 reg
->BB50
= 0x27106200;
1562 pltmp
[9] = 0; /* 0x1054 */
1563 reg
->BB54
= 0x00000000;
1564 pltmp
[10] = 0x52523232; /* 0x1058 IQ_Alpha */
1565 reg
->BB58
= 0x52523232;
1566 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1567 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1569 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1571 case RF_AIROHA_7230
:
1572 BBProcessor_AL7230_2400(pHwData
);
1574 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1578 pltmp
[0] = 0x16A8525D; /* 0x1000 AGC_Ctrl1 */
1579 pltmp
[1] = 0x9AFF9ABA; /* 0x1004 AGC_Ctrl2 */
1580 pltmp
[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1581 pltmp
[3] = 0xEEE91C32; /* 0x100c AGC_Ctrl4 */
1582 reg
->BB0C
= 0xEEE91C32;
1583 pltmp
[4] = 0x0FACDCC5; /* 0x1010 AGC_Ctrl5 */
1584 pltmp
[5] = 0x000AA344; /* 0x1014 AGC_Ctrl6 */
1585 pltmp
[6] = 0x22222221; /* 0x1018 AGC_Ctrl7 */
1586 pltmp
[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1587 pltmp
[8] = 0x04CC3440; /* 0x1020 AGC_Ctrl9 */
1588 pltmp
[9] = 0xA9002A79; /* 0x1024 AGC_Ctrl10 */
1589 pltmp
[10] = 0x40000528; /* 0x1028 */
1590 pltmp
[11] = 0x23457F30; /* 0x102c A_ACQ_Ctrl */
1591 reg
->BB2C
= 0x23457F30;
1592 Wb35Reg_BurstWrite(pHwData
, 0x1000, pltmp
, 12, AUTO_INCREMENT
);
1594 pltmp
[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1595 reg
->BB30
= 0x00002C54;
1596 pltmp
[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1597 pltmp
[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1598 pltmp
[3] = pHwData
->BB3c_cal
; /* 0x103c 11a TX LS filter */
1599 reg
->BB3C
= pHwData
->BB3c_cal
;
1600 pltmp
[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1601 pltmp
[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1602 pltmp
[6] = BB48_DEFAULT_WB242_11G
; /* 0x1048 11b TX RC filter */
1603 reg
->BB48
= BB48_DEFAULT_WB242_11G
;
1604 pltmp
[7] = BB4C_DEFAULT_WB242_11G
; /* 0x104c 11b TX RC filter */
1605 reg
->BB4C
= BB4C_DEFAULT_WB242_11G
;
1606 pltmp
[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1607 reg
->BB50
= 0x27106208;
1608 pltmp
[9] = pHwData
->BB54_cal
; /* 0x1054 */
1609 reg
->BB54
= pHwData
->BB54_cal
;
1610 pltmp
[10] = 0x52523131; /* 0x1058 IQ_Alpha */
1611 reg
->BB58
= 0x52523131;
1612 pltmp
[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1613 Wb35Reg_BurstWrite(pHwData
, 0x1030, pltmp
, 12, AUTO_INCREMENT
);
1615 Wb35Reg_Write(pHwData
, 0x1070, 0x00000045);
1619 /* Fill the LNA table */
1620 reg
->LNAValue
[0] = (u8
) (reg
->BB0C
& 0xff);
1621 reg
->LNAValue
[1] = 0;
1622 reg
->LNAValue
[2] = (u8
) ((reg
->BB0C
& 0xff00) >> 8);
1623 reg
->LNAValue
[3] = 0;
1625 /* Fill SQ3 table */
1626 for (i
= 0; i
< MAX_SQ3_FILTER_SIZE
; i
++)
1627 reg
->SQ3_filter
[i
] = 0x2f; /* half of Bit 0 ~ 6 */
1630 void set_tx_power_per_channel_max2829(struct hw_data
*pHwData
, struct chan_info Channel
)
1632 RFSynthesizer_SetPowerIndex(pHwData
, 100);
1635 void set_tx_power_per_channel_al2230(struct hw_data
*pHwData
, struct chan_info Channel
)
1639 if (pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1] != 0xff)
1640 index
= pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1];
1642 RFSynthesizer_SetPowerIndex(pHwData
, index
);
1645 void set_tx_power_per_channel_al7230(struct hw_data
*pHwData
, struct chan_info Channel
)
1649 switch (Channel
.band
) {
1650 case BAND_TYPE_DSSS
:
1651 case BAND_TYPE_OFDM_24
:
1652 if (pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1] != 0xff)
1653 index
= pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1];
1655 case BAND_TYPE_OFDM_5
:
1656 for (i
= 0; i
< 35; i
++) {
1657 if (Channel
.ChanNo
== pHwData
->TxVgaFor50
[i
].ChanNo
) {
1658 if (pHwData
->TxVgaFor50
[i
].TxVgaValue
!= 0xff)
1659 index
= pHwData
->TxVgaFor50
[i
].TxVgaValue
;
1665 RFSynthesizer_SetPowerIndex(pHwData
, index
);
1668 void set_tx_power_per_channel_wb242(struct hw_data
*pHwData
, struct chan_info Channel
)
1672 switch (Channel
.band
) {
1673 case BAND_TYPE_DSSS
:
1674 case BAND_TYPE_OFDM_24
:
1675 if (pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1] != 0xff)
1676 index
= pHwData
->TxVgaFor24
[Channel
.ChanNo
- 1];
1678 case BAND_TYPE_OFDM_5
:
1681 RFSynthesizer_SetPowerIndex(pHwData
, index
);
1685 * ==========================================================================
1686 * RFSynthesizer_SwitchingChannel --
1689 * Swithch the RF channel.
1692 * pHwData - Handle of the USB Device.
1693 * Channel - The channel no.
1697 * ===========================================================================
1699 void RFSynthesizer_SwitchingChannel(struct hw_data
*pHwData
, struct chan_info Channel
)
1701 struct wb35_reg
*reg
= &pHwData
->reg
;
1702 u32 pltmp
[16]; /* The 16 is the maximum capability of hardware */
1707 switch (pHwData
->phy_type
) {
1709 case RF_MAXIM_V1
: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1711 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 13 */
1712 for (i
= 0; i
< 3; i
++)
1713 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_channel_data_24
[Channel
.ChanNo
-1][i
], 18);
1714 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1716 RFSynthesizer_SetPowerIndex(pHwData
, 100);
1719 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 13 */
1720 for (i
= 0; i
< 3; i
++)
1721 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_24
[Channel
.ChanNo
-1][i
], 18);
1722 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1723 } else if (Channel
.band
== BAND_TYPE_OFDM_5
) { /* channel 36 ~ 64 */
1724 ChnlTmp
= (Channel
.ChanNo
- 36) / 4;
1725 for (i
= 0; i
< 3; i
++)
1726 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_50
[ChnlTmp
][i
], 18);
1727 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1729 RFSynthesizer_SetPowerIndex(pHwData
, 100);
1732 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 13 */
1733 for (i
= 0; i
< 3; i
++)
1734 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_24
[Channel
.ChanNo
-1][i
], 18);
1735 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1736 } else if (Channel
.band
== BAND_TYPE_OFDM_5
) { /* channel 36 ~ 64 */
1737 ChnlTmp
= (Channel
.ChanNo
- 36) / 4;
1738 for (i
= 0; i
< 3; i
++)
1739 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_50
[ChnlTmp
][i
], 18);
1740 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1742 RFSynthesizer_SetPowerIndex(pHwData
, 100);
1745 if (Channel
.band
<= BAND_TYPE_OFDM_24
) {
1746 for (i
= 0; i
< 3; i
++)
1747 pltmp
[i
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24
[Channel
.ChanNo
-1][i
], 18);
1748 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1749 } else if (Channel
.band
== BAND_TYPE_OFDM_5
) {
1750 count
= ARRAY_SIZE(max2829_channel_data_50
);
1752 for (i
= 0; i
< count
; i
++) {
1753 if (max2829_channel_data_50
[i
][0] == Channel
.ChanNo
) {
1754 for (j
= 0; j
< 3; j
++)
1755 pltmp
[j
] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_50
[i
][j
+1], 18);
1756 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1758 if ((max2829_channel_data_50
[i
][3] & 0x3FFFF) == 0x2A946) {
1759 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A906, 18);
1760 Wb35Reg_Write(pHwData
, 0x0864, ltmp
);
1761 } else { /* 0x2A9C6 */
1762 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A986, 18);
1763 Wb35Reg_Write(pHwData
, 0x0864, ltmp
);
1768 set_tx_power_per_channel_max2829(pHwData
, Channel
);
1770 case RF_AIROHA_2230
:
1771 case RF_AIROHA_2230S
:
1772 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 14 */
1773 for (i
= 0; i
< 2; i
++)
1774 pltmp
[i
] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_channel_data_24
[Channel
.ChanNo
-1][i
], 20);
1775 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 2, NO_INCREMENT
);
1777 set_tx_power_per_channel_al2230(pHwData
, Channel
);
1779 case RF_AIROHA_7230
:
1780 /* Channel independent registers */
1781 if (Channel
.band
!= pHwData
->band
) {
1782 if (Channel
.band
<= BAND_TYPE_OFDM_24
) {
1783 /* Update BB register */
1784 BBProcessor_AL7230_2400(pHwData
);
1786 number
= ARRAY_SIZE(al7230_rf_data_24
);
1787 Set_ChanIndep_RfData_al7230_24(pHwData
, pltmp
, number
);
1789 /* Update BB register */
1790 BBProcessor_AL7230_5000(pHwData
);
1792 number
= ARRAY_SIZE(al7230_rf_data_50
);
1793 Set_ChanIndep_RfData_al7230_50(pHwData
, pltmp
, number
);
1796 /* Write to register. number must less and equal than 16 */
1797 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, number
, NO_INCREMENT
);
1798 #ifdef _PE_STATE_DUMP_
1799 printk("Band changed\n");
1803 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 14 */
1804 for (i
= 0; i
< 2; i
++)
1805 pltmp
[i
] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24
[Channel
.ChanNo
-1][i
]&0xffffff);
1806 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 2, NO_INCREMENT
);
1807 } else if (Channel
.band
== BAND_TYPE_OFDM_5
) {
1809 if ((Channel
.ChanNo
> 64) && (Channel
.ChanNo
<= 165)) {
1810 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
1811 Wb35Reg_Write(pHwData
, 0x0864, ltmp
);
1812 } else { /* reg12 = 0x00147c at Channel 4920 ~ 5320 */
1813 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
1814 Wb35Reg_Write(pHwData
, 0x0864, ltmp
);
1817 count
= ARRAY_SIZE(al7230_channel_data_5
);
1819 for (i
= 0; i
< count
; i
++) {
1820 if (al7230_channel_data_5
[i
][0] == Channel
.ChanNo
) {
1821 for (j
= 0; j
< 3; j
++)
1822 pltmp
[j
] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_5
[i
][j
+1] & 0xffffff);
1823 Wb35Reg_BurstWrite(pHwData
, 0x0864, pltmp
, 3, NO_INCREMENT
);
1827 set_tx_power_per_channel_al7230(pHwData
, Channel
);
1832 if (Channel
.band
<= BAND_TYPE_OFDM_24
) { /* channel 1 ~ 14 */
1833 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_channel_data_24
[Channel
.ChanNo
-1][0], 24);
1834 Wb35Reg_Write(pHwData
, 0x864, ltmp
);
1836 set_tx_power_per_channel_wb242(pHwData
, Channel
);
1840 if (Channel
.band
<= BAND_TYPE_OFDM_24
) {
1841 /* BB: select 2.4 GHz, bit[12-11]=00 */
1842 reg
->BB50
&= ~(BIT(11) | BIT(12));
1843 Wb35Reg_Write(pHwData
, 0x1050, reg
->BB50
); /* MODE_Ctrl */
1844 /* MAC: select 2.4 GHz, bit[5]=0 */
1845 reg
->M78_ERPInformation
&= ~BIT(5);
1846 Wb35Reg_Write(pHwData
, 0x0878, reg
->M78_ERPInformation
);
1847 /* enable 11b Baseband */
1848 reg
->BB30
&= ~BIT(31);
1849 Wb35Reg_Write(pHwData
, 0x1030, reg
->BB30
);
1850 } else if (Channel
.band
== BAND_TYPE_OFDM_5
) {
1851 /* BB: select 5 GHz */
1852 reg
->BB50
&= ~(BIT(11) | BIT(12));
1853 if (Channel
.ChanNo
<= 64)
1854 reg
->BB50
|= BIT(12); /* 10-5.25GHz */
1855 else if ((Channel
.ChanNo
>= 100) && (Channel
.ChanNo
<= 124))
1856 reg
->BB50
|= BIT(11); /* 01-5.48GHz */
1857 else if ((Channel
.ChanNo
>= 128) && (Channel
.ChanNo
<= 161))
1858 reg
->BB50
|= (BIT(12) | BIT(11)); /* 11-5.775GHz */
1859 else /* Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 */
1860 reg
->BB50
|= BIT(12);
1861 Wb35Reg_Write(pHwData
, 0x1050, reg
->BB50
); /* MODE_Ctrl */
1863 /* (1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 */
1864 /* (2) BB30 has been updated previously. */
1865 if (pHwData
->phy_type
!= RF_AIROHA_7230
) {
1866 /* MAC: select 5 GHz, bit[5]=1 */
1867 reg
->M78_ERPInformation
|= BIT(5);
1868 Wb35Reg_Write(pHwData
, 0x0878, reg
->M78_ERPInformation
);
1870 /* disable 11b Baseband */
1871 reg
->BB30
|= BIT(31);
1872 Wb35Reg_Write(pHwData
, 0x1030, reg
->BB30
);
1878 * Set the tx power directly from DUT GUI, not from the EEPROM.
1879 * Return the current setting
1881 u8
RFSynthesizer_SetPowerIndex(struct hw_data
*pHwData
, u8 PowerIndex
)
1883 u32 Band
= pHwData
->band
;
1886 if (pHwData
->power_index
== PowerIndex
)
1889 if (RF_MAXIM_2825
== pHwData
->phy_type
) {
1890 /* Channel 1 - 13 */
1891 index
= RFSynthesizer_SetMaxim2825Power(pHwData
, PowerIndex
);
1892 } else if (RF_MAXIM_2827
== pHwData
->phy_type
) {
1893 if (Band
<= BAND_TYPE_OFDM_24
) /* Channel 1 - 13 */
1894 index
= RFSynthesizer_SetMaxim2827_24Power(pHwData
, PowerIndex
);
1895 else /* Channel 36 - 64 */
1896 index
= RFSynthesizer_SetMaxim2827_50Power(pHwData
, PowerIndex
);
1897 } else if (RF_MAXIM_2828
== pHwData
->phy_type
) {
1898 if (Band
<= BAND_TYPE_OFDM_24
) /* Channel 1 - 13 */
1899 index
= RFSynthesizer_SetMaxim2828_24Power(pHwData
, PowerIndex
);
1900 else /* Channel 36 - 64 */
1901 index
= RFSynthesizer_SetMaxim2828_50Power(pHwData
, PowerIndex
);
1902 } else if (RF_AIROHA_2230
== pHwData
->phy_type
) {
1903 /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1904 index
= RFSynthesizer_SetAiroha2230Power(pHwData
, PowerIndex
);
1905 index
= (u8
) al2230_txvga_data
[index
][1];
1906 } else if (RF_AIROHA_2230S
== pHwData
->phy_type
) {
1907 /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1908 index
= RFSynthesizer_SetAiroha2230Power(pHwData
, PowerIndex
);
1909 index
= (u8
) al2230_txvga_data
[index
][1];
1910 } else if (RF_AIROHA_7230
== pHwData
->phy_type
) {
1911 /* Power index: 0 ~ 63 */
1912 index
= RFSynthesizer_SetAiroha7230Power(pHwData
, PowerIndex
);
1913 index
= (u8
)al7230_txvga_data
[index
][1];
1914 } else if ((RF_WB_242
== pHwData
->phy_type
) ||
1915 (RF_WB_242_1
== pHwData
->phy_type
)) {
1916 /* Power index: 0 ~ 19 for original. New range is 0 ~ 33 */
1917 index
= RFSynthesizer_SetWinbond242Power(pHwData
, PowerIndex
);
1918 index
= (u8
)w89rf242_txvga_data
[index
][1];
1921 pHwData
->power_index
= index
; /* Backup current */
1925 /* -- Sub function */
1926 u8
RFSynthesizer_SetMaxim2828_24Power(struct hw_data
*pHwData
, u8 index
)
1931 PowerData
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_24
[index
], 18);
1932 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1936 u8
RFSynthesizer_SetMaxim2828_50Power(struct hw_data
*pHwData
, u8 index
)
1941 PowerData
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_50
[index
], 18);
1942 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1946 u8
RFSynthesizer_SetMaxim2827_24Power(struct hw_data
*pHwData
, u8 index
)
1951 PowerData
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_24
[index
], 18);
1952 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1956 u8
RFSynthesizer_SetMaxim2827_50Power(struct hw_data
*pHwData
, u8 index
)
1961 PowerData
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_50
[index
], 18);
1962 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1966 u8
RFSynthesizer_SetMaxim2825Power(struct hw_data
*pHwData
, u8 index
)
1971 PowerData
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_power_data_24
[index
], 18);
1972 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1976 u8
RFSynthesizer_SetAiroha2230Power(struct hw_data
*pHwData
, u8 index
)
1981 count
= ARRAY_SIZE(al2230_txvga_data
);
1982 for (i
= 0; i
< count
; i
++) {
1983 if (al2230_txvga_data
[i
][1] >= index
)
1989 PowerData
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_txvga_data
[i
][0], 20);
1990 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
1994 u8
RFSynthesizer_SetAiroha7230Power(struct hw_data
*pHwData
, u8 index
)
1999 count
= ARRAY_SIZE(al7230_txvga_data
);
2000 for (i
= 0; i
< count
; i
++) {
2001 if (al7230_txvga_data
[i
][1] >= index
)
2006 PowerData
= (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data
[i
][0] & 0xffffff);
2007 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
2011 u8
RFSynthesizer_SetWinbond242Power(struct hw_data
*pHwData
, u8 index
)
2016 count
= ARRAY_SIZE(w89rf242_txvga_data
);
2017 for (i
= 0; i
< count
; i
++) {
2018 if (w89rf242_txvga_data
[i
][1] >= index
)
2024 /* Set TxVga into RF */
2025 PowerData
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_txvga_data
[i
][0], 24);
2026 Wb35Reg_Write(pHwData
, 0x0864, PowerData
);
2028 /* Update BB48 BB4C BB58 for high precision txvga */
2029 Wb35Reg_Write(pHwData
, 0x1048, w89rf242_txvga_data
[i
][2]);
2030 Wb35Reg_Write(pHwData
, 0x104c, w89rf242_txvga_data
[i
][3]);
2031 Wb35Reg_Write(pHwData
, 0x1058, w89rf242_txvga_data
[i
][4]);
2037 * ===========================================================================
2041 * Routine Description:
2042 * Initial the hardware setting and module variable
2043 * ===========================================================================
2045 void Dxx_initial(struct hw_data
*pHwData
)
2047 struct wb35_reg
*reg
= &pHwData
->reg
;
2050 * Old IC: Single mode only.
2051 * New IC: operation decide by Software set bit[4]. 1:multiple 0: single
2053 reg
->D00_DmaControl
= 0xc0000004; /* Txon, Rxon, multiple Rx for new 4k DMA */
2054 /* Txon, Rxon, single Rx for old 8k ASIC */
2055 if (!HAL_USB_MODE_BURST(pHwData
))
2056 reg
->D00_DmaControl
= 0xc0000000; /* Txon, Rxon, single Rx for new 4k DMA */
2058 Wb35Reg_WriteSync(pHwData
, 0x0400, reg
->D00_DmaControl
);
2061 void Mxx_initial(struct hw_data
*pHwData
)
2063 struct wb35_reg
*reg
= &pHwData
->reg
;
2070 * ======================================================
2071 * Initial Mxx register
2072 * ======================================================
2076 #ifdef _IBSS_BEACON_SEQ_STICK_
2077 reg
->M00_MacControl
= 0; /* Solve beacon sequence number stop by software */
2079 reg
->M00_MacControl
= 0x80000000; /* Solve beacon sequence number stop by hardware */
2082 /* M24 disable enter power save, BB RxOn and enable NAV attack */
2083 reg
->M24_MacControl
= 0x08040042;
2084 pltmp
[0] = reg
->M24_MacControl
;
2086 pltmp
[1] = 0; /* Skip M28, because no initialize value is required. */
2088 /* M2C CWmin and CWmax setting */
2089 pHwData
->cwmin
= DEFAULT_CWMIN
;
2090 pHwData
->cwmax
= DEFAULT_CWMAX
;
2091 reg
->M2C_MacControl
= DEFAULT_CWMIN
<< 10;
2092 reg
->M2C_MacControl
|= DEFAULT_CWMAX
;
2093 pltmp
[2] = reg
->M2C_MacControl
;
2096 pltmp
[3] = *(u32
*)pHwData
->bssid
;
2099 pHwData
->AID
= DEFAULT_AID
;
2100 tmp
= *(u16
*) (pHwData
->bssid
+ 4);
2101 tmp
|= DEFAULT_AID
<< 16;
2105 reg
->M38_MacControl
= (DEFAULT_RATE_RETRY_LIMIT
<< 8) | (DEFAULT_LONG_RETRY_LIMIT
<< 4) | DEFAULT_SHORT_RETRY_LIMIT
;
2106 pltmp
[5] = reg
->M38_MacControl
;
2109 tmp
= (DEFAULT_PIFST
<< 26) | (DEFAULT_EIFST
<< 16) | (DEFAULT_DIFST
<< 8) | (DEFAULT_SIFST
<< 4) | DEFAULT_OSIFST
;
2110 reg
->M3C_MacControl
= tmp
;
2114 pHwData
->slot_time_select
= DEFAULT_SLOT_TIME
;
2115 tmp
= (DEFAULT_ATIMWD
<< 16) | DEFAULT_SLOT_TIME
;
2116 reg
->M40_MacControl
= tmp
;
2120 tmp
= DEFAULT_MAX_TX_MSDU_LIFE_TIME
<< 10; /* *1024 */
2121 reg
->M44_MacControl
= tmp
;
2125 pHwData
->BeaconPeriod
= DEFAULT_BEACON_INTERVAL
;
2126 pHwData
->ProbeDelay
= DEFAULT_PROBE_DELAY_TIME
;
2127 tmp
= (DEFAULT_BEACON_INTERVAL
<< 16) | DEFAULT_PROBE_DELAY_TIME
;
2128 reg
->M48_MacControl
= tmp
;
2132 reg
->M4C_MacStatus
= (DEFAULT_PROTOCOL_VERSION
<< 30) | (DEFAULT_MAC_POWER_STATE
<< 28) | (DEFAULT_DTIM_ALERT_TIME
<< 24);
2133 pltmp
[10] = reg
->M4C_MacStatus
;
2135 for (i
= 0; i
< 11; i
++)
2136 Wb35Reg_WriteSync(pHwData
, 0x0824 + i
* 4, pltmp
[i
]);
2139 Wb35Reg_WriteSync(pHwData
, 0x0860, 0x12481248);
2140 reg
->M60_MacControl
= 0x12481248;
2143 Wb35Reg_WriteSync(pHwData
, 0x0868, 0x00050900);
2144 reg
->M68_MacControl
= 0x00050900;
2147 Wb35Reg_WriteSync(pHwData
, 0x0898, 0xffff8888);
2148 reg
->M98_MacControl
= 0xffff8888;
2152 void Uxx_power_off_procedure(struct hw_data
*pHwData
)
2154 /* SW, PMU reset and turn off clock */
2155 Wb35Reg_WriteSync(pHwData
, 0x03b0, 3);
2156 Wb35Reg_WriteSync(pHwData
, 0x03f0, 0xf9);
2159 /*Decide the TxVga of every channel */
2160 void GetTxVgaFromEEPROM(struct hw_data
*pHwData
)
2163 u16 Value
[MAX_TXVGA_EEPROM
];
2167 /* Get the entire TxVga setting in EEPROM */
2168 for (i
= 0; i
< MAX_TXVGA_EEPROM
; i
++) {
2169 Wb35Reg_WriteSync(pHwData
, 0x03b4, 0x08100000 + 0x00010000 * i
);
2170 Wb35Reg_ReadSync(pHwData
, 0x03b4, <mp
);
2171 Value
[i
] = (u16
) (ltmp
& 0xffff); /* Get 16 bit available */
2172 Value
[i
] = cpu_to_le16(Value
[i
]); /* [7:0]2412 [7:0]2417 .... */
2175 /* Adjust the filed which fills with reserved value. */
2176 pctmp
= (u8
*) Value
;
2177 for (i
= 0; i
< (MAX_TXVGA_EEPROM
* 2); i
++) {
2178 if (pctmp
[i
] != 0xff)
2184 /* Adjust WB_242 to WB_242_1 TxVga scale */
2185 if (pHwData
->phy_type
== RF_WB_242
) {
2186 for (i
= 0; i
< 4; i
++) { /* Only 2412 2437 2462 2484 case must be modified */
2187 for (j
= 0; j
< ARRAY_SIZE(w89rf242_txvga_old_mapping
); j
++) {
2188 if (pctmp
[i
] < (u8
) w89rf242_txvga_old_mapping
[j
][1]) {
2189 pctmp
[i
] = (u8
) w89rf242_txvga_old_mapping
[j
][0];
2194 if (j
== ARRAY_SIZE(w89rf242_txvga_old_mapping
))
2195 pctmp
[i
] = (u8
)w89rf242_txvga_old_mapping
[j
-1][0];
2199 memcpy(pHwData
->TxVgaSettingInEEPROM
, pctmp
, MAX_TXVGA_EEPROM
* 2); /* MAX_TXVGA_EEPROM is u16 count */
2200 EEPROMTxVgaAdjust(pHwData
);
2204 * This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2205 * or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2206 * TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2207 * This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2209 void EEPROMTxVgaAdjust(struct hw_data
*pHwData
)
2211 u8
*pTxVga
= pHwData
->TxVgaSettingInEEPROM
;
2216 stmp
= pTxVga
[1] - pTxVga
[0];
2217 for (i
= 0; i
< 5; i
++)
2218 pHwData
->TxVgaFor24
[i
] = pTxVga
[0] + stmp
* i
/ 4;
2219 /* channel 6 ~ 10 */
2220 stmp
= pTxVga
[2] - pTxVga
[1];
2221 for (i
= 5; i
< 10; i
++)
2222 pHwData
->TxVgaFor24
[i
] = pTxVga
[1] + stmp
* (i
- 5) / 4;
2223 /* channel 11 ~ 13 */
2224 stmp
= pTxVga
[3] - pTxVga
[2];
2225 for (i
= 10; i
< 13; i
++)
2226 pHwData
->TxVgaFor24
[i
] = pTxVga
[2] + stmp
* (i
- 10) / 2;
2228 pHwData
->TxVgaFor24
[13] = pTxVga
[3];
2231 if (pHwData
->phy_type
== RF_AIROHA_7230
) {
2233 pHwData
->TxVgaFor50
[0].ChanNo
= 184;
2234 pHwData
->TxVgaFor50
[0].TxVgaValue
= pTxVga
[4];
2236 pHwData
->TxVgaFor50
[3].ChanNo
= 196;
2237 pHwData
->TxVgaFor50
[3].TxVgaValue
= pTxVga
[5];
2239 pHwData
->TxVgaFor50
[1].ChanNo
= 188;
2240 pHwData
->TxVgaFor50
[2].ChanNo
= 192;
2241 stmp
= pTxVga
[5] - pTxVga
[4];
2242 pHwData
->TxVgaFor50
[2].TxVgaValue
= pTxVga
[5] - stmp
/ 3;
2243 pHwData
->TxVgaFor50
[1].TxVgaValue
= pTxVga
[5] - stmp
* 2 / 3;
2246 pHwData
->TxVgaFor50
[6].ChanNo
= 16;
2247 pHwData
->TxVgaFor50
[6].TxVgaValue
= pTxVga
[6];
2248 pHwData
->TxVgaFor50
[4].ChanNo
= 8;
2249 pHwData
->TxVgaFor50
[4].TxVgaValue
= pTxVga
[6];
2250 pHwData
->TxVgaFor50
[5].ChanNo
= 12;
2251 pHwData
->TxVgaFor50
[5].TxVgaValue
= pTxVga
[6];
2254 pHwData
->TxVgaFor50
[8].ChanNo
= 36;
2255 pHwData
->TxVgaFor50
[8].TxVgaValue
= pTxVga
[7];
2256 pHwData
->TxVgaFor50
[7].ChanNo
= 34;
2257 pHwData
->TxVgaFor50
[7].TxVgaValue
= pTxVga
[7];
2258 pHwData
->TxVgaFor50
[9].ChanNo
= 38;
2259 pHwData
->TxVgaFor50
[9].TxVgaValue
= pTxVga
[7];
2262 pHwData
->TxVgaFor50
[10].ChanNo
= 40;
2263 pHwData
->TxVgaFor50
[10].TxVgaValue
= pTxVga
[8];
2265 pHwData
->TxVgaFor50
[14].ChanNo
= 48;
2266 pHwData
->TxVgaFor50
[14].TxVgaValue
= pTxVga
[9];
2268 pHwData
->TxVgaFor50
[11].ChanNo
= 42;
2269 pHwData
->TxVgaFor50
[12].ChanNo
= 44;
2270 pHwData
->TxVgaFor50
[13].ChanNo
= 46;
2271 stmp
= pTxVga
[9] - pTxVga
[8];
2272 pHwData
->TxVgaFor50
[13].TxVgaValue
= pTxVga
[9] - stmp
/ 4;
2273 pHwData
->TxVgaFor50
[12].TxVgaValue
= pTxVga
[9] - stmp
* 2 / 4;
2274 pHwData
->TxVgaFor50
[11].TxVgaValue
= pTxVga
[9] - stmp
* 3 / 4;
2277 pHwData
->TxVgaFor50
[15].ChanNo
= 52;
2278 pHwData
->TxVgaFor50
[15].TxVgaValue
= pTxVga
[10];
2280 pHwData
->TxVgaFor50
[18].ChanNo
= 64;
2281 pHwData
->TxVgaFor50
[18].TxVgaValue
= pTxVga
[11];
2283 pHwData
->TxVgaFor50
[16].ChanNo
= 56;
2284 pHwData
->TxVgaFor50
[17].ChanNo
= 60;
2285 stmp
= pTxVga
[11] - pTxVga
[10];
2286 pHwData
->TxVgaFor50
[17].TxVgaValue
= pTxVga
[11] - stmp
/ 3;
2287 pHwData
->TxVgaFor50
[16].TxVgaValue
= pTxVga
[11] - stmp
* 2 / 3;
2290 pHwData
->TxVgaFor50
[19].ChanNo
= 100;
2291 pHwData
->TxVgaFor50
[19].TxVgaValue
= pTxVga
[12];
2293 pHwData
->TxVgaFor50
[22].ChanNo
= 112;
2294 pHwData
->TxVgaFor50
[22].TxVgaValue
= pTxVga
[13];
2296 pHwData
->TxVgaFor50
[20].ChanNo
= 104;
2297 pHwData
->TxVgaFor50
[21].ChanNo
= 108;
2298 stmp
= pTxVga
[13] - pTxVga
[12];
2299 pHwData
->TxVgaFor50
[21].TxVgaValue
= pTxVga
[13] - stmp
/ 3;
2300 pHwData
->TxVgaFor50
[20].TxVgaValue
= pTxVga
[13] - stmp
* 2 / 3;
2303 pHwData
->TxVgaFor50
[26].ChanNo
= 128;
2304 pHwData
->TxVgaFor50
[26].TxVgaValue
= pTxVga
[14];
2306 pHwData
->TxVgaFor50
[23].ChanNo
= 116;
2307 pHwData
->TxVgaFor50
[24].ChanNo
= 120;
2308 pHwData
->TxVgaFor50
[25].ChanNo
= 124;
2309 stmp
= pTxVga
[14] - pTxVga
[13];
2310 pHwData
->TxVgaFor50
[25].TxVgaValue
= pTxVga
[14] - stmp
/ 4;
2311 pHwData
->TxVgaFor50
[24].TxVgaValue
= pTxVga
[14] - stmp
* 2 / 4;
2312 pHwData
->TxVgaFor50
[23].TxVgaValue
= pTxVga
[14] - stmp
* 3 / 4;
2315 pHwData
->TxVgaFor50
[29].ChanNo
= 140;
2316 pHwData
->TxVgaFor50
[29].TxVgaValue
= pTxVga
[15];
2318 pHwData
->TxVgaFor50
[27].ChanNo
= 132;
2319 pHwData
->TxVgaFor50
[28].ChanNo
= 136;
2320 stmp
= pTxVga
[15] - pTxVga
[14];
2321 pHwData
->TxVgaFor50
[28].TxVgaValue
= pTxVga
[15] - stmp
/ 3;
2322 pHwData
->TxVgaFor50
[27].TxVgaValue
= pTxVga
[15] - stmp
* 2 / 3;
2325 pHwData
->TxVgaFor50
[30].ChanNo
= 149;
2326 pHwData
->TxVgaFor50
[30].TxVgaValue
= pTxVga
[16];
2328 pHwData
->TxVgaFor50
[34].ChanNo
= 165;
2329 pHwData
->TxVgaFor50
[34].TxVgaValue
= pTxVga
[17];
2331 pHwData
->TxVgaFor50
[31].ChanNo
= 153;
2332 pHwData
->TxVgaFor50
[32].ChanNo
= 157;
2333 pHwData
->TxVgaFor50
[33].ChanNo
= 161;
2334 stmp
= pTxVga
[17] - pTxVga
[16];
2335 pHwData
->TxVgaFor50
[33].TxVgaValue
= pTxVga
[17] - stmp
/ 4;
2336 pHwData
->TxVgaFor50
[32].TxVgaValue
= pTxVga
[17] - stmp
* 2 / 4;
2337 pHwData
->TxVgaFor50
[31].TxVgaValue
= pTxVga
[17] - stmp
* 3 / 4;
2340 #ifdef _PE_STATE_DUMP_
2341 printk(" TxVgaFor24 :\n");
2342 DataDmp((u8
*)pHwData
->TxVgaFor24
, 14 , 0);
2343 printk(" TxVgaFor50 :\n");
2344 DataDmp((u8
*)pHwData
->TxVgaFor50
, 70 , 0);
2348 void BBProcessor_RateChanging(struct hw_data
*pHwData
, u8 rate
)
2350 struct wb35_reg
*reg
= &pHwData
->reg
;
2351 unsigned char Is11bRate
;
2353 Is11bRate
= (rate
% 6) ? 1 : 0;
2354 switch (pHwData
->phy_type
) {
2355 case RF_AIROHA_2230
:
2356 case RF_AIROHA_2230S
:
2358 if ((reg
->BB48
!= BB48_DEFAULT_AL2230_11B
) &&
2359 (reg
->BB4C
!= BB4C_DEFAULT_AL2230_11B
)) {
2360 Wb35Reg_Write(pHwData
, 0x1048, BB48_DEFAULT_AL2230_11B
);
2361 Wb35Reg_Write(pHwData
, 0x104c, BB4C_DEFAULT_AL2230_11B
);
2364 if ((reg
->BB48
!= BB48_DEFAULT_AL2230_11G
) &&
2365 (reg
->BB4C
!= BB4C_DEFAULT_AL2230_11G
)) {
2366 Wb35Reg_Write(pHwData
, 0x1048, BB48_DEFAULT_AL2230_11G
);
2367 Wb35Reg_Write(pHwData
, 0x104c, BB4C_DEFAULT_AL2230_11G
);
2373 if ((reg
->BB48
!= BB48_DEFAULT_WB242_11B
) &&
2374 (reg
->BB4C
!= BB4C_DEFAULT_WB242_11B
)) {
2375 reg
->BB48
= BB48_DEFAULT_WB242_11B
;
2376 reg
->BB4C
= BB4C_DEFAULT_WB242_11B
;
2377 Wb35Reg_Write(pHwData
, 0x1048, BB48_DEFAULT_WB242_11B
);
2378 Wb35Reg_Write(pHwData
, 0x104c, BB4C_DEFAULT_WB242_11B
);
2381 if ((reg
->BB48
!= BB48_DEFAULT_WB242_11G
) &&
2382 (reg
->BB4C
!= BB4C_DEFAULT_WB242_11G
)) {
2383 reg
->BB48
= BB48_DEFAULT_WB242_11G
;
2384 reg
->BB4C
= BB4C_DEFAULT_WB242_11G
;
2385 Wb35Reg_Write(pHwData
, 0x1048, BB48_DEFAULT_WB242_11G
);
2386 Wb35Reg_Write(pHwData
, 0x104c, BB4C_DEFAULT_WB242_11G
);