2 * phy_302_calibration.c
4 * Copyright (C) 2002, 2005 Winbond Electronics Corp.
7 * ---------------------------------------------------------------------------
8 * 0.01.001, 2003-04-16, Kevin created
12 /****************** INCLUDE FILES SECTION ***********************************/
14 #include "phy_calibration.h"
18 /****************** DEBUG CONSTANT AND MACRO SECTION ************************/
20 /****************** LOCAL CONSTANT AND MACRO SECTION ************************/
22 #define US 1000//MICROSECOND
24 #define AG_CONST 0.6072529350
25 #define FIXED(X) ((s32)((X) * 32768.0))
26 #define DEG2RAD(X) 0.017453 * (X)
28 static const s32 Angles
[] =
30 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
31 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
32 FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)),
33 FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
36 /****************** LOCAL FUNCTION DECLARATION SECTION **********************/
37 //void _phy_rf_write_delay(struct hw_data *phw_data);
38 //void phy_init_rf(struct hw_data *phw_data);
40 /****************** FUNCTION DEFINITION SECTION *****************************/
42 s32
_s13_to_s32(u32 data
)
46 val
= (data
& 0x0FFF);
48 if ((data
& BIT(12)) != 0)
56 u32
_s32_to_s13(s32 data
)
64 else if (data
< -4096)
74 /****************************************************************************/
75 s32
_s4_to_s32(u32 data
)
79 val
= (data
& 0x0007);
81 if ((data
& BIT(3)) != 0)
89 u32
_s32_to_s4(s32 data
)
107 /****************************************************************************/
108 s32
_s5_to_s32(u32 data
)
112 val
= (data
& 0x000F);
114 if ((data
& BIT(4)) != 0)
122 u32
_s32_to_s5(s32 data
)
140 /****************************************************************************/
141 s32
_s6_to_s32(u32 data
)
145 val
= (data
& 0x001F);
147 if ((data
& BIT(5)) != 0)
155 u32
_s32_to_s6(s32 data
)
173 /****************************************************************************/
174 s32
_s9_to_s32(u32 data
)
180 if ((data
& BIT(8)) != 0)
188 u32
_s32_to_s9(s32 data
)
196 else if (data
< -256)
206 /****************************************************************************/
221 /****************************************************************************/
222 // The following code is sqare-root function.
223 // sqsum is the input and the output is sq_rt;
224 // The maximum of sqsum = 2^27 -1;
229 int g0
, g1
, g2
, g3
, g4
;
234 g4
= sqsum
/ 100000000;
235 g3
= (sqsum
- g4
*100000000) /1000000;
236 g2
= (sqsum
- g4
*100000000 - g3
*1000000) /10000;
237 g1
= (sqsum
- g4
*100000000 - g3
*1000000 - g2
*10000) /100;
238 g0
= (sqsum
- g4
*100000000 - g3
*1000000 - g2
*10000 - g1
*100);
243 while (((seed
+1)*(step
+1)) <= next
)
249 sq_rt
= seed
* 10000;
250 next
= (next
-(seed
*step
))*100 + g3
;
253 seed
= 2 * seed
* 10;
254 while (((seed
+1)*(step
+1)) <= next
)
260 sq_rt
= sq_rt
+ step
* 1000;
261 next
= (next
- seed
* step
) * 100 + g2
;
262 seed
= (seed
+ step
) * 10;
264 while (((seed
+1)*(step
+1)) <= next
)
270 sq_rt
= sq_rt
+ step
* 100;
271 next
= (next
- seed
* step
) * 100 + g1
;
272 seed
= (seed
+ step
) * 10;
275 while (((seed
+1)*(step
+1)) <= next
)
281 sq_rt
= sq_rt
+ step
* 10;
282 next
= (next
- seed
* step
) * 100 + g0
;
283 seed
= (seed
+ step
) * 10;
286 while (((seed
+1)*(step
+1)) <= next
)
292 sq_rt
= sq_rt
+ step
;
297 /****************************************************************************/
298 void _sin_cos(s32 angle
, s32
*sin
, s32
*cos
)
300 s32 X
, Y
, TargetAngle
, CurrAngle
;
303 X
=FIXED(AG_CONST
); // AG_CONST * cos(0)
304 Y
=0; // AG_CONST * sin(0)
305 TargetAngle
=abs(angle
);
308 for (Step
=0; Step
< 12; Step
++)
312 if(TargetAngle
> CurrAngle
)
314 NewX
=X
- (Y
>> Step
);
317 CurrAngle
+= Angles
[Step
];
321 NewX
=X
+ (Y
>> Step
);
324 CurrAngle
-= Angles
[Step
];
340 static unsigned char hal_get_dxx_reg(struct hw_data
*pHwData
, u16 number
, u32
* pValue
)
344 return Wb35Reg_ReadSync(pHwData
, number
, pValue
);
346 #define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C )
348 static unsigned char hal_set_dxx_reg(struct hw_data
*pHwData
, u16 number
, u32 value
)
354 ret
= Wb35Reg_WriteSync(pHwData
, number
, value
);
357 #define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
360 void _reset_rx_cal(struct hw_data
*phw_data
)
364 hw_get_dxx_reg(phw_data
, 0x54, &val
);
366 if (phw_data
->revision
== 0x2002) // 1st-cut
375 hw_set_dxx_reg(phw_data
, 0x54, val
);
379 // ************for winbond calibration*********
384 // *********************************************
385 void _rxadc_dc_offset_cancellation_winbond(struct hw_data
*phw_data
, u32 frequency
)
392 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
393 phy_init_rf(phw_data
);
395 // set calibration channel
396 if( (RF_WB_242
== phw_data
->phy_type
) ||
397 (RF_WB_242_1
== phw_data
->phy_type
) ) // 20060619.5 Add
399 if ((frequency
>= 2412) && (frequency
<= 2484))
401 // w89rf242 change frequency to 2390Mhz
402 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
403 phy_set_rf_data(phw_data
, 3, (3<<24)|0x025586);
412 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
413 hw_get_dxx_reg(phw_data
, 0x5C, &val
);
415 hw_set_dxx_reg(phw_data
, 0x5C, val
);
417 // reset the TX and RX IQ calibration data
418 hw_set_dxx_reg(phw_data
, 0x3C, 0);
419 hw_set_dxx_reg(phw_data
, 0x54, 0);
421 hw_set_dxx_reg(phw_data
, 0x58, 0x30303030); // IQ_Alpha Changed
424 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL3
, ®_agc_ctrl3
);
425 reg_agc_ctrl3
&= ~BIT(2);
426 reg_agc_ctrl3
|= (MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
427 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
429 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL5
, &val
);
430 val
|= MASK_AGC_FIX_GAIN
;
431 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL5
, val
);
434 hw_get_dxx_reg(phw_data
, REG_A_ACQ_CTRL
, ®_a_acq_ctrl
);
435 reg_a_acq_ctrl
|= MASK_AMER_OFF_REG
;
436 hw_set_dxx_reg(phw_data
, REG_A_ACQ_CTRL
, reg_a_acq_ctrl
);
438 hw_get_dxx_reg(phw_data
, REG_B_ACQ_CTRL
, ®_b_acq_ctrl
);
439 reg_b_acq_ctrl
|= MASK_BMER_OFF_REG
;
440 hw_set_dxx_reg(phw_data
, REG_B_ACQ_CTRL
, reg_b_acq_ctrl
);
442 // c. Make sure MAC is in receiving mode
443 // d. Turn ON ADC calibration
444 // - ADC calibrator is triggered by this signal rising from 0 to 1
445 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, &val
);
446 val
&= ~MASK_ADC_DC_CAL_STR
;
447 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, val
);
449 val
|= MASK_ADC_DC_CAL_STR
;
450 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, val
);
452 // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]"
454 hw_get_dxx_reg(phw_data
, REG_OFFSET_READ
, &val
);
455 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val
));
457 PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n",
458 _s9_to_s32(val
&0x000001FF), val
&0x000001FF));
459 PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n",
460 _s9_to_s32((val
&0x0003FE00)>>9), (val
&0x0003FE00)>>9));
463 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, &val
);
464 val
&= ~MASK_ADC_DC_CAL_STR
;
465 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, val
);
468 //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, ®_a_acq_ctrl);
469 reg_a_acq_ctrl
&= ~MASK_AMER_OFF_REG
;
470 hw_set_dxx_reg(phw_data
, REG_A_ACQ_CTRL
, reg_a_acq_ctrl
);
472 //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, ®_b_acq_ctrl);
473 reg_b_acq_ctrl
&= ~MASK_BMER_OFF_REG
;
474 hw_set_dxx_reg(phw_data
, REG_B_ACQ_CTRL
, reg_b_acq_ctrl
);
477 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
478 reg_agc_ctrl3
|= BIT(2);
479 reg_agc_ctrl3
&= ~(MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
480 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
483 ////////////////////////////////////////////////////////
484 void _txidac_dc_offset_cancellation_winbond(struct hw_data
*phw_data
)
494 s32 fix_cancel_dc_i
= 0;
498 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
500 // a. Set to "TX calibration mode"
502 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
503 phy_set_rf_data(phw_data
, 1, (1<<24)|0xEE3FC2);
504 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
505 phy_set_rf_data(phw_data
, 11, (11<<24)|0x1901D6);
506 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
507 phy_set_rf_data(phw_data
, 5, (5<<24)|0x24C48A);
508 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
509 phy_set_rf_data(phw_data
, 6, (6<<24)|0x06890C);
510 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
511 phy_set_rf_data(phw_data
, 0, (0<<24)|0xFDF1C0);
513 hw_set_dxx_reg(phw_data
, 0x58, 0x30303030); // IQ_Alpha Changed
516 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL3
, ®_agc_ctrl3
);
517 reg_agc_ctrl3
&= ~BIT(2);
518 reg_agc_ctrl3
|= (MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
519 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
521 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL5
, &val
);
522 val
|= MASK_AGC_FIX_GAIN
;
523 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL5
, val
);
525 // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0
526 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
528 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl
));
529 reg_mode_ctrl
&= ~(MASK_IQCAL_TONE_SEL
|MASK_IQCAL_MODE
);
532 //reg_mode_ctrl |= (MASK_CALIB_START|2);
535 //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2));
538 reg_mode_ctrl
|= (MASK_CALIB_START
|2|(2<<2));
539 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
540 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
542 hw_get_dxx_reg(phw_data
, 0x5C, ®_dc_cancel
);
543 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel
));
545 for (loop
= 0; loop
< LOOP_TIMES
; loop
++)
547 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop
));
550 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
551 reg_dc_cancel
&= ~(0x03FF);
552 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
553 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
555 hw_get_dxx_reg(phw_data
, REG_CALIB_READ2
, &val
);
556 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val
));
558 iqcal_image_i
= _s13_to_s32(val
& 0x00001FFF);
559 iqcal_image_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
560 sqsum
= iqcal_image_i
*iqcal_image_i
+ iqcal_image_q
*iqcal_image_q
;
561 mag_0
= (s32
) _sqrt(sqsum
);
562 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
563 mag_0
, iqcal_image_i
, iqcal_image_q
));
566 reg_dc_cancel
|= (1 << CANCEL_DC_I_SHIFT
);
567 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
568 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
570 hw_get_dxx_reg(phw_data
, REG_CALIB_READ2
, &val
);
571 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val
));
573 iqcal_image_i
= _s13_to_s32(val
& 0x00001FFF);
574 iqcal_image_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
575 sqsum
= iqcal_image_i
*iqcal_image_i
+ iqcal_image_q
*iqcal_image_q
;
576 mag_1
= (s32
) _sqrt(sqsum
);
577 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
578 mag_1
, iqcal_image_i
, iqcal_image_q
));
580 // e. Calculate the correct DC offset cancellation value for I
583 fix_cancel_dc_i
= (mag_0
*10000) / (mag_0
*10000 - mag_1
*10000);
589 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
595 PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n",
596 fix_cancel_dc_i
, _s32_to_s5(fix_cancel_dc_i
)));
598 if ((abs(mag_1
-mag_0
)*6) > mag_0
)
607 reg_dc_cancel
&= ~(0x03FF);
608 reg_dc_cancel
|= (_s32_to_s5(fix_cancel_dc_i
) << CANCEL_DC_I_SHIFT
);
609 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
610 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
613 reg_mode_ctrl
&= ~MASK_CALIB_START
;
614 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
615 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
618 ///////////////////////////////////////////////////////
619 void _txqdac_dc_offset_cacellation_winbond(struct hw_data
*phw_data
)
629 s32 fix_cancel_dc_q
= 0;
633 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
634 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
635 phy_set_rf_data(phw_data
, 1, (1<<24)|0xEE3FC2);
636 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
637 phy_set_rf_data(phw_data
, 11, (11<<24)|0x1901D6);
638 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
639 phy_set_rf_data(phw_data
, 5, (5<<24)|0x24C48A);
640 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
641 phy_set_rf_data(phw_data
, 6, (6<<24)|0x06890C);
642 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
643 phy_set_rf_data(phw_data
, 0, (0<<24)|0xFDF1C0);
645 hw_set_dxx_reg(phw_data
, 0x58, 0x30303030); // IQ_Alpha Changed
648 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL3
, ®_agc_ctrl3
);
649 reg_agc_ctrl3
&= ~BIT(2);
650 reg_agc_ctrl3
|= (MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
651 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
653 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL5
, &val
);
654 val
|= MASK_AGC_FIX_GAIN
;
655 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL5
, val
);
657 // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0
658 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
659 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl
));
661 //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
662 reg_mode_ctrl
&= ~(MASK_IQCAL_MODE
);
663 reg_mode_ctrl
|= (MASK_CALIB_START
|3);
664 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
665 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
667 hw_get_dxx_reg(phw_data
, 0x5C, ®_dc_cancel
);
668 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel
));
670 for (loop
= 0; loop
< LOOP_TIMES
; loop
++)
672 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop
));
675 // reset cancel_dc_q[4:0] in register DC_Cancel
676 reg_dc_cancel
&= ~(0x001F);
677 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
678 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
680 hw_get_dxx_reg(phw_data
, REG_CALIB_READ2
, &val
);
681 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val
));
683 iqcal_image_i
= _s13_to_s32(val
& 0x00001FFF);
684 iqcal_image_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
685 sqsum
= iqcal_image_i
*iqcal_image_i
+ iqcal_image_q
*iqcal_image_q
;
686 mag_0
= _sqrt(sqsum
);
687 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
688 mag_0
, iqcal_image_i
, iqcal_image_q
));
691 reg_dc_cancel
|= (1 << CANCEL_DC_Q_SHIFT
);
692 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
693 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
695 hw_get_dxx_reg(phw_data
, REG_CALIB_READ2
, &val
);
696 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val
));
698 iqcal_image_i
= _s13_to_s32(val
& 0x00001FFF);
699 iqcal_image_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
700 sqsum
= iqcal_image_i
*iqcal_image_i
+ iqcal_image_q
*iqcal_image_q
;
701 mag_1
= _sqrt(sqsum
);
702 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
703 mag_1
, iqcal_image_i
, iqcal_image_q
));
705 // d. Calculate the correct DC offset cancellation value for I
708 fix_cancel_dc_q
= (mag_0
*10000) / (mag_0
*10000 - mag_1
*10000);
714 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
720 PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
721 fix_cancel_dc_q
, _s32_to_s5(fix_cancel_dc_q
)));
723 if ((abs(mag_1
-mag_0
)*6) > mag_0
)
732 reg_dc_cancel
&= ~(0x001F);
733 reg_dc_cancel
|= (_s32_to_s5(fix_cancel_dc_q
) << CANCEL_DC_Q_SHIFT
);
734 hw_set_dxx_reg(phw_data
, 0x5C, reg_dc_cancel
);
735 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel
));
739 reg_mode_ctrl
&= ~MASK_CALIB_START
;
740 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
741 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
744 //20060612.1.a 20060718.1 Modify
745 u8
_tx_iq_calibration_loop_winbond(struct hw_data
*phw_data
,
768 s32 iqcal_tone_i_avg
,iqcal_tone_q_avg
;
772 PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n"));
773 PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold
));
774 PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold
));
778 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
779 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl
));
785 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES
-loop
+1)));
789 if( !hw_set_dxx_reg(phw_data
, 0x3C, 0x00) ) // 20060718.1 modify
791 for(capture_time
=0;capture_time
<10;capture_time
++)
793 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
794 // enable "IQ alibration Mode II"
795 reg_mode_ctrl
&= ~(MASK_IQCAL_TONE_SEL
|MASK_IQCAL_MODE
);
796 reg_mode_ctrl
&= ~MASK_IQCAL_MODE
;
797 reg_mode_ctrl
|= (MASK_CALIB_START
|0x02);
798 reg_mode_ctrl
|= (MASK_CALIB_START
|0x02|2<<2);
799 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
800 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
803 hw_get_dxx_reg(phw_data
, REG_CALIB_READ1
, &val
);
804 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val
));
806 iqcal_tone_i0
= _s13_to_s32(val
& 0x00001FFF);
807 iqcal_tone_q0
= _s13_to_s32((val
& 0x03FFE000) >> 13);
808 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
809 iqcal_tone_i0
, iqcal_tone_q0
));
811 sqsum
= iqcal_tone_i0
*iqcal_tone_i0
+
812 iqcal_tone_q0
*iqcal_tone_q0
;
813 iq_mag_0_tx
= (s32
) _sqrt(sqsum
);
814 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx
));
816 // c. Set "calib_start" to 0x0
817 reg_mode_ctrl
&= ~MASK_CALIB_START
;
818 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
819 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
821 // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
822 // enable "IQ alibration Mode II"
823 //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
824 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
825 reg_mode_ctrl
&= ~MASK_IQCAL_MODE
;
826 reg_mode_ctrl
|= (MASK_CALIB_START
|0x03);
827 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
828 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
831 hw_get_dxx_reg(phw_data
, REG_CALIB_READ1
, &val
);
832 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val
));
834 iqcal_tone_i
= _s13_to_s32(val
& 0x00001FFF);
835 iqcal_tone_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
836 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
837 iqcal_tone_i
, iqcal_tone_q
));
838 if( capture_time
== 0)
844 iqcal_tone_i_avg
=( iqcal_tone_i_avg
*(capture_time
-1) +iqcal_tone_i
)/capture_time
;
845 iqcal_tone_q_avg
=( iqcal_tone_q_avg
*(capture_time
-1) +iqcal_tone_q
)/capture_time
;
849 iqcal_tone_i
= iqcal_tone_i_avg
;
850 iqcal_tone_q
= iqcal_tone_q_avg
;
853 rot_i_b
= (iqcal_tone_i
* iqcal_tone_i0
+
854 iqcal_tone_q
* iqcal_tone_q0
) / 1024;
855 rot_q_b
= (iqcal_tone_i
* iqcal_tone_q0
* (-1) +
856 iqcal_tone_q
* iqcal_tone_i0
) / 1024;
857 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
861 divisor
= ((iq_mag_0_tx
* iq_mag_0_tx
* 2)/1024 - rot_i_b
) * 2;
865 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
866 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
867 PHY_DEBUG(("[CAL] ******************************************\n"));
871 a_2
= (rot_i_b
* 32768) / divisor
;
872 b_2
= (rot_q_b
* (-32768)) / divisor
;
873 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2
));
874 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2
));
876 phw_data
->iq_rsdl_gain_tx_d2
= a_2
;
877 phw_data
->iq_rsdl_phase_tx_d2
= b_2
;
879 //if ((abs(a_2) < 150) && (abs(b_2) < 100))
880 //if ((abs(a_2) < 200) && (abs(b_2) < 200))
881 if ((abs(a_2
) < a_2_threshold
) && (abs(b_2
) < b_2_threshold
))
885 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
886 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count
));
887 PHY_DEBUG(("[CAL] ******************************************\n"));
889 if (verify_count
> 2)
891 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
892 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
893 PHY_DEBUG(("[CAL] **************************************\n"));
904 _sin_cos(b_2
, &sin_b
, &cos_b
);
905 _sin_cos(b_2
*2, &sin_2b
, &cos_2b
);
906 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b
, cos_b
));
907 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b
, cos_2b
));
911 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
912 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
913 PHY_DEBUG(("[CAL] ******************************************\n"));
917 // 1280 * 32768 = 41943040
918 temp1
= (41943040/cos_2b
)*cos_b
;
920 //temp2 = (41943040/cos_2b)*sin_b*(-1);
921 if (phw_data
->revision
== 0x2002) // 1st-cut
923 temp2
= (41943040/cos_2b
)*sin_b
*(-1);
927 temp2
= (41943040*4/cos_2b
)*sin_b
*(-1);
930 tx_cal_flt_b
[0] = _floor(temp1
/(32768+a_2
));
931 tx_cal_flt_b
[1] = _floor(temp2
/(32768+a_2
));
932 tx_cal_flt_b
[2] = _floor(temp2
/(32768-a_2
));
933 tx_cal_flt_b
[3] = _floor(temp1
/(32768-a_2
));
934 PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b
[0]));
935 PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b
[1]));
936 PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b
[2]));
937 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b
[3]));
939 tx_cal
[2] = tx_cal_flt_b
[2];
940 tx_cal
[2] = tx_cal
[2] +3;
941 tx_cal
[1] = tx_cal
[2];
942 tx_cal
[3] = tx_cal_flt_b
[3] - 128;
943 tx_cal
[0] = -tx_cal
[3]+1;
945 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal
[0]));
946 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal
[1]));
947 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal
[2]));
948 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal
[3]));
950 //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
951 // (tx_cal[2] == 0) && (tx_cal[3] == 0))
953 // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
954 // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
955 // PHY_DEBUG(("[CAL] ******************************************\n"));
960 if (phw_data
->revision
== 0x2002) // 1st-cut
962 hw_get_dxx_reg(phw_data
, 0x54, &val
);
963 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val
));
964 tx_cal_reg
[0] = _s4_to_s32((val
& 0xF0000000) >> 28);
965 tx_cal_reg
[1] = _s4_to_s32((val
& 0x0F000000) >> 24);
966 tx_cal_reg
[2] = _s4_to_s32((val
& 0x00F00000) >> 20);
967 tx_cal_reg
[3] = _s4_to_s32((val
& 0x000F0000) >> 16);
971 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
972 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val
));
973 tx_cal_reg
[0] = _s5_to_s32((val
& 0xF8000000) >> 27);
974 tx_cal_reg
[1] = _s6_to_s32((val
& 0x07E00000) >> 21);
975 tx_cal_reg
[2] = _s6_to_s32((val
& 0x001F8000) >> 15);
976 tx_cal_reg
[3] = _s5_to_s32((val
& 0x00007C00) >> 10);
980 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg
[0]));
981 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg
[1]));
982 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg
[2]));
983 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg
[3]));
985 if (phw_data
->revision
== 0x2002) // 1st-cut
987 if (((tx_cal_reg
[0]==7) || (tx_cal_reg
[0]==(-8))) &&
988 ((tx_cal_reg
[3]==7) || (tx_cal_reg
[3]==(-8))))
990 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
991 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
992 PHY_DEBUG(("[CAL] **************************************\n"));
998 if (((tx_cal_reg
[0]==31) || (tx_cal_reg
[0]==(-32))) &&
999 ((tx_cal_reg
[3]==31) || (tx_cal_reg
[3]==(-32))))
1001 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
1002 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
1003 PHY_DEBUG(("[CAL] **************************************\n"));
1008 tx_cal
[0] = tx_cal
[0] + tx_cal_reg
[0];
1009 tx_cal
[1] = tx_cal
[1] + tx_cal_reg
[1];
1010 tx_cal
[2] = tx_cal
[2] + tx_cal_reg
[2];
1011 tx_cal
[3] = tx_cal
[3] + tx_cal_reg
[3];
1012 PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal
[0]));
1013 PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal
[1]));
1014 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal
[2]));
1015 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal
[3]));
1017 if (phw_data
->revision
== 0x2002) // 1st-cut
1020 val
|= ((_s32_to_s4(tx_cal
[0]) << 28)|
1021 (_s32_to_s4(tx_cal
[1]) << 24)|
1022 (_s32_to_s4(tx_cal
[2]) << 20)|
1023 (_s32_to_s4(tx_cal
[3]) << 16));
1024 hw_set_dxx_reg(phw_data
, 0x54, val
);
1025 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val
));
1031 val
|= ((_s32_to_s5(tx_cal
[0]) << 27)|
1032 (_s32_to_s6(tx_cal
[1]) << 21)|
1033 (_s32_to_s6(tx_cal
[2]) << 15)|
1034 (_s32_to_s5(tx_cal
[3]) << 10));
1035 hw_set_dxx_reg(phw_data
, 0x3C, val
);
1036 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val
));
1040 // i. Set "calib_start" to 0x0
1041 reg_mode_ctrl
&= ~MASK_CALIB_START
;
1042 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
1043 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1051 void _tx_iq_calibration_winbond(struct hw_data
*phw_data
)
1062 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
1064 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
1065 phy_set_rf_data(phw_data
, 1, (1<<24)|0xEE3FC2);
1066 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
1067 phy_set_rf_data(phw_data
, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6);
1068 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
1069 phy_set_rf_data(phw_data
, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature)
1070 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
1071 phy_set_rf_data(phw_data
, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C);
1072 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
1073 phy_set_rf_data(phw_data
, 0, (0<<24)|0xFDF1C0);
1074 //; [BB-chip]: Calibration (6f).Send test pattern
1075 //; [BB-chip]: Calibration (6g). Search RXGCL optimal value
1076 //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table
1077 //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
1079 msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines
1080 //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
1081 adjust_TXVGA_for_iq_mag( phw_data
);
1084 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL3
, ®_agc_ctrl3
);
1085 reg_agc_ctrl3
&= ~BIT(2);
1086 reg_agc_ctrl3
|= (MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
1087 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
1089 hw_get_dxx_reg(phw_data
, REG_AGC_CTRL5
, &val
);
1090 val
|= MASK_AGC_FIX_GAIN
;
1091 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL5
, val
);
1093 result
= _tx_iq_calibration_loop_winbond(phw_data
, 150, 100);
1097 if (phw_data
->revision
== 0x2002) // 1st-cut
1099 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1101 hw_set_dxx_reg(phw_data
, 0x54, val
);
1105 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
1107 hw_set_dxx_reg(phw_data
, 0x3C, val
);
1110 result
= _tx_iq_calibration_loop_winbond(phw_data
, 300, 200);
1114 if (phw_data
->revision
== 0x2002) // 1st-cut
1116 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1118 hw_set_dxx_reg(phw_data
, 0x54, val
);
1122 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
1124 hw_set_dxx_reg(phw_data
, 0x3C, val
);
1127 result
= _tx_iq_calibration_loop_winbond(phw_data
, 500, 400);
1130 if (phw_data
->revision
== 0x2002) // 1st-cut
1132 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1134 hw_set_dxx_reg(phw_data
, 0x54, val
);
1138 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
1140 hw_set_dxx_reg(phw_data
, 0x3C, val
);
1144 result
= _tx_iq_calibration_loop_winbond(phw_data
, 700, 500);
1148 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
1149 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
1150 PHY_DEBUG(("[CAL] **************************************\n"));
1152 if (phw_data
->revision
== 0x2002) // 1st-cut
1154 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1156 hw_set_dxx_reg(phw_data
, 0x54, val
);
1160 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
1162 hw_set_dxx_reg(phw_data
, 0x3C, val
);
1169 // i. Set "calib_start" to 0x0
1170 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
1171 reg_mode_ctrl
&= ~MASK_CALIB_START
;
1172 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
1173 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1176 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
1177 reg_agc_ctrl3
|= BIT(2);
1178 reg_agc_ctrl3
&= ~(MASK_LNA_FIX_GAIN
|MASK_AGC_FIX
);
1179 hw_set_dxx_reg(phw_data
, REG_AGC_CTRL3
, reg_agc_ctrl3
);
1182 if (phw_data
->revision
== 0x2002) // 1st-cut
1184 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1185 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val
));
1186 tx_cal_reg
[0] = _s4_to_s32((val
& 0xF0000000) >> 28);
1187 tx_cal_reg
[1] = _s4_to_s32((val
& 0x0F000000) >> 24);
1188 tx_cal_reg
[2] = _s4_to_s32((val
& 0x00F00000) >> 20);
1189 tx_cal_reg
[3] = _s4_to_s32((val
& 0x000F0000) >> 16);
1193 hw_get_dxx_reg(phw_data
, 0x3C, &val
);
1194 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val
));
1195 tx_cal_reg
[0] = _s5_to_s32((val
& 0xF8000000) >> 27);
1196 tx_cal_reg
[1] = _s6_to_s32((val
& 0x07E00000) >> 21);
1197 tx_cal_reg
[2] = _s6_to_s32((val
& 0x001F8000) >> 15);
1198 tx_cal_reg
[3] = _s5_to_s32((val
& 0x00007C00) >> 10);
1202 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg
[0]));
1203 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg
[1]));
1204 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg
[2]));
1205 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg
[3]));
1210 // RF Control Override
1213 /////////////////////////////////////////////////////////////////////////////////////////
1214 u8
_rx_iq_calibration_loop_winbond(struct hw_data
*phw_data
, u16 factor
, u32 frequency
)
1225 s32 rx_cal_flt_b
[4];
1239 s32 iqcal_tone_i_avg
,iqcal_tone_q_avg
;
1240 s32 iqcal_image_i_avg
,iqcal_image_q_avg
;
1243 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
1244 PHY_DEBUG(("[CAL] ** factor = %d\n", factor
));
1247 // RF Control Override
1248 hw_get_cxx_reg(phw_data
, 0x80, &val
);
1250 hw_set_cxx_reg(phw_data
, 0x80, val
);
1253 hw_get_cxx_reg(phw_data
, 0xE4, &val
);
1255 hw_set_cxx_reg(phw_data
, 0xE4, val
);
1256 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val
));
1258 hw_set_dxx_reg(phw_data
, 0x58, 0x44444444); // IQ_Alpha
1262 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
1263 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl
));
1267 //for (loop = 0; loop < 1; loop++)
1268 //for (loop = 0; loop < LOOP_TIMES; loop++)
1272 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES
-loop
+1)));
1275 iqcal_image_i_avg
=0;
1276 iqcal_image_q_avg
=0;
1279 for(capture_time
=0; capture_time
<10; capture_time
++)
1281 // i. Set "calib_start" to 0x0
1282 reg_mode_ctrl
&= ~MASK_CALIB_START
;
1283 if( !hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
) )//20060718.1 modify
1285 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1287 reg_mode_ctrl
&= ~MASK_IQCAL_MODE
;
1288 reg_mode_ctrl
|= (MASK_CALIB_START
|0x1);
1289 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
1290 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1293 hw_get_dxx_reg(phw_data
, REG_CALIB_READ1
, &val
);
1294 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val
));
1296 iqcal_tone_i
= _s13_to_s32(val
& 0x00001FFF);
1297 iqcal_tone_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
1298 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
1299 iqcal_tone_i
, iqcal_tone_q
));
1301 hw_get_dxx_reg(phw_data
, REG_CALIB_READ2
, &val
);
1302 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val
));
1304 iqcal_image_i
= _s13_to_s32(val
& 0x00001FFF);
1305 iqcal_image_q
= _s13_to_s32((val
& 0x03FFE000) >> 13);
1306 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1307 iqcal_image_i
, iqcal_image_q
));
1308 if( capture_time
== 0)
1314 iqcal_image_i_avg
=( iqcal_image_i_avg
*(capture_time
-1) +iqcal_image_i
)/capture_time
;
1315 iqcal_image_q_avg
=( iqcal_image_q_avg
*(capture_time
-1) +iqcal_image_q
)/capture_time
;
1316 iqcal_tone_i_avg
=( iqcal_tone_i_avg
*(capture_time
-1) +iqcal_tone_i
)/capture_time
;
1317 iqcal_tone_q_avg
=( iqcal_tone_q_avg
*(capture_time
-1) +iqcal_tone_q
)/capture_time
;
1322 iqcal_image_i
= iqcal_image_i_avg
;
1323 iqcal_image_q
= iqcal_image_q_avg
;
1324 iqcal_tone_i
= iqcal_tone_i_avg
;
1325 iqcal_tone_q
= iqcal_tone_q_avg
;
1328 rot_tone_i_b
= (iqcal_tone_i
* iqcal_tone_i
+
1329 iqcal_tone_q
* iqcal_tone_q
) / 1024;
1330 rot_tone_q_b
= (iqcal_tone_i
* iqcal_tone_q
* (-1) +
1331 iqcal_tone_q
* iqcal_tone_i
) / 1024;
1332 rot_image_i_b
= (iqcal_image_i
* iqcal_tone_i
-
1333 iqcal_image_q
* iqcal_tone_q
) / 1024;
1334 rot_image_q_b
= (iqcal_image_i
* iqcal_tone_q
+
1335 iqcal_image_q
* iqcal_tone_i
) / 1024;
1337 PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b
));
1338 PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b
));
1339 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b
));
1340 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b
));
1343 if (rot_tone_i_b
== 0)
1345 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1346 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
1347 PHY_DEBUG(("[CAL] ******************************************\n"));
1351 a_2
= (rot_image_i_b
* 32768) / rot_tone_i_b
-
1352 phw_data
->iq_rsdl_gain_tx_d2
;
1353 b_2
= (rot_image_q_b
* 32768) / rot_tone_i_b
-
1354 phw_data
->iq_rsdl_phase_tx_d2
;
1356 PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data
->iq_rsdl_gain_tx_d2
));
1357 PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data
->iq_rsdl_phase_tx_d2
));
1358 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2
));
1359 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2
));
1361 _sin_cos(b_2
, &sin_b
, &cos_b
);
1362 _sin_cos(b_2
*2, &sin_2b
, &cos_2b
);
1363 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b
, cos_b
));
1364 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b
, cos_2b
));
1368 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1369 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
1370 PHY_DEBUG(("[CAL] ******************************************\n"));
1374 // 1280 * 32768 = 41943040
1375 temp1
= (41943040/cos_2b
)*cos_b
;
1377 //temp2 = (41943040/cos_2b)*sin_b*(-1);
1378 if (phw_data
->revision
== 0x2002) // 1st-cut
1380 temp2
= (41943040/cos_2b
)*sin_b
*(-1);
1384 temp2
= (41943040*4/cos_2b
)*sin_b
*(-1);
1387 rx_cal_flt_b
[0] = _floor(temp1
/(32768+a_2
));
1388 rx_cal_flt_b
[1] = _floor(temp2
/(32768-a_2
));
1389 rx_cal_flt_b
[2] = _floor(temp2
/(32768+a_2
));
1390 rx_cal_flt_b
[3] = _floor(temp1
/(32768-a_2
));
1392 PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b
[0]));
1393 PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b
[1]));
1394 PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b
[2]));
1395 PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b
[3]));
1397 rx_cal
[0] = rx_cal_flt_b
[0] - 128;
1398 rx_cal
[1] = rx_cal_flt_b
[1];
1399 rx_cal
[2] = rx_cal_flt_b
[2];
1400 rx_cal
[3] = rx_cal_flt_b
[3] - 128;
1401 PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal
[0]));
1402 PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal
[1]));
1403 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal
[2]));
1404 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal
[3]));
1407 pwr_tone
= (iqcal_tone_i
*iqcal_tone_i
+ iqcal_tone_q
*iqcal_tone_q
);
1408 pwr_image
= (iqcal_image_i
*iqcal_image_i
+ iqcal_image_q
*iqcal_image_q
)*factor
;
1410 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone
));
1411 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image
));
1413 if (pwr_tone
> pwr_image
)
1417 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
1418 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count
));
1419 PHY_DEBUG(("[CAL] ******************************************\n"));
1421 if (verify_count
> 2)
1423 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1424 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
1425 PHY_DEBUG(("[CAL] **************************************\n"));
1432 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1433 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val
));
1435 if (phw_data
->revision
== 0x2002) // 1st-cut
1437 rx_cal_reg
[0] = _s4_to_s32((val
& 0x0000F000) >> 12);
1438 rx_cal_reg
[1] = _s4_to_s32((val
& 0x00000F00) >> 8);
1439 rx_cal_reg
[2] = _s4_to_s32((val
& 0x000000F0) >> 4);
1440 rx_cal_reg
[3] = _s4_to_s32((val
& 0x0000000F));
1444 rx_cal_reg
[0] = _s5_to_s32((val
& 0xF8000000) >> 27);
1445 rx_cal_reg
[1] = _s6_to_s32((val
& 0x07E00000) >> 21);
1446 rx_cal_reg
[2] = _s6_to_s32((val
& 0x001F8000) >> 15);
1447 rx_cal_reg
[3] = _s5_to_s32((val
& 0x00007C00) >> 10);
1450 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg
[0]));
1451 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg
[1]));
1452 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg
[2]));
1453 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg
[3]));
1455 if (phw_data
->revision
== 0x2002) // 1st-cut
1457 if (((rx_cal_reg
[0]==7) || (rx_cal_reg
[0]==(-8))) &&
1458 ((rx_cal_reg
[3]==7) || (rx_cal_reg
[3]==(-8))))
1460 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1461 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1462 PHY_DEBUG(("[CAL] **************************************\n"));
1468 if (((rx_cal_reg
[0]==31) || (rx_cal_reg
[0]==(-32))) &&
1469 ((rx_cal_reg
[3]==31) || (rx_cal_reg
[3]==(-32))))
1471 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1472 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1473 PHY_DEBUG(("[CAL] **************************************\n"));
1478 rx_cal
[0] = rx_cal
[0] + rx_cal_reg
[0];
1479 rx_cal
[1] = rx_cal
[1] + rx_cal_reg
[1];
1480 rx_cal
[2] = rx_cal
[2] + rx_cal_reg
[2];
1481 rx_cal
[3] = rx_cal
[3] + rx_cal_reg
[3];
1482 PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal
[0]));
1483 PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal
[1]));
1484 PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal
[2]));
1485 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal
[3]));
1487 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1488 if (phw_data
->revision
== 0x2002) // 1st-cut
1491 val
|= ((_s32_to_s4(rx_cal
[0]) << 12)|
1492 (_s32_to_s4(rx_cal
[1]) << 8)|
1493 (_s32_to_s4(rx_cal
[2]) << 4)|
1494 (_s32_to_s4(rx_cal
[3])));
1495 hw_set_dxx_reg(phw_data
, 0x54, val
);
1500 val
|= ((_s32_to_s5(rx_cal
[0]) << 27)|
1501 (_s32_to_s6(rx_cal
[1]) << 21)|
1502 (_s32_to_s6(rx_cal
[2]) << 15)|
1503 (_s32_to_s5(rx_cal
[3]) << 10));
1504 hw_set_dxx_reg(phw_data
, 0x54, val
);
1509 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val
));
1517 //////////////////////////////////////////////////////////
1519 //////////////////////////////////////////////////////////////////////////
1520 void _rx_iq_calibration_winbond(struct hw_data
*phw_data
, u32 frequency
)
1522 // figo 20050523 marked thsi flag for can't compile for relesase
1530 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
1531 // a. Set RFIC to "RX calibration mode"
1532 //; ----- Calibration (7). RX path IQ imbalance calibration loop
1533 // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits
1534 phy_set_rf_data(phw_data
, 1, (1<<24)|0xEFBFC2);
1535 // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit
1536 phy_set_rf_data(phw_data
, 11, (11<<24)|0x1A05D6);
1537 //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized
1538 phy_set_rf_data(phw_data
, 5, (5<<24)| phw_data
->txvga_setting_for_cal
);
1539 //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized
1540 phy_set_rf_data(phw_data
, 6, (6<<24)|0x06834C);
1541 //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode
1542 phy_set_rf_data(phw_data
, 0, (0<<24)|0xFFF1C0);
1544 // ; [BB-chip]: Calibration (7f). Send test pattern
1545 // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value
1546 // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table
1548 result
= _rx_iq_calibration_loop_winbond(phw_data
, 12589, frequency
);
1552 _reset_rx_cal(phw_data
);
1553 result
= _rx_iq_calibration_loop_winbond(phw_data
, 7943, frequency
);
1557 _reset_rx_cal(phw_data
);
1558 result
= _rx_iq_calibration_loop_winbond(phw_data
, 5011, frequency
);
1562 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
1563 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
1564 PHY_DEBUG(("[CAL] **************************************\n"));
1565 _reset_rx_cal(phw_data
);
1571 hw_get_dxx_reg(phw_data
, 0x54, &val
);
1572 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val
));
1574 if (phw_data
->revision
== 0x2002) // 1st-cut
1576 rx_cal_reg
[0] = _s4_to_s32((val
& 0x0000F000) >> 12);
1577 rx_cal_reg
[1] = _s4_to_s32((val
& 0x00000F00) >> 8);
1578 rx_cal_reg
[2] = _s4_to_s32((val
& 0x000000F0) >> 4);
1579 rx_cal_reg
[3] = _s4_to_s32((val
& 0x0000000F));
1583 rx_cal_reg
[0] = _s5_to_s32((val
& 0xF8000000) >> 27);
1584 rx_cal_reg
[1] = _s6_to_s32((val
& 0x07E00000) >> 21);
1585 rx_cal_reg
[2] = _s6_to_s32((val
& 0x001F8000) >> 15);
1586 rx_cal_reg
[3] = _s5_to_s32((val
& 0x00007C00) >> 10);
1589 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg
[0]));
1590 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg
[1]));
1591 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg
[2]));
1592 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg
[3]));
1597 ////////////////////////////////////////////////////////////////////////
1598 void phy_calibration_winbond(struct hw_data
*phw_data
, u32 frequency
)
1603 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
1605 // 20040701 1.1.25.1000 kevin
1606 hw_get_cxx_reg(phw_data
, 0x80, &mac_ctrl
);
1607 hw_get_cxx_reg(phw_data
, 0xE4, &rf_ctrl
);
1608 hw_get_dxx_reg(phw_data
, 0x58, &iq_alpha
);
1612 _rxadc_dc_offset_cancellation_winbond(phw_data
, frequency
);
1613 //_txidac_dc_offset_cancellation_winbond(phw_data);
1614 //_txqdac_dc_offset_cacellation_winbond(phw_data);
1616 _tx_iq_calibration_winbond(phw_data
);
1617 _rx_iq_calibration_winbond(phw_data
, frequency
);
1619 //------------------------------------------------------------------------
1620 hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
);
1621 reg_mode_ctrl
&= ~(MASK_IQCAL_TONE_SEL
|MASK_IQCAL_MODE
|MASK_CALIB_START
); // set when finish
1622 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
1623 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1625 // i. Set RFIC to "Normal mode"
1626 hw_set_cxx_reg(phw_data
, 0x80, mac_ctrl
);
1627 hw_set_cxx_reg(phw_data
, 0xE4, rf_ctrl
);
1628 hw_set_dxx_reg(phw_data
, 0x58, iq_alpha
);
1631 //------------------------------------------------------------------------
1632 phy_init_rf(phw_data
);
1636 //===========================
1637 void phy_set_rf_data( struct hw_data
* pHwData
, u32 index
, u32 value
)
1641 switch( pHwData
->phy_type
)
1644 case RF_MAXIM_V1
: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1645 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value
, 18 );
1649 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value
, 18 );
1653 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value
, 18 );
1657 ltmp
= (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value
, 18 );
1660 case RF_AIROHA_2230
:
1661 case RF_AIROHA_2230S
: // 20060420 Add this
1662 ltmp
= (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value
, 20 );
1665 case RF_AIROHA_7230
:
1666 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | (value
&0xffffff);
1670 case RF_WB_242_1
: // 20060619.5 Add
1671 ltmp
= (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value
, 24 );
1675 Wb35Reg_WriteSync( pHwData
, 0x0864, ltmp
);
1678 // 20060717 modify as Bruce's mail
1679 unsigned char adjust_TXVGA_for_iq_mag(struct hw_data
*phw_data
)
1693 for( init_txvga
=0; init_txvga
<10; init_txvga
++)
1695 current_txvga
= ( 0x24C40A|(init_txvga
<<6) );
1696 phy_set_rf_data(phw_data
, 5, ((5<<24)|current_txvga
) );
1697 phw_data
->txvga_setting_for_cal
= current_txvga
;
1699 msleep(30); // 20060612.1.a
1701 if( !hw_get_dxx_reg(phw_data
, REG_MODE_CTRL
, ®_mode_ctrl
) ) // 20060718.1 modify
1704 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl
));
1706 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
1707 // enable "IQ alibration Mode II"
1708 reg_mode_ctrl
&= ~(MASK_IQCAL_TONE_SEL
|MASK_IQCAL_MODE
);
1709 reg_mode_ctrl
&= ~MASK_IQCAL_MODE
;
1710 reg_mode_ctrl
|= (MASK_CALIB_START
|0x02);
1711 reg_mode_ctrl
|= (MASK_CALIB_START
|0x02|2<<2);
1712 hw_set_dxx_reg(phw_data
, REG_MODE_CTRL
, reg_mode_ctrl
);
1713 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl
));
1715 udelay(1); // 20060612.1.a
1717 udelay(300); // 20060612.1.a
1720 hw_get_dxx_reg(phw_data
, REG_CALIB_READ1
, &val
);
1722 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val
));
1723 udelay(300); // 20060612.1.a
1725 iqcal_tone_i0
= _s13_to_s32(val
& 0x00001FFF);
1726 iqcal_tone_q0
= _s13_to_s32((val
& 0x03FFE000) >> 13);
1727 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
1728 iqcal_tone_i0
, iqcal_tone_q0
));
1730 sqsum
= iqcal_tone_i0
*iqcal_tone_i0
+ iqcal_tone_q0
*iqcal_tone_q0
;
1731 iq_mag_0_tx
= (s32
) _sqrt(sqsum
);
1732 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx
));
1734 if( iq_mag_0_tx
>=700 && iq_mag_0_tx
<=1750 )
1736 else if(iq_mag_0_tx
> 1750)
1746 if( iq_mag_0_tx
>=700 && iq_mag_0_tx
<=1750 )