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Merge remote branch 'nouveau/for-airlied' into drm-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / vme / bridges / vme_tsi148.c
1 /*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mm.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/proc_fs.h>
22 #include <linux/pci.h>
23 #include <linux/poll.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <asm/time.h>
29 #include <asm/io.h>
30 #include <asm/uaccess.h>
31
32 #include "../vme.h"
33 #include "../vme_bridge.h"
34 #include "vme_tsi148.h"
35
36 static int __init tsi148_init(void);
37 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
38 static void tsi148_remove(struct pci_dev *);
39 static void __exit tsi148_exit(void);
40
41
42 int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
43 unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
44 int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
45 unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
46
47 int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
48 unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
49 int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
50 unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
51 ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
52 loff_t);
53 ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
54 loff_t);
55 unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
56 unsigned int, unsigned int, loff_t);
57 int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
58 struct vme_dma_attr *, size_t);
59 int tsi148_dma_list_exec(struct vme_dma_list *);
60 int tsi148_dma_list_empty(struct vme_dma_list *);
61 int tsi148_generate_irq(int, int);
62 int tsi148_slot_get(void);
63
64 /* Modue parameter */
65 int err_chk = 0;
66
67 /* XXX These should all be in a per device structure */
68 struct vme_bridge *tsi148_bridge;
69 wait_queue_head_t dma_queue[2];
70 wait_queue_head_t iack_queue;
71 void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */
72 void *crcsr_kernel;
73 dma_addr_t crcsr_bus;
74 struct vme_master_resource *flush_image;
75 struct mutex vme_rmw; /* Only one RMW cycle at a time */
76 struct mutex vme_int; /*
77 * Only one VME interrupt can be
78 * generated at a time, provide locking
79 */
80
81 static char driver_name[] = "vme_tsi148";
82
83 static struct pci_device_id tsi148_ids[] = {
84 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
85 { },
86 };
87
88 static struct pci_driver tsi148_driver = {
89 .name = driver_name,
90 .id_table = tsi148_ids,
91 .probe = tsi148_probe,
92 .remove = tsi148_remove,
93 };
94
95 static void reg_join(unsigned int high, unsigned int low,
96 unsigned long long *variable)
97 {
98 *variable = (unsigned long long)high << 32;
99 *variable |= (unsigned long long)low;
100 }
101
102 static void reg_split(unsigned long long variable, unsigned int *high,
103 unsigned int *low)
104 {
105 *low = (unsigned int)variable & 0xFFFFFFFF;
106 *high = (unsigned int)(variable >> 32);
107 }
108
109 /*
110 * Wakes up DMA queue.
111 */
112 static u32 tsi148_DMA_irqhandler(int channel_mask)
113 {
114 u32 serviced = 0;
115
116 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
117 wake_up(&dma_queue[0]);
118 serviced |= TSI148_LCSR_INTC_DMA0C;
119 }
120 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
121 wake_up(&dma_queue[1]);
122 serviced |= TSI148_LCSR_INTC_DMA1C;
123 }
124
125 return serviced;
126 }
127
128 /*
129 * Wake up location monitor queue
130 */
131 static u32 tsi148_LM_irqhandler(u32 stat)
132 {
133 int i;
134 u32 serviced = 0;
135
136 for (i = 0; i < 4; i++) {
137 if(stat & TSI148_LCSR_INTS_LMS[i]) {
138 /* We only enable interrupts if the callback is set */
139 lm_callback[i](i);
140 serviced |= TSI148_LCSR_INTC_LMC[i];
141 }
142 }
143
144 return serviced;
145 }
146
147 /*
148 * Wake up mail box queue.
149 *
150 * XXX This functionality is not exposed up though API.
151 */
152 static u32 tsi148_MB_irqhandler(u32 stat)
153 {
154 int i;
155 u32 val;
156 u32 serviced = 0;
157
158 for (i = 0; i < 4; i++) {
159 if(stat & TSI148_LCSR_INTS_MBS[i]) {
160 val = ioread32be(tsi148_bridge->base +
161 TSI148_GCSR_MBOX[i]);
162 printk("VME Mailbox %d received: 0x%x\n", i, val);
163 serviced |= TSI148_LCSR_INTC_MBC[i];
164 }
165 }
166
167 return serviced;
168 }
169
170 /*
171 * Display error & status message when PERR (PCI) exception interrupt occurs.
172 */
173 static u32 tsi148_PERR_irqhandler(void)
174 {
175 printk(KERN_ERR
176 "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
177 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU),
178 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL),
179 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT)
180 );
181 printk(KERN_ERR
182 "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
183 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA),
184 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS)
185 );
186
187 iowrite32be(TSI148_LCSR_EDPAT_EDPCL,
188 tsi148_bridge->base + TSI148_LCSR_EDPAT);
189
190 return TSI148_LCSR_INTC_PERRC;
191 }
192
193 /*
194 * Save address and status when VME error interrupt occurs.
195 */
196 static u32 tsi148_VERR_irqhandler(void)
197 {
198 unsigned int error_addr_high, error_addr_low;
199 unsigned long long error_addr;
200 u32 error_attrib;
201 struct vme_bus_error *error;
202
203 error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU);
204 error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL);
205 error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT);
206
207 reg_join(error_addr_high, error_addr_low, &error_addr);
208
209 /* Check for exception register overflow (we have lost error data) */
210 if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
211 printk(KERN_ERR "VME Bus Exception Overflow Occurred\n");
212 }
213
214 error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
215 GFP_ATOMIC);
216 if (error) {
217 error->address = error_addr;
218 error->attributes = error_attrib;
219 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
220 } else {
221 printk(KERN_ERR
222 "Unable to alloc memory for VMEbus Error reporting\n");
223 printk(KERN_ERR
224 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
225 error_addr, error_attrib);
226 }
227
228 /* Clear Status */
229 iowrite32be(TSI148_LCSR_VEAT_VESCL,
230 tsi148_bridge->base + TSI148_LCSR_VEAT);
231
232 return TSI148_LCSR_INTC_VERRC;
233 }
234
235 /*
236 * Wake up IACK queue.
237 */
238 static u32 tsi148_IACK_irqhandler(void)
239 {
240 wake_up(&iack_queue);
241
242 return TSI148_LCSR_INTC_IACKC;
243 }
244
245 /*
246 * Calling VME bus interrupt callback if provided.
247 */
248 static u32 tsi148_VIRQ_irqhandler(u32 stat)
249 {
250 int vec, i, serviced = 0;
251
252 for (i = 7; i > 0; i--) {
253 if (stat & (1 << i)) {
254 /*
255 * Note: Even though the registers are defined
256 * as 32-bits in the spec, we only want to issue
257 * 8-bit IACK cycles on the bus, read from offset
258 * 3.
259 */
260 vec = ioread8(tsi148_bridge->base +
261 TSI148_LCSR_VIACK[i] + 3);
262
263 vme_irq_handler(tsi148_bridge, i, vec);
264
265 serviced |= (1 << i);
266 }
267 }
268
269 return serviced;
270 }
271
272 /*
273 * Top level interrupt handler. Clears appropriate interrupt status bits and
274 * then calls appropriate sub handler(s).
275 */
276 static irqreturn_t tsi148_irqhandler(int irq, void *dev_id)
277 {
278 u32 stat, enable, serviced = 0;
279
280 /* Determine which interrupts are unmasked and set */
281 enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
282 stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS);
283
284 /* Only look at unmasked interrupts */
285 stat &= enable;
286
287 if (unlikely(!stat)) {
288 return IRQ_NONE;
289 }
290
291 /* Call subhandlers as appropriate */
292 /* DMA irqs */
293 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
294 serviced |= tsi148_DMA_irqhandler(stat);
295
296 /* Location monitor irqs */
297 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
298 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
299 serviced |= tsi148_LM_irqhandler(stat);
300
301 /* Mail box irqs */
302 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
303 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
304 serviced |= tsi148_MB_irqhandler(stat);
305
306 /* PCI bus error */
307 if (stat & TSI148_LCSR_INTS_PERRS)
308 serviced |= tsi148_PERR_irqhandler();
309
310 /* VME bus error */
311 if (stat & TSI148_LCSR_INTS_VERRS)
312 serviced |= tsi148_VERR_irqhandler();
313
314 /* IACK irq */
315 if (stat & TSI148_LCSR_INTS_IACKS)
316 serviced |= tsi148_IACK_irqhandler();
317
318 /* VME bus irqs */
319 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
320 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
321 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
322 TSI148_LCSR_INTS_IRQ1S))
323 serviced |= tsi148_VIRQ_irqhandler(stat);
324
325 /* Clear serviced interrupts */
326 iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC);
327
328 return IRQ_HANDLED;
329 }
330
331 static int tsi148_irq_init(struct vme_bridge *bridge)
332 {
333 int result;
334 unsigned int tmp;
335 struct pci_dev *pdev;
336
337 /* Need pdev */
338 pdev = container_of(bridge->parent, struct pci_dev, dev);
339
340 /* Initialise list for VME bus errors */
341 INIT_LIST_HEAD(&(bridge->vme_errors));
342
343 mutex_init(&(bridge->irq_mtx));
344
345 result = request_irq(pdev->irq,
346 tsi148_irqhandler,
347 IRQF_SHARED,
348 driver_name, pdev);
349 if (result) {
350 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
351 pdev->irq);
352 return result;
353 }
354
355 /* Enable and unmask interrupts */
356 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
357 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
358 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
359 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
360 TSI148_LCSR_INTEO_IACKEO;
361
362 /* XXX This leaves the following interrupts masked.
363 * TSI148_LCSR_INTEO_VIEEO
364 * TSI148_LCSR_INTEO_SYSFLEO
365 * TSI148_LCSR_INTEO_ACFLEO
366 */
367
368 /* Don't enable Location Monitor interrupts here - they will be
369 * enabled when the location monitors are properly configured and
370 * a callback has been attached.
371 * TSI148_LCSR_INTEO_LM0EO
372 * TSI148_LCSR_INTEO_LM1EO
373 * TSI148_LCSR_INTEO_LM2EO
374 * TSI148_LCSR_INTEO_LM3EO
375 */
376
377 /* Don't enable VME interrupts until we add a handler, else the board
378 * will respond to it and we don't want that unless it knows how to
379 * properly deal with it.
380 * TSI148_LCSR_INTEO_IRQ7EO
381 * TSI148_LCSR_INTEO_IRQ6EO
382 * TSI148_LCSR_INTEO_IRQ5EO
383 * TSI148_LCSR_INTEO_IRQ4EO
384 * TSI148_LCSR_INTEO_IRQ3EO
385 * TSI148_LCSR_INTEO_IRQ2EO
386 * TSI148_LCSR_INTEO_IRQ1EO
387 */
388
389 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
390 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
391
392 return 0;
393 }
394
395 static void tsi148_irq_exit(struct pci_dev *pdev)
396 {
397 /* Turn off interrupts */
398 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
399 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN);
400
401 /* Clear all interrupts */
402 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
403
404 /* Detach interrupt handler */
405 free_irq(pdev->irq, pdev);
406 }
407
408 /*
409 * Check to see if an IACk has been received, return true (1) or false (0).
410 */
411 int tsi148_iack_received(void)
412 {
413 u32 tmp;
414
415 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
416
417 if (tmp & TSI148_LCSR_VICR_IRQS)
418 return 0;
419 else
420 return 1;
421 }
422
423 /*
424 * Configure VME interrupt
425 */
426 void tsi148_irq_set(int level, int state, int sync)
427 {
428 struct pci_dev *pdev;
429 u32 tmp;
430
431 /* We need to do the ordering differently for enabling and disabling */
432 if (state == 0) {
433 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
434 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
435 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
436
437 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
438 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
439 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
440
441 if (sync != 0) {
442 pdev = container_of(tsi148_bridge->parent,
443 struct pci_dev, dev);
444
445 synchronize_irq(pdev->irq);
446 }
447 } else {
448 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
449 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
450 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
451
452 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
453 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
454 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
455 }
456 }
457
458 /*
459 * Generate a VME bus interrupt at the requested level & vector. Wait for
460 * interrupt to be acked.
461 */
462 int tsi148_irq_generate(int level, int statid)
463 {
464 u32 tmp;
465
466 mutex_lock(&(vme_int));
467
468 /* Read VICR register */
469 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
470
471 /* Set Status/ID */
472 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
473 (statid & TSI148_LCSR_VICR_STID_M);
474 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
475
476 /* Assert VMEbus IRQ */
477 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
478 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
479
480 /* XXX Consider implementing a timeout? */
481 wait_event_interruptible(iack_queue, tsi148_iack_received());
482
483 mutex_unlock(&(vme_int));
484
485 return 0;
486 }
487
488 /*
489 * Find the first error in this address range
490 */
491 static struct vme_bus_error *tsi148_find_error(vme_address_t aspace,
492 unsigned long long address, size_t count)
493 {
494 struct list_head *err_pos;
495 struct vme_bus_error *vme_err, *valid = NULL;
496 unsigned long long bound;
497
498 bound = address + count;
499
500 /*
501 * XXX We are currently not looking at the address space when parsing
502 * for errors. This is because parsing the Address Modifier Codes
503 * is going to be quite resource intensive to do properly. We
504 * should be OK just looking at the addresses and this is certainly
505 * much better than what we had before.
506 */
507 err_pos = NULL;
508 /* Iterate through errors */
509 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
510 vme_err = list_entry(err_pos, struct vme_bus_error, list);
511 if((vme_err->address >= address) && (vme_err->address < bound)){
512 valid = vme_err;
513 break;
514 }
515 }
516
517 return valid;
518 }
519
520 /*
521 * Clear errors in the provided address range.
522 */
523 static void tsi148_clear_errors(vme_address_t aspace,
524 unsigned long long address, size_t count)
525 {
526 struct list_head *err_pos, *temp;
527 struct vme_bus_error *vme_err;
528 unsigned long long bound;
529
530 bound = address + count;
531
532 /*
533 * XXX We are currently not looking at the address space when parsing
534 * for errors. This is because parsing the Address Modifier Codes
535 * is going to be quite resource intensive to do properly. We
536 * should be OK just looking at the addresses and this is certainly
537 * much better than what we had before.
538 */
539 err_pos = NULL;
540 /* Iterate through errors */
541 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
542 vme_err = list_entry(err_pos, struct vme_bus_error, list);
543
544 if((vme_err->address >= address) && (vme_err->address < bound)){
545 list_del(err_pos);
546 kfree(vme_err);
547 }
548 }
549 }
550
551 /*
552 * Initialize a slave window with the requested attributes.
553 */
554 int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
555 unsigned long long vme_base, unsigned long long size,
556 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
557 {
558 unsigned int i, addr = 0, granularity = 0;
559 unsigned int temp_ctl = 0;
560 unsigned int vme_base_low, vme_base_high;
561 unsigned int vme_bound_low, vme_bound_high;
562 unsigned int pci_offset_low, pci_offset_high;
563 unsigned long long vme_bound, pci_offset;
564
565 #if 0
566 printk("Set slave image %d to:\n", image->number);
567 printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no");
568 printk("\tVME Base:0x%llx\n", vme_base);
569 printk("\tWindow Size:0x%llx\n", size);
570 printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base);
571 printk("\tAddress Space:0x%x\n", aspace);
572 printk("\tTransfer Cycle Properties:0x%x\n", cycle);
573 #endif
574
575 i = image->number;
576
577 switch (aspace) {
578 case VME_A16:
579 granularity = 0x10;
580 addr |= TSI148_LCSR_ITAT_AS_A16;
581 break;
582 case VME_A24:
583 granularity = 0x1000;
584 addr |= TSI148_LCSR_ITAT_AS_A24;
585 break;
586 case VME_A32:
587 granularity = 0x10000;
588 addr |= TSI148_LCSR_ITAT_AS_A32;
589 break;
590 case VME_A64:
591 granularity = 0x10000;
592 addr |= TSI148_LCSR_ITAT_AS_A64;
593 break;
594 case VME_CRCSR:
595 case VME_USER1:
596 case VME_USER2:
597 case VME_USER3:
598 case VME_USER4:
599 default:
600 printk("Invalid address space\n");
601 return -EINVAL;
602 break;
603 }
604
605 /* Convert 64-bit variables to 2x 32-bit variables */
606 reg_split(vme_base, &vme_base_high, &vme_base_low);
607
608 /*
609 * Bound address is a valid address for the window, adjust
610 * accordingly
611 */
612 vme_bound = vme_base + size - granularity;
613 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
614 pci_offset = (unsigned long long)pci_base - vme_base;
615 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
616
617 if (vme_base_low & (granularity - 1)) {
618 printk("Invalid VME base alignment\n");
619 return -EINVAL;
620 }
621 if (vme_bound_low & (granularity - 1)) {
622 printk("Invalid VME bound alignment\n");
623 return -EINVAL;
624 }
625 if (pci_offset_low & (granularity - 1)) {
626 printk("Invalid PCI Offset alignment\n");
627 return -EINVAL;
628 }
629
630 #if 0
631 printk("\tVME Bound:0x%llx\n", vme_bound);
632 printk("\tPCI Offset:0x%llx\n", pci_offset);
633 #endif
634
635 /* Disable while we are mucking around */
636 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
637 TSI148_LCSR_OFFSET_ITAT);
638 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
639 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
640 TSI148_LCSR_OFFSET_ITAT);
641
642 /* Setup mapping */
643 iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
644 TSI148_LCSR_OFFSET_ITSAU);
645 iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
646 TSI148_LCSR_OFFSET_ITSAL);
647 iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
648 TSI148_LCSR_OFFSET_ITEAU);
649 iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
650 TSI148_LCSR_OFFSET_ITEAL);
651 iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
652 TSI148_LCSR_OFFSET_ITOFU);
653 iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
654 TSI148_LCSR_OFFSET_ITOFL);
655
656 /* XXX Prefetch stuff currently unsupported */
657 #if 0
658
659 for (x = 0; x < 4; x++) {
660 if ((64 << x) >= vmeIn->prefetchSize) {
661 break;
662 }
663 }
664 if (x == 4)
665 x--;
666 temp_ctl |= (x << 16);
667
668 if (vmeIn->prefetchThreshold)
669 if (vmeIn->prefetchThreshold)
670 temp_ctl |= 0x40000;
671 #endif
672
673 /* Setup 2eSST speeds */
674 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
675 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
676 case VME_2eSST160:
677 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
678 break;
679 case VME_2eSST267:
680 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
681 break;
682 case VME_2eSST320:
683 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
684 break;
685 }
686
687 /* Setup cycle types */
688 temp_ctl &= ~(0x1F << 7);
689 if (cycle & VME_BLT)
690 temp_ctl |= TSI148_LCSR_ITAT_BLT;
691 if (cycle & VME_MBLT)
692 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
693 if (cycle & VME_2eVME)
694 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
695 if (cycle & VME_2eSST)
696 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
697 if (cycle & VME_2eSSTB)
698 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
699
700 /* Setup address space */
701 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
702 temp_ctl |= addr;
703
704 temp_ctl &= ~0xF;
705 if (cycle & VME_SUPER)
706 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
707 if (cycle & VME_USER)
708 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
709 if (cycle & VME_PROG)
710 temp_ctl |= TSI148_LCSR_ITAT_PGM;
711 if (cycle & VME_DATA)
712 temp_ctl |= TSI148_LCSR_ITAT_DATA;
713
714 /* Write ctl reg without enable */
715 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
716 TSI148_LCSR_OFFSET_ITAT);
717
718 if (enabled)
719 temp_ctl |= TSI148_LCSR_ITAT_EN;
720
721 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
722 TSI148_LCSR_OFFSET_ITAT);
723
724 return 0;
725 }
726
727 /*
728 * Get slave window configuration.
729 *
730 * XXX Prefetch currently unsupported.
731 */
732 int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
733 unsigned long long *vme_base, unsigned long long *size,
734 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
735 {
736 unsigned int i, granularity = 0, ctl = 0;
737 unsigned int vme_base_low, vme_base_high;
738 unsigned int vme_bound_low, vme_bound_high;
739 unsigned int pci_offset_low, pci_offset_high;
740 unsigned long long vme_bound, pci_offset;
741
742
743 i = image->number;
744
745 /* Read registers */
746 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
747 TSI148_LCSR_OFFSET_ITAT);
748
749 vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
750 TSI148_LCSR_OFFSET_ITSAU);
751 vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
752 TSI148_LCSR_OFFSET_ITSAL);
753 vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
754 TSI148_LCSR_OFFSET_ITEAU);
755 vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
756 TSI148_LCSR_OFFSET_ITEAL);
757 pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
758 TSI148_LCSR_OFFSET_ITOFU);
759 pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
760 TSI148_LCSR_OFFSET_ITOFL);
761
762 /* Convert 64-bit variables to 2x 32-bit variables */
763 reg_join(vme_base_high, vme_base_low, vme_base);
764 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
765 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
766
767 *pci_base = (dma_addr_t)vme_base + pci_offset;
768
769 *enabled = 0;
770 *aspace = 0;
771 *cycle = 0;
772
773 if (ctl & TSI148_LCSR_ITAT_EN)
774 *enabled = 1;
775
776 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
777 granularity = 0x10;
778 *aspace |= VME_A16;
779 }
780 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
781 granularity = 0x1000;
782 *aspace |= VME_A24;
783 }
784 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
785 granularity = 0x10000;
786 *aspace |= VME_A32;
787 }
788 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
789 granularity = 0x10000;
790 *aspace |= VME_A64;
791 }
792
793 /* Need granularity before we set the size */
794 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
795
796
797 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
798 *cycle |= VME_2eSST160;
799 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
800 *cycle |= VME_2eSST267;
801 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
802 *cycle |= VME_2eSST320;
803
804 if (ctl & TSI148_LCSR_ITAT_BLT)
805 *cycle |= VME_BLT;
806 if (ctl & TSI148_LCSR_ITAT_MBLT)
807 *cycle |= VME_MBLT;
808 if (ctl & TSI148_LCSR_ITAT_2eVME)
809 *cycle |= VME_2eVME;
810 if (ctl & TSI148_LCSR_ITAT_2eSST)
811 *cycle |= VME_2eSST;
812 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
813 *cycle |= VME_2eSSTB;
814
815 if (ctl & TSI148_LCSR_ITAT_SUPR)
816 *cycle |= VME_SUPER;
817 if (ctl & TSI148_LCSR_ITAT_NPRIV)
818 *cycle |= VME_USER;
819 if (ctl & TSI148_LCSR_ITAT_PGM)
820 *cycle |= VME_PROG;
821 if (ctl & TSI148_LCSR_ITAT_DATA)
822 *cycle |= VME_DATA;
823
824 return 0;
825 }
826
827 /*
828 * Allocate and map PCI Resource
829 */
830 static int tsi148_alloc_resource(struct vme_master_resource *image,
831 unsigned long long size)
832 {
833 unsigned long long existing_size;
834 int retval = 0;
835 struct pci_dev *pdev;
836
837 /* Find pci_dev container of dev */
838 if (tsi148_bridge->parent == NULL) {
839 printk("Dev entry NULL\n");
840 return -EINVAL;
841 }
842 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
843
844 existing_size = (unsigned long long)(image->pci_resource.end -
845 image->pci_resource.start);
846
847 /* If the existing size is OK, return */
848 if ((size != 0) && (existing_size == (size - 1)))
849 return 0;
850
851 if (existing_size != 0) {
852 iounmap(image->kern_base);
853 image->kern_base = NULL;
854 if (image->pci_resource.name != NULL)
855 kfree(image->pci_resource.name);
856 release_resource(&(image->pci_resource));
857 memset(&(image->pci_resource), 0, sizeof(struct resource));
858 }
859
860 /* Exit here if size is zero */
861 if (size == 0) {
862 return 0;
863 }
864
865 if (image->pci_resource.name == NULL) {
866 image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
867 if (image->pci_resource.name == NULL) {
868 printk(KERN_ERR "Unable to allocate memory for resource"
869 " name\n");
870 retval = -ENOMEM;
871 goto err_name;
872 }
873 }
874
875 sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name,
876 image->number);
877
878 image->pci_resource.start = 0;
879 image->pci_resource.end = (unsigned long)size;
880 image->pci_resource.flags = IORESOURCE_MEM;
881
882 retval = pci_bus_alloc_resource(pdev->bus,
883 &(image->pci_resource), size, size, PCIBIOS_MIN_MEM,
884 0, NULL, NULL);
885 if (retval) {
886 printk(KERN_ERR "Failed to allocate mem resource for "
887 "window %d size 0x%lx start 0x%lx\n",
888 image->number, (unsigned long)size,
889 (unsigned long)image->pci_resource.start);
890 goto err_resource;
891 }
892
893 image->kern_base = ioremap_nocache(
894 image->pci_resource.start, size);
895 if (image->kern_base == NULL) {
896 printk(KERN_ERR "Failed to remap resource\n");
897 retval = -ENOMEM;
898 goto err_remap;
899 }
900
901 return 0;
902
903 iounmap(image->kern_base);
904 image->kern_base = NULL;
905 err_remap:
906 release_resource(&(image->pci_resource));
907 err_resource:
908 kfree(image->pci_resource.name);
909 memset(&(image->pci_resource), 0, sizeof(struct resource));
910 err_name:
911 return retval;
912 }
913
914 /*
915 * Free and unmap PCI Resource
916 */
917 static void tsi148_free_resource(struct vme_master_resource *image)
918 {
919 iounmap(image->kern_base);
920 image->kern_base = NULL;
921 release_resource(&(image->pci_resource));
922 kfree(image->pci_resource.name);
923 memset(&(image->pci_resource), 0, sizeof(struct resource));
924 }
925
926 /*
927 * Set the attributes of an outbound window.
928 */
929 int tsi148_master_set( struct vme_master_resource *image, int enabled,
930 unsigned long long vme_base, unsigned long long size,
931 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
932 {
933 int retval = 0;
934 unsigned int i;
935 unsigned int temp_ctl = 0;
936 unsigned int pci_base_low, pci_base_high;
937 unsigned int pci_bound_low, pci_bound_high;
938 unsigned int vme_offset_low, vme_offset_high;
939 unsigned long long pci_bound, vme_offset, pci_base;
940
941 /* Verify input data */
942 if (vme_base & 0xFFFF) {
943 printk(KERN_ERR "Invalid VME Window alignment\n");
944 retval = -EINVAL;
945 goto err_window;
946 }
947
948 if ((size == 0) && (enabled != 0)) {
949 printk(KERN_ERR "Size must be non-zero for enabled windows\n");
950 retval = -EINVAL;
951 goto err_window;
952 }
953
954 spin_lock(&(image->lock));
955
956 /* Let's allocate the resource here rather than further up the stack as
957 * it avoids pushing loads of bus dependant stuff up the stack. If size
958 * is zero, any existing resource will be freed.
959 */
960 retval = tsi148_alloc_resource(image, size);
961 if (retval) {
962 spin_unlock(&(image->lock));
963 printk(KERN_ERR "Unable to allocate memory for "
964 "resource\n");
965 goto err_res;
966 }
967
968 if (size == 0) {
969 pci_base = 0;
970 pci_bound = 0;
971 vme_offset = 0;
972 } else {
973 pci_base = (unsigned long long)image->pci_resource.start;
974
975 /*
976 * Bound address is a valid address for the window, adjust
977 * according to window granularity.
978 */
979 pci_bound = pci_base + (size - 0x10000);
980 vme_offset = vme_base - pci_base;
981 }
982
983 /* Convert 64-bit variables to 2x 32-bit variables */
984 reg_split(pci_base, &pci_base_high, &pci_base_low);
985 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
986 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
987
988 if (pci_base_low & 0xFFFF) {
989 spin_unlock(&(image->lock));
990 printk(KERN_ERR "Invalid PCI base alignment\n");
991 retval = -EINVAL;
992 goto err_gran;
993 }
994 if (pci_bound_low & 0xFFFF) {
995 spin_unlock(&(image->lock));
996 printk(KERN_ERR "Invalid PCI bound alignment\n");
997 retval = -EINVAL;
998 goto err_gran;
999 }
1000 if (vme_offset_low & 0xFFFF) {
1001 spin_unlock(&(image->lock));
1002 printk(KERN_ERR "Invalid VME Offset alignment\n");
1003 retval = -EINVAL;
1004 goto err_gran;
1005 }
1006
1007 i = image->number;
1008
1009 /* Disable while we are mucking around */
1010 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1011 TSI148_LCSR_OFFSET_OTAT);
1012 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
1013 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1014 TSI148_LCSR_OFFSET_OTAT);
1015
1016 /* XXX Prefetch stuff currently unsupported */
1017 #if 0
1018 if (vmeOut->prefetchEnable) {
1019 temp_ctl |= 0x40000;
1020 for (x = 0; x < 4; x++) {
1021 if ((2 << x) >= vmeOut->prefetchSize)
1022 break;
1023 }
1024 if (x == 4)
1025 x = 3;
1026 temp_ctl |= (x << 16);
1027 }
1028 #endif
1029
1030 /* Setup 2eSST speeds */
1031 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
1032 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1033 case VME_2eSST160:
1034 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1035 break;
1036 case VME_2eSST267:
1037 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1038 break;
1039 case VME_2eSST320:
1040 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1041 break;
1042 }
1043
1044 /* Setup cycle types */
1045 if (cycle & VME_BLT) {
1046 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1047 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1048 }
1049 if (cycle & VME_MBLT) {
1050 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1051 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1052 }
1053 if (cycle & VME_2eVME) {
1054 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1055 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1056 }
1057 if (cycle & VME_2eSST) {
1058 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1059 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1060 }
1061 if (cycle & VME_2eSSTB) {
1062 printk(KERN_WARNING "Currently not setting Broadcast Select "
1063 "Registers\n");
1064 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1065 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1066 }
1067
1068 /* Setup data width */
1069 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1070 switch (dwidth) {
1071 case VME_D16:
1072 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1073 break;
1074 case VME_D32:
1075 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1076 break;
1077 default:
1078 spin_unlock(&(image->lock));
1079 printk(KERN_ERR "Invalid data width\n");
1080 retval = -EINVAL;
1081 goto err_dwidth;
1082 }
1083
1084 /* Setup address space */
1085 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1086 switch (aspace) {
1087 case VME_A16:
1088 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1089 break;
1090 case VME_A24:
1091 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1092 break;
1093 case VME_A32:
1094 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1095 break;
1096 case VME_A64:
1097 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1098 break;
1099 case VME_CRCSR:
1100 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1101 break;
1102 case VME_USER1:
1103 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1104 break;
1105 case VME_USER2:
1106 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1107 break;
1108 case VME_USER3:
1109 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1110 break;
1111 case VME_USER4:
1112 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1113 break;
1114 default:
1115 spin_unlock(&(image->lock));
1116 printk(KERN_ERR "Invalid address space\n");
1117 retval = -EINVAL;
1118 goto err_aspace;
1119 break;
1120 }
1121
1122 temp_ctl &= ~(3<<4);
1123 if (cycle & VME_SUPER)
1124 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1125 if (cycle & VME_PROG)
1126 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1127
1128 /* Setup mapping */
1129 iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1130 TSI148_LCSR_OFFSET_OTSAU);
1131 iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1132 TSI148_LCSR_OFFSET_OTSAL);
1133 iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1134 TSI148_LCSR_OFFSET_OTEAU);
1135 iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1136 TSI148_LCSR_OFFSET_OTEAL);
1137 iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1138 TSI148_LCSR_OFFSET_OTOFU);
1139 iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1140 TSI148_LCSR_OFFSET_OTOFL);
1141
1142 /* XXX We need to deal with OTBS */
1143 #if 0
1144 iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base +
1145 TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS);
1146 #endif
1147
1148 /* Write ctl reg without enable */
1149 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1150 TSI148_LCSR_OFFSET_OTAT);
1151
1152 if (enabled)
1153 temp_ctl |= TSI148_LCSR_OTAT_EN;
1154
1155 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1156 TSI148_LCSR_OFFSET_OTAT);
1157
1158 spin_unlock(&(image->lock));
1159 return 0;
1160
1161 err_aspace:
1162 err_dwidth:
1163 err_gran:
1164 tsi148_free_resource(image);
1165 err_res:
1166 err_window:
1167 return retval;
1168
1169 }
1170
1171 /*
1172 * Set the attributes of an outbound window.
1173 *
1174 * XXX Not parsing prefetch information.
1175 */
1176 int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
1177 unsigned long long *vme_base, unsigned long long *size,
1178 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1179 {
1180 unsigned int i, ctl;
1181 unsigned int pci_base_low, pci_base_high;
1182 unsigned int pci_bound_low, pci_bound_high;
1183 unsigned int vme_offset_low, vme_offset_high;
1184
1185 unsigned long long pci_base, pci_bound, vme_offset;
1186
1187 i = image->number;
1188
1189 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1190 TSI148_LCSR_OFFSET_OTAT);
1191
1192 pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1193 TSI148_LCSR_OFFSET_OTSAU);
1194 pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1195 TSI148_LCSR_OFFSET_OTSAL);
1196 pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1197 TSI148_LCSR_OFFSET_OTEAU);
1198 pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1199 TSI148_LCSR_OFFSET_OTEAL);
1200 vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1201 TSI148_LCSR_OFFSET_OTOFU);
1202 vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1203 TSI148_LCSR_OFFSET_OTOFL);
1204
1205 /* Convert 64-bit variables to 2x 32-bit variables */
1206 reg_join(pci_base_high, pci_base_low, &pci_base);
1207 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1208 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1209
1210 *vme_base = pci_base + vme_offset;
1211 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1212
1213 *enabled = 0;
1214 *aspace = 0;
1215 *cycle = 0;
1216 *dwidth = 0;
1217
1218 if (ctl & TSI148_LCSR_OTAT_EN)
1219 *enabled = 1;
1220
1221 /* Setup address space */
1222 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1223 *aspace |= VME_A16;
1224 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1225 *aspace |= VME_A24;
1226 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1227 *aspace |= VME_A32;
1228 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1229 *aspace |= VME_A64;
1230 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1231 *aspace |= VME_CRCSR;
1232 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1233 *aspace |= VME_USER1;
1234 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1235 *aspace |= VME_USER2;
1236 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1237 *aspace |= VME_USER3;
1238 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1239 *aspace |= VME_USER4;
1240
1241 /* Setup 2eSST speeds */
1242 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1243 *cycle |= VME_2eSST160;
1244 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1245 *cycle |= VME_2eSST267;
1246 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1247 *cycle |= VME_2eSST320;
1248
1249 /* Setup cycle types */
1250 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
1251 *cycle |= VME_SCT;
1252 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
1253 *cycle |= VME_BLT;
1254 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
1255 *cycle |= VME_MBLT;
1256 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
1257 *cycle |= VME_2eVME;
1258 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
1259 *cycle |= VME_2eSST;
1260 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
1261 *cycle |= VME_2eSSTB;
1262
1263 if (ctl & TSI148_LCSR_OTAT_SUP)
1264 *cycle |= VME_SUPER;
1265 else
1266 *cycle |= VME_USER;
1267
1268 if (ctl & TSI148_LCSR_OTAT_PGM)
1269 *cycle |= VME_PROG;
1270 else
1271 *cycle |= VME_DATA;
1272
1273 /* Setup data width */
1274 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1275 *dwidth = VME_D16;
1276 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1277 *dwidth = VME_D32;
1278
1279 return 0;
1280 }
1281
1282
1283 int tsi148_master_get( struct vme_master_resource *image, int *enabled,
1284 unsigned long long *vme_base, unsigned long long *size,
1285 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1286 {
1287 int retval;
1288
1289 spin_lock(&(image->lock));
1290
1291 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1292 cycle, dwidth);
1293
1294 spin_unlock(&(image->lock));
1295
1296 return retval;
1297 }
1298
1299 ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1300 size_t count, loff_t offset)
1301 {
1302 int retval, enabled;
1303 unsigned long long vme_base, size;
1304 vme_address_t aspace;
1305 vme_cycle_t cycle;
1306 vme_width_t dwidth;
1307 struct vme_bus_error *vme_err = NULL;
1308
1309 spin_lock(&(image->lock));
1310
1311 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1312 retval = count;
1313
1314 if (!err_chk)
1315 goto skip_chk;
1316
1317 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1318 &dwidth);
1319
1320 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1321 if(vme_err != NULL) {
1322 dev_err(image->parent->parent, "First VME read error detected "
1323 "an at address 0x%llx\n", vme_err->address);
1324 retval = vme_err->address - (vme_base + offset);
1325 /* Clear down save errors in this address range */
1326 tsi148_clear_errors(aspace, vme_base + offset, count);
1327 }
1328
1329 skip_chk:
1330 spin_unlock(&(image->lock));
1331
1332 return retval;
1333 }
1334
1335
1336 /* XXX We need to change vme_master_resource->mtx to a spinlock so that read
1337 * and write functions can be used in an interrupt context
1338 */
1339 ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1340 size_t count, loff_t offset)
1341 {
1342 int retval = 0, enabled;
1343 unsigned long long vme_base, size;
1344 vme_address_t aspace;
1345 vme_cycle_t cycle;
1346 vme_width_t dwidth;
1347
1348 struct vme_bus_error *vme_err = NULL;
1349
1350 spin_lock(&(image->lock));
1351
1352 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1353 retval = count;
1354
1355 /*
1356 * Writes are posted. We need to do a read on the VME bus to flush out
1357 * all of the writes before we check for errors. We can't guarentee
1358 * that reading the data we have just written is safe. It is believed
1359 * that there isn't any read, write re-ordering, so we can read any
1360 * location in VME space, so lets read the Device ID from the tsi148's
1361 * own registers as mapped into CR/CSR space.
1362 *
1363 * We check for saved errors in the written address range/space.
1364 */
1365
1366 if (!err_chk)
1367 goto skip_chk;
1368
1369 /*
1370 * Get window info first, to maximise the time that the buffers may
1371 * fluch on their own
1372 */
1373 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1374 &dwidth);
1375
1376 ioread16(flush_image->kern_base + 0x7F000);
1377
1378 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1379 if(vme_err != NULL) {
1380 printk("First VME write error detected an at address 0x%llx\n",
1381 vme_err->address);
1382 retval = vme_err->address - (vme_base + offset);
1383 /* Clear down save errors in this address range */
1384 tsi148_clear_errors(aspace, vme_base + offset, count);
1385 }
1386
1387 skip_chk:
1388 spin_unlock(&(image->lock));
1389
1390 return retval;
1391 }
1392
1393 /*
1394 * Perform an RMW cycle on the VME bus.
1395 *
1396 * Requires a previously configured master window, returns final value.
1397 */
1398 unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1399 unsigned int mask, unsigned int compare, unsigned int swap,
1400 loff_t offset)
1401 {
1402 unsigned long long pci_addr;
1403 unsigned int pci_addr_high, pci_addr_low;
1404 u32 tmp, result;
1405 int i;
1406
1407
1408 /* Find the PCI address that maps to the desired VME address */
1409 i = image->number;
1410
1411 /* Locking as we can only do one of these at a time */
1412 mutex_lock(&(vme_rmw));
1413
1414 /* Lock image */
1415 spin_lock(&(image->lock));
1416
1417 pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1418 TSI148_LCSR_OFFSET_OTSAU);
1419 pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1420 TSI148_LCSR_OFFSET_OTSAL);
1421
1422 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1423 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1424
1425 /* Configure registers */
1426 iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN);
1427 iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC);
1428 iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS);
1429 iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU);
1430 iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL);
1431
1432 /* Enable RMW */
1433 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1434 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1435 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1436
1437 /* Kick process off with a read to the required address. */
1438 result = ioread32be(image->kern_base + offset);
1439
1440 /* Disable RMW */
1441 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1442 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1443 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1444
1445 spin_unlock(&(image->lock));
1446
1447 mutex_unlock(&(vme_rmw));
1448
1449 return result;
1450 }
1451
1452 static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace,
1453 vme_cycle_t cycle, vme_width_t dwidth)
1454 {
1455 /* Setup 2eSST speeds */
1456 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1457 case VME_2eSST160:
1458 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1459 break;
1460 case VME_2eSST267:
1461 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1462 break;
1463 case VME_2eSST320:
1464 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1465 break;
1466 }
1467
1468 /* Setup cycle types */
1469 if (cycle & VME_SCT) {
1470 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1471 }
1472 if (cycle & VME_BLT) {
1473 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1474 }
1475 if (cycle & VME_MBLT) {
1476 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1477 }
1478 if (cycle & VME_2eVME) {
1479 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1480 }
1481 if (cycle & VME_2eSST) {
1482 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1483 }
1484 if (cycle & VME_2eSSTB) {
1485 printk("Currently not setting Broadcast Select Registers\n");
1486 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1487 }
1488
1489 /* Setup data width */
1490 switch (dwidth) {
1491 case VME_D16:
1492 *attr |= TSI148_LCSR_DSAT_DBW_16;
1493 break;
1494 case VME_D32:
1495 *attr |= TSI148_LCSR_DSAT_DBW_32;
1496 break;
1497 default:
1498 printk("Invalid data width\n");
1499 return -EINVAL;
1500 }
1501
1502 /* Setup address space */
1503 switch (aspace) {
1504 case VME_A16:
1505 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1506 break;
1507 case VME_A24:
1508 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1509 break;
1510 case VME_A32:
1511 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1512 break;
1513 case VME_A64:
1514 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1515 break;
1516 case VME_CRCSR:
1517 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1518 break;
1519 case VME_USER1:
1520 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1521 break;
1522 case VME_USER2:
1523 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1524 break;
1525 case VME_USER3:
1526 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1527 break;
1528 case VME_USER4:
1529 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1530 break;
1531 default:
1532 printk("Invalid address space\n");
1533 return -EINVAL;
1534 break;
1535 }
1536
1537 if (cycle & VME_SUPER)
1538 *attr |= TSI148_LCSR_DSAT_SUP;
1539 if (cycle & VME_PROG)
1540 *attr |= TSI148_LCSR_DSAT_PGM;
1541
1542 return 0;
1543 }
1544
1545 static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace,
1546 vme_cycle_t cycle, vme_width_t dwidth)
1547 {
1548 /* Setup 2eSST speeds */
1549 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1550 case VME_2eSST160:
1551 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1552 break;
1553 case VME_2eSST267:
1554 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1555 break;
1556 case VME_2eSST320:
1557 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1558 break;
1559 }
1560
1561 /* Setup cycle types */
1562 if (cycle & VME_SCT) {
1563 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1564 }
1565 if (cycle & VME_BLT) {
1566 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1567 }
1568 if (cycle & VME_MBLT) {
1569 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1570 }
1571 if (cycle & VME_2eVME) {
1572 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1573 }
1574 if (cycle & VME_2eSST) {
1575 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1576 }
1577 if (cycle & VME_2eSSTB) {
1578 printk("Currently not setting Broadcast Select Registers\n");
1579 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1580 }
1581
1582 /* Setup data width */
1583 switch (dwidth) {
1584 case VME_D16:
1585 *attr |= TSI148_LCSR_DDAT_DBW_16;
1586 break;
1587 case VME_D32:
1588 *attr |= TSI148_LCSR_DDAT_DBW_32;
1589 break;
1590 default:
1591 printk("Invalid data width\n");
1592 return -EINVAL;
1593 }
1594
1595 /* Setup address space */
1596 switch (aspace) {
1597 case VME_A16:
1598 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1599 break;
1600 case VME_A24:
1601 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1602 break;
1603 case VME_A32:
1604 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1605 break;
1606 case VME_A64:
1607 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1608 break;
1609 case VME_CRCSR:
1610 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1611 break;
1612 case VME_USER1:
1613 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1614 break;
1615 case VME_USER2:
1616 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1617 break;
1618 case VME_USER3:
1619 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1620 break;
1621 case VME_USER4:
1622 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1623 break;
1624 default:
1625 printk("Invalid address space\n");
1626 return -EINVAL;
1627 break;
1628 }
1629
1630 if (cycle & VME_SUPER)
1631 *attr |= TSI148_LCSR_DDAT_SUP;
1632 if (cycle & VME_PROG)
1633 *attr |= TSI148_LCSR_DDAT_PGM;
1634
1635 return 0;
1636 }
1637
1638 /*
1639 * Add a link list descriptor to the list
1640 *
1641 * XXX Need to handle 2eSST Broadcast select bits
1642 */
1643 int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
1644 struct vme_dma_attr *dest, size_t count)
1645 {
1646 struct tsi148_dma_entry *entry, *prev;
1647 u32 address_high, address_low;
1648 struct vme_dma_pattern *pattern_attr;
1649 struct vme_dma_pci *pci_attr;
1650 struct vme_dma_vme *vme_attr;
1651 dma_addr_t desc_ptr;
1652 int retval = 0;
1653
1654 /* XXX descriptor must be aligned on 64-bit boundaries */
1655 entry = (struct tsi148_dma_entry *)kmalloc(
1656 sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1657 if (entry == NULL) {
1658 printk("Failed to allocate memory for dma resource "
1659 "structure\n");
1660 retval = -ENOMEM;
1661 goto err_mem;
1662 }
1663
1664 /* Test descriptor alignment */
1665 if ((unsigned long)&(entry->descriptor) & 0x7) {
1666 printk("Descriptor not aligned to 8 byte boundary as "
1667 "required: %p\n", &(entry->descriptor));
1668 retval = -EINVAL;
1669 goto err_align;
1670 }
1671
1672 /* Given we are going to fill out the structure, we probably don't
1673 * need to zero it, but better safe than sorry for now.
1674 */
1675 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1676
1677 /* Fill out source part */
1678 switch (src->type) {
1679 case VME_DMA_PATTERN:
1680 pattern_attr = (struct vme_dma_pattern *)src->private;
1681
1682 entry->descriptor.dsal = pattern_attr->pattern;
1683 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1684 /* Default behaviour is 32 bit pattern */
1685 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
1686 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1687 }
1688 /* It seems that the default behaviour is to increment */
1689 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
1690 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1691 }
1692 break;
1693 case VME_DMA_PCI:
1694 pci_attr = (struct vme_dma_pci *)src->private;
1695
1696 reg_split((unsigned long long)pci_attr->address, &address_high,
1697 &address_low);
1698 entry->descriptor.dsau = address_high;
1699 entry->descriptor.dsal = address_low;
1700 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1701 break;
1702 case VME_DMA_VME:
1703 vme_attr = (struct vme_dma_vme *)src->private;
1704
1705 reg_split((unsigned long long)vme_attr->address, &address_high,
1706 &address_low);
1707 entry->descriptor.dsau = address_high;
1708 entry->descriptor.dsal = address_low;
1709 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1710
1711 retval = tsi148_dma_set_vme_src_attributes(
1712 &(entry->descriptor.dsat), vme_attr->aspace,
1713 vme_attr->cycle, vme_attr->dwidth);
1714 if(retval < 0 )
1715 goto err_source;
1716 break;
1717 default:
1718 printk("Invalid source type\n");
1719 retval = -EINVAL;
1720 goto err_source;
1721 break;
1722 }
1723
1724 /* Assume last link - this will be over-written by adding another */
1725 entry->descriptor.dnlau = 0;
1726 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1727
1728
1729 /* Fill out destination part */
1730 switch (dest->type) {
1731 case VME_DMA_PCI:
1732 pci_attr = (struct vme_dma_pci *)dest->private;
1733
1734 reg_split((unsigned long long)pci_attr->address, &address_high,
1735 &address_low);
1736 entry->descriptor.ddau = address_high;
1737 entry->descriptor.ddal = address_low;
1738 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1739 break;
1740 case VME_DMA_VME:
1741 vme_attr = (struct vme_dma_vme *)dest->private;
1742
1743 reg_split((unsigned long long)vme_attr->address, &address_high,
1744 &address_low);
1745 entry->descriptor.ddau = address_high;
1746 entry->descriptor.ddal = address_low;
1747 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1748
1749 retval = tsi148_dma_set_vme_dest_attributes(
1750 &(entry->descriptor.ddat), vme_attr->aspace,
1751 vme_attr->cycle, vme_attr->dwidth);
1752 if(retval < 0 )
1753 goto err_dest;
1754 break;
1755 default:
1756 printk("Invalid destination type\n");
1757 retval = -EINVAL;
1758 goto err_dest;
1759 break;
1760 }
1761
1762 /* Fill out count */
1763 entry->descriptor.dcnt = (u32)count;
1764
1765 /* Add to list */
1766 list_add_tail(&(entry->list), &(list->entries));
1767
1768 /* Fill out previous descriptors "Next Address" */
1769 if(entry->list.prev != &(list->entries)){
1770 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1771 list);
1772 /* We need the bus address for the pointer */
1773 desc_ptr = virt_to_bus(&(entry->descriptor));
1774 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1775 &(prev->descriptor.dnlal));
1776 }
1777
1778 return 0;
1779
1780 err_dest:
1781 err_source:
1782 err_align:
1783 kfree(entry);
1784 err_mem:
1785 return retval;
1786 }
1787
1788 /*
1789 * Check to see if the provided DMA channel is busy.
1790 */
1791 static int tsi148_dma_busy(int channel)
1792 {
1793 u32 tmp;
1794
1795 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1796 TSI148_LCSR_OFFSET_DSTA);
1797
1798 if (tmp & TSI148_LCSR_DSTA_BSY)
1799 return 0;
1800 else
1801 return 1;
1802
1803 }
1804
1805 /*
1806 * Execute a previously generated link list
1807 *
1808 * XXX Need to provide control register configuration.
1809 */
1810 int tsi148_dma_list_exec(struct vme_dma_list *list)
1811 {
1812 struct vme_dma_resource *ctrlr;
1813 int channel, retval = 0;
1814 struct tsi148_dma_entry *entry;
1815 dma_addr_t bus_addr;
1816 u32 bus_addr_high, bus_addr_low;
1817 u32 val, dctlreg = 0;
1818 #if 0
1819 int x;
1820 #endif
1821
1822 ctrlr = list->parent;
1823
1824 mutex_lock(&(ctrlr->mtx));
1825
1826 channel = ctrlr->number;
1827
1828 if (! list_empty(&(ctrlr->running))) {
1829 /*
1830 * XXX We have an active DMA transfer and currently haven't
1831 * sorted out the mechanism for "pending" DMA transfers.
1832 * Return busy.
1833 */
1834 /* Need to add to pending here */
1835 mutex_unlock(&(ctrlr->mtx));
1836 return -EBUSY;
1837 } else {
1838 list_add(&(list->list), &(ctrlr->running));
1839 }
1840 #if 0
1841 /* XXX Still todo */
1842 for (x = 0; x < 8; x++) { /* vme block size */
1843 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
1844 break;
1845 }
1846 }
1847 if (x == 8)
1848 x = 7;
1849 dctlreg |= (x << 12);
1850
1851 for (x = 0; x < 8; x++) { /* pci block size */
1852 if ((32 << x) >= vmeDma->maxPciBlockSize) {
1853 break;
1854 }
1855 }
1856 if (x == 8)
1857 x = 7;
1858 dctlreg |= (x << 4);
1859
1860 if (vmeDma->vmeBackOffTimer) {
1861 for (x = 1; x < 8; x++) { /* vme timer */
1862 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
1863 break;
1864 }
1865 }
1866 if (x == 8)
1867 x = 7;
1868 dctlreg |= (x << 8);
1869 }
1870
1871 if (vmeDma->pciBackOffTimer) {
1872 for (x = 1; x < 8; x++) { /* pci timer */
1873 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
1874 break;
1875 }
1876 }
1877 if (x == 8)
1878 x = 7;
1879 dctlreg |= (x << 0);
1880 }
1881 #endif
1882
1883 /* Get first bus address and write into registers */
1884 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1885 list);
1886
1887 bus_addr = virt_to_bus(&(entry->descriptor));
1888
1889 mutex_unlock(&(ctrlr->mtx));
1890
1891 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1892
1893 iowrite32be(bus_addr_high, tsi148_bridge->base +
1894 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1895 iowrite32be(bus_addr_low, tsi148_bridge->base +
1896 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1897
1898 /* Start the operation */
1899 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base +
1900 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1901
1902 wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel));
1903 /*
1904 * Read status register, this register is valid until we kick off a
1905 * new transfer.
1906 */
1907 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1908 TSI148_LCSR_OFFSET_DSTA);
1909
1910 if (val & TSI148_LCSR_DSTA_VBE) {
1911 printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val);
1912 retval = -EIO;
1913 }
1914
1915 /* Remove list from running list */
1916 mutex_lock(&(ctrlr->mtx));
1917 list_del(&(list->list));
1918 mutex_unlock(&(ctrlr->mtx));
1919
1920 return retval;
1921 }
1922
1923 /*
1924 * Clean up a previously generated link list
1925 *
1926 * We have a separate function, don't assume that the chain can't be reused.
1927 */
1928 int tsi148_dma_list_empty(struct vme_dma_list *list)
1929 {
1930 struct list_head *pos, *temp;
1931 struct tsi148_dma_entry *entry;
1932
1933 /* detach and free each entry */
1934 list_for_each_safe(pos, temp, &(list->entries)) {
1935 list_del(pos);
1936 entry = list_entry(pos, struct tsi148_dma_entry, list);
1937 kfree(entry);
1938 }
1939
1940 return (0);
1941 }
1942
1943 /*
1944 * All 4 location monitors reside at the same base - this is therefore a
1945 * system wide configuration.
1946 *
1947 * This does not enable the LM monitor - that should be done when the first
1948 * callback is attached and disabled when the last callback is removed.
1949 */
1950 int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1951 vme_address_t aspace, vme_cycle_t cycle)
1952 {
1953 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1954 int i;
1955
1956 mutex_lock(&(lm->mtx));
1957
1958 /* If we already have a callback attached, we can't move it! */
1959 for (i = 0; i < lm->monitors; i++) {
1960 if(lm_callback[i] != NULL) {
1961 mutex_unlock(&(lm->mtx));
1962 printk("Location monitor callback attached, can't "
1963 "reset\n");
1964 return -EBUSY;
1965 }
1966 }
1967
1968 switch (aspace) {
1969 case VME_A16:
1970 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1971 break;
1972 case VME_A24:
1973 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1974 break;
1975 case VME_A32:
1976 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1977 break;
1978 case VME_A64:
1979 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1980 break;
1981 default:
1982 mutex_unlock(&(lm->mtx));
1983 printk("Invalid address space\n");
1984 return -EINVAL;
1985 break;
1986 }
1987
1988 if (cycle & VME_SUPER)
1989 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1990 if (cycle & VME_USER)
1991 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1992 if (cycle & VME_PROG)
1993 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1994 if (cycle & VME_DATA)
1995 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1996
1997 reg_split(lm_base, &lm_base_high, &lm_base_low);
1998
1999 iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU);
2000 iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL);
2001 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2002
2003 mutex_unlock(&(lm->mtx));
2004
2005 return 0;
2006 }
2007
2008 /* Get configuration of the callback monitor and return whether it is enabled
2009 * or disabled.
2010 */
2011 int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
2012 vme_address_t *aspace, vme_cycle_t *cycle)
2013 {
2014 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2015
2016 mutex_lock(&(lm->mtx));
2017
2018 lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU);
2019 lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL);
2020 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2021
2022 reg_join(lm_base_high, lm_base_low, lm_base);
2023
2024 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2025 enabled = 1;
2026
2027 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
2028 *aspace |= VME_A16;
2029 }
2030 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
2031 *aspace |= VME_A24;
2032 }
2033 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
2034 *aspace |= VME_A32;
2035 }
2036 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
2037 *aspace |= VME_A64;
2038 }
2039
2040 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2041 *cycle |= VME_SUPER;
2042 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2043 *cycle |= VME_USER;
2044 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2045 *cycle |= VME_PROG;
2046 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2047 *cycle |= VME_DATA;
2048
2049 mutex_unlock(&(lm->mtx));
2050
2051 return enabled;
2052 }
2053
2054 /*
2055 * Attach a callback to a specific location monitor.
2056 *
2057 * Callback will be passed the monitor triggered.
2058 */
2059 int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2060 void (*callback)(int))
2061 {
2062 u32 lm_ctl, tmp;
2063
2064 mutex_lock(&(lm->mtx));
2065
2066 /* Ensure that the location monitor is configured - need PGM or DATA */
2067 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2068 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2069 mutex_unlock(&(lm->mtx));
2070 printk("Location monitor not properly configured\n");
2071 return -EINVAL;
2072 }
2073
2074 /* Check that a callback isn't already attached */
2075 if (lm_callback[monitor] != NULL) {
2076 mutex_unlock(&(lm->mtx));
2077 printk("Existing callback attached\n");
2078 return -EBUSY;
2079 }
2080
2081 /* Attach callback */
2082 lm_callback[monitor] = callback;
2083
2084 /* Enable Location Monitor interrupt */
2085 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2086 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2087 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
2088
2089 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2090 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2091 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2092
2093 /* Ensure that global Location Monitor Enable set */
2094 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2095 lm_ctl |= TSI148_LCSR_LMAT_EN;
2096 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2097 }
2098
2099 mutex_unlock(&(lm->mtx));
2100
2101 return 0;
2102 }
2103
2104 /*
2105 * Detach a callback function forn a specific location monitor.
2106 */
2107 int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2108 {
2109 u32 lm_en, tmp;
2110
2111 mutex_lock(&(lm->mtx));
2112
2113 /* Disable Location Monitor and ensure previous interrupts are clear */
2114 lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2115 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2116 iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN);
2117
2118 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2119 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2120 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2121
2122 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2123 tsi148_bridge->base + TSI148_LCSR_INTC);
2124
2125 /* Detach callback */
2126 lm_callback[monitor] = NULL;
2127
2128 /* If all location monitors disabled, disable global Location Monitor */
2129 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2130 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2131 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2132 tmp &= ~TSI148_LCSR_LMAT_EN;
2133 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT);
2134 }
2135
2136 mutex_unlock(&(lm->mtx));
2137
2138 return 0;
2139 }
2140
2141 /*
2142 * Determine Geographical Addressing
2143 */
2144 int tsi148_slot_get(void)
2145 {
2146 u32 slot = 0;
2147
2148 slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2149 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2150 return (int)slot;
2151 }
2152
2153 static int __init tsi148_init(void)
2154 {
2155 return pci_register_driver(&tsi148_driver);
2156 }
2157
2158 /*
2159 * Configure CR/CSR space
2160 *
2161 * Access to the CR/CSR can be configured at power-up. The location of the
2162 * CR/CSR registers in the CR/CSR address space is determined by the boards
2163 * Auto-ID or Geographic address. This function ensures that the window is
2164 * enabled at an offset consistent with the boards geopgraphic address.
2165 *
2166 * Each board has a 512kB window, with the highest 4kB being used for the
2167 * boards registers, this means there is a fix length 508kB window which must
2168 * be mapped onto PCI memory.
2169 */
2170 static int tsi148_crcsr_init(struct pci_dev *pdev)
2171 {
2172 u32 cbar, crat, vstat;
2173 u32 crcsr_bus_high, crcsr_bus_low;
2174 int retval;
2175
2176 /* Allocate mem for CR/CSR image */
2177 crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2178 &crcsr_bus);
2179 if (crcsr_kernel == NULL) {
2180 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
2181 "image\n");
2182 return -ENOMEM;
2183 }
2184
2185 memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2186
2187 reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2188
2189 iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU);
2190 iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL);
2191
2192 /* Ensure that the CR/CSR is configured at the correct offset */
2193 cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR);
2194 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2195
2196 vstat = tsi148_slot_get();
2197
2198 if (cbar != vstat) {
2199 dev_info(&pdev->dev, "Setting CR/CSR offset\n");
2200 iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR);
2201 }
2202 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar);
2203
2204 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2205 if (crat & TSI148_LCSR_CRAT_EN) {
2206 dev_info(&pdev->dev, "Enabling CR/CSR space\n");
2207 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2208 tsi148_bridge->base + TSI148_LCSR_CRAT);
2209 } else
2210 dev_info(&pdev->dev, "CR/CSR already enabled\n");
2211
2212 /* If we want flushed, error-checked writes, set up a window
2213 * over the CR/CSR registers. We read from here to safely flush
2214 * through VME writes.
2215 */
2216 if(err_chk) {
2217 retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000),
2218 0x80000, VME_CRCSR, VME_SCT, VME_D16);
2219 if (retval)
2220 dev_err(&pdev->dev, "Configuring flush image failed\n");
2221 }
2222
2223 return 0;
2224
2225 }
2226
2227 static void tsi148_crcsr_exit(struct pci_dev *pdev)
2228 {
2229 u32 crat;
2230
2231 /* Turn off CR/CSR space */
2232 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2233 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2234 tsi148_bridge->base + TSI148_LCSR_CRAT);
2235
2236 /* Free image */
2237 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU);
2238 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL);
2239
2240 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus);
2241 }
2242
2243 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2244 {
2245 int retval, i, master_num;
2246 u32 data;
2247 struct list_head *pos = NULL;
2248 struct vme_master_resource *master_image;
2249 struct vme_slave_resource *slave_image;
2250 struct vme_dma_resource *dma_ctrlr;
2251 struct vme_lm_resource *lm;
2252
2253 /* If we want to support more than one of each bridge, we need to
2254 * dynamically generate this so we get one per device
2255 */
2256 tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
2257 GFP_KERNEL);
2258 if (tsi148_bridge == NULL) {
2259 dev_err(&pdev->dev, "Failed to allocate memory for device "
2260 "structure\n");
2261 retval = -ENOMEM;
2262 goto err_struct;
2263 }
2264
2265 memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2266
2267 /* Enable the device */
2268 retval = pci_enable_device(pdev);
2269 if (retval) {
2270 dev_err(&pdev->dev, "Unable to enable device\n");
2271 goto err_enable;
2272 }
2273
2274 /* Map Registers */
2275 retval = pci_request_regions(pdev, driver_name);
2276 if (retval) {
2277 dev_err(&pdev->dev, "Unable to reserve resources\n");
2278 goto err_resource;
2279 }
2280
2281 /* map registers in BAR 0 */
2282 tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096);
2283 if (!tsi148_bridge->base) {
2284 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2285 retval = -EIO;
2286 goto err_remap;
2287 }
2288
2289 /* Check to see if the mapping worked out */
2290 data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF;
2291 if (data != PCI_VENDOR_ID_TUNDRA) {
2292 dev_err(&pdev->dev, "CRG region check failed\n");
2293 retval = -EIO;
2294 goto err_test;
2295 }
2296
2297 /* Initialize wait queues & mutual exclusion flags */
2298 /* XXX These need to be moved to the vme_bridge structure */
2299 init_waitqueue_head(&dma_queue[0]);
2300 init_waitqueue_head(&dma_queue[1]);
2301 init_waitqueue_head(&iack_queue);
2302 mutex_init(&(vme_int));
2303 mutex_init(&(vme_rmw));
2304
2305 tsi148_bridge->parent = &(pdev->dev);
2306 strcpy(tsi148_bridge->name, driver_name);
2307
2308 /* Setup IRQ */
2309 retval = tsi148_irq_init(tsi148_bridge);
2310 if (retval != 0) {
2311 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2312 goto err_irq;
2313 }
2314
2315 /* If we are going to flush writes, we need to read from the VME bus.
2316 * We need to do this safely, thus we read the devices own CR/CSR
2317 * register. To do this we must set up a window in CR/CSR space and
2318 * hence have one less master window resource available.
2319 */
2320 master_num = TSI148_MAX_MASTER;
2321 if(err_chk){
2322 master_num--;
2323 /* XXX */
2324 flush_image = (struct vme_master_resource *)kmalloc(
2325 sizeof(struct vme_master_resource), GFP_KERNEL);
2326 if (flush_image == NULL) {
2327 dev_err(&pdev->dev, "Failed to allocate memory for "
2328 "flush resource structure\n");
2329 retval = -ENOMEM;
2330 goto err_master;
2331 }
2332 flush_image->parent = tsi148_bridge;
2333 spin_lock_init(&(flush_image->lock));
2334 flush_image->locked = 1;
2335 flush_image->number = master_num;
2336 flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2337 VME_A64;
2338 flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2339 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2340 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2341 VME_PROG | VME_DATA;
2342 flush_image->width_attr = VME_D16 | VME_D32;
2343 memset(&(flush_image->pci_resource), 0,
2344 sizeof(struct resource));
2345 flush_image->kern_base = NULL;
2346 }
2347
2348 /* Add master windows to list */
2349 INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2350 for (i = 0; i < master_num; i++) {
2351 master_image = (struct vme_master_resource *)kmalloc(
2352 sizeof(struct vme_master_resource), GFP_KERNEL);
2353 if (master_image == NULL) {
2354 dev_err(&pdev->dev, "Failed to allocate memory for "
2355 "master resource structure\n");
2356 retval = -ENOMEM;
2357 goto err_master;
2358 }
2359 master_image->parent = tsi148_bridge;
2360 spin_lock_init(&(master_image->lock));
2361 master_image->locked = 0;
2362 master_image->number = i;
2363 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2364 VME_A64;
2365 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2366 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2367 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2368 VME_PROG | VME_DATA;
2369 master_image->width_attr = VME_D16 | VME_D32;
2370 memset(&(master_image->pci_resource), 0,
2371 sizeof(struct resource));
2372 master_image->kern_base = NULL;
2373 list_add_tail(&(master_image->list),
2374 &(tsi148_bridge->master_resources));
2375 }
2376
2377 /* Add slave windows to list */
2378 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2379 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2380 slave_image = (struct vme_slave_resource *)kmalloc(
2381 sizeof(struct vme_slave_resource), GFP_KERNEL);
2382 if (slave_image == NULL) {
2383 dev_err(&pdev->dev, "Failed to allocate memory for "
2384 "slave resource structure\n");
2385 retval = -ENOMEM;
2386 goto err_slave;
2387 }
2388 slave_image->parent = tsi148_bridge;
2389 mutex_init(&(slave_image->mtx));
2390 slave_image->locked = 0;
2391 slave_image->number = i;
2392 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2393 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2394 VME_USER3 | VME_USER4;
2395 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2396 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2397 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2398 VME_PROG | VME_DATA;
2399 list_add_tail(&(slave_image->list),
2400 &(tsi148_bridge->slave_resources));
2401 }
2402
2403 /* Add dma engines to list */
2404 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2405 for (i = 0; i < TSI148_MAX_DMA; i++) {
2406 dma_ctrlr = (struct vme_dma_resource *)kmalloc(
2407 sizeof(struct vme_dma_resource), GFP_KERNEL);
2408 if (dma_ctrlr == NULL) {
2409 dev_err(&pdev->dev, "Failed to allocate memory for "
2410 "dma resource structure\n");
2411 retval = -ENOMEM;
2412 goto err_dma;
2413 }
2414 dma_ctrlr->parent = tsi148_bridge;
2415 mutex_init(&(dma_ctrlr->mtx));
2416 dma_ctrlr->locked = 0;
2417 dma_ctrlr->number = i;
2418 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2419 INIT_LIST_HEAD(&(dma_ctrlr->running));
2420 list_add_tail(&(dma_ctrlr->list),
2421 &(tsi148_bridge->dma_resources));
2422 }
2423
2424 /* Add location monitor to list */
2425 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2426 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2427 if (lm == NULL) {
2428 dev_err(&pdev->dev, "Failed to allocate memory for "
2429 "location monitor resource structure\n");
2430 retval = -ENOMEM;
2431 goto err_lm;
2432 }
2433 lm->parent = tsi148_bridge;
2434 mutex_init(&(lm->mtx));
2435 lm->locked = 0;
2436 lm->number = 1;
2437 lm->monitors = 4;
2438 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2439
2440 tsi148_bridge->slave_get = tsi148_slave_get;
2441 tsi148_bridge->slave_set = tsi148_slave_set;
2442 tsi148_bridge->master_get = tsi148_master_get;
2443 tsi148_bridge->master_set = tsi148_master_set;
2444 tsi148_bridge->master_read = tsi148_master_read;
2445 tsi148_bridge->master_write = tsi148_master_write;
2446 tsi148_bridge->master_rmw = tsi148_master_rmw;
2447 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2448 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2449 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2450 tsi148_bridge->irq_set = tsi148_irq_set;
2451 tsi148_bridge->irq_generate = tsi148_irq_generate;
2452 tsi148_bridge->lm_set = tsi148_lm_set;
2453 tsi148_bridge->lm_get = tsi148_lm_get;
2454 tsi148_bridge->lm_attach = tsi148_lm_attach;
2455 tsi148_bridge->lm_detach = tsi148_lm_detach;
2456 tsi148_bridge->slot_get = tsi148_slot_get;
2457
2458 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2459 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2460 (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
2461 dev_info(&pdev->dev, "VME geographical address is %d\n",
2462 data & TSI148_LCSR_VSTAT_GA_M);
2463 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2464 err_chk ? "enabled" : "disabled");
2465
2466 if(tsi148_crcsr_init(pdev)) {
2467 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2468 goto err_crcsr;
2469
2470 }
2471
2472 /* Need to save tsi148_bridge pointer locally in link list for use in
2473 * tsi148_remove()
2474 */
2475 retval = vme_register_bridge(tsi148_bridge);
2476 if (retval != 0) {
2477 dev_err(&pdev->dev, "Chip Registration failed.\n");
2478 goto err_reg;
2479 }
2480
2481 /* Clear VME bus "board fail", and "power-up reset" lines */
2482 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2483 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2484 data |= TSI148_LCSR_VSTAT_CPURST;
2485 iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT);
2486
2487 return 0;
2488
2489 vme_unregister_bridge(tsi148_bridge);
2490 err_reg:
2491 tsi148_crcsr_exit(pdev);
2492 err_crcsr:
2493 err_lm:
2494 /* resources are stored in link list */
2495 list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2496 lm = list_entry(pos, struct vme_lm_resource, list);
2497 list_del(pos);
2498 kfree(lm);
2499 }
2500 err_dma:
2501 /* resources are stored in link list */
2502 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2503 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2504 list_del(pos);
2505 kfree(dma_ctrlr);
2506 }
2507 err_slave:
2508 /* resources are stored in link list */
2509 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2510 slave_image = list_entry(pos, struct vme_slave_resource, list);
2511 list_del(pos);
2512 kfree(slave_image);
2513 }
2514 err_master:
2515 /* resources are stored in link list */
2516 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2517 master_image = list_entry(pos, struct vme_master_resource, list);
2518 list_del(pos);
2519 kfree(master_image);
2520 }
2521
2522 tsi148_irq_exit(pdev);
2523 err_irq:
2524 err_test:
2525 iounmap(tsi148_bridge->base);
2526 err_remap:
2527 pci_release_regions(pdev);
2528 err_resource:
2529 pci_disable_device(pdev);
2530 err_enable:
2531 kfree(tsi148_bridge);
2532 err_struct:
2533 return retval;
2534
2535 }
2536
2537 static void tsi148_remove(struct pci_dev *pdev)
2538 {
2539 struct list_head *pos = NULL;
2540 struct vme_master_resource *master_image;
2541 struct vme_slave_resource *slave_image;
2542 struct vme_dma_resource *dma_ctrlr;
2543 int i;
2544
2545 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2546
2547 /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */
2548
2549 /*
2550 * Shutdown all inbound and outbound windows.
2551 */
2552 for (i = 0; i < 8; i++) {
2553 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] +
2554 TSI148_LCSR_OFFSET_ITAT);
2555 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] +
2556 TSI148_LCSR_OFFSET_OTAT);
2557 }
2558
2559 /*
2560 * Shutdown Location monitor.
2561 */
2562 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT);
2563
2564 /*
2565 * Shutdown CRG map.
2566 */
2567 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT);
2568
2569 /*
2570 * Clear error status.
2571 */
2572 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT);
2573 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT);
2574 iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT);
2575
2576 /*
2577 * Remove VIRQ interrupt (if any)
2578 */
2579 if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) {
2580 iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR);
2581 }
2582
2583 /*
2584 * Map all Interrupts to PCI INTA
2585 */
2586 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1);
2587 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2);
2588
2589 tsi148_irq_exit(pdev);
2590
2591 vme_unregister_bridge(tsi148_bridge);
2592
2593 tsi148_crcsr_exit(pdev);
2594
2595 /* resources are stored in link list */
2596 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2597 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2598 list_del(pos);
2599 kfree(dma_ctrlr);
2600 }
2601
2602 /* resources are stored in link list */
2603 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2604 slave_image = list_entry(pos, struct vme_slave_resource, list);
2605 list_del(pos);
2606 kfree(slave_image);
2607 }
2608
2609 /* resources are stored in link list */
2610 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2611 master_image = list_entry(pos, struct vme_master_resource, list);
2612 list_del(pos);
2613 kfree(master_image);
2614 }
2615
2616 tsi148_irq_exit(pdev);
2617
2618 iounmap(tsi148_bridge->base);
2619
2620 pci_release_regions(pdev);
2621
2622 pci_disable_device(pdev);
2623
2624 kfree(tsi148_bridge);
2625 }
2626
2627 static void __exit tsi148_exit(void)
2628 {
2629 pci_unregister_driver(&tsi148_driver);
2630
2631 printk(KERN_DEBUG "Driver removed.\n");
2632 }
2633
2634 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2635 module_param(err_chk, bool, 0);
2636
2637 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2638 MODULE_LICENSE("GPL");
2639
2640 module_init(tsi148_init);
2641 module_exit(tsi148_exit);
2642
2643 /*----------------------------------------------------------------------------
2644 * STAGING
2645 *--------------------------------------------------------------------------*/
2646
2647 #if 0
2648 /*
2649 * Direct Mode DMA transfer
2650 *
2651 * XXX Not looking at direct mode for now, we can always use link list mode
2652 * with a single entry.
2653 */
2654 int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src,
2655 struct vme_dma_attr dest, size_t count)
2656 {
2657 u32 dctlreg = 0;
2658 unsigned int tmp;
2659 int val;
2660 int channel, x;
2661 struct vmeDmaPacket *cur_dma;
2662 struct tsi148_dma_descriptor *dmaLL;
2663
2664 /* direct mode */
2665 dctlreg = 0x800000;
2666
2667 for (x = 0; x < 8; x++) { /* vme block size */
2668 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
2669 break;
2670 }
2671 }
2672 if (x == 8)
2673 x = 7;
2674 dctlreg |= (x << 12);
2675
2676 for (x = 0; x < 8; x++) { /* pci block size */
2677 if ((32 << x) >= vmeDma->maxPciBlockSize) {
2678 break;
2679 }
2680 }
2681 if (x == 8)
2682 x = 7;
2683 dctlreg |= (x << 4);
2684
2685 if (vmeDma->vmeBackOffTimer) {
2686 for (x = 1; x < 8; x++) { /* vme timer */
2687 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
2688 break;
2689 }
2690 }
2691 if (x == 8)
2692 x = 7;
2693 dctlreg |= (x << 8);
2694 }
2695
2696 if (vmeDma->pciBackOffTimer) {
2697 for (x = 1; x < 8; x++) { /* pci timer */
2698 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
2699 break;
2700 }
2701 }
2702 if (x == 8)
2703 x = 7;
2704 dctlreg |= (x << 0);
2705 }
2706
2707 /* Program registers for DMA transfer */
2708 iowrite32be(dmaLL->dsau, tsi148_bridge->base +
2709 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU);
2710 iowrite32be(dmaLL->dsal, tsi148_bridge->base +
2711 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL);
2712 iowrite32be(dmaLL->ddau, tsi148_bridge->base +
2713 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU);
2714 iowrite32be(dmaLL->ddal, tsi148_bridge->base +
2715 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL);
2716 iowrite32be(dmaLL->dsat, tsi148_bridge->base +
2717 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT);
2718 iowrite32be(dmaLL->ddat, tsi148_bridge->base +
2719 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT);
2720 iowrite32be(dmaLL->dcnt, tsi148_bridge->base +
2721 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT);
2722 iowrite32be(dmaLL->ddbs, tsi148_bridge->base +
2723 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS);
2724
2725 /* Start the operation */
2726 iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base +
2727 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
2728
2729 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2730 TSI148_LCSR_OFFSET_DSTA);
2731 wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0);
2732
2733 /*
2734 * Read status register, we should probably do this in some error
2735 * handler rather than here so that we can be sure we haven't kicked off
2736 * another DMA transfer.
2737 */
2738 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2739 TSI148_LCSR_OFFSET_DSTA);
2740
2741 vmeDma->vmeDmaStatus = 0;
2742 if (val & 0x10000000) {
2743 printk(KERN_ERR
2744 "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n",
2745 val);
2746 vmeDma->vmeDmaStatus = val;
2747
2748 }
2749 return (0);
2750 }
2751 #endif
2752
2753 #if 0
2754
2755 /* Global VME controller information */
2756 struct pci_dev *vme_pci_dev;
2757
2758 /*
2759 * Set the VME bus arbiter with the requested attributes
2760 */
2761 int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb)
2762 {
2763 int temp_ctl = 0;
2764 int gto = 0;
2765
2766 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2767 temp_ctl &= 0xFFEFFF00;
2768
2769 if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
2770 gto = 8;
2771 } else if (vmeArb->globalTimeoutTimer > 2048) {
2772 return (-EINVAL);
2773 } else if (vmeArb->globalTimeoutTimer == 0) {
2774 gto = 0;
2775 } else {
2776 gto = 1;
2777 while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) {
2778 gto += 1;
2779 }
2780 }
2781 temp_ctl |= gto;
2782
2783 if (vmeArb->arbiterMode != VME_PRIORITY_MODE) {
2784 temp_ctl |= 1 << 6;
2785 }
2786
2787 if (vmeArb->arbiterTimeoutFlag) {
2788 temp_ctl |= 1 << 7;
2789 }
2790
2791 if (vmeArb->noEarlyReleaseFlag) {
2792 temp_ctl |= 1 << 20;
2793 }
2794 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL);
2795
2796 return (0);
2797 }
2798
2799 /*
2800 * Return the attributes of the VME bus arbiter.
2801 */
2802 int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb)
2803 {
2804 int temp_ctl = 0;
2805 int gto = 0;
2806
2807
2808 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2809
2810 gto = temp_ctl & 0xF;
2811 if (gto != 0) {
2812 vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1)));
2813 }
2814
2815 if (temp_ctl & (1 << 6)) {
2816 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
2817 } else {
2818 vmeArb->arbiterMode = VME_PRIORITY_MODE;
2819 }
2820
2821 if (temp_ctl & (1 << 7)) {
2822 vmeArb->arbiterTimeoutFlag = 1;
2823 }
2824
2825 if (temp_ctl & (1 << 20)) {
2826 vmeArb->noEarlyReleaseFlag = 1;
2827 }
2828
2829 return (0);
2830 }
2831
2832 /*
2833 * Set the VME bus requestor with the requested attributes
2834 */
2835 int tempe_set_requestor(vmeRequesterCfg_t * vmeReq)
2836 {
2837 int temp_ctl = 0;
2838
2839 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2840 temp_ctl &= 0xFFFF0000;
2841
2842 if (vmeReq->releaseMode == 1) {
2843 temp_ctl |= (1 << 3);
2844 }
2845
2846 if (vmeReq->fairMode == 1) {
2847 temp_ctl |= (1 << 2);
2848 }
2849
2850 temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8;
2851 temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12;
2852 temp_ctl |= vmeReq->requestLevel;
2853
2854 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2855 return (0);
2856 }
2857
2858 /*
2859 * Return the attributes of the VME bus requestor
2860 */
2861 int tempe_get_requestor(vmeRequesterCfg_t * vmeReq)
2862 {
2863 int temp_ctl = 0;
2864
2865 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2866
2867 if (temp_ctl & 0x18) {
2868 vmeReq->releaseMode = 1;
2869 }
2870
2871 if (temp_ctl & (1 << 2)) {
2872 vmeReq->fairMode = 1;
2873 }
2874
2875 vmeReq->requestLevel = temp_ctl & 3;
2876 vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7;
2877 vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7;
2878
2879 return (0);
2880 }
2881
2882
2883 #endif
kernel source for telekom puls (alcatel/mediatek)