1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
33 static inline void spi_set_err_code(struct rtsx_chip
*chip
, u8 err_code
)
35 struct spi_info
*spi
= &(chip
->spi
);
37 spi
->err_code
= err_code
;
40 static int spi_init(struct rtsx_chip
*chip
)
42 RTSX_WRITE_REG(chip
, SPI_CONTROL
, 0xFF,
43 CS_POLARITY_LOW
| DTO_MSB_FIRST
| SPI_MASTER
| SPI_MODE0
| SPI_AUTO
);
44 RTSX_WRITE_REG(chip
, SPI_TCTL
, EDO_TIMING_MASK
, SAMPLE_DELAY_HALF
);
46 return STATUS_SUCCESS
;
49 static int spi_set_init_para(struct rtsx_chip
*chip
)
51 struct spi_info
*spi
= &(chip
->spi
);
54 RTSX_WRITE_REG(chip
, SPI_CLK_DIVIDER1
, 0xFF, (u8
)(spi
->clk_div
>> 8));
55 RTSX_WRITE_REG(chip
, SPI_CLK_DIVIDER0
, 0xFF, (u8
)(spi
->clk_div
));
57 retval
= switch_clock(chip
, spi
->spi_clock
);
58 if (retval
!= STATUS_SUCCESS
)
59 TRACE_RET(chip
, STATUS_FAIL
);
61 retval
= select_card(chip
, SPI_CARD
);
62 if (retval
!= STATUS_SUCCESS
)
63 TRACE_RET(chip
, STATUS_FAIL
);
65 RTSX_WRITE_REG(chip
, CARD_CLK_EN
, SPI_CLK_EN
, SPI_CLK_EN
);
66 RTSX_WRITE_REG(chip
, CARD_OE
, SPI_OUTPUT_EN
, SPI_OUTPUT_EN
);
70 retval
= spi_init(chip
);
71 if (retval
!= STATUS_SUCCESS
)
72 TRACE_RET(chip
, STATUS_FAIL
);
74 return STATUS_SUCCESS
;
77 static int sf_polling_status(struct rtsx_chip
*chip
, int msec
)
83 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, SPI_RDSR
);
84 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_POLLING_MODE0
);
85 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
87 retval
= rtsx_send_cmd(chip
, 0, msec
);
89 rtsx_clear_spi_error(chip
);
90 spi_set_err_code(chip
, SPI_BUSY_ERR
);
91 TRACE_RET(chip
, STATUS_FAIL
);
94 return STATUS_SUCCESS
;
97 static int sf_enable_write(struct rtsx_chip
*chip
, u8 ins
)
99 struct spi_info
*spi
= &(chip
->spi
);
103 return STATUS_SUCCESS
;
107 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
108 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
109 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_C_MODE0
);
110 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
112 retval
= rtsx_send_cmd(chip
, 0, 100);
114 rtsx_clear_spi_error(chip
);
115 spi_set_err_code(chip
, SPI_HW_ERR
);
116 TRACE_RET(chip
, STATUS_FAIL
);
119 return STATUS_SUCCESS
;
122 static int sf_disable_write(struct rtsx_chip
*chip
, u8 ins
)
124 struct spi_info
*spi
= &(chip
->spi
);
128 return STATUS_SUCCESS
;
132 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
133 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
134 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_C_MODE0
);
135 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
137 retval
= rtsx_send_cmd(chip
, 0, 100);
139 rtsx_clear_spi_error(chip
);
140 spi_set_err_code(chip
, SPI_HW_ERR
);
141 TRACE_RET(chip
, STATUS_FAIL
);
144 return STATUS_SUCCESS
;
147 static void sf_program(struct rtsx_chip
*chip
, u8 ins
, u8 addr_mode
, u32 addr
, u16 len
)
149 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
150 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
151 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, (u8
)len
);
152 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, (u8
)(len
>> 8));
154 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
155 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
156 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 16));
157 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CADO_MODE0
);
159 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CDO_MODE0
);
161 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
164 static int sf_erase(struct rtsx_chip
*chip
, u8 ins
, u8 addr_mode
, u32 addr
)
170 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
171 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
173 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
174 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
175 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 16));
176 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
178 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_C_MODE0
);
180 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
182 retval
= rtsx_send_cmd(chip
, 0, 100);
184 rtsx_clear_spi_error(chip
);
185 spi_set_err_code(chip
, SPI_HW_ERR
);
186 TRACE_RET(chip
, STATUS_FAIL
);
189 return STATUS_SUCCESS
;
192 static int spi_init_eeprom(struct rtsx_chip
*chip
)
202 RTSX_WRITE_REG(chip
, SPI_CLK_DIVIDER1
, 0xFF, 0x00);
203 RTSX_WRITE_REG(chip
, SPI_CLK_DIVIDER0
, 0xFF, 0x27);
205 retval
= switch_clock(chip
, clk
);
206 if (retval
!= STATUS_SUCCESS
)
207 TRACE_RET(chip
, STATUS_FAIL
);
209 retval
= select_card(chip
, SPI_CARD
);
210 if (retval
!= STATUS_SUCCESS
)
211 TRACE_RET(chip
, STATUS_FAIL
);
213 RTSX_WRITE_REG(chip
, CARD_CLK_EN
, SPI_CLK_EN
, SPI_CLK_EN
);
214 RTSX_WRITE_REG(chip
, CARD_OE
, SPI_OUTPUT_EN
, SPI_OUTPUT_EN
);
218 RTSX_WRITE_REG(chip
, SPI_CONTROL
, 0xFF, CS_POLARITY_HIGH
| SPI_EEPROM_AUTO
);
219 RTSX_WRITE_REG(chip
, SPI_TCTL
, EDO_TIMING_MASK
, SAMPLE_DELAY_HALF
);
221 return STATUS_SUCCESS
;
224 static int spi_eeprom_program_enable(struct rtsx_chip
*chip
)
230 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x86);
231 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x13);
232 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
233 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
235 retval
= rtsx_send_cmd(chip
, 0, 100);
237 TRACE_RET(chip
, STATUS_FAIL
);
239 return STATUS_SUCCESS
;
242 int spi_erase_eeprom_chip(struct rtsx_chip
*chip
)
246 retval
= spi_init_eeprom(chip
);
247 if (retval
!= STATUS_SUCCESS
)
248 TRACE_RET(chip
, STATUS_FAIL
);
250 retval
= spi_eeprom_program_enable(chip
);
251 if (retval
!= STATUS_SUCCESS
)
252 TRACE_RET(chip
, STATUS_FAIL
);
256 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
257 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
258 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x12);
259 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x84);
260 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
261 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
263 retval
= rtsx_send_cmd(chip
, 0, 100);
265 TRACE_RET(chip
, STATUS_FAIL
);
267 RTSX_WRITE_REG(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
269 return STATUS_SUCCESS
;
272 int spi_erase_eeprom_byte(struct rtsx_chip
*chip
, u16 addr
)
276 retval
= spi_init_eeprom(chip
);
277 if (retval
!= STATUS_SUCCESS
)
278 TRACE_RET(chip
, STATUS_FAIL
);
280 retval
= spi_eeprom_program_enable(chip
);
281 if (retval
!= STATUS_SUCCESS
)
282 TRACE_RET(chip
, STATUS_FAIL
);
286 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
287 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
288 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x07);
289 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
290 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
291 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x46);
292 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
293 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
295 retval
= rtsx_send_cmd(chip
, 0, 100);
297 TRACE_RET(chip
, STATUS_FAIL
);
299 RTSX_WRITE_REG(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
301 return STATUS_SUCCESS
;
305 int spi_read_eeprom(struct rtsx_chip
*chip
, u16 addr
, u8
*val
)
310 retval
= spi_init_eeprom(chip
);
311 if (retval
!= STATUS_SUCCESS
)
312 TRACE_RET(chip
, STATUS_FAIL
);
316 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
317 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
318 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x06);
319 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
320 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
321 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x46);
322 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, 1);
323 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
324 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
326 retval
= rtsx_send_cmd(chip
, 0, 100);
328 TRACE_RET(chip
, STATUS_FAIL
);
331 RTSX_READ_REG(chip
, SPI_DATA
, &data
);
336 RTSX_WRITE_REG(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
338 return STATUS_SUCCESS
;
341 int spi_write_eeprom(struct rtsx_chip
*chip
, u16 addr
, u8 val
)
345 retval
= spi_init_eeprom(chip
);
346 if (retval
!= STATUS_SUCCESS
)
347 TRACE_RET(chip
, STATUS_FAIL
);
349 retval
= spi_eeprom_program_enable(chip
);
350 if (retval
!= STATUS_SUCCESS
)
351 TRACE_RET(chip
, STATUS_FAIL
);
355 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
356 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
357 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x05);
358 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, val
);
359 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)addr
);
360 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 8));
361 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x4E);
362 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
363 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
365 retval
= rtsx_send_cmd(chip
, 0, 100);
367 TRACE_RET(chip
, STATUS_FAIL
);
369 RTSX_WRITE_REG(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
371 return STATUS_SUCCESS
;
375 int spi_get_status(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
377 struct spi_info
*spi
= &(chip
->spi
);
379 RTSX_DEBUGP("spi_get_status: err_code = 0x%x\n", spi
->err_code
);
380 rtsx_stor_set_xfer_buf(&(spi
->err_code
), min((int)scsi_bufflen(srb
), 1), srb
);
381 scsi_set_resid(srb
, scsi_bufflen(srb
) - 1);
383 return STATUS_SUCCESS
;
386 int spi_set_parameter(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
388 struct spi_info
*spi
= &(chip
->spi
);
390 spi_set_err_code(chip
, SPI_NO_ERR
);
393 spi
->spi_clock
= ((u16
)(srb
->cmnd
[8]) << 8) | srb
->cmnd
[9];
395 spi
->spi_clock
= srb
->cmnd
[3];
397 spi
->clk_div
= ((u16
)(srb
->cmnd
[4]) << 8) | srb
->cmnd
[5];
398 spi
->write_en
= srb
->cmnd
[6];
400 RTSX_DEBUGP("spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
401 spi
->spi_clock
, spi
->clk_div
, spi
->write_en
);
403 return STATUS_SUCCESS
;
406 int spi_read_flash_id(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
412 spi_set_err_code(chip
, SPI_NO_ERR
);
414 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
416 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
417 TRACE_RET(chip
, STATUS_FAIL
);
420 retval
= spi_set_init_para(chip
);
421 if (retval
!= STATUS_SUCCESS
) {
422 spi_set_err_code(chip
, SPI_HW_ERR
);
423 TRACE_RET(chip
, STATUS_FAIL
);
428 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
430 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, srb
->cmnd
[3]);
431 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, srb
->cmnd
[4]);
432 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, srb
->cmnd
[5]);
433 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, srb
->cmnd
[6]);
434 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
435 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, srb
->cmnd
[7]);
436 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, srb
->cmnd
[8]);
440 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
441 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
443 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
444 0xFF, SPI_TRANSFER0_START
| SPI_C_MODE0
);
448 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
449 0xFF, SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
451 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
452 0xFF, SPI_TRANSFER0_START
| SPI_CDI_MODE0
);
456 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
458 retval
= rtsx_send_cmd(chip
, 0, 100);
460 rtsx_clear_spi_error(chip
);
461 spi_set_err_code(chip
, SPI_HW_ERR
);
462 TRACE_RET(chip
, STATUS_FAIL
);
466 buf
= kmalloc(len
, GFP_KERNEL
);
468 TRACE_RET(chip
, STATUS_ERROR
);
470 retval
= rtsx_read_ppbuf(chip
, buf
, len
);
471 if (retval
!= STATUS_SUCCESS
) {
472 spi_set_err_code(chip
, SPI_READ_ERR
);
474 TRACE_RET(chip
, STATUS_FAIL
);
477 rtsx_stor_set_xfer_buf(buf
, scsi_bufflen(srb
), srb
);
478 scsi_set_resid(srb
, 0);
483 return STATUS_SUCCESS
;
486 int spi_read_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
489 unsigned int index
= 0, offset
= 0;
495 spi_set_err_code(chip
, SPI_NO_ERR
);
498 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5]) << 8) | srb
->cmnd
[6];
499 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
500 slow_read
= srb
->cmnd
[9];
502 retval
= spi_set_init_para(chip
);
503 if (retval
!= STATUS_SUCCESS
) {
504 spi_set_err_code(chip
, SPI_HW_ERR
);
505 TRACE_RET(chip
, STATUS_FAIL
);
508 buf
= kmalloc(SF_PAGE_LEN
, GFP_KERNEL
);
510 TRACE_RET(chip
, STATUS_ERROR
);
513 u16 pagelen
= SF_PAGE_LEN
- (u8
)addr
;
520 trans_dma_enable(DMA_FROM_DEVICE
, chip
, 256, DMA_256
);
522 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
525 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
526 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
527 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 16));
528 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
530 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)addr
);
531 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 8));
532 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR3
, 0xFF, (u8
)(addr
>> 16));
533 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_32
);
536 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, (u8
)(pagelen
>> 8));
537 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, (u8
)pagelen
);
539 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
540 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
542 rtsx_send_cmd_no_wait(chip
);
544 retval
= rtsx_transfer_data(chip
, 0, buf
, pagelen
, 0, DMA_FROM_DEVICE
, 10000);
547 rtsx_clear_spi_error(chip
);
548 spi_set_err_code(chip
, SPI_HW_ERR
);
549 TRACE_RET(chip
, STATUS_FAIL
);
552 rtsx_stor_access_xfer_buf(buf
, pagelen
, srb
, &index
, &offset
, TO_XFER_BUF
);
558 scsi_set_resid(srb
, 0);
561 return STATUS_SUCCESS
;
564 int spi_write_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
567 u8 ins
, program_mode
;
571 unsigned int index
= 0, offset
= 0;
573 spi_set_err_code(chip
, SPI_NO_ERR
);
576 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5]) << 8) | srb
->cmnd
[6];
577 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
578 program_mode
= srb
->cmnd
[9];
580 retval
= spi_set_init_para(chip
);
581 if (retval
!= STATUS_SUCCESS
) {
582 spi_set_err_code(chip
, SPI_HW_ERR
);
583 TRACE_RET(chip
, STATUS_FAIL
);
586 if (program_mode
== BYTE_PROGRAM
) {
587 buf
= kmalloc(4, GFP_KERNEL
);
589 TRACE_RET(chip
, STATUS_ERROR
);
592 retval
= sf_enable_write(chip
, SPI_WREN
);
593 if (retval
!= STATUS_SUCCESS
) {
595 TRACE_RET(chip
, STATUS_FAIL
);
598 rtsx_stor_access_xfer_buf(buf
, 1, srb
, &index
, &offset
, FROM_XFER_BUF
);
602 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
603 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF, buf
[0]);
604 sf_program(chip
, ins
, 1, addr
, 1);
606 retval
= rtsx_send_cmd(chip
, 0, 100);
609 rtsx_clear_spi_error(chip
);
610 spi_set_err_code(chip
, SPI_HW_ERR
);
611 TRACE_RET(chip
, STATUS_FAIL
);
614 retval
= sf_polling_status(chip
, 100);
615 if (retval
!= STATUS_SUCCESS
) {
617 TRACE_RET(chip
, STATUS_FAIL
);
626 } else if (program_mode
== AAI_PROGRAM
) {
629 retval
= sf_enable_write(chip
, SPI_WREN
);
630 if (retval
!= STATUS_SUCCESS
)
631 TRACE_RET(chip
, STATUS_FAIL
);
633 buf
= kmalloc(4, GFP_KERNEL
);
635 TRACE_RET(chip
, STATUS_ERROR
);
638 rtsx_stor_access_xfer_buf(buf
, 1, srb
, &index
, &offset
, FROM_XFER_BUF
);
642 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
643 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF, buf
[0]);
645 sf_program(chip
, ins
, 1, addr
, 1);
648 sf_program(chip
, ins
, 0, 0, 1);
651 retval
= rtsx_send_cmd(chip
, 0, 100);
654 rtsx_clear_spi_error(chip
);
655 spi_set_err_code(chip
, SPI_HW_ERR
);
656 TRACE_RET(chip
, STATUS_FAIL
);
659 retval
= sf_polling_status(chip
, 100);
660 if (retval
!= STATUS_SUCCESS
) {
662 TRACE_RET(chip
, STATUS_FAIL
);
670 retval
= sf_disable_write(chip
, SPI_WRDI
);
671 if (retval
!= STATUS_SUCCESS
)
672 TRACE_RET(chip
, STATUS_FAIL
);
674 retval
= sf_polling_status(chip
, 100);
675 if (retval
!= STATUS_SUCCESS
)
676 TRACE_RET(chip
, STATUS_FAIL
);
677 } else if (program_mode
== PAGE_PROGRAM
) {
678 buf
= kmalloc(SF_PAGE_LEN
, GFP_KERNEL
);
680 TRACE_RET(chip
, STATUS_NOMEM
);
683 u16 pagelen
= SF_PAGE_LEN
- (u8
)addr
;
688 retval
= sf_enable_write(chip
, SPI_WREN
);
689 if (retval
!= STATUS_SUCCESS
) {
691 TRACE_RET(chip
, STATUS_FAIL
);
696 trans_dma_enable(DMA_TO_DEVICE
, chip
, 256, DMA_256
);
697 sf_program(chip
, ins
, 1, addr
, pagelen
);
699 rtsx_send_cmd_no_wait(chip
);
701 rtsx_stor_access_xfer_buf(buf
, pagelen
, srb
, &index
, &offset
, FROM_XFER_BUF
);
703 retval
= rtsx_transfer_data(chip
, 0, buf
, pagelen
, 0, DMA_TO_DEVICE
, 100);
706 rtsx_clear_spi_error(chip
);
707 spi_set_err_code(chip
, SPI_HW_ERR
);
708 TRACE_RET(chip
, STATUS_FAIL
);
711 retval
= sf_polling_status(chip
, 100);
712 if (retval
!= STATUS_SUCCESS
) {
714 TRACE_RET(chip
, STATUS_FAIL
);
723 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
724 TRACE_RET(chip
, STATUS_FAIL
);
727 return STATUS_SUCCESS
;
730 int spi_erase_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
736 spi_set_err_code(chip
, SPI_NO_ERR
);
739 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5]) << 8) | srb
->cmnd
[6];
740 erase_mode
= srb
->cmnd
[9];
742 retval
= spi_set_init_para(chip
);
743 if (retval
!= STATUS_SUCCESS
) {
744 spi_set_err_code(chip
, SPI_HW_ERR
);
745 TRACE_RET(chip
, STATUS_FAIL
);
748 if (erase_mode
== PAGE_ERASE
) {
749 retval
= sf_enable_write(chip
, SPI_WREN
);
750 if (retval
!= STATUS_SUCCESS
)
751 TRACE_RET(chip
, STATUS_FAIL
);
753 retval
= sf_erase(chip
, ins
, 1, addr
);
754 if (retval
!= STATUS_SUCCESS
)
755 TRACE_RET(chip
, STATUS_FAIL
);
756 } else if (erase_mode
== CHIP_ERASE
) {
757 retval
= sf_enable_write(chip
, SPI_WREN
);
758 if (retval
!= STATUS_SUCCESS
)
759 TRACE_RET(chip
, STATUS_FAIL
);
761 retval
= sf_erase(chip
, ins
, 0, 0);
762 if (retval
!= STATUS_SUCCESS
)
763 TRACE_RET(chip
, STATUS_FAIL
);
765 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
766 TRACE_RET(chip
, STATUS_FAIL
);
769 return STATUS_SUCCESS
;
772 int spi_write_flash_status(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
775 u8 ins
, status
, ewsr
;
778 status
= srb
->cmnd
[4];
781 retval
= spi_set_init_para(chip
);
782 if (retval
!= STATUS_SUCCESS
) {
783 spi_set_err_code(chip
, SPI_HW_ERR
);
784 TRACE_RET(chip
, STATUS_FAIL
);
787 retval
= sf_enable_write(chip
, ewsr
);
788 if (retval
!= STATUS_SUCCESS
)
789 TRACE_RET(chip
, STATUS_FAIL
);
793 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
795 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
796 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
797 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, 0);
798 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, 1);
799 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF, status
);
800 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF, SPI_TRANSFER0_START
| SPI_CDO_MODE0
);
801 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
803 retval
= rtsx_send_cmd(chip
, 0, 100);
804 if (retval
!= STATUS_SUCCESS
) {
805 rtsx_clear_spi_error(chip
);
806 spi_set_err_code(chip
, SPI_HW_ERR
);
807 TRACE_RET(chip
, STATUS_FAIL
);
810 return STATUS_SUCCESS
;