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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jlbec...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rtl8192su / r8192S_phy.c
1 /******************************************************************************
2
3 (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
4
5 Module: hal8192sphy.c
6
7 Note: Merge 92SE/SU PHY config as below
8 1. BB register R/W API
9 2. RF register R/W API
10 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
11 3. Power setting API
12 4. Channel switch API
13 5. Initial gain switch API.
14 6. Other BB/MAC/RF API.
15
16 Function: PHY: Extern function, phy: local function
17
18 Export: PHY_FunctionName
19
20 Abbrev: NONE
21
22 History:
23 Data Who Remark
24 08/08/2008 MHC 1. Port from 9x series phycfg.c
25 2. Reorganize code arch and ad description.
26 3. Collect similar function.
27 4. Seperate extern/local API.
28 08/12/2008 MHC We must merge or move USB PHY relative function later.
29 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!)
30 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register
31 area to map with EEPROM/EFUSE tx pwr index.
32
33 ******************************************************************************/
34 #include "r8192U.h"
35 #include "r8192U_dm.h"
36 #include "r8192S_rtl6052.h"
37
38 #include "r8192S_hw.h"
39 #include "r8192S_phy.h"
40 #include "r8192S_phyreg.h"
41 #include "r8192SU_HWImg.h"
42
43 #include "ieee80211/dot11d.h"
44
45 /*---------------------------Define Local Constant---------------------------*/
46 /* Channel switch:The size of command tables for switch channel*/
47 #define MAX_PRECMD_CNT 16
48 #define MAX_RFDEPENDCMD_CNT 16
49 #define MAX_POSTCMD_CNT 16
50 #define MAX_DOZE_WAITING_TIMES_9x 64
51
52 /*------------------------Define local variable------------------------------*/
53 // 2004-05-11
54
55 static u32
56 phy_CalculateBitShift(u32 BitMask);
57 static RT_STATUS
58 phy_ConfigMACWithHeaderFile(struct net_device* dev);
59 static void
60 phy_InitBBRFRegisterDefinition(struct net_device* dev);
61 static RT_STATUS
62 phy_BB8192S_Config_ParaFile(struct net_device* dev);
63 static RT_STATUS
64 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
65 static bool
66 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
67 void
68 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
69 void
70 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
71 void
72 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
73 static void
74 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
75 static bool
76 phy_SwChnlStepByStep(
77 struct net_device* dev,
78 u8 channel,
79 u8 *stage,
80 u8 *step,
81 u32 *delay
82 );
83 static RT_STATUS
84 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
85 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
86 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
87 void phy_SetFwCmdIOCallback(struct net_device* dev);
88
89 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
90 //
91 // Description:
92 // Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
93 //
94 // Assumption:
95 // - Only use on RTL8192S USB interface.
96 // - PASSIVE LEVEL
97 //
98 // Created by Roger, 2008.09.06.
99 //
100 //use in phy only
101 u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr)
102 {
103 struct r8192_priv *priv = ieee80211_priv(dev);
104 u32 ReturnValue = 0xffffffff;
105 u8 PollingCnt = 50;
106 u8 BBWaitCounter = 0;
107
108
109 //
110 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
111 // We have to make sure that previous BB I/O has been done.
112 // 2008.08.20.
113 //
114 while(priv->bChangeBBInProgress)
115 {
116 BBWaitCounter ++;
117 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
118 msleep(1); // 1 ms
119
120 // Wait too long, return FALSE to avoid to be stuck here.
121 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
122 {
123 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
124 return ReturnValue;
125 }
126 }
127
128 priv->bChangeBBInProgress = true;
129
130 read_nic_dword(dev, RegAddr);
131
132 do
133 {// Make sure that access could be done.
134 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
135 break;
136 }while( --PollingCnt );
137
138 if(PollingCnt == 0)
139 {
140 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
141 }
142 else
143 {
144 // Data FW read back.
145 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
146 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
147 }
148
149 priv->bChangeBBInProgress = false;
150
151 return ReturnValue;
152 }
153
154
155
156 //
157 // Description:
158 // Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
159 //
160 // Assumption:
161 // - Only use on RTL8192S USB interface.
162 // - PASSIVE LEVEL
163 //
164 // Created by Roger, 2008.09.06.
165 //
166 //use in phy only
167 void
168 phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data)
169 {
170 struct r8192_priv *priv = ieee80211_priv(dev);
171 u8 BBWaitCounter = 0;
172
173 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
174
175 //
176 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
177 // We have to make sure that previous BB I/O has been done.
178 // 2008.08.20.
179 //
180 while(priv->bChangeBBInProgress)
181 {
182 BBWaitCounter ++;
183 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
184 msleep(1); // 1 ms
185
186 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
187 {
188 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
189 return;
190 }
191 }
192
193 priv->bChangeBBInProgress = true;
194 //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
195 write_nic_dword(dev, RegAddr, Data);
196
197 priv->bChangeBBInProgress = false;
198 }
199
200
201
202 //
203 // Description:
204 // RF read by 4181 to make sure that operation could be done in unlimited cycle.
205 //
206 // Assumption:
207 // - Only use on RTL8192S USB interface.
208 // - PASSIVE LEVEL
209 // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
210 //
211 // Created by Roger, 2008.09.06.
212 //
213 //use in phy only
214 u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
215 {
216
217 struct r8192_priv *priv = ieee80211_priv(dev);
218 //u32 value = 0, ReturnValue = 0;
219 u32 ReturnValue = 0;
220 //u32 tmplong,tmplong2;
221 u8 PollingCnt = 50;
222 u8 RFWaitCounter = 0;
223
224
225 //
226 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
227 // We have to make sure that previous RF I/O has been done.
228 // 2008.08.20.
229 //
230 while(priv->bChangeRFInProgress)
231 {
232 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
233 //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318
234 down(&priv->rf_sem);
235
236 RFWaitCounter ++;
237 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
238 msleep(1); // 1 ms
239
240 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
241 {
242 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
243 return 0xffffffff;
244 }
245 else
246 {
247 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
248 }
249 }
250
251 priv->bChangeRFInProgress = true;
252 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
253
254
255 Offset &= 0x3f; //RF_Offset= 0x00~0x3F
256
257 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
258 (Offset<<8)| //RF_Offset= 0x00~0x3F
259 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
260
261 do
262 {// Make sure that access could be done.
263 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
264 break;
265 }while( --PollingCnt );
266
267 // Data FW read back.
268 ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
269
270 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
271 //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318
272 up(&priv->rf_sem);
273 priv->bChangeRFInProgress = false;
274
275 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
276
277 return ReturnValue;
278
279 }
280
281
282 //
283 // Description:
284 // RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
285 //
286 // Assumption:
287 // - Only use on RTL8192S USB interface.
288 // - PASSIVE LEVEL
289 // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
290 //
291 // Created by Roger, 2008.09.06.
292 //
293 //use in phy only
294 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAddr,u32 Data)
295 {
296
297 struct r8192_priv *priv = ieee80211_priv(dev);
298 u8 PollingCnt = 50;
299 u8 RFWaitCounter = 0;
300
301
302 //
303 // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
304 // We have to make sure that previous BB I/O has been done.
305 // 2008.08.20.
306 //
307 while(priv->bChangeRFInProgress)
308 {
309 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
310 //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318
311 down(&priv->rf_sem);
312
313 RFWaitCounter ++;
314 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
315 msleep(1); // 1 ms
316
317 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
318 {
319 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
320 return;
321 }
322 else
323 {
324 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
325 }
326 }
327
328 priv->bChangeRFInProgress = true;
329 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
330
331
332 RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
333
334 write_nic_dword(dev, RF_BB_CMD_DATA, Data);
335 write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
336 (RegAddr<<8)| //RF_Offset= 0x00~0x3F
337 (eRFPath<<16)); //RF_Path = 0(A) or 1(B)
338
339 do
340 {// Make sure that access could be done.
341 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
342 break;
343 }while( --PollingCnt );
344
345 if(PollingCnt == 0)
346 {
347 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
348 }
349
350 //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
351 //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318
352 up(&priv->rf_sem);
353 priv->bChangeRFInProgress = false;
354
355 }
356
357
358 /*---------------------Define local function prototype-----------------------*/
359
360
361 /*----------------------------Function Body----------------------------------*/
362 //
363 // 1. BB register R/W API
364 //
365 /**
366 * Function: PHY_QueryBBReg
367 *
368 * OverView: Read "sepcific bits" from BB register
369 *
370 * Input:
371 * PADAPTER Adapter,
372 * u32 RegAddr, //The target address to be readback
373 * u32 BitMask //The target bit position in the target address
374 * //to be readback
375 * Output: None
376 * Return: u32 Data //The readback register value
377 * Note: This function is equal to "GetRegSetting" in PHY programming guide
378 */
379 //use phy dm core 8225 8256 6052
380 //u32 PHY_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask)
381 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
382 {
383
384 u32 ReturnValue = 0, OriginalValue, BitShift;
385
386
387 RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
388
389 //
390 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
391 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
392 // infinite cycle.
393 // 2008.09.06.
394 //
395 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
396 if(IS_BB_REG_OFFSET_92S(RegAddr))
397 {
398 //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
399
400 if((RegAddr & 0x03) != 0)
401 {
402 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
403 return 0;
404 }
405
406 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
407 }
408 else
409 {
410 OriginalValue = read_nic_dword(dev, RegAddr);
411 }
412
413 BitShift = phy_CalculateBitShift(BitMask);
414 ReturnValue = (OriginalValue & BitMask) >> BitShift;
415
416 //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
417 RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
418 return (ReturnValue);
419 }
420
421 /**
422 * Function: PHY_SetBBReg
423 *
424 * OverView: Write "Specific bits" to BB register (page 8~)
425 *
426 * Input:
427 * PADAPTER Adapter,
428 * u32 RegAddr, //The target address to be modified
429 * u32 BitMask //The target bit position in the target address
430 * //to be modified
431 * u32 Data //The new register value in the target bit position
432 * //of the target address
433 *
434 * Output: None
435 * Return: None
436 * Note: This function is equal to "PutRegSetting" in PHY programming guide
437 */
438 //use phy dm core 8225 8256
439 //void PHY_SetBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask, u32 Data )
440 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
441 {
442 u32 OriginalValue, BitShift, NewValue;
443
444
445 RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
446
447 //
448 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
449 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
450 // infinite cycle.
451 // 2008.09.06.
452 //
453 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
454 if(IS_BB_REG_OFFSET_92S(RegAddr))
455 {
456 if((RegAddr & 0x03) != 0)
457 {
458 printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
459 return;
460 }
461
462 if(BitMask!= bMaskDWord)
463 {//if not "double word" write
464 OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
465 BitShift = phy_CalculateBitShift(BitMask);
466 NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
467 phy_SetUsbBBReg(dev, RegAddr, NewValue);
468 }else
469 phy_SetUsbBBReg(dev, RegAddr, Data);
470 }
471 else
472 {
473 if(BitMask!= bMaskDWord)
474 {//if not "double word" write
475 OriginalValue = read_nic_dword(dev, RegAddr);
476 BitShift = phy_CalculateBitShift(BitMask);
477 NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
478 write_nic_dword(dev, RegAddr, NewValue);
479 }else
480 write_nic_dword(dev, RegAddr, Data);
481 }
482
483 //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
484
485 return;
486 }
487
488
489 //
490 // 2. RF register R/W API
491 //
492 /**
493 * Function: PHY_QueryRFReg
494 *
495 * OverView: Query "Specific bits" to RF register (page 8~)
496 *
497 * Input:
498 * PADAPTER Adapter,
499 * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
500 * u32 RegAddr, //The target address to be read
501 * u32 BitMask //The target bit position in the target address
502 * //to be read
503 *
504 * Output: None
505 * Return: u32 Readback value
506 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
507 */
508 //in dm 8256 and phy
509 //u32 PHY_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
510 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
511 {
512 u32 Original_Value, Readback_Value, BitShift;//, flags;
513 struct r8192_priv *priv = ieee80211_priv(dev);
514
515
516 RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
517
518 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
519 {
520 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
521 return 0;
522 }
523
524 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
525 {
526 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
527 return 0;
528 }
529
530 /* 2008/01/17 MH We get and release spin lock when reading RF register. */
531 //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
532 //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113
533 down(&priv->rf_sem);
534 //
535 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
536 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
537 // infinite cycle.
538 // 2008.09.06.
539 //
540 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
541 //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
542 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
543
544 BitShift = phy_CalculateBitShift(BitMask);
545 Readback_Value = (Original_Value & BitMask) >> BitShift;
546 //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113
547 up(&priv->rf_sem);
548 //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
549
550 //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
551
552 return (Readback_Value);
553 }
554
555 /**
556 * Function: PHY_SetRFReg
557 *
558 * OverView: Write "Specific bits" to RF register (page 8~)
559 *
560 * Input:
561 * PADAPTER Adapter,
562 * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
563 * u32 RegAddr, //The target address to be modified
564 * u32 BitMask //The target bit position in the target address
565 * //to be modified
566 * u32 Data //The new register Data in the target bit position
567 * //of the target address
568 *
569 * Output: None
570 * Return: None
571 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
572 */
573 //use phy 8225 8256
574 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask,u32 Data )
575 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
576 {
577
578 struct r8192_priv *priv = ieee80211_priv(dev);
579 u32 Original_Value, BitShift, New_Value;//, flags;
580
581 RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
582 RegAddr, BitMask, Data, eRFPath);
583
584 if (!((priv->rf_pathmap >> eRFPath) & 0x1))
585 {
586 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
587 return ;
588 }
589 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
590 {
591 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
592 return;
593 }
594
595 /* 2008/01/17 MH We get and release spin lock when writing RF register. */
596 //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
597 //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113
598 down(&priv->rf_sem);
599 //
600 // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
601 // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
602 // infinite cycle.
603 // 2008.09.06.
604 //
605 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
606 //if(RT_USB_CANNOT_IO(Adapter)) return;
607
608 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
609 {
610 Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
611 BitShift = phy_CalculateBitShift(BitMask);
612 New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
613 phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
614 }
615 else
616 phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
617 //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
618 //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113
619 up(&priv->rf_sem);
620 //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
621 RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
622 RegAddr, BitMask, Data, eRFPath);
623
624 }
625
626 /**
627 * Function: phy_CalculateBitShift
628 *
629 * OverView: Get shifted position of the BitMask
630 *
631 * Input:
632 * u32 BitMask,
633 *
634 * Output: none
635 * Return: u32 Return the shift bit bit position of the mask
636 */
637 //use in phy only
638 static u32 phy_CalculateBitShift(u32 BitMask)
639 {
640 u32 i;
641
642 for(i=0; i<=31; i++)
643 {
644 if ( ((BitMask>>i) & 0x1 ) == 1)
645 break;
646 }
647
648 return (i);
649 }
650
651
652 //
653 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
654 //
655 /*-----------------------------------------------------------------------------
656 * Function: PHY_MACConfig8192S
657 *
658 * Overview: Condig MAC by header file or parameter file.
659 *
660 * Input: NONE
661 *
662 * Output: NONE
663 *
664 * Return: NONE
665 *
666 * Revised History:
667 * When Who Remark
668 * 08/12/2008 MHC Create Version 0.
669 *
670 *---------------------------------------------------------------------------*/
671 //adapter_start
672 extern bool PHY_MACConfig8192S(struct net_device* dev)
673 {
674 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
675
676 //
677 // Config MAC
678 //
679 rtStatus = phy_ConfigMACWithHeaderFile(dev);
680 return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
681
682 }
683
684 //adapter_start
685 extern bool
686 PHY_BBConfig8192S(struct net_device* dev)
687 {
688 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
689
690 u8 PathMap = 0, index = 0, rf_num = 0;
691 struct r8192_priv *priv = ieee80211_priv(dev);
692 phy_InitBBRFRegisterDefinition(dev);
693
694 //
695 // Config BB and AGC
696 //
697 //switch( Adapter->MgntInfo.bRegHwParaFile )
698 //{
699 // case 0:
700 // phy_BB8190_Config_HardCode(dev);
701 // break;
702
703 // case 1:
704 rtStatus = phy_BB8192S_Config_ParaFile(dev);
705 // break;
706
707 // case 2:
708 // Partial Modify.
709 // phy_BB8190_Config_HardCode(dev);
710 // phy_BB8192S_Config_ParaFile(dev);
711 // break;
712
713 // default:
714 // phy_BB8190_Config_HardCode(dev);
715 // break;
716 //}
717 PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
718 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
719 priv->rf_pathmap = PathMap;
720 for(index = 0; index<4; index++)
721 {
722 if((PathMap>>index)&0x1)
723 rf_num++;
724 }
725
726 if((priv->rf_type==RF_1T1R && rf_num!=1) ||
727 (priv->rf_type==RF_1T2R && rf_num!=2) ||
728 (priv->rf_type==RF_2T2R && rf_num!=2) ||
729 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
730 (priv->rf_type==RF_2T4R && rf_num!=4))
731 {
732 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
733 }
734 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
735 }
736
737 //adapter_start
738 extern bool
739 PHY_RFConfig8192S(struct net_device* dev)
740 {
741 struct r8192_priv *priv = ieee80211_priv(dev);
742 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
743
744 //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
745
746 //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
747 priv->rf_chip = RF_6052;
748
749 //
750 // RF config
751 //
752 switch(priv->rf_chip)
753 {
754 case RF_8225:
755 case RF_6052:
756 rtStatus = PHY_RF6052_Config(dev);
757 break;
758
759 case RF_8256:
760 //rtStatus = PHY_RF8256_Config(dev);
761 break;
762
763 case RF_8258:
764 break;
765
766 case RF_PSEUDO_11N:
767 //rtStatus = PHY_RF8225_Config(dev);
768 break;
769 default:
770 break;
771 }
772
773 return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
774 }
775
776
777 // Joseph test: new initialize order!!
778 // Test only!! This part need to be re-organized.
779 // Now it is just for 8256.
780 //use in phy only
781 #ifdef TO_DO_LIST
782 static RT_STATUS
783 phy_BB8190_Config_HardCode(struct net_device* dev)
784 {
785 //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
786 return RT_STATUS_SUCCESS;
787 }
788 #endif
789
790 /*-----------------------------------------------------------------------------
791 * Function: phy_SetBBtoDiffRFWithHeaderFile()
792 *
793 * Overview: This function
794 *
795 *
796 * Input: PADAPTER Adapter
797 * u1Byte ConfigType 0 => PHY_CONFIG
798 *
799 * Output: NONE
800 *
801 * Return: RT_STATUS_SUCCESS: configuration file exist
802 * When Who Remark
803 * 2008/11/10 tynli
804 * use in phy only
805 *---------------------------------------------------------------------------*/
806 static RT_STATUS
807 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
808 {
809 int i;
810 struct r8192_priv *priv = ieee80211_priv(dev);
811 u32* Rtl819XPHY_REGArraytoXTXR_Table;
812 u16 PHY_REGArraytoXTXRLen;
813
814 //#if (HAL_CODE_BASE != RTL8192_S)
815
816 if(priv->rf_type == RF_1T1R)
817 {
818 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
819 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
820 }
821 else if(priv->rf_type == RF_1T2R)
822 {
823 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
824 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
825 }
826 //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
827 //{
828 // Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
829 // PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
830 //}
831 else
832 {
833 return RT_STATUS_FAILURE;
834 }
835
836 if(ConfigType == BaseBand_Config_PHY_REG)
837 {
838 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
839 {
840 if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
841 mdelay(50);
842 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
843 mdelay(5);
844 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
845 mdelay(1);
846 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
847 udelay(50);
848 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
849 udelay(5);
850 else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
851 udelay(1);
852 rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
853 //RT_TRACE(COMP_SEND,
854 //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
855 //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
856 }
857 }
858 else {
859 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
860 }
861 //#endif // #if (HAL_CODE_BASE != RTL8192_S)
862 return RT_STATUS_SUCCESS;
863 }
864
865
866 //use in phy only
867 static RT_STATUS
868 phy_BB8192S_Config_ParaFile(struct net_device* dev)
869 {
870 struct r8192_priv *priv = ieee80211_priv(dev);
871 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
872 //u8 u2RegValue;
873 //u16 u4RegValue;
874 //char szBBRegFile[] = RTL819X_PHY_REG;
875 //char szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
876 //char szBBRegPgFile[] = RTL819X_PHY_REG_PG;
877 //char szAGCTableFile[] = RTL819X_AGC_TAB;
878 //char szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
879 //char szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
880
881 RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
882
883 //
884 // 1. Read PHY_REG.TXT BB INIT!!
885 // We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R
886 //
887 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
888 priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
889 {
890 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
891 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
892 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
893 //so we should reconfig BB reg with the right PHY parameters.
894 rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
895 }
896 }else
897 rtStatus = RT_STATUS_FAILURE;
898
899 if(rtStatus != RT_STATUS_SUCCESS){
900 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
901 goto phy_BB8190_Config_ParaFile_Fail;
902 }
903
904 //
905 // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
906 //
907 if (priv->AutoloadFailFlag == false)
908 {
909 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
910 }
911 if(rtStatus != RT_STATUS_SUCCESS){
912 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
913 goto phy_BB8190_Config_ParaFile_Fail;
914 }
915
916 //
917 // 3. BB AGC table Initialization
918 //
919 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
920
921 if(rtStatus != RT_STATUS_SUCCESS){
922 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
923 goto phy_BB8190_Config_ParaFile_Fail;
924 }
925
926
927 // Check if the CCK HighPower is turned ON.
928 // This is used to calculate PWDB.
929 priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
930
931
932 phy_BB8190_Config_ParaFile_Fail:
933 return rtStatus;
934 }
935
936 /*-----------------------------------------------------------------------------
937 * Function: phy_ConfigMACWithHeaderFile()
938 *
939 * Overview: This function read BB parameters from Header file we gen, and do register
940 * Read/Write
941 *
942 * Input: PADAPTER Adapter
943 * char* pFileName
944 *
945 * Output: NONE
946 *
947 * Return: RT_STATUS_SUCCESS: configuration file exist
948 *
949 * Note: The format of MACPHY_REG.txt is different from PHY and RF.
950 * [Register][Mask][Value]
951 *---------------------------------------------------------------------------*/
952 //use in phy only
953 static RT_STATUS
954 phy_ConfigMACWithHeaderFile(struct net_device* dev)
955 {
956 u32 i = 0;
957 u32 ArrayLength = 0;
958 u32* ptrArray;
959 //struct r8192_priv *priv = ieee80211_priv(dev);
960
961 //#if (HAL_CODE_BASE != RTL8192_S)
962 /*if(Adapter->bInHctTest)
963 {
964 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
965 ArrayLength = MACPHY_ArrayLengthDTM;
966 ptrArray = Rtl819XMACPHY_ArrayDTM;
967 }
968 else if(pHalData->bTXPowerDataReadFromEEPORM)
969 {
970 // RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
971 // ArrayLength = MACPHY_Array_PGLength;
972 // ptrArray = Rtl819XMACPHY_Array_PG;
973
974 }else*/
975 { //2008.11.06 Modified by tynli.
976 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
977 ArrayLength = MAC_2T_ArrayLength;
978 ptrArray = Rtl819XMAC_Array;
979 }
980
981 /*for(i = 0 ;i < ArrayLength;i=i+3){
982 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
983 if(ptrArray[i] == 0x318)
984 {
985 ptrArray[i+2] = 0x00000800;
986 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
987 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
988 }
989 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
990 }*/
991 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
992 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
993 }
994 //#endif
995 return RT_STATUS_SUCCESS;
996 }
997
998 /*-----------------------------------------------------------------------------
999 * Function: phy_ConfigBBWithHeaderFile()
1000 *
1001 * Overview: This function read BB parameters from general file format, and do register
1002 * Read/Write
1003 *
1004 * Input: PADAPTER Adapter
1005 * u8 ConfigType 0 => PHY_CONFIG
1006 * 1 =>AGC_TAB
1007 *
1008 * Output: NONE
1009 *
1010 * Return: RT_STATUS_SUCCESS: configuration file exist
1011 *
1012 *---------------------------------------------------------------------------*/
1013 //use in phy only
1014 static RT_STATUS
1015 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1016 {
1017 int i;
1018 //u8 ArrayLength;
1019 u32* Rtl819XPHY_REGArray_Table;
1020 u32* Rtl819XAGCTAB_Array_Table;
1021 u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
1022 //struct r8192_priv *priv = ieee80211_priv(dev);
1023 //#if (HAL_CODE_BASE != RTL8192_S)
1024 /*if(Adapter->bInHctTest)
1025 {
1026
1027 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1028 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1029
1030 if(pHalData->RF_Type == RF_2T4R)
1031 {
1032 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1033 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1034 }
1035 else if (pHalData->RF_Type == RF_1T2R)
1036 {
1037 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1038 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1039 }
1040
1041 }
1042 else
1043 */
1044 //{
1045 //
1046 // 2008.11.06 Modified by tynli.
1047 //
1048 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1049 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1050 PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1051 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1052 //}
1053
1054 if(ConfigType == BaseBand_Config_PHY_REG)
1055 {
1056 for(i=0;i<PHY_REGArrayLen;i=i+2)
1057 {
1058 if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1059 mdelay(50);
1060 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1061 mdelay(5);
1062 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1063 mdelay(1);
1064 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1065 udelay(50);
1066 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1067 udelay(5);
1068 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1069 udelay(1);
1070 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1071 //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1072
1073 }
1074 }
1075 else if(ConfigType == BaseBand_Config_AGC_TAB){
1076 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1077 {
1078 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1079 }
1080 }
1081 //#endif // #if (HAL_CODE_BASE != RTL8192_S)
1082 return RT_STATUS_SUCCESS;
1083 }
1084
1085 /*-----------------------------------------------------------------------------
1086 * Function: phy_ConfigBBWithPgHeaderFile
1087 *
1088 * Overview: Config PHY_REG_PG array
1089 *
1090 * Input: NONE
1091 *
1092 * Output: NONE
1093 *
1094 * Return: NONE
1095 *
1096 * Revised History:
1097 * When Who Remark
1098 * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
1099 * 11/10/2008 tynli Modify to mew files.
1100 //use in phy only
1101 *---------------------------------------------------------------------------*/
1102 static RT_STATUS
1103 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1104 {
1105 int i;
1106 //u8 ArrayLength;
1107 u32* Rtl819XPHY_REGArray_Table_PG;
1108 u16 PHY_REGArrayPGLen;
1109 //struct r8192_priv *priv = ieee80211_priv(dev);
1110 //#if (HAL_CODE_BASE != RTL8192_S)
1111 // Default: pHalData->RF_Type = RF_2T2R.
1112
1113 PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1114 Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1115
1116 if(ConfigType == BaseBand_Config_PHY_REG)
1117 {
1118 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1119 {
1120 if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1121 mdelay(50);
1122 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1123 mdelay(5);
1124 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1125 mdelay(1);
1126 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1127 udelay(50);
1128 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1129 udelay(5);
1130 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1131 udelay(1);
1132 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1133 //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1134 // Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1135 }
1136 }else{
1137 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1138 }
1139 return RT_STATUS_SUCCESS;
1140
1141 } /* phy_ConfigBBWithPgHeaderFile */
1142
1143 /*-----------------------------------------------------------------------------
1144 * Function: PHY_ConfigRFWithHeaderFile()
1145 *
1146 * Overview: This function read RF parameters from general file format, and do RF 3-wire
1147 *
1148 * Input: PADAPTER Adapter
1149 * char* pFileName
1150 * RF90_RADIO_PATH_E eRFPath
1151 *
1152 * Output: NONE
1153 *
1154 * Return: RT_STATUS_SUCCESS: configuration file exist
1155 *
1156 * Note: Delay may be required for RF configuration
1157 *---------------------------------------------------------------------------*/
1158 //in 8256 phy_RF8256_Config_ParaFile only
1159 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1160 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1161 {
1162
1163 struct r8192_priv *priv = ieee80211_priv(dev);
1164 int i;
1165 //u32* pRFArray;
1166 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1167 u32 *Rtl819XRadioA_Array_Table;
1168 u32 *Rtl819XRadioB_Array_Table;
1169 //u32* Rtl819XRadioC_Array_Table;
1170 //u32* Rtl819XRadioD_Array_Table;
1171 u16 RadioA_ArrayLen,RadioB_ArrayLen;
1172
1173 { //2008.11.06 Modified by tynli
1174 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1175 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1176 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1177 RadioB_ArrayLen = RadioB_ArrayLength;
1178 }
1179
1180 if( priv->rf_type == RF_2T2R_GREEN )
1181 {
1182 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1183 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1184 }
1185 else
1186 {
1187 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1188 RadioB_ArrayLen = RadioB_ArrayLength;
1189 }
1190
1191 rtStatus = RT_STATUS_SUCCESS;
1192
1193 // When initialization, we want the delay function(mdelay(), delay_us()
1194 // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1195 // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1196 // to run at Dispatch level to achive it.
1197 //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1198
1199 switch(eRFPath){
1200 case RF90_PATH_A:
1201 for(i = 0;i<RadioA_ArrayLen; i=i+2){
1202 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1203 { // Deay specific ms. Only RF configuration require delay.
1204 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1205 mdelay(1000);
1206 }
1207 else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1208 mdelay(5);
1209 else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1210 mdelay(1);
1211 else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1212 udelay(50);
1213 //PlatformStallExecution(50);
1214 else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1215 udelay(5);
1216 else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1217 udelay(1);
1218 else
1219 {
1220 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1221 }
1222 }
1223 break;
1224 case RF90_PATH_B:
1225 for(i = 0;i<RadioB_ArrayLen; i=i+2){
1226 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1227 { // Deay specific ms. Only RF configuration require delay.
1228 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1229 mdelay(1000);
1230 }
1231 else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1232 mdelay(5);
1233 else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1234 mdelay(1);
1235 else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1236 udelay(50);
1237 else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1238 udelay(5);
1239 else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1240 udelay(1);
1241 else
1242 {
1243 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1244 }
1245 }
1246 break;
1247 case RF90_PATH_C:
1248 break;
1249 case RF90_PATH_D:
1250 break;
1251 default:
1252 break;
1253 }
1254
1255 return rtStatus;
1256
1257 }
1258
1259 /*-----------------------------------------------------------------------------
1260 * Function: PHY_CheckBBAndRFOK()
1261 *
1262 * Overview: This function is write register and then readback to make sure whether
1263 * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1264 *
1265 * Input: PADAPTER Adapter
1266 * HW90_BLOCK_E CheckBlock
1267 * RF90_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
1268 *
1269 * Output: NONE
1270 *
1271 * Return: RT_STATUS_SUCCESS: PHY is OK
1272 *
1273 * Note: This function may be removed in the ASIC
1274 *---------------------------------------------------------------------------*/
1275 //in 8256 phy_RF8256_Config_HardCode
1276 //but we don't use it temp
1277 RT_STATUS
1278 PHY_CheckBBAndRFOK(
1279 struct net_device* dev,
1280 HW90_BLOCK_E CheckBlock,
1281 RF90_RADIO_PATH_E eRFPath
1282 )
1283 {
1284 //struct r8192_priv *priv = ieee80211_priv(dev);
1285 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1286 u32 i, CheckTimes = 4,ulRegRead = 0;
1287 u32 WriteAddr[4];
1288 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1289
1290 // Initialize register address offset to be checked
1291 WriteAddr[HW90_BLOCK_MAC] = 0x100;
1292 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1293 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1294 WriteAddr[HW90_BLOCK_RF] = 0x3;
1295
1296 for(i=0 ; i < CheckTimes ; i++)
1297 {
1298
1299 //
1300 // Write Data to register and readback
1301 //
1302 switch(CheckBlock)
1303 {
1304 case HW90_BLOCK_MAC:
1305 //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
1306 RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1307 break;
1308
1309 case HW90_BLOCK_PHY0:
1310 case HW90_BLOCK_PHY1:
1311 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1312 ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1313 break;
1314
1315 case HW90_BLOCK_RF:
1316 // When initialization, we want the delay function(mdelay(), delay_us()
1317 // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1318 // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1319 // to run at Dispatch level to achive it.
1320 //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
1321 WriteData[i] &= 0xfff;
1322 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
1323 // TODO: we should not delay for such a long time. Ask SD3
1324 mdelay(10);
1325 ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1326 mdelay(10);
1327 //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
1328 break;
1329
1330 default:
1331 rtStatus = RT_STATUS_FAILURE;
1332 break;
1333 }
1334
1335
1336 //
1337 // Check whether readback data is correct
1338 //
1339 if(ulRegRead != WriteData[i])
1340 {
1341 //RT_TRACE(COMP_FPGA, ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
1342 RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1343 rtStatus = RT_STATUS_FAILURE;
1344 break;
1345 }
1346 }
1347
1348 return rtStatus;
1349 }
1350
1351 //no use temp in windows driver
1352 #ifdef TO_DO_LIST
1353 void
1354 PHY_SetRFPowerState8192SUsb(
1355 struct net_device* dev,
1356 RF_POWER_STATE RFPowerState
1357 )
1358 {
1359 struct r8192_priv *priv = ieee80211_priv(dev);
1360 bool WaitShutDown = FALSE;
1361 u32 DWordContent;
1362 //RF90_RADIO_PATH_E eRFPath;
1363 u8 eRFPath;
1364 BB_REGISTER_DEFINITION_T *pPhyReg;
1365
1366 if(priv->SetRFPowerStateInProgress == TRUE)
1367 return;
1368
1369 priv->SetRFPowerStateInProgress = TRUE;
1370
1371 // TODO: Emily, 2006.11.21, we should rewrite this function
1372
1373 if(RFPowerState==RF_SHUT_DOWN)
1374 {
1375 RFPowerState=RF_OFF;
1376 WaitShutDown=TRUE;
1377 }
1378
1379
1380 priv->RFPowerState = RFPowerState;
1381 switch( priv->rf_chip )
1382 {
1383 case RF_8225:
1384 case RF_6052:
1385 switch( RFPowerState )
1386 {
1387 case RF_ON:
1388 break;
1389
1390 case RF_SLEEP:
1391 break;
1392
1393 case RF_OFF:
1394 break;
1395 }
1396 break;
1397
1398 case RF_8256:
1399 switch( RFPowerState )
1400 {
1401 case RF_ON:
1402 break;
1403
1404 case RF_SLEEP:
1405 break;
1406
1407 case RF_OFF:
1408 for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1409 {
1410 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1411 continue;
1412
1413 pPhyReg = &priv->PHYRegDef[eRFPath];
1414 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1415 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1416 }
1417 break;
1418 }
1419 break;
1420
1421 case RF_8258:
1422 break;
1423 }// switch( priv->rf_chip )
1424
1425 priv->SetRFPowerStateInProgress = FALSE;
1426 }
1427 #endif
1428
1429 #ifdef RTL8192U
1430 //no use temp in windows driver
1431 void
1432 PHY_UpdateInitialGain(
1433 struct net_device* dev
1434 )
1435 {
1436 struct r8192_priv *priv = ieee80211_priv(dev);
1437 //unsigned char *IGTable;
1438 //u8 DIG_CurrentInitialGain = 4;
1439
1440 switch(priv->rf_chip)
1441 {
1442 case RF_8225:
1443 break;
1444 case RF_8256:
1445 break;
1446 case RF_8258:
1447 break;
1448 case RF_PSEUDO_11N:
1449 break;
1450 case RF_6052:
1451 break;
1452 default:
1453 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
1454 break;
1455 }
1456 }
1457 #endif
1458
1459 //YJ,modified,090107
1460 void PHY_GetHWRegOriginalValue(struct net_device* dev)
1461 {
1462 struct r8192_priv *priv = ieee80211_priv(dev);
1463
1464 // read tx power offset
1465 // Simulate 8192
1466 priv->MCSTxPowerLevelOriginalOffset[0] =
1467 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1468 priv->MCSTxPowerLevelOriginalOffset[1] =
1469 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1470 priv->MCSTxPowerLevelOriginalOffset[2] =
1471 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1472 priv->MCSTxPowerLevelOriginalOffset[3] =
1473 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1474 priv->MCSTxPowerLevelOriginalOffset[4] =
1475 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1476 priv->MCSTxPowerLevelOriginalOffset[5] =
1477 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1478
1479 // Read CCK offset
1480 priv->MCSTxPowerLevelOriginalOffset[6] =
1481 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1482 RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1483 priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1484 priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1485 priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1486
1487 // read rx initial gain
1488 priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1489 priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1490 priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1491 priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1492 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1493 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1494 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1495
1496 // read framesync
1497 priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1498 priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1499 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1500 rOFDM0_RxDetector3, priv->framesync);
1501 }
1502 //YJ,modified,090107,end
1503
1504
1505
1506 /**
1507 * Function: phy_InitBBRFRegisterDefinition
1508 *
1509 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
1510 *
1511 * Input:
1512 * PADAPTER Adapter,
1513 *
1514 * Output: None
1515 * Return: None
1516 * Note: The initialization value is constant and it should never be changes
1517 */
1518 //use in phy only
1519 static void phy_InitBBRFRegisterDefinition( struct net_device* dev)
1520 {
1521 struct r8192_priv *priv = ieee80211_priv(dev);
1522
1523 // RF Interface Sowrtware Control
1524 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1525 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1526 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1527 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1528
1529 // RF Interface Readback Value
1530 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1531 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1532 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1533 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1534
1535 // RF Interface Output (and Enable)
1536 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1537 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1538 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1539 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1540
1541 // RF Interface (Output and) Enable
1542 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1543 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1544 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1545 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1546
1547 //Addr of LSSI. Wirte RF register by driver
1548 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1549 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1550 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1551 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1552
1553 // RF parameter
1554 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
1555 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1556 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1557 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1558
1559 // Tx AGC Gain Stage (same for all path. Should we remove this?)
1560 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1561 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1562 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1563 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1564
1565 // Tranceiver A~D HSSI Parameter-1
1566 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
1567 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
1568 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
1569 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1570
1571 // Tranceiver A~D HSSI Parameter-2
1572 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
1573 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
1574 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
1575 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
1576
1577 // RF switch Control
1578 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1579 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1580 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1581 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1582
1583 // AGC control 1
1584 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1585 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1586 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1587 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1588
1589 // AGC control 2
1590 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1591 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1592 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1593 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1594
1595 // RX AFE control 1
1596 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1597 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1598 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1599 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1600
1601 // RX AFE control 1
1602 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1603 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1604 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1605 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1606
1607 // Tx AFE control 1
1608 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1609 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1610 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1611 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1612
1613 // Tx AFE control 2
1614 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1615 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1616 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1617 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1618
1619 // Tranceiver LSSI Readback SI mode
1620 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1621 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1622 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1623 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1624
1625 // Tranceiver LSSI Readback PI mode
1626 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1627 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1628 //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
1629 //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
1630
1631 }
1632
1633
1634 //
1635 // Description: Change RF power state.
1636 //
1637 // Assumption: This function must be executed in re-schdulable context,
1638 // ie. PASSIVE_LEVEL.
1639 //
1640 // 050823, by rcnjko.
1641 //not understand it seem's use in init
1642 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
1643 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1644 {
1645 struct r8192_priv *priv = ieee80211_priv(dev);
1646 bool bResult = FALSE;
1647
1648 RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1649
1650 if(eRFPowerState == priv->ieee80211->eRFPowerState)
1651 {
1652 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1653 return bResult;
1654 }
1655
1656 bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
1657
1658 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1659
1660 return bResult;
1661 }
1662
1663 //use in phy only
1664 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1665 {
1666 struct r8192_priv *priv = ieee80211_priv(dev);
1667 bool bResult = TRUE;
1668 //u8 eRFPath;
1669 //u8 i, QueueID;
1670 u8 u1bTmp;
1671
1672 if(priv->SetRFPowerStateInProgress == TRUE)
1673 return FALSE;
1674
1675 priv->SetRFPowerStateInProgress = TRUE;
1676
1677 switch(priv->rf_chip )
1678 {
1679 default:
1680 switch( eRFPowerState )
1681 {
1682 case eRfOn:
1683 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
1684 write_nic_word(dev, CMDR, 0x37FC);
1685 write_nic_byte(dev, PHY_CCA, 0x3);
1686 write_nic_byte(dev, TXPAUSE, 0x00);
1687 write_nic_byte(dev, SPS1_CTRL, 0x64);
1688 break;
1689
1690 //
1691 // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
1692 // By Bruce, 2008-01-16.
1693 //
1694 case eRfSleep:
1695 case eRfOff:
1696 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
1697 break;
1698 //
1699 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
1700 // Added by Bruce, 2008-11-22.
1701 //
1702 //==================================================================
1703 // (0) Disable FW BB reset checking
1704 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
1705
1706 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
1707 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
1708 u1bTmp |= BIT0;
1709 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
1710
1711 write_nic_byte(dev, SPS1_CTRL, 0x0);
1712 write_nic_byte(dev, TXPAUSE, 0xFF);
1713
1714 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
1715 write_nic_word(dev, CMDR, 0x77FC);
1716 write_nic_byte(dev, PHY_CCA, 0x0);
1717 udelay(100);
1718
1719 write_nic_word(dev, CMDR, 0x37FC);
1720 udelay(10);
1721
1722 write_nic_word(dev, CMDR, 0x77FC);
1723 udelay(10);
1724
1725 // (3) Reset BB TRX blocks
1726 write_nic_word(dev, CMDR, 0x57FC);
1727 break;
1728
1729 default:
1730 bResult = FALSE;
1731 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknown state to set: 0x%X!!!\n", eRFPowerState));
1732 break;
1733 }
1734 break;
1735
1736 }
1737 priv->ieee80211->eRFPowerState = eRFPowerState;
1738 #ifdef TO_DO_LIST
1739 if(bResult)
1740 {
1741 // Update current RF state variable.
1742 priv->ieee80211->eRFPowerState = eRFPowerState;
1743
1744 switch(priv->rf_chip )
1745 {
1746 case RF_8256:
1747 switch(priv->ieee80211->eRFPowerState)
1748 {
1749 case eRfOff:
1750 //
1751 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1752 //
1753 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1754 {
1755 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1756 }
1757 else
1758 {
1759 // Turn off LED if RF is not ON.
1760 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1761 }
1762 break;
1763
1764 case eRfOn:
1765 // Turn on RF we are still linked, which might happen when
1766 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1767 if( pMgntInfo->bMediaConnect == TRUE )
1768 {
1769 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
1770 }
1771 else
1772 {
1773 // Turn off LED if RF is not ON.
1774 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
1775 }
1776 break;
1777
1778 default:
1779 // do nothing.
1780 break;
1781 }// Switch RF state
1782
1783 break;
1784
1785 default:
1786 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
1787 break;
1788 }// Switch rf_chip
1789 }
1790 #endif
1791 priv->SetRFPowerStateInProgress = FALSE;
1792
1793 return bResult;
1794 }
1795
1796 /*-----------------------------------------------------------------------------
1797 * Function: GetTxPowerLevel8190()
1798 *
1799 * Overview: This function is export to "common" moudule
1800 *
1801 * Input: PADAPTER Adapter
1802 * psByte Power Level
1803 *
1804 * Output: NONE
1805 *
1806 * Return: NONE
1807 *
1808 *---------------------------------------------------------------------------*/
1809 // no use temp
1810 void
1811 PHY_GetTxPowerLevel8192S(
1812 struct net_device* dev,
1813 long* powerlevel
1814 )
1815 {
1816 struct r8192_priv *priv = ieee80211_priv(dev);
1817 u8 TxPwrLevel = 0;
1818 long TxPwrDbm;
1819 //
1820 // Because the Tx power indexes are different, we report the maximum of them to
1821 // meet the CCX TPC request. By Bruce, 2008-01-31.
1822 //
1823
1824 // CCK
1825 TxPwrLevel = priv->CurrentCckTxPwrIdx;
1826 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
1827
1828 // Legacy OFDM
1829 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
1830
1831 // Compare with Legacy OFDM Tx power.
1832 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
1833 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
1834
1835 // HT OFDM
1836 TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
1837
1838 // Compare with HT OFDM Tx power.
1839 if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
1840 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
1841
1842 *powerlevel = TxPwrDbm;
1843 }
1844
1845 /*-----------------------------------------------------------------------------
1846 * Function: SetTxPowerLevel8190()
1847 *
1848 * Overview: This function is export to "HalCommon" moudule
1849 *
1850 * Input: PADAPTER Adapter
1851 * u1Byte channel
1852 *
1853 * Output: NONE
1854 *
1855 * Return: NONE
1856 * 2008/11/04 MHC We remove EEPROM_93C56.
1857 * We need to move CCX relative code to independet file.
1858 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
1859 *---------------------------------------------------------------------------*/
1860 void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel)
1861 {
1862 struct r8192_priv *priv = ieee80211_priv(dev);
1863 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(dev);
1864 u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
1865 s8 ant_pwr_diff = 0;
1866 u32 u4RegValue;
1867 u8 index = (channel -1);
1868 // 2009/01/22 MH Add for new EEPROM format from SD3
1869 u8 pwrdiff[2] = {0};
1870 u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};
1871 u8 rfpath = 0, rfpathnum = 2;
1872
1873 if(priv->bTXPowerDataReadFromEEPORM == FALSE)
1874 return;
1875
1876 /*
1877 * Read predefined TX power index in EEPROM
1878 */
1879 {
1880 //
1881 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
1882 // Power must be calculated by the antenna diff.
1883 // So we have to rewrite Antenna gain offset register here.
1884 // Please refer to BB register 0x80c
1885 // 1. For CCK.
1886 // 2. For OFDM 1T or 2T
1887 //
1888
1889 // 1. CCK
1890 powerlevel = priv->RfTxPwrLevelCck[0][index];
1891
1892 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1893 {
1894 // Read HT 40 OFDM TX power
1895 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
1896 // RF B HT OFDM pwr-RFA HT OFDM pwr
1897 // Only one RF we need not to decide B <-> A pwr diff
1898
1899 // Legacy<->HT pwr diff, we only care about path A.
1900
1901 // We only assume 1T as RF path A
1902 rfpathnum = 1;
1903 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1904 }
1905 else if (priv->rf_type == RF_2T2R)
1906 {
1907 // Read HT 40 OFDM TX power
1908 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
1909 // RF B HT OFDM pwr-RFA HT OFDM pwr
1910 ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
1911 priv->RfTxPwrLevelOfdm2T[0][index];
1912 // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
1913 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
1914
1915 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
1916 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
1917 //priv->RfTxPwrLevelOfdm2T[1][index],
1918 //priv->RfTxPwrLevelOfdm2T[0][index],
1919 //priv->RfTxPwrLevelOfdm2T[1][index]));
1920
1921 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1922 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1923 }
1924
1925 //
1926 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
1927 // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
1928 //
1929 if (priv->EEPROMVersion == 2) // Defined by SD1 Jong
1930 {
1931 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1932 {
1933 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1934 {
1935 // HT 20<->40 pwr diff
1936 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
1937
1938 // Calculate Antenna pwr diff
1939 if (pwrdiff[rfpath] < 8) // 0~+7
1940 {
1941 ht20pwr[rfpath] += pwrdiff[rfpath];
1942 }
1943 else // index8-15=-8~-1
1944 {
1945 ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
1946 }
1947 }
1948
1949 // RF B HT OFDM pwr-RFA HT OFDM pwr
1950 if (priv->rf_type == RF_2T2R)
1951 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1952
1953 //RTPRINT(FPHY, PHY_TXPWR,
1954 //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
1955 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
1956 }
1957
1958 // Band Edge scheme is enabled for FCC mode
1959 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
1960 {
1961 for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1962 {
1963 pwrdiff[rfpath] = 0;
1964 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1965 {
1966 if (channel <= 3)
1967 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
1968 else if (channel >= 9)
1969 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
1970 else
1971 pwrdiff[rfpath] = 0;
1972
1973 ht40pwr[rfpath] -= pwrdiff[rfpath];
1974 }
1975 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1976 {
1977 if (channel == 1)
1978 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
1979 else if (channel >= 11)
1980 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
1981 else
1982 pwrdiff[rfpath] = 0;
1983
1984 ht20pwr[rfpath] -= pwrdiff[rfpath];
1985 }
1986 }
1987
1988 if (priv->rf_type == RF_2T2R)
1989 {
1990 // HT 20/40 must decide if they need to minus BD pwr offset
1991 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1992 ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
1993 else
1994 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1995 }
1996 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1997 {
1998 if (channel <= 1 || channel >= 11)
1999 {
2000 //RTPRINT(FPHY, PHY_TXPWR,
2001 //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2002 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2003 }
2004 }
2005 else
2006 {
2007 if (channel <= 3 || channel >= 9)
2008 {
2009 //RTPRINT(FPHY, PHY_TXPWR,
2010 //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2011 //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2012 }
2013 }
2014 }
2015 }
2016
2017 //Cosa added for protection, the reg rFPGA0_TxGainStage
2018 // range is from 7~-8, index = 0x0~0xf
2019 if(ant_pwr_diff > 7)
2020 ant_pwr_diff = 7;
2021 if(ant_pwr_diff < -8)
2022 ant_pwr_diff = -8;
2023
2024 //RTPRINT(FPHY, PHY_TXPWR,
2025 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2026 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2027
2028 ant_pwr_diff &= 0xf;
2029
2030 // Antenna TX power difference
2031 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2032 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2033 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B
2034
2035 // Antenna gain offset from B/C/D to A
2036 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2037 priv->AntennaTxPwDiff[1]<<4 |
2038 priv->AntennaTxPwDiff[0] );
2039
2040 // Notify Tx power difference for B/C/D to A!!!
2041 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2042 }
2043
2044 //
2045 // CCX 2 S31, AP control of client transmit power:
2046 // 1. We shall not exceed Cell Power Limit as possible as we can.
2047 // 2. Tolerance is +/- 5dB.
2048 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2049 //
2050 // TODO:
2051 // 1. 802.11h power contraint
2052 //
2053 // 071011, by rcnjko.
2054 //
2055 #ifdef TODO //WB, 11h has not implemented now.
2056 if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2057 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2058 {
2059 u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2060 u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2061 u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2062
2063 RT_TRACE(COMP_TXAGC,
2064 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2065 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2066 RT_TRACE(COMP_TXAGC,
2067 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2068 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2069
2070 // CCK
2071 if(powerlevel > CckCellPwrIdx)
2072 powerlevel = CckCellPwrIdx;
2073 // Legacy OFDM, HT OFDM
2074 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2075 {
2076 if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2077 {
2078 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2079 }
2080 else
2081 {
2082 powerlevelOFDM24G = 0;
2083 }
2084 }
2085
2086 RT_TRACE(COMP_TXAGC,
2087 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2088 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2089 }
2090 #endif
2091
2092 priv->CurrentCckTxPwrIdx = powerlevel;
2093 priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2094
2095 switch(priv->rf_chip)
2096 {
2097 case RF_8225:
2098 //PHY_SetRF8225CckTxPower(dev, powerlevel);
2099 //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2100 break;
2101
2102 case RF_8256:
2103 break;
2104
2105 case RF_6052:
2106 PHY_RF6052SetCckTxPower(dev, powerlevel);
2107 PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2108 break;
2109
2110 case RF_8258:
2111 break;
2112 default:
2113 break;
2114 }
2115
2116 }
2117
2118 //
2119 // Description:
2120 // Update transmit power level of all channel supported.
2121 //
2122 // TODO:
2123 // A mode.
2124 // By Bruce, 2008-02-04.
2125 // no use temp
2126 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2127 {
2128 struct r8192_priv *priv = ieee80211_priv(dev);
2129 u8 idx;
2130 u8 rf_path;
2131
2132 // TODO: A mode Tx power.
2133 u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2134 u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2135
2136 if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2137 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2138 else
2139 OfdmTxPwrIdx = 0;
2140
2141 for(idx = 0; idx < 14; idx++)
2142 {
2143 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2144 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2145 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2146 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2147 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2148 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2149
2150 for (rf_path = 0; rf_path < 2; rf_path++)
2151 {
2152 priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2153 priv->RfTxPwrLevelOfdm1T[rf_path][idx] = \
2154 priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2155 }
2156 }
2157
2158 PHY_SetTxPowerLevel8192S(dev, priv->chan);
2159
2160 return TRUE;
2161 }
2162
2163 /*
2164 Description:
2165 When beacon interval is changed, the values of the
2166 hw registers should be modified.
2167 By tynli, 2008.10.24.
2168
2169 */
2170
2171 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2172 {
2173 u32 NewBeaconNum;
2174
2175 NewBeaconNum = BeaconInterval *32 - 64;
2176 //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2177 //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2178 write_nic_dword(dev, WFM3+4, NewBeaconNum);
2179 write_nic_dword(dev, WFM3, 0xB026007C);
2180 }
2181
2182 //
2183 // Description:
2184 // Map dBm into Tx power index according to
2185 // current HW model, for example, RF and PA, and
2186 // current wireless mode.
2187 // By Bruce, 2008-01-29.
2188 // use in phy only
2189 static u8 phy_DbmToTxPwrIdx(
2190 struct net_device* dev,
2191 WIRELESS_MODE WirelessMode,
2192 long PowerInDbm
2193 )
2194 {
2195 //struct r8192_priv *priv = ieee80211_priv(dev);
2196 u8 TxPwrIdx = 0;
2197 long Offset = 0;
2198
2199
2200 //
2201 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2202 // 3dbm, and OFDM HT equals to 0dbm repectively.
2203 // Note:
2204 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2205 // By Bruce, 2008-01-29.
2206 //
2207 switch(WirelessMode)
2208 {
2209 case WIRELESS_MODE_B:
2210 Offset = -7;
2211 break;
2212
2213 case WIRELESS_MODE_G:
2214 case WIRELESS_MODE_N_24G:
2215 Offset = -8;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 if((PowerInDbm - Offset) > 0)
2222 {
2223 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2224 }
2225 else
2226 {
2227 TxPwrIdx = 0;
2228 }
2229
2230 // Tx Power Index is too large.
2231 if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2232 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2233
2234 return TxPwrIdx;
2235 }
2236 //
2237 // Description:
2238 // Map Tx power index into dBm according to
2239 // current HW model, for example, RF and PA, and
2240 // current wireless mode.
2241 // By Bruce, 2008-01-29.
2242 // use in phy only
2243 static long phy_TxPwrIdxToDbm(
2244 struct net_device* dev,
2245 WIRELESS_MODE WirelessMode,
2246 u8 TxPwrIdx
2247 )
2248 {
2249 //struct r8192_priv *priv = ieee80211_priv(dev);
2250 long Offset = 0;
2251 long PwrOutDbm = 0;
2252
2253 //
2254 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2255 // 3dbm, and OFDM HT equals to 0dbm repectively.
2256 // Note:
2257 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2258 // By Bruce, 2008-01-29.
2259 //
2260 switch(WirelessMode)
2261 {
2262 case WIRELESS_MODE_B:
2263 Offset = -7;
2264 break;
2265
2266 case WIRELESS_MODE_G:
2267 case WIRELESS_MODE_N_24G:
2268 Offset = -8;
2269 break;
2270 default:
2271 break;
2272 }
2273
2274 PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2275
2276 return PwrOutDbm;
2277 }
2278
2279 #ifdef TO_DO_LIST
2280 extern VOID
2281 PHY_ScanOperationBackup8192S(
2282 IN PADAPTER Adapter,
2283 IN u1Byte Operation
2284 )
2285 {
2286
2287 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2288 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
2289 u4Byte BitMask;
2290 u1Byte initial_gain;
2291
2292
2293
2294
2295
2296 if(!Adapter->bDriverStopped)
2297 {
2298 switch(Operation)
2299 {
2300 case SCAN_OPT_BACKUP:
2301 //
2302 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
2303 // and resume both two DMs while scan complete.
2304 // 2008.11.27.
2305 //
2306 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2307 break;
2308
2309 case SCAN_OPT_RESTORE:
2310 //
2311 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
2312 // recover earlier DIG settings.
2313 // 2008.11.27.
2314 //
2315 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2316 break;
2317
2318 default:
2319 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2320 break;
2321 }
2322 }
2323 }
2324 #endif
2325
2326 //nouse temp
2327 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation )
2328 {
2329
2330 //struct r8192_priv *priv = ieee80211_priv(dev);
2331 //u32 BitMask;
2332 //u8 initial_gain;
2333 }
2334
2335 /*-----------------------------------------------------------------------------
2336 * Function: SetBWModeCallback8190Pci()
2337 *
2338 * Overview: Timer callback function for SetSetBWMode
2339 *
2340 * Input: PRT_TIMER pTimer
2341 *
2342 * Output: NONE
2343 *
2344 * Return: NONE
2345 *
2346 * Note: (1) We do not take j mode into consideration now
2347 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2348 * concurrently?
2349 *---------------------------------------------------------------------------*/
2350 // use in phy only (in win it's timer)
2351 void PHY_SetBWModeCallback8192S(struct net_device *dev)
2352 {
2353 struct r8192_priv *priv = ieee80211_priv(dev);
2354 u8 regBwOpMode;
2355
2356 //return;
2357
2358 // Added it for 20/40 mhz switch time evaluation by guangan 070531
2359 //u32 NowL, NowH;
2360 //u8Byte BeginTime, EndTime;
2361 u8 regRRSR_RSC;
2362
2363 RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
2364 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2365
2366 if(priv->rf_chip == RF_PSEUDO_11N)
2367 {
2368 priv->SetBWModeInProgress= FALSE;
2369 return;
2370 }
2371
2372 if(!priv->up)
2373 return;
2374
2375 // Added it for 20/40 mhz switch time evaluation by guangan 070531
2376 //NowL = read_nic_dword(dev, TSFR);
2377 //NowH = read_nic_dword(dev, TSFR+4);
2378 //BeginTime = ((u8Byte)NowH << 32) + NowL;
2379
2380 //3//
2381 //3//<1>Set MAC register
2382 //3//
2383 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2384 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2385
2386 switch(priv->CurrentChannelBW)
2387 {
2388 case HT_CHANNEL_WIDTH_20:
2389 //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2390 // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2391
2392 regBwOpMode |= BW_OPMODE_20MHZ;
2393 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2394 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2395 break;
2396
2397 case HT_CHANNEL_WIDTH_20_40:
2398 //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2399 // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2400
2401 regBwOpMode &= ~BW_OPMODE_20MHZ;
2402 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2403 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2404 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
2405 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
2406 break;
2407
2408 default:
2409 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n",
2410 priv->CurrentChannelBW);
2411 break;
2412 }
2413
2414 //3//
2415 //3//<2>Set PHY related register
2416 //3//
2417 switch(priv->CurrentChannelBW)
2418 {
2419 /* 20 MHz channel*/
2420 case HT_CHANNEL_WIDTH_20:
2421 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2422 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2423
2424 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2425 // It is set in Tx descriptor for 8192x series
2426 //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2427 //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2428 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2429
2430 if (priv->card_8192_version >= VERSION_8192S_BCUT)
2431 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2432
2433
2434 break;
2435
2436 /* 40 MHz channel*/
2437 case HT_CHANNEL_WIDTH_20_40:
2438 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2439 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2440
2441 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2442 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2443 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2444 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2445
2446 // Set Control channel to upper or lower. These settings are required only for 40MHz
2447 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2448 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2449
2450 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
2451 if (priv->card_8192_version >= VERSION_8192S_BCUT)
2452 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2453
2454 break;
2455
2456 default:
2457 RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
2458 ,priv->CurrentChannelBW);
2459 break;
2460
2461 }
2462 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2463
2464 // Added it for 20/40 mhz switch time evaluation by guangan 070531
2465 //NowL = read_nic_dword(dev, TSFR);
2466 //NowH = read_nic_dword(dev, TSFR+4);
2467 //EndTime = ((u8Byte)NowH << 32) + NowL;
2468 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
2469
2470 //3<3>Set RF related register
2471 switch( priv->rf_chip )
2472 {
2473 case RF_8225:
2474 //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
2475 break;
2476
2477 case RF_8256:
2478 // Please implement this function in Hal8190PciPhy8256.c
2479 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2480 break;
2481
2482 case RF_8258:
2483 // Please implement this function in Hal8190PciPhy8258.c
2484 // PHY_SetRF8258Bandwidth();
2485 break;
2486
2487 case RF_PSEUDO_11N:
2488 // Do Nothing
2489 break;
2490
2491 case RF_6052:
2492 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2493 break;
2494 default:
2495 printk("Unknown rf_chip: %d\n", priv->rf_chip);
2496 break;
2497 }
2498
2499 priv->SetBWModeInProgress= FALSE;
2500
2501 RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
2502 }
2503
2504
2505 /*-----------------------------------------------------------------------------
2506 * Function: SetBWMode8190Pci()
2507 *
2508 * Overview: This function is export to "HalCommon" moudule
2509 *
2510 * Input: PADAPTER Adapter
2511 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2512 *
2513 * Output: NONE
2514 *
2515 * Return: NONE
2516 *
2517 * Note: We do not take j mode into consideration now
2518 *---------------------------------------------------------------------------*/
2519 //extern void PHY_SetBWMode8192S( struct net_device* dev,
2520 // HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M
2521 // HT_EXTCHNL_OFFSET Offset // Upper, Lower, or Don't care
2522 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2523 {
2524 struct r8192_priv *priv = ieee80211_priv(dev);
2525 HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
2526
2527
2528 // Modified it for 20/40 mhz switch by guangan 070531
2529
2530 //return;
2531
2532 //if(priv->SwChnlInProgress)
2533 // if(pMgntInfo->bScanInProgress)
2534 // {
2535 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
2536 // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2537 // return;
2538 // }
2539
2540 // if(priv->SetBWModeInProgress)
2541 // {
2542 // // Modified it for 20/40 mhz switch by guangan 070531
2543 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
2544 // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2545 // PlatformCancelTimer(dev, &priv->SetBWModeTimer);
2546 // //return;
2547 // }
2548
2549 if(priv->SetBWModeInProgress)
2550 return;
2551
2552 priv->SetBWModeInProgress= TRUE;
2553
2554 priv->CurrentChannelBW = Bandwidth;
2555
2556 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2557 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2558 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2559 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2560 else
2561 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2562
2563 if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
2564 {
2565 SetBWModeCallback8192SUsbWorkItem(dev);
2566 }
2567 else
2568 {
2569 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
2570 priv->SetBWModeInProgress= FALSE;
2571 priv->CurrentChannelBW = tmpBW;
2572 }
2573 }
2574
2575 // use in phy only (in win it's timer)
2576 void PHY_SwChnlCallback8192S(struct net_device *dev)
2577 {
2578
2579 struct r8192_priv *priv = ieee80211_priv(dev);
2580 u32 delay;
2581 //bool ret;
2582
2583 RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2584
2585 if(!priv->up)
2586 return;
2587
2588 if(priv->rf_chip == RF_PSEUDO_11N)
2589 {
2590 priv->SwChnlInProgress=FALSE;
2591 return; //return immediately if it is peudo-phy
2592 }
2593
2594 do{
2595 if(!priv->SwChnlInProgress)
2596 break;
2597
2598 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2599 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2600 {
2601 if(delay>0)
2602 {
2603 mdelay(delay);
2604 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
2605 //mod_timer(&priv->SwChnlTimer, jiffies + MSECS(delay));
2606 //==>PHY_SwChnlCallback8192S(dev); for 92se
2607 //==>SwChnlCallback8192SUsb(dev) for 92su
2608 }
2609 else
2610 continue;
2611 }
2612 else
2613 {
2614 priv->SwChnlInProgress=FALSE;
2615 break;
2616 }
2617 }while(true);
2618 }
2619
2620 // Call after initialization
2621 //extern void PHY_SwChnl8192S(struct net_device* dev, u8 channel)
2622 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2623 {
2624 struct r8192_priv *priv = ieee80211_priv(dev);
2625 //u8 tmpchannel =channel;
2626 //bool bResult = false;
2627
2628 if(!priv->up)
2629 return false;
2630
2631 if(priv->SwChnlInProgress)
2632 return false;
2633
2634 if(priv->SetBWModeInProgress)
2635 return false;
2636
2637 //--------------------------------------------
2638 switch(priv->ieee80211->mode)
2639 {
2640 case WIRELESS_MODE_A:
2641 case WIRELESS_MODE_N_5G:
2642 if (channel<=14){
2643 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2644 return false;
2645 }
2646 break;
2647
2648 case WIRELESS_MODE_B:
2649 if (channel>14){
2650 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2651 return false;
2652 }
2653 break;
2654
2655 case WIRELESS_MODE_G:
2656 case WIRELESS_MODE_N_24G:
2657 if (channel>14){
2658 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2659 return false;
2660 }
2661 break;
2662
2663 default:
2664 ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
2665 break;
2666 }
2667 //--------------------------------------------
2668
2669 priv->SwChnlInProgress = TRUE;
2670 if( channel == 0)
2671 channel = 1;
2672
2673 priv->chan=channel;
2674
2675 priv->SwChnlStage=0;
2676 priv->SwChnlStep=0;
2677
2678 if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
2679 {
2680 SwChnlCallback8192SUsbWorkItem(dev);
2681 #ifdef TO_DO_LIST
2682 if(bResult)
2683 {
2684 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
2685 }
2686 else
2687 {
2688 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
2689 priv->SwChnlInProgress = false;
2690 priv->CurrentChannel = tmpchannel;
2691 }
2692 #endif
2693 }
2694 else
2695 {
2696 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
2697 priv->SwChnlInProgress = false;
2698 //priv->CurrentChannel = tmpchannel;
2699 }
2700 return true;
2701 }
2702
2703
2704 //
2705 // Description:
2706 // Switch channel synchronously. Called by SwChnlByDelayHandler.
2707 //
2708 // Implemented by Bruce, 2008-02-14.
2709 // The following procedure is operted according to SwChanlCallback8190Pci().
2710 // However, this procedure is performed synchronously which should be running under
2711 // passive level.
2712 //
2713 //not understand it
2714 void PHY_SwChnlPhy8192S( // Only called during initialize
2715 struct net_device* dev,
2716 u8 channel
2717 )
2718 {
2719 struct r8192_priv *priv = ieee80211_priv(dev);
2720
2721 RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
2722
2723 #ifdef TO_DO_LIST
2724 // Cannot IO.
2725 if(RT_CANNOT_IO(dev))
2726 return;
2727 #endif
2728
2729 // Channel Switching is in progress.
2730 if(priv->SwChnlInProgress)
2731 return;
2732
2733 //return immediately if it is peudo-phy
2734 if(priv->rf_chip == RF_PSEUDO_11N)
2735 {
2736 priv->SwChnlInProgress=FALSE;
2737 return;
2738 }
2739
2740 priv->SwChnlInProgress = TRUE;
2741 if( channel == 0)
2742 channel = 1;
2743
2744 priv->chan=channel;
2745
2746 priv->SwChnlStage = 0;
2747 priv->SwChnlStep = 0;
2748
2749 phy_FinishSwChnlNow(dev,channel);
2750
2751 priv->SwChnlInProgress = FALSE;
2752 }
2753
2754 // use in phy only
2755 static bool
2756 phy_SetSwChnlCmdArray(
2757 SwChnlCmd* CmdTable,
2758 u32 CmdTableIdx,
2759 u32 CmdTableSz,
2760 SwChnlCmdID CmdID,
2761 u32 Para1,
2762 u32 Para2,
2763 u32 msDelay
2764 )
2765 {
2766 SwChnlCmd* pCmd;
2767
2768 if(CmdTable == NULL)
2769 {
2770 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
2771 return FALSE;
2772 }
2773 if(CmdTableIdx >= CmdTableSz)
2774 {
2775 //RT_ASSERT(FALSE,
2776 // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2777 //CmdTableIdx, CmdTableSz));
2778 return FALSE;
2779 }
2780
2781 pCmd = CmdTable + CmdTableIdx;
2782 pCmd->CmdID = CmdID;
2783 pCmd->Para1 = Para1;
2784 pCmd->Para2 = Para2;
2785 pCmd->msDelay = msDelay;
2786
2787 return TRUE;
2788 }
2789
2790 // use in phy only
2791 static bool
2792 phy_SwChnlStepByStep(
2793 struct net_device* dev,
2794 u8 channel,
2795 u8 *stage,
2796 u8 *step,
2797 u32 *delay
2798 )
2799 {
2800 struct r8192_priv *priv = ieee80211_priv(dev);
2801 //PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2802 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2803 u32 PreCommonCmdCnt;
2804 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2805 u32 PostCommonCmdCnt;
2806 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2807 u32 RfDependCmdCnt;
2808 SwChnlCmd *CurrentCmd = NULL;
2809 u8 eRFPath;
2810
2811 //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
2812 //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
2813 RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2814 //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
2815 if (!IsLegalChannel(priv->ieee80211, channel))
2816 {
2817 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2818 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2819 }
2820
2821 //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
2822 //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
2823
2824 //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
2825 //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2826 //{
2827 // <1> Fill up pre common command.
2828 PreCommonCmdCnt = 0;
2829 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2830 CmdID_SetTxPowerLevel, 0, 0, 0);
2831 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2832 CmdID_End, 0, 0, 0);
2833
2834 // <2> Fill up post common command.
2835 PostCommonCmdCnt = 0;
2836
2837 phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2838 CmdID_End, 0, 0, 0);
2839
2840 // <3> Fill up RF dependent command.
2841 RfDependCmdCnt = 0;
2842 switch( priv->rf_chip )
2843 {
2844 case RF_8225:
2845 if (channel < 1 || channel > 14)
2846 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2847 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2848 // 2008/09/04 MH Change channel.
2849 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2850 CmdID_RF_WriteReg, rRfChannel, channel, 10);
2851 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2852 CmdID_End, 0, 0, 0);
2853 break;
2854
2855 case RF_8256:
2856 if (channel < 1 || channel > 14)
2857 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2858 // TEST!! This is not the table for 8256!!
2859 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2860 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2861 CmdID_RF_WriteReg, rRfChannel, channel, 10);
2862 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2863 CmdID_End, 0, 0, 0);
2864 break;
2865
2866 case RF_6052:
2867 if (channel < 1 || channel > 14)
2868 RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2869 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2870 CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
2871 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2872 CmdID_End, 0, 0, 0);
2873 break;
2874
2875 case RF_8258:
2876 break;
2877
2878 default:
2879 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
2880 return FALSE;
2881 break;
2882 }
2883
2884
2885 do{
2886 switch(*stage)
2887 {
2888 case 0:
2889 CurrentCmd=&PreCommonCmd[*step];
2890 break;
2891 case 1:
2892 CurrentCmd=&RfDependCmd[*step];
2893 break;
2894 case 2:
2895 CurrentCmd=&PostCommonCmd[*step];
2896 break;
2897 }
2898
2899 if(CurrentCmd->CmdID==CmdID_End)
2900 {
2901 if((*stage)==2)
2902 {
2903 return TRUE;
2904 }
2905 else
2906 {
2907 (*stage)++;
2908 (*step)=0;
2909 continue;
2910 }
2911 }
2912
2913 switch(CurrentCmd->CmdID)
2914 {
2915 case CmdID_SetTxPowerLevel:
2916 //if(priv->card_8192_version > VERSION_8190_BD)
2917 PHY_SetTxPowerLevel8192S(dev,channel);
2918 break;
2919 case CmdID_WritePortUlong:
2920 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2921 break;
2922 case CmdID_WritePortUshort:
2923 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2924 break;
2925 case CmdID_WritePortUchar:
2926 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2927 break;
2928 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
2929 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2930 {
2931 // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
2932 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
2933 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
2934 }
2935 break;
2936 default:
2937 break;
2938 }
2939
2940 break;
2941 }while(TRUE);
2942 //cosa }/*for(Number of RF paths)*/
2943
2944 (*delay)=CurrentCmd->msDelay;
2945 (*step)++;
2946 RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2947 return FALSE;
2948 }
2949
2950 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
2951 // use in phy only
2952 static void
2953 phy_FinishSwChnlNow( // We should not call this function directly
2954 struct net_device* dev,
2955 u8 channel
2956 )
2957 {
2958 struct r8192_priv *priv = ieee80211_priv(dev);
2959 u32 delay;
2960
2961 while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2962 {
2963 if(delay>0)
2964 mdelay(delay);
2965 if(!priv->up)
2966 break;
2967 }
2968 }
2969
2970
2971 /*-----------------------------------------------------------------------------
2972 * Function: PHYCheckIsLegalRfPath8190Pci()
2973 *
2974 * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
2975 * We will return false.
2976 *
2977 * Input: NONE
2978 *
2979 * Output: NONE
2980 *
2981 * Return: NONE
2982 *
2983 * Revised History:
2984 * When Who Remark
2985 * 11/15/2007 MHC Create Version 0.
2986 *
2987 *---------------------------------------------------------------------------*/
2988 //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
2989 //extern bool
2990 //PHY_CheckIsLegalRfPath8192S(
2991 // struct net_device* dev,
2992 // u32 eRFPath)
2993 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
2994 {
2995 // struct r8192_priv *priv = ieee80211_priv(dev);
2996 bool rtValue = TRUE;
2997
2998 // NOt check RF Path now.!
2999 return rtValue;
3000
3001 } /* PHY_CheckIsLegalRfPath8192S */
3002
3003
3004
3005 /*-----------------------------------------------------------------------------
3006 * Function: PHY_IQCalibrate8192S()
3007 *
3008 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
3009 * to improve RF EVM!!?
3010 *
3011 * Input: IN PADAPTER pAdapter
3012 *
3013 * Output: NONE
3014 *
3015 * Return: NONE
3016 *
3017 * Revised History:
3018 * When Who Remark
3019 * 10/07/2008 MHC Create. Document from SD3 RFSI Jenyu.
3020 *
3021 *---------------------------------------------------------------------------*/
3022 //called by InitializeAdapter8192SE
3023 void
3024 PHY_IQCalibrate( struct net_device* dev)
3025 {
3026 //struct r8192_priv *priv = ieee80211_priv(dev);
3027 u32 i, reg;
3028 u32 old_value;
3029 long X, Y, TX0[4];
3030 u32 TXA[4];
3031
3032 // 1. Check QFN68 or 64 92S (Read from EEPROM)
3033
3034 //
3035 // 2. QFN 68
3036 //
3037 // For 1T2R IQK only now !!!
3038 for (i = 0; i < 10; i++)
3039 {
3040 // IQK
3041 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3042 //PlatformStallExecution(5);
3043 udelay(5);
3044 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3045 udelay(5);
3046 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3047 udelay(5);
3048 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3049 udelay(5);
3050 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3051 udelay(5);
3052 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3053 udelay(5);
3054 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3055 udelay(5);
3056 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3057 udelay(5);
3058 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3059 udelay(5);
3060 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3061 udelay(5);
3062 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3063 udelay(2000);
3064 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3065 udelay(5);
3066 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3067 udelay(5);
3068 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3069
3070
3071 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3072
3073 // Readback IQK value and rewrite
3074 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3075 {
3076 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3077
3078 // Calibrate init gain for A path for TX0
3079 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3080 TXA[RF90_PATH_A] = (X * old_value)/0x100;
3081 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3082 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3083 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3084 udelay(5);
3085
3086 // Calibrate init gain for C path for TX0
3087 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3088 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3089 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3090 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3091 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3092 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3093 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3094 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3095 udelay(5);
3096
3097 // Calibrate RX A and B for RX0
3098 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3099 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3100 reg = (reg & 0xFFFFFC00) |X;
3101 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3102 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3103 reg = (reg & 0xFFFF03FF) |Y<<10;
3104 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3105 udelay(5);
3106 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3107
3108 // Calibrate init gain for A path for TX1 !!!!!!
3109 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3110 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3111 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3112 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3113 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3114 udelay(5);
3115
3116 // Calibrate init gain for C path for TX1
3117 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3118 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3119 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3120 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3121 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3122 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3123 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3124 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3125 udelay(5);
3126
3127 // Calibrate RX A and B for RX1
3128 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3129 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3130 reg = (reg & 0xFFFFFC00) |X;
3131 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3132
3133 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3134 reg = (reg & 0xFFFF03FF) |Y<<10;
3135 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3136 udelay(5);
3137
3138 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3139 break;
3140 }
3141
3142 }
3143
3144
3145 //
3146 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3147 //
3148
3149
3150 }
3151
3152 /*-----------------------------------------------------------------------------
3153 * Function: PHY_IQCalibrateBcut()
3154 *
3155 * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration
3156 * to improve RF EVM!!?
3157 *
3158 * Input: IN PADAPTER pAdapter
3159 *
3160 * Output: NONE
3161 *
3162 * Return: NONE
3163 *
3164 * Revised History:
3165 * When Who Remark
3166 * 11/18/2008 MHC Create. Document from SD3 RFSI Jenyu.
3167 * 92S B-cut QFN 68 pin IQ calibration procedure.doc
3168 *
3169 *---------------------------------------------------------------------------*/
3170 extern void PHY_IQCalibrateBcut(struct net_device* dev)
3171 {
3172 //struct r8192_priv *priv = ieee80211_priv(dev);
3173 //PMGNT_INFO pMgntInfo = &pAdapter->MgntInfo;
3174 u32 i, reg;
3175 u32 old_value;
3176 long X, Y, TX0[4];
3177 u32 TXA[4];
3178 u32 calibrate_set[13] = {0};
3179 u32 load_value[13];
3180 u8 RfPiEnable=0;
3181
3182 // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
3183
3184 //
3185 // 1. Save e70~ee0 register setting, and load calibration setting
3186 //
3187 /*
3188 0xee0[31:0]=0x3fed92fb;
3189 0xedc[31:0] =0x3fed92fb;
3190 0xe70[31:0] =0x3fed92fb;
3191 0xe74[31:0] =0x3fed92fb;
3192 0xe78[31:0] =0x3fed92fb;
3193 0xe7c[31:0]= 0x3fed92fb;
3194 0xe80[31:0]= 0x3fed92fb;
3195 0xe84[31:0]= 0x3fed92fb;
3196 0xe88[31:0]= 0x3fed92fb;
3197 0xe8c[31:0]= 0x3fed92fb;
3198 0xed0[31:0]= 0x3fed92fb;
3199 0xed4[31:0]= 0x3fed92fb;
3200 0xed8[31:0]= 0x3fed92fb;
3201 */
3202 calibrate_set [0] = 0xee0;
3203 calibrate_set [1] = 0xedc;
3204 calibrate_set [2] = 0xe70;
3205 calibrate_set [3] = 0xe74;
3206 calibrate_set [4] = 0xe78;
3207 calibrate_set [5] = 0xe7c;
3208 calibrate_set [6] = 0xe80;
3209 calibrate_set [7] = 0xe84;
3210 calibrate_set [8] = 0xe88;
3211 calibrate_set [9] = 0xe8c;
3212 calibrate_set [10] = 0xed0;
3213 calibrate_set [11] = 0xed4;
3214 calibrate_set [12] = 0xed8;
3215 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
3216 for (i = 0; i < 13; i++)
3217 {
3218 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
3219 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
3220
3221 }
3222
3223 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
3224
3225 //
3226 // 2. QFN 68
3227 //
3228 // For 1T2R IQK only now !!!
3229 for (i = 0; i < 10; i++)
3230 {
3231 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
3232 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
3233 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
3234 {
3235 //DbgPrint("IQK Switch to PI mode\n");
3236 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
3237 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
3238 }
3239
3240 // IQK
3241 // 2. IQ calibration & LO leakage calibration
3242 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3243 udelay(5);
3244 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3245 udelay(5);
3246 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3247 udelay(5);
3248 //path-A IQ K and LO K gain setting
3249 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
3250 udelay(5);
3251 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
3252 udelay(5);
3253 //set LO calibration
3254 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3255 udelay(5);
3256 //path-B IQ K and LO K gain setting
3257 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
3258 udelay(5);
3259 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
3260 udelay(5);
3261 //K idac_I & IQ
3262 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3263 udelay(5);
3264 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3265 udelay(5);
3266
3267 // delay 2ms
3268 udelay(2000);
3269
3270 //idac_Q setting
3271 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
3272 udelay(5);
3273 //K idac_Q & IQ
3274 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3275 udelay(5);
3276 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3277
3278 // delay 2ms
3279 udelay(2000);
3280
3281 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3282 udelay(5);
3283 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3284 udelay(5);
3285 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3286
3287 if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
3288 {
3289 //DbgPrint("IQK Switch back to SI mode\n");
3290 rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
3291 rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
3292 }
3293
3294
3295 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3296
3297 // 3. check fail bit, and fill BB IQ matrix
3298 // Readback IQK value and rewrite
3299 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3300 {
3301 old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3302
3303 // Calibrate init gain for A path for TX0
3304 X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3305 TXA[RF90_PATH_A] = (X * old_value)/0x100;
3306 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3307 reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3308 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3309 udelay(5);
3310
3311 // Calibrate init gain for C path for TX0
3312 Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3313 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3314 reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3315 reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3316 rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3317 reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3318 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3319 rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3320 udelay(5);
3321
3322 // Calibrate RX A and B for RX0
3323 reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3324 X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3325 reg = (reg & 0xFFFFFC00) |X;
3326 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3327 Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3328 reg = (reg & 0xFFFF03FF) |Y<<10;
3329 rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3330 udelay(5);
3331 old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3332
3333 // Calibrate init gain for A path for TX1 !!!!!!
3334 X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3335 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3336 TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3337 reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3338 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3339 udelay(5);
3340
3341 // Calibrate init gain for C path for TX1
3342 Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3343 TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3344 reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3345 reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3346 rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3347 reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3348 reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3349 rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3350 udelay(5);
3351
3352 // Calibrate RX A and B for RX1
3353 reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3354 X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3355 reg = (reg & 0xFFFFFC00) |X;
3356 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3357
3358 Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3359 reg = (reg & 0xFFFF03FF) |Y<<10;
3360 rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3361 udelay(5);
3362
3363 RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3364 break;
3365 }
3366
3367 }
3368
3369 //
3370 // 4. Reload e70~ee0 register setting.
3371 //
3372 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
3373 for (i = 0; i < 13; i++)
3374 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
3375
3376
3377 //
3378 // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3379 //
3380
3381
3382
3383 } // PHY_IQCalibrateBcut
3384
3385
3386 //
3387 // Move from phycfg.c to gen.c to be code independent later
3388 //
3389 //-------------------------Move to other DIR later----------------------------*/
3390 //#if (DEV_BUS_TYPE == USB_INTERFACE)
3391
3392 // use in phy only (in win it's timer)
3393 void SwChnlCallback8192SUsb(struct net_device *dev)
3394 {
3395
3396 struct r8192_priv *priv = ieee80211_priv(dev);
3397 u32 delay;
3398 // bool ret;
3399
3400 RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel %d\n",
3401 priv->chan);
3402
3403
3404 if(!priv->up)
3405 return;
3406
3407 if(priv->rf_chip == RF_PSEUDO_11N)
3408 {
3409 priv->SwChnlInProgress=FALSE;
3410 return; //return immediately if it is peudo-phy
3411 }
3412
3413 do{
3414 if(!priv->SwChnlInProgress)
3415 break;
3416
3417 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3418 {
3419 if(delay>0)
3420 {
3421 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3422
3423 }
3424 else
3425 continue;
3426 }
3427 else
3428 {
3429 priv->SwChnlInProgress=FALSE;
3430 }
3431 break;
3432 }while(TRUE);
3433 }
3434
3435
3436 //
3437 // Callback routine of the work item for switch channel.
3438 //
3439 // use in phy only (in win it's work)
3440 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
3441 {
3442 struct r8192_priv *priv = ieee80211_priv(dev);
3443
3444 RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
3445 #ifdef TO_DO_LIST
3446 if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
3447 {
3448 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
3449
3450 pHalData->SwChnlInProgress = FALSE;
3451 return;
3452 }
3453 #endif
3454 phy_FinishSwChnlNow(dev, priv->chan);
3455 priv->SwChnlInProgress = FALSE;
3456
3457 RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
3458 }
3459
3460
3461 /*-----------------------------------------------------------------------------
3462 * Function: SetBWModeCallback8192SUsb()
3463 *
3464 * Overview: Timer callback function for SetSetBWMode
3465 *
3466 * Input: PRT_TIMER pTimer
3467 *
3468 * Output: NONE
3469 *
3470 * Return: NONE
3471 *
3472 * Note: (1) We do not take j mode into consideration now
3473 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3474 * concurrently?
3475 *---------------------------------------------------------------------------*/
3476 //====>//rtl8192_SetBWMode
3477 // use in phy only (in win it's timer)
3478 void SetBWModeCallback8192SUsb(struct net_device *dev)
3479 {
3480 struct r8192_priv *priv = ieee80211_priv(dev);
3481 u8 regBwOpMode;
3482
3483 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3484 //u32 NowL, NowH;
3485 //u8Byte BeginTime, EndTime;
3486 u8 regRRSR_RSC;
3487
3488 RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \
3489 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3490
3491 if(priv->rf_chip == RF_PSEUDO_11N)
3492 {
3493 priv->SetBWModeInProgress= FALSE;
3494 return;
3495 }
3496
3497 if(!priv->up)
3498 return;
3499
3500 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3501 //NowL = read_nic_dword(dev, TSFR);
3502 //NowH = read_nic_dword(dev, TSFR+4);
3503 //BeginTime = ((u8Byte)NowH << 32) + NowL;
3504
3505 //3<1>Set MAC register
3506 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3507 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3508
3509 switch(priv->CurrentChannelBW)
3510 {
3511 case HT_CHANNEL_WIDTH_20:
3512 regBwOpMode |= BW_OPMODE_20MHZ;
3513 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3514 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3515 break;
3516
3517 case HT_CHANNEL_WIDTH_20_40:
3518 regBwOpMode &= ~BW_OPMODE_20MHZ;
3519 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3520 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3521
3522 regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3523 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3524 break;
3525
3526 default:
3527 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n",
3528 priv->CurrentChannelBW);
3529 break;
3530 }
3531
3532 //3 <2>Set PHY related register
3533 switch(priv->CurrentChannelBW)
3534 {
3535 case HT_CHANNEL_WIDTH_20:
3536 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3537 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3538
3539 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3540 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3541
3542 break;
3543 case HT_CHANNEL_WIDTH_20_40:
3544 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3545 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3546 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3547 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3548
3549 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3550 //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3551 //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3552 //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3553 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3554
3555 if (priv->card_8192_version >= VERSION_8192S_BCUT)
3556 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3557
3558 break;
3559 default:
3560 RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
3561 ,priv->CurrentChannelBW);
3562 break;
3563
3564 }
3565 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3566
3567 // Added it for 20/40 mhz switch time evaluation by guangan 070531
3568 //NowL = read_nic_dword(dev, TSFR);
3569 //NowH = read_nic_dword(dev, TSFR+4);
3570 //EndTime = ((u8Byte)NowH << 32) + NowL;
3571 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3572
3573 #if 1
3574 //3<3>Set RF related register
3575 switch( priv->rf_chip )
3576 {
3577 case RF_8225:
3578 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3579 break;
3580
3581 case RF_8256:
3582 // Please implement this function in Hal8190PciPhy8256.c
3583 //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3584 break;
3585
3586 case RF_6052:
3587 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3588 break;
3589
3590 case RF_8258:
3591 // Please implement this function in Hal8190PciPhy8258.c
3592 // PHY_SetRF8258Bandwidth();
3593 break;
3594
3595 case RF_PSEUDO_11N:
3596 // Do Nothing
3597 break;
3598
3599 default:
3600 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3601 break;
3602 }
3603 #endif
3604 priv->SetBWModeInProgress= FALSE;
3605
3606 RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
3607 }
3608
3609 /*
3610 * Callback routine of the work item for set bandwidth mode.
3611 *
3612 * use in phy only (in win it's work)
3613 */
3614 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
3615 {
3616 struct r8192_priv *priv = ieee80211_priv(dev);
3617 u8 regBwOpMode;
3618 u8 regRRSR_RSC;
3619
3620 RT_TRACE(COMP_SCAN, "%s(): Switch to %s bandwidth", __func__,
3621 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz");
3622
3623 if (priv->rf_chip == RF_PSEUDO_11N) {
3624 priv->SetBWModeInProgress= FALSE;
3625 return;
3626 }
3627 if(!priv->up)
3628 return;
3629 /* Set MAC register */
3630 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3631 regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3632 switch (priv->CurrentChannelBW) {
3633 case HT_CHANNEL_WIDTH_20:
3634 regBwOpMode |= BW_OPMODE_20MHZ;
3635 /* we have not verified whether this register works */
3636 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3637 break;
3638 case HT_CHANNEL_WIDTH_20_40:
3639 regBwOpMode &= ~BW_OPMODE_20MHZ;
3640 /* we have not verified whether this register works */
3641 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3642 regRRSR_RSC = (regRRSR_RSC&0x90) | (priv->nCur40MhzPrimeSC<<5);
3643 write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3644 break;
3645 default:
3646 RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
3647 priv->CurrentChannelBW);
3648 break;
3649 }
3650 /* Set PHY related register */
3651 switch (priv->CurrentChannelBW) {
3652 case HT_CHANNEL_WIDTH_20:
3653 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3654 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3655 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3656 break;
3657 case HT_CHANNEL_WIDTH_20_40:
3658 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3659 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3660 /*
3661 * Set Control channel to upper or lower.
3662 * These settings are required only for 40MHz
3663 */
3664 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
3665 (priv->nCur40MhzPrimeSC>>1));
3666 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
3667 priv->nCur40MhzPrimeSC);
3668 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3669 break;
3670 default:
3671 RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
3672 priv->CurrentChannelBW);
3673 break;
3674
3675 }
3676 /*
3677 * Skip over setting of J-mode in BB register here.
3678 * Default value is "None J mode".
3679 */
3680
3681 /* Set RF related register */
3682 switch (priv->rf_chip) {
3683 case RF_8225:
3684 PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3685 break;
3686 case RF_8256:
3687 /* Please implement this function in Hal8190PciPhy8256.c */
3688 /* PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); */
3689 break;
3690 case RF_6052:
3691 PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3692 break;
3693 case RF_8258:
3694 /* Please implement this function in Hal8190PciPhy8258.c */
3695 /* PHY_SetRF8258Bandwidth(); */
3696 break;
3697 case RF_PSEUDO_11N:
3698 /* Do Nothing */
3699 break;
3700 default:
3701 RT_TRACE(COMP_DBG, "%s(): unknown rf_chip: %d", __func__,
3702 priv->rf_chip);
3703 break;
3704 }
3705 priv->SetBWModeInProgress= FALSE;
3706 }
3707
3708 //--------------------------Move to oter DIR later-------------------------------*/
3709 void InitialGain8192S(struct net_device *dev, u8 Operation)
3710 {
3711 #ifdef TO_DO_LIST
3712 struct r8192_priv *priv = ieee80211_priv(dev);
3713 #endif
3714
3715 }
3716
3717 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
3718 {
3719 struct r8192_priv *priv = ieee80211_priv(dev);
3720
3721 priv->InitialGainOperateType = Operation;
3722
3723 if(priv->up)
3724 {
3725 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
3726 }
3727 }
3728
3729 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
3730 {
3731 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3732 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
3733 struct net_device *dev = priv->ieee80211->dev;
3734 #define SCAN_RX_INITIAL_GAIN 0x17
3735 #define POWER_DETECTION_TH 0x08
3736 u32 BitMask;
3737 u8 initial_gain;
3738 u8 Operation;
3739
3740 Operation = priv->InitialGainOperateType;
3741
3742 switch(Operation)
3743 {
3744 case IG_Backup:
3745 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3746 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
3747 BitMask = bMaskByte0;
3748 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3749 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3750 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3751 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3752 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3753 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3754 BitMask = bMaskByte2;
3755 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3756
3757 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3758 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3759 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3760 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3761 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3762
3763 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3764 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3765 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3766 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3767 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3768 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3769 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3770 break;
3771 case IG_Restore:
3772 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3773 BitMask = 0x7f; //Bit0~ Bit6
3774 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3775 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3776
3777 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3778 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3779 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3780 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3781 BitMask = bMaskByte2;
3782 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3783
3784 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3785 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3786 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3787 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3788 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3789
3790 PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
3791
3792 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3793 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3794 break;
3795 default:
3796 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3797 break;
3798 }
3799 }
3800
3801
3802 //-----------------------------------------------------------------------------
3803 // Description:
3804 // Schedule workitem to send specific CMD IO to FW.
3805 // Added by Roger, 2008.12.03.
3806 //
3807 //-----------------------------------------------------------------------------
3808 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)
3809 {
3810 struct r8192_priv *priv = ieee80211_priv(dev);
3811 u16 FwCmdWaitCounter = 0;
3812
3813 u16 FwCmdWaitLimit = 1000;
3814
3815 //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
3816 if(priv->bInHctTest)
3817 return true;
3818
3819 RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
3820
3821 // Will be done by high power respectively.
3822 if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
3823 {
3824 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
3825 return false;
3826 }
3827
3828 #if 1
3829 while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
3830 {
3831 //if(RT_USB_CANNOT_IO(Adapter))
3832 //{
3833 // RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
3834 // return FALSE;
3835 //}
3836
3837 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
3838 return false;
3839 FwCmdWaitCounter ++;
3840 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
3841 udelay(100);
3842 }
3843
3844 if(FwCmdWaitCounter == FwCmdWaitLimit)
3845 {
3846 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
3847 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
3848 //return false;
3849 }
3850 #endif
3851 if (priv->SetFwCmdInProgress)
3852 {
3853 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
3854 return false;
3855 }
3856 priv->SetFwCmdInProgress = TRUE;
3857 priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
3858
3859 phy_SetFwCmdIOCallback(dev);
3860 return true;
3861 }
3862 void ChkFwCmdIoDone(struct net_device* dev)
3863 {
3864 u16 PollingCnt = 1000;
3865 u32 tmpValue;
3866
3867 do
3868 {// Make sure that CMD IO has be accepted by FW.
3869 #ifdef TO_DO_LIST
3870 if(RT_USB_CANNOT_IO(Adapter))
3871 {
3872 RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
3873 return;
3874 }
3875 #endif
3876 udelay(10); // sleep 20us
3877 tmpValue = read_nic_dword(dev, WFM5);
3878 if(tmpValue == 0)
3879 {
3880 RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
3881 break;
3882 }
3883 else
3884 {
3885 RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
3886 }
3887 }while( --PollingCnt );
3888
3889 if(PollingCnt == 0)
3890 {
3891 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
3892 }
3893 }
3894 // Callback routine of the timer callback for FW Cmd IO.
3895 //
3896 // Description:
3897 // This routine will send specific CMD IO to FW and check whether it is done.
3898 //
3899 void phy_SetFwCmdIOCallback(struct net_device* dev)
3900 {
3901 //struct net_device* dev = (struct net_device*) data;
3902 u32 input;
3903 static u32 ScanRegister;
3904 struct r8192_priv *priv = ieee80211_priv(dev);
3905 if(!priv->up)
3906 {
3907 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
3908 return;
3909 }
3910
3911 RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
3912
3913 switch(priv->CurrentFwCmdIO)
3914 {
3915 case FW_CMD_HIGH_PWR_ENABLE:
3916 if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3917 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
3918 break;
3919
3920 case FW_CMD_HIGH_PWR_DISABLE:
3921 write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
3922 break;
3923
3924 case FW_CMD_DIG_RESUME:
3925 write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3926 break;
3927
3928 case FW_CMD_DIG_HALT:
3929 write_nic_dword(dev, WFM5, FW_DIG_HALT);
3930 break;
3931
3932 //
3933 // <Roger_Notes> The following FW CMD IO was combined into single operation
3934 // (i.e., to prevent number of system workitem out of resource!!).
3935 // 2008.12.04.
3936 //
3937 case FW_CMD_RESUME_DM_BY_SCAN:
3938 RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
3939 if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3940 {
3941 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
3942 ChkFwCmdIoDone(dev);
3943 }
3944 write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3945 break;
3946
3947 case FW_CMD_PAUSE_DM_BY_SCAN:
3948 RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
3949 write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
3950 ChkFwCmdIoDone(dev);
3951 write_nic_dword(dev, WFM5, FW_DIG_HALT);
3952 break;
3953
3954 //
3955 // <Roger_Notes> The following FW CMD IO should be checked
3956 // (i.e., workitem schedule timing issue!!).
3957 // 2008.12.04.
3958 //
3959 case FW_CMD_DIG_DISABLE:
3960 RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
3961 write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
3962 break;
3963
3964 case FW_CMD_DIG_ENABLE:
3965 RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
3966 write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
3967 break;
3968
3969 case FW_CMD_RA_RESET:
3970 write_nic_dword(dev, WFM5, FW_RA_RESET);
3971 break;
3972
3973 case FW_CMD_RA_ACTIVE:
3974 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
3975 break;
3976
3977 case FW_CMD_RA_REFRESH_N:
3978 RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
3979 if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
3980 input = FW_RA_REFRESH;
3981 else
3982 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
3983 write_nic_dword(dev, WFM5, input);
3984 break;
3985 case FW_CMD_RA_REFRESH_BG:
3986 RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
3987 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
3988 ChkFwCmdIoDone(dev);
3989 write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
3990 break;
3991
3992 case FW_CMD_IQK_ENABLE:
3993 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
3994 break;
3995
3996 case FW_CMD_TXPWR_TRACK_ENABLE:
3997 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
3998 break;
3999
4000 case FW_CMD_TXPWR_TRACK_DISABLE:
4001 write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4002 break;
4003
4004 default:
4005 RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4006 break;
4007 }
4008
4009 ChkFwCmdIoDone(dev);
4010
4011 switch(priv->CurrentFwCmdIO)
4012 {
4013 case FW_CMD_HIGH_PWR_DISABLE:
4014 //if(pMgntInfo->bTurboScan)
4015 {
4016 //Lower initial gain
4017 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4018 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4019 // CCA threshold
4020 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4021 // Disable OFDM Part
4022 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4023 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4024 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4025 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4026 }
4027 break;
4028
4029 case FW_CMD_HIGH_PWR_ENABLE:
4030 //if(pMgntInfo->bTurboScan)
4031 {
4032 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4033 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4034
4035 // CCA threshold
4036 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4037 // Enable OFDM Part
4038 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4039
4040 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4041 if(ScanRegister != 0){
4042 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4043 }
4044
4045 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4046 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4047 else
4048 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4049 }
4050 break;
4051 }
4052
4053 priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
4054 RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
4055
4056 }
4057
kernel source for telekom puls (alcatel/mediatek)