drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2  * This is part of the rtl8180-sa2400 driver
   3  * released under the GPL (See file COPYING for details).
   4  * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5  *
   6  * This files contains programming code for the rtl8225
   7  * radio frontend.
   8  *
   9  * *Many* thanks to Realtek Corp. for their great support!
  10  */
  11
  12 #include "r8180_hw.h"
  13 #include "r8180_rtl8225.h"
  14 #include "r8180_93cx6.h"
  15
  16 #include "ieee80211/dot11d.h"
  17
  18 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
  19 {
  20         int i;
  21         u16 out, select;
  22         u8 bit;
  23         u32 bangdata = (data << 4) | (adr & 0xf);
  24
  25         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
  26
  27         write_nic_word(dev, RFPinsEnable,
  28                 (read_nic_word(dev, RFPinsEnable) | 0x7));
  29
  30         select = read_nic_word(dev, RFPinsSelect);
  31
  32         write_nic_word(dev, RFPinsSelect, select | 0x7 |
  33                        SW_CONTROL_GPIO);
  34
  35         force_pci_posting(dev);
  36         udelay(10);
  37
  38         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  39
  40         force_pci_posting(dev);
  41         udelay(2);
  42
  43         write_nic_word(dev, RFPinsOutput, out);
  44
  45         force_pci_posting(dev);
  46         udelay(10);
  47
  48         for (i = 15; i >= 0; i--) {
  49                 bit = (bangdata & (1 << i)) >> i;
  50
  51                 write_nic_word(dev, RFPinsOutput, bit | out);
  52
  53                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  54                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  55
  56                 i--;
  57                 bit = (bangdata & (1 << i)) >> i;
  58
  59                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  60                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  61
  62                 write_nic_word(dev, RFPinsOutput, bit | out);
  63
  64         }
  65
  66         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  67
  68         force_pci_posting(dev);
  69         udelay(10);
  70
  71         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  72
  73         write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
  74
  75         rtl8185_rf_pins_enable(dev);
  76 }
  77
  78 static const u8 rtl8225_agc[] = {
  79         0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
  80         0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
  81         0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
  82         0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
  83         0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
  84         0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
  85         0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
  86         0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
  87         0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
  88         0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
  89         0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
  90         0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
  91         0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
  92         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  93         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  94         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  95 };
  96
  97 static const u32 rtl8225_chan[] = {
  98         0,
  99         0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
 100         0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
 101 };
 102
 103 static const u8 rtl8225z2_gain_bg[] = {
 104         0x23, 0x15, 0xa5, /* -82-1dBm */
 105         0x23, 0x15, 0xb5, /* -82-2dBm */
 106         0x23, 0x15, 0xc5, /* -82-3dBm */
 107         0x33, 0x15, 0xc5, /* -78dBm */
 108         0x43, 0x15, 0xc5, /* -74dBm */
 109         0x53, 0x15, 0xc5, /* -70dBm */
 110         0x63, 0x15, 0xc5, /* -66dBm */
 111 };
 112
 113 static const u8 rtl8225z2_gain_a[] = {
 114         0x13, 0x27, 0x5a, /* -82dBm */
 115         0x23, 0x23, 0x58, /* -82dBm */
 116         0x33, 0x1f, 0x56, /* -82dBm */
 117         0x43, 0x1b, 0x54, /* -78dBm */
 118         0x53, 0x17, 0x51, /* -74dBm */
 119         0x63, 0x24, 0x4f, /* -70dBm */
 120         0x73, 0x0f, 0x4c, /* -66dBm */
 121 };
 122
 123 static const u16 rtl8225z2_rxgain[] = {
 124         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 125         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 126         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
 127         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
 128         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
 129         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
 130         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
 131         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
 132         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
 133         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
 134         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
 135         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb
 136
 137 };
 138
 139 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 140 {
 141         const u8 *rtl8225_gain;
 142         struct r8180_priv *priv = ieee80211_priv(dev);
 143         u8 mode = priv->ieee80211->mode;
 144
 145         if (mode == IEEE_B || mode == IEEE_G)
 146                 rtl8225_gain = rtl8225z2_gain_bg;
 147         else
 148                 rtl8225_gain = rtl8225z2_gain_a;
 149
 150         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 151         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 152         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 153         write_phy_ofdm(dev, 0x21, 0x37);
 154 }
 155
 156 static u32 read_rtl8225(struct net_device *dev, u8 adr)
 157 {
 158         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 159         u32 dataRead;
 160         u32 mask;
 161         u16 oval, oval2, oval3, tmp;
 162         int i;
 163         short bit, rw;
 164         u8 wLength = 6;
 165         u8 rLength = 12;
 166         u8 low2high = 0;
 167
 168         oval = read_nic_word(dev, RFPinsOutput);
 169         oval2 = read_nic_word(dev, RFPinsEnable);
 170         oval3 = read_nic_word(dev, RFPinsSelect);
 171
 172         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 173         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 174
 175         dataRead = 0;
 176
 177         oval &= ~0xf;
 178
 179         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN);
 180         udelay(4);
 181
 182         write_nic_word(dev, RFPinsOutput, oval);
 183         udelay(5);
 184
 185         rw = 0;
 186
 187         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 188
 189         for (i = 0; i < wLength/2; i++) {
 190                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 191                 write_nic_word(dev, RFPinsOutput, bit | oval | rw);
 192                 udelay(1);
 193
 194                 write_nic_word(dev, RFPinsOutput,
 195                                 bit | oval | BB_HOST_BANG_CLK | rw);
 196                 udelay(2);
 197                 write_nic_word(dev, RFPinsOutput,
 198                                 bit | oval | BB_HOST_BANG_CLK | rw);
 199                 udelay(2);
 200
 201                 mask = (low2high) ? (mask<<1) : (mask>>1);
 202
 203                 if (i == 2) {
 204                         rw = BB_HOST_BANG_RW;
 205                         write_nic_word(dev, RFPinsOutput,
 206                                         bit | oval | BB_HOST_BANG_CLK | rw);
 207                         udelay(2);
 208                         write_nic_word(dev, RFPinsOutput, bit | oval | rw);
 209                         udelay(2);
 210                         break;
 211                 }
 212
 213                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 214
 215                 write_nic_word(dev, RFPinsOutput,
 216                                 oval | bit | rw | BB_HOST_BANG_CLK);
 217                 udelay(2);
 218                 write_nic_word(dev, RFPinsOutput,
 219                                 oval | bit | rw | BB_HOST_BANG_CLK);
 220                 udelay(2);
 221
 222                 write_nic_word(dev, RFPinsOutput, oval | bit | rw);
 223                 udelay(1);
 224
 225                 mask = (low2high) ? (mask<<1) : (mask>>1);
 226         }
 227
 228         write_nic_word(dev, RFPinsOutput, rw|oval);
 229         udelay(2);
 230         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 231
 232         /*
 233          * We must set data pin to HW controlled, otherwise RF can't driver it
 234          * and value RF register won't be able to read back properly.
 235          */
 236         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 237
 238         for (i = 0; i < rLength; i++) {
 239                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 240
 241                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 242                 udelay(2);
 243                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 244                 udelay(2);
 245                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 246                 udelay(2);
 247                 tmp = read_nic_word(dev, RFPinsInput);
 248
 249                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 250
 251                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 252
 253                 mask = (low2high) ? (mask<<1) : (mask>>1);
 254         }
 255
 256         write_nic_word(dev, RFPinsOutput,
 257                         BB_HOST_BANG_EN | BB_HOST_BANG_RW | oval);
 258         udelay(2);
 259
 260         write_nic_word(dev, RFPinsEnable, oval2);
 261         write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
 262         write_nic_word(dev, RFPinsOutput, 0x3a0);
 263
 264         return dataRead;
 265 }
 266
 267 void rtl8225z2_rf_close(struct net_device *dev)
 268 {
 269         RF_WriteReg(dev, 0x4, 0x1f);
 270
 271         force_pci_posting(dev);
 272         mdelay(1);
 273
 274         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 275         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 276 }
 277
 278 /*
 279  * Map dBm into Tx power index according to current HW model, for example,
 280  * RF and PA, and current wireless mode.
 281  */
 282 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
 283                  s32 PowerInDbm)
 284 {
 285         bool bUseDefault = true;
 286         s8 TxPwrIdx = 0;
 287
 288         /*
 289          * OFDM Power in dBm = Index * 0.5 + 0
 290          * CCK Power in dBm = Index * 0.25 + 13
 291          */
 292         s32 tmp = 0;
 293
 294         if (WirelessMode == WIRELESS_MODE_G) {
 295                 bUseDefault = false;
 296                 tmp = (2 * PowerInDbm);
 297
 298                 if (tmp < 0)
 299                         TxPwrIdx = 0;
 300                 else if (tmp > 40) /* 40 means 20 dBm. */
 301                         TxPwrIdx = 40;
 302                 else
 303                         TxPwrIdx = (s8)tmp;
 304         } else if (WirelessMode == WIRELESS_MODE_B) {
 305                 bUseDefault = false;
 306                 tmp = (4 * PowerInDbm) - 52;
 307
 308                 if (tmp < 0)
 309                         TxPwrIdx = 0;
 310                 else if (tmp > 28) /* 28 means 20 dBm. */
 311                         TxPwrIdx = 28;
 312                 else
 313                         TxPwrIdx = (s8)tmp;
 314         }
 315
 316         /*
 317          * TRUE if we want to use a default implementation.
 318          * We shall set it to FALSE when we have exact translation formula
 319          * for target IC. 070622, by rcnjko.
 320          */
 321         if (bUseDefault) {
 322                 if (PowerInDbm < 0)
 323                         TxPwrIdx = 0;
 324                 else if (PowerInDbm > 35)
 325                         TxPwrIdx = 35;
 326                 else
 327                         TxPwrIdx = (u8)PowerInDbm;
 328         }
 329
 330         return TxPwrIdx;
 331 }
 332
 333 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 334 {
 335         struct r8180_priv *priv = ieee80211_priv(dev);
 336         u8 max_cck_power_level;
 337         u8 max_ofdm_power_level;
 338         u8 min_ofdm_power_level;
 339         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
 340         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
 341
 342         if (IS_DOT11D_ENABLE(priv->ieee80211) &&
 343             IS_DOT11D_STATE_DONE(priv->ieee80211)) {
 344                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 345                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B,
 346                                                         MaxTxPwrInDbm);
 347                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G,
 348                                                         MaxTxPwrInDbm);
 349
 350                 if (cck_power_level > CckMaxPwrIdx)
 351                         cck_power_level = CckMaxPwrIdx;
 352                 if (ofdm_power_level > OfdmMaxPwrIdx)
 353                         ofdm_power_level = OfdmMaxPwrIdx;
 354         }
 355
 356         max_cck_power_level = 15;
 357         max_ofdm_power_level = 25;
 358         min_ofdm_power_level = 10;
 359
 360         if (cck_power_level > 35)
 361                 cck_power_level = 35;
 362
 363         write_nic_byte(dev, CCK_TXAGC, cck_power_level);
 364         force_pci_posting(dev);
 365         mdelay(1);
 366
 367         if (ofdm_power_level > 35)
 368                 ofdm_power_level = 35;
 369
 370         if (priv->up == 0) {
 371                 write_phy_ofdm(dev, 2, 0x42);
 372                 write_phy_ofdm(dev, 5, 0x00);
 373                 write_phy_ofdm(dev, 6, 0x40);
 374                 write_phy_ofdm(dev, 7, 0x00);
 375                 write_phy_ofdm(dev, 8, 0x40);
 376         }
 377
 378         write_nic_byte(dev, OFDM_TXAGC, ofdm_power_level);
 379
 380         if (ofdm_power_level <= 11) {
 381                 write_phy_ofdm(dev, 0x07, 0x5c);
 382                 write_phy_ofdm(dev, 0x09, 0x5c);
 383         }
 384
 385         if (ofdm_power_level <= 17) {
 386                 write_phy_ofdm(dev, 0x07, 0x54);
 387                 write_phy_ofdm(dev, 0x09, 0x54);
 388         } else {
 389                 write_phy_ofdm(dev, 0x07, 0x50);
 390                 write_phy_ofdm(dev, 0x09, 0x50);
 391         }
 392
 393         force_pci_posting(dev);
 394         mdelay(1);
 395 }
 396
 397 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 398 {
 399         rtl8225z2_SetTXPowerLevel(dev, ch);
 400
 401         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 402
 403         if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 404                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 405
 406         mdelay(1);
 407
 408         force_pci_posting(dev);
 409         mdelay(10);
 410 }
 411
 412 static void rtl8225_host_pci_init(struct net_device *dev)
 413 {
 414         write_nic_word(dev, RFPinsOutput, 0x480);
 415
 416         rtl8185_rf_pins_enable(dev);
 417
 418         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
 419
 420         write_nic_byte(dev, GP_ENABLE, 0);
 421
 422         force_pci_posting(dev);
 423         mdelay(200);
 424
 425         /* bit 6 is for RF on/off detection */
 426         write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
 427 }
 428
 429 void rtl8225z2_rf_init(struct net_device *dev)
 430 {
 431         struct r8180_priv *priv = ieee80211_priv(dev);
 432         int i;
 433         short channel = 1;
 434         u16 brsr;
 435         u32 data;
 436
 437         priv->chan = channel;
 438
 439         rtl8225_host_pci_init(dev);
 440
 441         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 442
 443         brsr = read_nic_word(dev, BRSR);
 444
 445         write_nic_word(dev, BRSR, 0xffff);
 446
 447         write_nic_dword(dev, RF_PARA, 0x100044);
 448
 449         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 450         write_nic_byte(dev, CONFIG3, 0x44);
 451         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 452
 453         rtl8185_rf_pins_enable(dev);
 454
 455         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 456         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 457         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 458         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 459         write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
 460         write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
 461         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 462         write_rtl8225(dev, 0x7, rtl8225_chan[channel]);  mdelay(1);
 463         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 464         write_rtl8225(dev, 0x9, 0x335); mdelay(1);
 465         write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
 466         write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
 467         write_rtl8225(dev, 0xc, 0x850); mdelay(1);
 468         write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
 469         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 470         write_rtl8225(dev, 0xf, 0x114);
 471
 472         mdelay(100);
 473
 474         write_rtl8225(dev, 0x0, 0x1b7);
 475
 476         for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) {
 477                 write_rtl8225(dev, 0x1, i + 1);
 478                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 479         }
 480
 481         write_rtl8225(dev, 0x3, 0x80);
 482         write_rtl8225(dev, 0x5, 0x4);
 483
 484         write_rtl8225(dev, 0x0, 0xb7);
 485
 486         write_rtl8225(dev, 0x2, 0xc4d);
 487
 488         /* FIXME!! rtl8187 we have to check if calibrarion
 489          * is successful and eventually cal. again (repeat
 490          * the two write on reg 2)
 491          */
 492         data = read_rtl8225(dev, 6);
 493         if (!(data & 0x00000080)) {
 494                 write_rtl8225(dev, 0x02, 0x0c4d);
 495                 force_pci_posting(dev); mdelay(200);
 496                 write_rtl8225(dev, 0x02, 0x044d);
 497                 force_pci_posting(dev); mdelay(100);
 498                 data = read_rtl8225(dev, 6);
 499                 if (!(data & 0x00000080))
 500                         DMESGW("RF Calibration Failed!!!!\n");
 501         }
 502
 503         mdelay(200);
 504
 505         write_rtl8225(dev, 0x0, 0x2bf);
 506
 507         for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) {
 508                 write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
 509                 mdelay(1);
 510
 511                 /* enable writing AGC table */
 512                 write_phy_ofdm(dev, 0xa, i + 0x80);
 513                 mdelay(1);
 514         }
 515
 516         force_pci_posting(dev);
 517         mdelay(1);
 518
 519         write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
 520         write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
 521         write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
 522         write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
 523         write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
 524         write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
 525         write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
 526         write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
 527         write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
 528         write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
 529         write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
 530         write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
 531         write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
 532         write_phy_ofdm(dev, 0x0d, 0x43);
 533         write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
 534         write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
 535         write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
 536         write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
 537         write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
 538         write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
 539         write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
 540         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
 541         write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
 542         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
 543         write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
 544         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
 545         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
 546         write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
 547         write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
 548         write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
 549         write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
 550         write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
 551         write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
 552         write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
 553         write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
 554         write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
 555         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
 556         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
 557         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
 558         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
 559
 560         rtl8225z2_set_gain(dev, 4);
 561
 562         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
 563         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
 564         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
 565         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
 566         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
 567         write_phy_cck(dev, 0x7, 0x78); mdelay(1);
 568         write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
 569         write_phy_cck(dev, 0x10, 0x93); mdelay(1);
 570         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
 571         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
 572         write_phy_cck(dev, 0x13, 0xd0);
 573         write_phy_cck(dev, 0x19, 0x00);
 574         write_phy_cck(dev, 0x1a, 0xa0);
 575         write_phy_cck(dev, 0x1b, 0x08);
 576         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
 577         write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
 578         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
 579         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
 580         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
 581         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
 582         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
 583         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
 584         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
 585         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
 586         write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
 587         write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
 588         write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
 589
 590         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
 591
 592         rtl8225z2_SetTXPowerLevel(dev, channel);
 593
 594         /* RX antenna default to A */
 595         write_phy_cck(dev, 0x11, 0x9b); mdelay(1);              /* B: 0xDB */
 596         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);             /* B: 0x10 */
 597
 598         rtl8185_tx_antenna(dev, 0x03);                          /* B: 0x00 */
 599
 600         /* switch to high-speed 3-wire
 601          * last digit. 2 for both cck and ofdm
 602          */
 603         write_nic_dword(dev, 0x94, 0x15c00002);
 604         rtl8185_rf_pins_enable(dev);
 605
 606         rtl8225z2_rf_set_chan(dev, priv->chan);
 607 }
 608
 609 void rtl8225z2_rf_set_mode(struct net_device *dev)
 610 {
 611         struct r8180_priv *priv = ieee80211_priv(dev);
 612
 613         if (priv->ieee80211->mode == IEEE_A) {
 614                 write_rtl8225(dev, 0x5, 0x1865);
 615                 write_nic_dword(dev, RF_PARA, 0x10084);
 616                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 617                 write_phy_ofdm(dev, 0x0, 0x0);
 618                 write_phy_ofdm(dev, 0xa, 0x6);
 619                 write_phy_ofdm(dev, 0xb, 0x99);
 620                 write_phy_ofdm(dev, 0xf, 0x20);
 621                 write_phy_ofdm(dev, 0x11, 0x7);
 622
 623                 rtl8225z2_set_gain(dev, 4);
 624
 625                 write_phy_ofdm(dev, 0x15, 0x40);
 626                 write_phy_ofdm(dev, 0x17, 0x40);
 627
 628                 write_nic_dword(dev, 0x94, 0x10000000);
 629         } else {
 630                 write_rtl8225(dev, 0x5, 0x1864);
 631                 write_nic_dword(dev, RF_PARA, 0x10044);
 632                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 633                 write_phy_ofdm(dev, 0x0, 0x1);
 634                 write_phy_ofdm(dev, 0xa, 0x6);
 635                 write_phy_ofdm(dev, 0xb, 0x99);
 636                 write_phy_ofdm(dev, 0xf, 0x20);
 637                 write_phy_ofdm(dev, 0x11, 0x7);
 638
 639                 rtl8225z2_set_gain(dev, 4);
 640
 641                 write_phy_ofdm(dev, 0x15, 0x40);
 642                 write_phy_ofdm(dev, 0x17, 0x40);
 643
 644                 write_nic_dword(dev, 0x94, 0x04000002);
 645         }
 646 }
 647
 648 #define MAX_DOZE_WAITING_TIMES_85B              20
 649 #define MAX_POLLING_24F_TIMES_87SE              10
 650 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
 651
 652 bool SetZebraRFPowerState8185(struct net_device *dev,
 653                               RT_RF_POWER_STATE eRFPowerState)
 654 {
 655         struct r8180_priv *priv = ieee80211_priv(dev);
 656         u8                      btCR9346, btConfig3;
 657         bool bActionAllowed = true, bTurnOffBB = true;
 658         u8                      u1bTmp;
 659         int                     i;
 660         bool            bResult = true;
 661         u8                      QueueID;
 662
 663         if (priv->SetRFPowerStateInProgress == true)
 664                 return false;
 665
 666         priv->SetRFPowerStateInProgress = true;
 667
 668         btCR9346 = read_nic_byte(dev, CR9346);
 669         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
 670
 671         btConfig3 = read_nic_byte(dev, CONFIG3);
 672         write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
 673
 674         switch (eRFPowerState) {
 675         case eRfOn:
 676                 write_nic_word(dev, 0x37C, 0x00EC);
 677
 678                 /* turn on AFE */
 679                 write_nic_byte(dev, 0x54, 0x00);
 680                 write_nic_byte(dev, 0x62, 0x00);
 681
 682                 /* turn on RF */
 683                 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 684                 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 685
 686                 /* turn on RF again */
 687                 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 688                 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 689
 690                 /* turn on BB */
 691                 write_phy_ofdm(dev, 0x10, 0x40);
 692                 write_phy_ofdm(dev, 0x12, 0x40);
 693
 694                 /* Avoid power down at init time. */
 695                 write_nic_byte(dev, CONFIG4, priv->RFProgType);
 696
 697                 u1bTmp = read_nic_byte(dev, 0x24E);
 698                 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 699                 break;
 700         case eRfSleep:
 701                 for (QueueID = 0, i = 0; QueueID < 6;) {
 702                         if (get_curr_tx_free_desc(dev, QueueID) ==
 703                                                         priv->txringcount) {
 704                                 QueueID++;
 705                                 continue;
 706                         } else {
 707                                 priv->TxPollingTimes++;
 708                                 if (priv->TxPollingTimes >=
 709                                         LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 710                                         bActionAllowed = false;
 711                                         break;
 712                                 } else
 713                                         udelay(10);
 714                         }
 715                 }
 716
 717                 if (bActionAllowed) {
 718                         /* turn off BB RXIQ matrix to cut off rx signal */
 719                         write_phy_ofdm(dev, 0x10, 0x00);
 720                         write_phy_ofdm(dev, 0x12, 0x00);
 721
 722                         /* turn off RF */
 723                         RF_WriteReg(dev, 0x4, 0x0000);
 724                         RF_WriteReg(dev, 0x0, 0x0000);
 725
 726                         /* turn off AFE except PLL */
 727                         write_nic_byte(dev, 0x62, 0xff);
 728                         write_nic_byte(dev, 0x54, 0xec);
 729
 730                         mdelay(1);
 731
 732                         {
 733                                 int i = 0;
 734                                 while (true) {
 735                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
 736
 737                                         if ((tmp24F == 0x01) ||
 738                                                         (tmp24F == 0x09)) {
 739                                                 bTurnOffBB = true;
 740                                                 break;
 741                                         } else {
 742                                                 udelay(10);
 743                                                 i++;
 744                                                 priv->TxPollingTimes++;
 745
 746                                                 if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 747                                                         bTurnOffBB = false;
 748                                                         break;
 749                                                 } else
 750                                                         udelay(10);
 751                                         }
 752                                 }
 753                         }
 754
 755                         if (bTurnOffBB) {
 756                                 /* turn off BB */
 757                                 u1bTmp = read_nic_byte(dev, 0x24E);
 758                                 write_nic_byte(dev, 0x24E,
 759                                                 (u1bTmp | BIT5 | BIT6));
 760
 761                                 /* turn off AFE PLL */
 762                                 write_nic_byte(dev, 0x54, 0xFC);
 763                                 write_nic_word(dev, 0x37C, 0x00FC);
 764                         }
 765                 }
 766                 break;
 767         case eRfOff:
 768                 for (QueueID = 0, i = 0; QueueID < 6;) {
 769                         if (get_curr_tx_free_desc(dev, QueueID) ==
 770                                         priv->txringcount) {
 771                                 QueueID++;
 772                                 continue;
 773                         } else {
 774                                 udelay(10);
 775                                 i++;
 776                         }
 777
 778                         if (i >= MAX_DOZE_WAITING_TIMES_85B)
 779                                 break;
 780                 }
 781
 782                 /* turn off BB RXIQ matrix to cut off rx signal */
 783                 write_phy_ofdm(dev, 0x10, 0x00);
 784                 write_phy_ofdm(dev, 0x12, 0x00);
 785
 786                 /* turn off RF */
 787                 RF_WriteReg(dev, 0x4, 0x0000);
 788                 RF_WriteReg(dev, 0x0, 0x0000);
 789
 790                 /* turn off AFE except PLL */
 791                 write_nic_byte(dev, 0x62, 0xff);
 792                 write_nic_byte(dev, 0x54, 0xec);
 793
 794                 mdelay(1);
 795
 796                 {
 797                         int i = 0;
 798
 799                         while (true) {
 800                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
 801
 802                                 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
 803                                         bTurnOffBB = true;
 804                                         break;
 805                                 } else {
 806                                         bTurnOffBB = false;
 807                                         udelay(10);
 808                                         i++;
 809                                 }
 810
 811                                 if (i > MAX_POLLING_24F_TIMES_87SE)
 812                                         break;
 813                         }
 814                 }
 815
 816                 if (bTurnOffBB) {
 817                         /* turn off BB */
 818                         u1bTmp = read_nic_byte(dev, 0x24E);
 819                         write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
 820
 821                         /* turn off AFE PLL (80M) */
 822                         write_nic_byte(dev, 0x54, 0xFC);
 823                         write_nic_word(dev, 0x37C, 0x00FC);
 824                 }
 825                 break;
 826         }
 827
 828         btConfig3 &= ~(CONFIG3_PARM_En);
 829         write_nic_byte(dev, CONFIG3, btConfig3);
 830
 831         btCR9346 &= ~(0xC0);
 832         write_nic_byte(dev, CR9346, btCR9346);
 833
 834         if (bResult && bActionAllowed)
 835                 priv->eRFPowerState = eRFPowerState;
 836
 837         priv->SetRFPowerStateInProgress = false;
 838
 839         return bResult && bActionAllowed;
 840 }
 841
 842 void rtl8225z4_rf_sleep(struct net_device *dev)
 843 {
 844         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
 845 }
 846
 847 void rtl8225z4_rf_wakeup(struct net_device *dev)
 848 {
 849         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
 850 }