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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rt2860 / rt28xx.h
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rt28xx.h
29
30 Abstract:
31 RT28xx ASIC related definition & structures
32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
36 Jan Lee Jan-3-2006 created for RT2860c
37 */
38
39 #ifndef __RT28XX_H__
40 #define __RT28XX_H__
41
42
43 //
44 // PCI registers - base address 0x0000
45 //
46 #define PCI_CFG 0x0000
47 #define PCI_EECTRL 0x0004
48 #define PCI_MCUCTRL 0x0008
49
50 typedef int NTSTATUS;
51
52 #define OPT_14 0x114
53
54 //
55 // SCH/DMA registers - base address 0x0200
56 //
57 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
58 //
59 #define DMA_CSR0 0x200
60 #define INT_SOURCE_CSR 0x200
61 typedef union _INT_SOURCE_CSR_STRUC {
62 struct {
63 UINT32 RxDelayINT:1;
64 UINT32 TxDelayINT:1;
65 UINT32 RxDone:1;
66 UINT32 Ac0DmaDone:1;//4
67 UINT32 Ac1DmaDone:1;
68 UINT32 Ac2DmaDone:1;
69 UINT32 Ac3DmaDone:1;
70 UINT32 HccaDmaDone:1; // bit7
71 UINT32 MgmtDmaDone:1;
72 UINT32 MCUCommandINT:1;//bit 9
73 UINT32 RxTxCoherent:1;
74 UINT32 TBTTInt:1;
75 UINT32 PreTBTT:1;
76 UINT32 TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
77 UINT32 AutoWakeup:1;//bit14
78 UINT32 GPTimer:1;
79 UINT32 RxCoherent:1;//bit16
80 UINT32 TxCoherent:1;
81 UINT32 :14;
82 } field;
83 UINT32 word;
84 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
85
86 //
87 // INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF
88 //
89 #define INT_MASK_CSR 0x204
90 typedef union _INT_MASK_CSR_STRUC {
91 struct {
92 UINT32 RXDelay_INT_MSK:1;
93 UINT32 TxDelay:1;
94 UINT32 RxDone:1;
95 UINT32 Ac0DmaDone:1;
96 UINT32 Ac1DmaDone:1;
97 UINT32 Ac2DmaDone:1;
98 UINT32 Ac3DmaDone:1;
99 UINT32 HccaDmaDone:1;
100 UINT32 MgmtDmaDone:1;
101 UINT32 MCUCommandINT:1;
102 UINT32 :20;
103 UINT32 RxCoherent:1;
104 UINT32 TxCoherent:1;
105 } field;
106 UINT32 word;
107 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
108
109 #define WPDMA_GLO_CFG 0x208
110 typedef union _WPDMA_GLO_CFG_STRUC {
111 struct {
112 UINT32 EnableTxDMA:1;
113 UINT32 TxDMABusy:1;
114 UINT32 EnableRxDMA:1;
115 UINT32 RxDMABusy:1;
116 UINT32 WPDMABurstSIZE:2;
117 UINT32 EnTXWriteBackDDONE:1;
118 UINT32 BigEndian:1;
119 UINT32 RXHdrScater:8;
120 UINT32 HDR_SEG_LEN:16;
121 } field;
122 UINT32 word;
123 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
124
125 #define WPDMA_RST_IDX 0x20c
126 typedef union _WPDMA_RST_IDX_STRUC {
127 struct {
128 UINT32 RST_DTX_IDX0:1;
129 UINT32 RST_DTX_IDX1:1;
130 UINT32 RST_DTX_IDX2:1;
131 UINT32 RST_DTX_IDX3:1;
132 UINT32 RST_DTX_IDX4:1;
133 UINT32 RST_DTX_IDX5:1;
134 UINT32 rsv:10;
135 UINT32 RST_DRX_IDX0:1;
136 UINT32 :15;
137 } field;
138 UINT32 word;
139 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
140
141 #define DELAY_INT_CFG 0x0210
142 typedef union _DELAY_INT_CFG_STRUC {
143 struct {
144 UINT32 RXMAX_PTIME:8;
145 UINT32 RXMAX_PINT:7;
146 UINT32 RXDLY_INT_EN:1;
147 UINT32 TXMAX_PTIME:8;
148 UINT32 TXMAX_PINT:7;
149 UINT32 TXDLY_INT_EN:1;
150 } field;
151 UINT32 word;
152 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
153
154 #define WMM_AIFSN_CFG 0x0214
155 typedef union _AIFSN_CSR_STRUC {
156 struct {
157 UINT32 Aifsn0:4; // for AC_BE
158 UINT32 Aifsn1:4; // for AC_BK
159 UINT32 Aifsn2:4; // for AC_VI
160 UINT32 Aifsn3:4; // for AC_VO
161 UINT32 Rsv:16;
162 } field;
163 UINT32 word;
164 } AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
165
166 //
167 // CWMIN_CSR: CWmin for each EDCA AC
168 //
169 #define WMM_CWMIN_CFG 0x0218
170 typedef union _CWMIN_CSR_STRUC {
171 struct {
172 UINT32 Cwmin0:4; // for AC_BE
173 UINT32 Cwmin1:4; // for AC_BK
174 UINT32 Cwmin2:4; // for AC_VI
175 UINT32 Cwmin3:4; // for AC_VO
176 UINT32 Rsv:16;
177 } field;
178 UINT32 word;
179 } CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
180
181 //
182 // CWMAX_CSR: CWmin for each EDCA AC
183 //
184 #define WMM_CWMAX_CFG 0x021c
185 typedef union _CWMAX_CSR_STRUC {
186 struct {
187 UINT32 Cwmax0:4; // for AC_BE
188 UINT32 Cwmax1:4; // for AC_BK
189 UINT32 Cwmax2:4; // for AC_VI
190 UINT32 Cwmax3:4; // for AC_VO
191 UINT32 Rsv:16;
192 } field;
193 UINT32 word;
194 } CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
195
196 //
197 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
198 //
199 #define WMM_TXOP0_CFG 0x0220
200 typedef union _AC_TXOP_CSR0_STRUC {
201 struct {
202 USHORT Ac0Txop; // for AC_BK, in unit of 32us
203 USHORT Ac1Txop; // for AC_BE, in unit of 32us
204 } field;
205 UINT32 word;
206 } AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
207
208 //
209 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
210 //
211 #define WMM_TXOP1_CFG 0x0224
212 typedef union _AC_TXOP_CSR1_STRUC {
213 struct {
214 USHORT Ac2Txop; // for AC_VI, in unit of 32us
215 USHORT Ac3Txop; // for AC_VO, in unit of 32us
216 } field;
217 UINT32 word;
218 } AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
219
220 #define RINGREG_DIFF 0x10
221 #define GPIO_CTRL_CFG 0x0228 //MAC_CSR13
222 #define MCU_CMD_CFG 0x022c
223 #define TX_BASE_PTR0 0x0230 //AC_BK base address
224 #define TX_MAX_CNT0 0x0234
225 #define TX_CTX_IDX0 0x0238
226 #define TX_DTX_IDX0 0x023c
227 #define TX_BASE_PTR1 0x0240 //AC_BE base address
228 #define TX_MAX_CNT1 0x0244
229 #define TX_CTX_IDX1 0x0248
230 #define TX_DTX_IDX1 0x024c
231 #define TX_BASE_PTR2 0x0250 //AC_VI base address
232 #define TX_MAX_CNT2 0x0254
233 #define TX_CTX_IDX2 0x0258
234 #define TX_DTX_IDX2 0x025c
235 #define TX_BASE_PTR3 0x0260 //AC_VO base address
236 #define TX_MAX_CNT3 0x0264
237 #define TX_CTX_IDX3 0x0268
238 #define TX_DTX_IDX3 0x026c
239 #define TX_BASE_PTR4 0x0270 //HCCA base address
240 #define TX_MAX_CNT4 0x0274
241 #define TX_CTX_IDX4 0x0278
242 #define TX_DTX_IDX4 0x027c
243 #define TX_BASE_PTR5 0x0280 //MGMT base address
244 #define TX_MAX_CNT5 0x0284
245 #define TX_CTX_IDX5 0x0288
246 #define TX_DTX_IDX5 0x028c
247 #define TX_MGMTMAX_CNT TX_MAX_CNT5
248 #define TX_MGMTCTX_IDX TX_CTX_IDX5
249 #define TX_MGMTDTX_IDX TX_DTX_IDX5
250 #define RX_BASE_PTR 0x0290 //RX base address
251 #define RX_MAX_CNT 0x0294
252 #define RX_CRX_IDX 0x0298
253 #define RX_DRX_IDX 0x029c
254 #define USB_DMA_CFG 0x02a0
255
256 typedef union _USB_DMA_CFG_STRUC {
257 struct {
258 UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns
259 UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 256 bytes
260 UINT32 phyclear:1; //phy watch dog enable. write 1
261 UINT32 rsv:2;
262 UINT32 TxClear:1; //Clear USB DMA TX path
263 UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full.
264 UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation
265 UINT32 RxBulkEn:1; //Enable USB DMA Rx
266 UINT32 TxBulkEn:1; //Enable USB DMA Tx
267 UINT32 EpoutValid:6; //OUT endpoint data valid
268 UINT32 RxBusy:1; //USB DMA RX FSM busy
269 UINT32 TxBusy:1; //USB DMA TX FSM busy
270 } field;
271 UINT32 word;
272 } USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
273
274 //
275 // 3 PBF registers
276 //
277 //
278 // Most are for debug. Driver doesn't touch PBF register.
279 #define PBF_SYS_CTRL 0x0400
280 #define PBF_CFG 0x0408
281 #define PBF_MAX_PCNT 0x040C
282 #define PBF_CTRL 0x0410
283 #define PBF_INT_STA 0x0414
284 #define PBF_INT_ENA 0x0418
285 #define TXRXQ_PCNT 0x0438
286 #define PBF_DBG 0x043c
287 #define PBF_CAP_CTRL 0x0440
288
289 // eFuse registers
290 #define EFUSE_CTRL 0x0580
291 #define EFUSE_DATA0 0x0590
292 #define EFUSE_DATA1 0x0594
293 #define EFUSE_DATA2 0x0598
294 #define EFUSE_DATA3 0x059c
295 #define EFUSE_USAGE_MAP_START 0x2d0
296 #define EFUSE_USAGE_MAP_END 0x2fc
297 #define EFUSE_TAG 0x2fe
298 #define EFUSE_USAGE_MAP_SIZE 45
299
300 typedef union _EFUSE_CTRL_STRUC {
301 struct {
302 UINT32 EFSROM_AOUT:6;
303 UINT32 EFSROM_MODE:2;
304 UINT32 EFSROM_LDO_OFF_TIME:6;
305 UINT32 EFSROM_LDO_ON_TIME:2;
306 UINT32 EFSROM_AIN:10;
307 UINT32 RESERVED:4;
308 UINT32 EFSROM_KICK:1;
309 UINT32 SEL_EFUSE:1;
310 } field;
311 UINT32 word;
312 } EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;
313
314 #define LDO_CFG0 0x05d4
315 #define GPIO_SWITCH 0x05dc
316
317 //
318 // 4 MAC registers
319 //
320 //
321 // 4.1 MAC SYSTEM configuration registers (offset:0x1000)
322 //
323 #define MAC_CSR0 0x1000
324 typedef union _ASIC_VER_ID_STRUC {
325 struct {
326 USHORT ASICRev; // reversion : 0
327 USHORT ASICVer; // version : 2860
328 } field;
329 UINT32 word;
330 } ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
331
332 #define MAC_SYS_CTRL 0x1004 //MAC_CSR1
333 #define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0
334 #define MAC_ADDR_DW1 0x100c // MAC ADDR DW1
335 //
336 // MAC_CSR2: STA MAC register 0
337 //
338 typedef union _MAC_DW0_STRUC {
339 struct {
340 UCHAR Byte0; // MAC address byte 0
341 UCHAR Byte1; // MAC address byte 1
342 UCHAR Byte2; // MAC address byte 2
343 UCHAR Byte3; // MAC address byte 3
344 } field;
345 UINT32 word;
346 } MAC_DW0_STRUC, *PMAC_DW0_STRUC;
347
348 //
349 // MAC_CSR3: STA MAC register 1
350 //
351 typedef union _MAC_DW1_STRUC {
352 struct {
353 UCHAR Byte4; // MAC address byte 4
354 UCHAR Byte5; // MAC address byte 5
355 UCHAR U2MeMask;
356 UCHAR Rsvd1;
357 } field;
358 UINT32 word;
359 } MAC_DW1_STRUC, *PMAC_DW1_STRUC;
360
361 #define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0
362 #define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1
363
364 //
365 // MAC_CSR5: BSSID register 1
366 //
367 typedef union _MAC_CSR5_STRUC {
368 struct {
369 UCHAR Byte4; // BSSID byte 4
370 UCHAR Byte5; // BSSID byte 5
371 USHORT BssIdMask:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID
372 USHORT MBssBcnNum:3;
373 USHORT Rsvd:11;
374 } field;
375 UINT32 word;
376 } MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
377
378 #define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
379 #define BBP_CSR_CFG 0x101c //
380 //
381 // BBP_CSR_CFG: BBP serial control register
382 //
383 typedef union _BBP_CSR_CFG_STRUC {
384 struct {
385 UINT32 Value:8; // Register value to program into BBP
386 UINT32 RegNum:8; // Selected BBP register
387 UINT32 fRead:1; // 0: Write BBP, 1: Read BBP
388 UINT32 Busy:1; // 1: ASIC is busy execute BBP programming.
389 UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles
390 UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel
391 UINT32 :12;
392 } field;
393 UINT32 word;
394 } BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
395
396 #define RF_CSR_CFG0 0x1020
397 //
398 // RF_CSR_CFG: RF control register
399 //
400 typedef union _RF_CSR_CFG0_STRUC {
401 struct {
402 UINT32 RegIdAndContent:24; // Register value to program into BBP
403 UINT32 bitwidth:5; // Selected BBP register
404 UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby
405 UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate
406 UINT32 Busy:1; // 0: idle 1: 8busy
407 } field;
408 UINT32 word;
409 } RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
410
411 #define RF_CSR_CFG1 0x1024
412 typedef union _RF_CSR_CFG1_STRUC {
413 struct {
414 UINT32 RegIdAndContent:24; // Register value to program into BBP
415 UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
416 UINT32 rsv:7; // 0: idle 1: 8busy
417 } field;
418 UINT32 word;
419 } RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
420
421 #define RF_CSR_CFG2 0x1028 //
422 typedef union _RF_CSR_CFG2_STRUC {
423 struct {
424 UINT32 RegIdAndContent:24; // Register value to program into BBP
425 UINT32 rsv:8; // 0: idle 1: 8busy
426 } field;
427 UINT32 word;
428 } RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
429
430 #define LED_CFG 0x102c // MAC_CSR14
431 typedef union _LED_CFG_STRUC {
432 struct {
433 UINT32 OnPeriod:8; // blinking on period unit 1ms
434 UINT32 OffPeriod:8; // blinking off period unit 1ms
435 UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms
436 UINT32 rsv:2;
437 UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on
438 UINT32 GLedMode:2; // green Led Mode
439 UINT32 YLedMode:2; // yellow Led Mode
440 UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high
441 UINT32 :1;
442 } field;
443 UINT32 word;
444 } LED_CFG_STRUC, *PLED_CFG_STRUC;
445
446 //
447 // 4.2 MAC TIMING configuration registers (offset:0x1100)
448 //
449 #define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9
450 typedef union _IFS_SLOT_CFG_STRUC {
451 struct {
452 UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX
453 UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX
454 UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
455 UINT32 EIFS:9; // unit 1us
456 UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer
457 UINT32 rsv:2;
458 } field;
459 UINT32 word;
460 } IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
461
462 #define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits
463 #define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15)
464 #define CH_TIME_CFG 0x110C // Count as channel busy
465 #define PBF_LIFE_TIMER 0x1110 //TX/RX MPDU timestamp timer (free run)Unit: 1us
466 #define BCN_TIME_CFG 0x1114 // TXRX_CSR9
467
468 #define BCN_OFFSET0 0x042C
469 #define BCN_OFFSET1 0x0430
470
471 //
472 // BCN_TIME_CFG : Synchronization control register
473 //
474 typedef union _BCN_TIME_CFG_STRUC {
475 struct {
476 UINT32 BeaconInterval:16; // in unit of 1/16 TU
477 UINT32 bTsfTicking:1; // Enable TSF auto counting
478 UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
479 UINT32 bTBTTEnable:1;
480 UINT32 bBeaconGen:1; // Enable beacon generator
481 UINT32 :3;
482 UINT32 TxTimestampCompensate:8;
483 } field;
484 UINT32 word;
485 } BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
486
487 #define TBTT_SYNC_CFG 0x1118 // txrx_csr10
488 #define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only
489 #define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only.
490 #define TBTT_TIMER 0x1124 // TImer remains till next TBTT. Read-only. TXRX_CSR14
491 #define INT_TIMER_CFG 0x1128 //
492 #define INT_TIMER_EN 0x112c // GP-timer and pre-tbtt Int enable
493 #define CH_IDLE_STA 0x1130 // channel idle time
494 #define CH_BUSY_STA 0x1134 // channle busy time
495 //
496 // 4.2 MAC POWER configuration registers (offset:0x1200)
497 //
498 #define MAC_STATUS_CFG 0x1200 // old MAC_CSR12
499 #define PWR_PIN_CFG 0x1204 // old MAC_CSR12
500 #define AUTO_WAKEUP_CFG 0x1208 // old MAC_CSR10
501 //
502 // AUTO_WAKEUP_CFG: Manual power control / status register
503 //
504 typedef union _AUTO_WAKEUP_STRUC {
505 struct {
506 UINT32 AutoLeadTime:8;
507 UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set
508 UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake
509 UINT32 :16;
510 } field;
511 UINT32 word;
512 } AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
513
514 //
515 // 4.3 MAC TX configuration registers (offset:0x1300)
516 //
517
518 #define EDCA_AC0_CFG 0x1300 //AC_TXOP_CSR0 0x3474
519 #define EDCA_AC1_CFG 0x1304
520 #define EDCA_AC2_CFG 0x1308
521 #define EDCA_AC3_CFG 0x130c
522 typedef union _EDCA_AC_CFG_STRUC {
523 struct {
524 UINT32 AcTxop:8; // in unit of 32us
525 UINT32 Aifsn:4; // # of slot time
526 UINT32 Cwmin:4; //
527 UINT32 Cwmax:4; //unit power of 2
528 UINT32 :12; //
529 } field;
530 UINT32 word;
531 } EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
532
533 #define EDCA_TID_AC_MAP 0x1310
534 #define TX_PWR_CFG_0 0x1314
535 #define TX_PWR_CFG_1 0x1318
536 #define TX_PWR_CFG_2 0x131C
537 #define TX_PWR_CFG_3 0x1320
538 #define TX_PWR_CFG_4 0x1324
539 #define TX_PIN_CFG 0x1328
540 #define TX_BAND_CFG 0x132c // 0x1 use upper 20MHz. 0 juse lower 20MHz
541 #define TX_SW_CFG0 0x1330
542 #define TX_SW_CFG1 0x1334
543 #define TX_SW_CFG2 0x1338
544 #define TXOP_THRES_CFG 0x133c
545 #define TXOP_CTRL_CFG 0x1340
546 #define TX_RTS_CFG 0x1344
547
548 typedef union _TX_RTS_CFG_STRUC {
549 struct {
550 UINT32 AutoRtsRetryLimit:8;
551 UINT32 RtsThres:16; // unit:byte
552 UINT32 RtsFbkEn:1; // enable rts rate fallback
553 UINT32 rsv:7; // 1: HT non-STBC control frame enable
554 } field;
555 UINT32 word;
556 } TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
557
558 #define TX_TIMEOUT_CFG 0x1348
559 typedef union _TX_TIMEOUT_CFG_STRUC {
560 struct {
561 UINT32 rsv:4;
562 UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us
563 UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure
564 UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
565 UINT32 rsv2:8; // 1: HT non-STBC control frame enable
566 } field;
567 UINT32 word;
568 } TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
569
570 #define TX_RTY_CFG 0x134c
571 typedef union PACKED _TX_RTY_CFG_STRUC {
572 struct {
573 UINT32 ShortRtyLimit:8; // short retry limit
574 UINT32 LongRtyLimit:8; //long retry limit
575 UINT32 LongRtyThre:12; // Long retry threshoold
576 UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
577 UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
578 UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable
579 UINT32 rsv:1; // 1: HT non-STBC control frame enable
580 } field;
581 UINT32 word;
582 } TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
583
584 #define TX_LINK_CFG 0x1350
585 typedef union PACKED _TX_LINK_CFG_STRUC {
586 struct PACKED {
587 UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us
588 UINT32 MFBEnable:1; // TX apply remote MFB 1:enable
589 UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7)
590 UINT32 TxMRQEn:1; // MCS request TX enable
591 UINT32 TxRDGEn:1; // RDG TX enable
592 UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable
593 UINT32 rsv:3; //
594 UINT32 RemotMFB:8; // remote MCS feedback
595 UINT32 RemotMFS:8; //remote MCS feedback sequence number
596 } field;
597 UINT32 word;
598 } TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
599
600 #define HT_FBK_CFG0 0x1354
601 typedef union PACKED _HT_FBK_CFG0_STRUC {
602 struct {
603 UINT32 HTMCS0FBK:4;
604 UINT32 HTMCS1FBK:4;
605 UINT32 HTMCS2FBK:4;
606 UINT32 HTMCS3FBK:4;
607 UINT32 HTMCS4FBK:4;
608 UINT32 HTMCS5FBK:4;
609 UINT32 HTMCS6FBK:4;
610 UINT32 HTMCS7FBK:4;
611 } field;
612 UINT32 word;
613 } HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
614
615 #define HT_FBK_CFG1 0x1358
616 typedef union _HT_FBK_CFG1_STRUC {
617 struct {
618 UINT32 HTMCS8FBK:4;
619 UINT32 HTMCS9FBK:4;
620 UINT32 HTMCS10FBK:4;
621 UINT32 HTMCS11FBK:4;
622 UINT32 HTMCS12FBK:4;
623 UINT32 HTMCS13FBK:4;
624 UINT32 HTMCS14FBK:4;
625 UINT32 HTMCS15FBK:4;
626 } field;
627 UINT32 word;
628 } HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
629
630 #define LG_FBK_CFG0 0x135c
631 typedef union _LG_FBK_CFG0_STRUC {
632 struct {
633 UINT32 OFDMMCS0FBK:4; //initial value is 0
634 UINT32 OFDMMCS1FBK:4; //initial value is 0
635 UINT32 OFDMMCS2FBK:4; //initial value is 1
636 UINT32 OFDMMCS3FBK:4; //initial value is 2
637 UINT32 OFDMMCS4FBK:4; //initial value is 3
638 UINT32 OFDMMCS5FBK:4; //initial value is 4
639 UINT32 OFDMMCS6FBK:4; //initial value is 5
640 UINT32 OFDMMCS7FBK:4; //initial value is 6
641 } field;
642 UINT32 word;
643 } LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
644
645 #define LG_FBK_CFG1 0x1360
646 typedef union _LG_FBK_CFG1_STRUC {
647 struct {
648 UINT32 CCKMCS0FBK:4; //initial value is 0
649 UINT32 CCKMCS1FBK:4; //initial value is 0
650 UINT32 CCKMCS2FBK:4; //initial value is 1
651 UINT32 CCKMCS3FBK:4; //initial value is 2
652 UINT32 rsv:16;
653 } field;
654 UINT32 word;
655 } LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
656
657 //=======================================================
658 //================ Protection Paramater================================
659 //=======================================================
660 #define CCK_PROT_CFG 0x1364 //CCK Protection
661 #define ASIC_SHORTNAV 1
662 #define ASIC_LONGNAV 2
663 #define ASIC_RTS 1
664 #define ASIC_CTS 2
665 typedef union _PROT_CFG_STRUC {
666 struct {
667 UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
668 UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
669 UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv
670 UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow.
671 UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow.
672 UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow.
673 UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow.
674 UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow.
675 UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow.
676 UINT32 RTSThEn:1; //RTS threshold enable on CCK TX
677 UINT32 rsv:5;
678 } field;
679 UINT32 word;
680 } PROT_CFG_STRUC, *PPROT_CFG_STRUC;
681
682 #define OFDM_PROT_CFG 0x1368 //OFDM Protection
683 #define MM20_PROT_CFG 0x136C //MM20 Protection
684 #define MM40_PROT_CFG 0x1370 //MM40 Protection
685 #define GF20_PROT_CFG 0x1374 //GF20 Protection
686 #define GF40_PROT_CFG 0x1378 //GR40 Protection
687 #define EXP_CTS_TIME 0x137C //
688 #define EXP_ACK_TIME 0x1380 //
689
690 //
691 // 4.4 MAC RX configuration registers (offset:0x1400)
692 //
693 #define RX_FILTR_CFG 0x1400 //TXRX_CSR0
694 #define AUTO_RSP_CFG 0x1404 //TXRX_CSR4
695 //
696 // TXRX_CSR4: Auto-Responder/
697 //
698 typedef union _AUTO_RSP_CFG_STRUC {
699 struct {
700 UINT32 AutoResponderEnable:1;
701 UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble
702 UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode
703 UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode
704 UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble
705 UINT32 rsv:1; // Power bit value in conrtrol frame
706 UINT32 DualCTSEn:1; // Power bit value in conrtrol frame
707 UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame
708 UINT32 :24;
709 } field;
710 UINT32 word;
711 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
712
713 #define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054
714 #define HT_BASIC_RATE 0x140c
715 #define HT_CTRL_CFG 0x1410
716 #define SIFS_COST_CFG 0x1414
717 #define RX_PARSER_CFG 0x1418 //Set NAV for all received frames
718
719 //
720 // 4.5 MAC Security configuration (offset:0x1500)
721 //
722 #define TX_SEC_CNT0 0x1500 //
723 #define RX_SEC_CNT0 0x1504 //
724 #define CCMP_FC_MUTE 0x1508 //
725 //
726 // 4.6 HCCA/PSMP (offset:0x1600)
727 //
728 #define TXOP_HLDR_ADDR0 0x1600
729 #define TXOP_HLDR_ADDR1 0x1604
730 #define TXOP_HLDR_ET 0x1608
731 #define QOS_CFPOLL_RA_DW0 0x160c
732 #define QOS_CFPOLL_A1_DW1 0x1610
733 #define QOS_CFPOLL_QC 0x1614
734 //
735 // 4.7 MAC Statistis registers (offset:0x1700)
736 //
737 #define RX_STA_CNT0 0x1700 //
738 #define RX_STA_CNT1 0x1704 //
739 #define RX_STA_CNT2 0x1708 //
740
741 //
742 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
743 //
744 typedef union _RX_STA_CNT0_STRUC {
745 struct {
746 USHORT CrcErr;
747 USHORT PhyErr;
748 } field;
749 UINT32 word;
750 } RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
751
752 //
753 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
754 //
755 typedef union _RX_STA_CNT1_STRUC {
756 struct {
757 USHORT FalseCca;
758 USHORT PlcpErr;
759 } field;
760 UINT32 word;
761 } RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
762
763 //
764 // RX_STA_CNT2_STRUC:
765 //
766 typedef union _RX_STA_CNT2_STRUC {
767 struct {
768 USHORT RxDupliCount;
769 USHORT RxFifoOverflowCount;
770 } field;
771 UINT32 word;
772 } RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
773
774 #define TX_STA_CNT0 0x170C //
775 //
776 // STA_CSR3: TX Beacon count
777 //
778 typedef union _TX_STA_CNT0_STRUC {
779 struct {
780 USHORT TxFailCount;
781 USHORT TxBeaconCount;
782 } field;
783 UINT32 word;
784 } TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
785
786 #define TX_STA_CNT1 0x1710 //
787 //
788 // TX_STA_CNT1: TX tx count
789 //
790 typedef union _TX_STA_CNT1_STRUC {
791 struct {
792 USHORT TxSuccess;
793 USHORT TxRetransmit;
794 } field;
795 UINT32 word;
796 } TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
797
798 #define TX_STA_CNT2 0x1714 //
799 //
800 // TX_STA_CNT2: TX tx count
801 //
802 typedef union _TX_STA_CNT2_STRUC {
803 struct {
804 USHORT TxZeroLenCount;
805 USHORT TxUnderFlowCount;
806 } field;
807 UINT32 word;
808 } TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
809
810 #define TX_STA_FIFO 0x1718 //
811 //
812 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
813 //
814 typedef union PACKED _TX_STA_FIFO_STRUC {
815 struct {
816 UINT32 bValid:1; // 1:This register contains a valid TX result
817 UINT32 PidType:4;
818 UINT32 TxSuccess:1; // Tx No retry success
819 UINT32 TxAggre:1; // Tx Retry Success
820 UINT32 TxAckRequired:1; // Tx fail
821 UINT32 wcid:8; //wireless client index
822 // UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
823 UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
824 UINT32 TxBF:1;
825 UINT32 Reserve:2;
826 } field;
827 UINT32 word;
828 } TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
829
830 // Debug counter
831 #define TX_AGG_CNT 0x171c
832 typedef union _TX_AGG_CNT_STRUC {
833 struct {
834 USHORT NonAggTxCount;
835 USHORT AggTxCount;
836 } field;
837 UINT32 word;
838 } TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
839
840 // Debug counter
841 #define TX_AGG_CNT0 0x1720
842 typedef union _TX_AGG_CNT0_STRUC {
843 struct {
844 USHORT AggSize1Count;
845 USHORT AggSize2Count;
846 } field;
847 UINT32 word;
848 } TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
849
850 // Debug counter
851 #define TX_AGG_CNT1 0x1724
852 typedef union _TX_AGG_CNT1_STRUC {
853 struct {
854 USHORT AggSize3Count;
855 USHORT AggSize4Count;
856 } field;
857 UINT32 word;
858 } TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
859
860 #define TX_AGG_CNT2 0x1728
861 typedef union _TX_AGG_CNT2_STRUC {
862 struct {
863 USHORT AggSize5Count;
864 USHORT AggSize6Count;
865 } field;
866 UINT32 word;
867 } TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
868
869 // Debug counter
870 #define TX_AGG_CNT3 0x172c
871 typedef union _TX_AGG_CNT3_STRUC {
872 struct {
873 USHORT AggSize7Count;
874 USHORT AggSize8Count;
875 } field;
876 UINT32 word;
877 } TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
878
879 // Debug counter
880 #define TX_AGG_CNT4 0x1730
881 typedef union _TX_AGG_CNT4_STRUC {
882 struct {
883 USHORT AggSize9Count;
884 USHORT AggSize10Count;
885 } field;
886 UINT32 word;
887 } TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
888
889 #define TX_AGG_CNT5 0x1734
890 typedef union _TX_AGG_CNT5_STRUC {
891 struct {
892 USHORT AggSize11Count;
893 USHORT AggSize12Count;
894 } field;
895 UINT32 word;
896 } TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
897
898 #define TX_AGG_CNT6 0x1738
899 typedef union _TX_AGG_CNT6_STRUC {
900 struct {
901 USHORT AggSize13Count;
902 USHORT AggSize14Count;
903 } field;
904 UINT32 word;
905 } TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
906
907 #define TX_AGG_CNT7 0x173c
908 typedef union _TX_AGG_CNT7_STRUC {
909 struct {
910 USHORT AggSize15Count;
911 USHORT AggSize16Count;
912 } field;
913 UINT32 word;
914 } TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
915
916 #define MPDU_DENSITY_CNT 0x1740
917 typedef union _MPDU_DEN_CNT_STRUC {
918 struct {
919 USHORT TXZeroDelCount; //TX zero length delimiter count
920 USHORT RXZeroDelCount; //RX zero length delimiter count
921 } field;
922 UINT32 word;
923 } MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
924
925 //
926 // TXRX control registers - base address 0x3000
927 //
928 // rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
929 #define TXRX_CSR1 0x77d0
930
931 //
932 // Security key table memory, base address = 0x1000
933 //
934 #define MAC_WCID_BASE 0x1800 //8-bytes(use only 6-bytes) * 256 entry =
935 #define HW_WCID_ENTRY_SIZE 8
936 #define PAIRWISE_KEY_TABLE_BASE 0x4000 // 32-byte * 256-entry = -byte
937 #define HW_KEY_ENTRY_SIZE 0x20
938 #define PAIRWISE_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
939 #define MAC_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
940 #define HW_IVEIV_ENTRY_SIZE 8
941 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 // 4-byte * 256-entry = -byte
942 #define HW_WCID_ATTRI_SIZE 4
943 #define WCID_RESERVED 0x6bfc
944 #define SHARED_KEY_TABLE_BASE 0x6c00 // 32-byte * 16-entry = 512-byte
945 #define SHARED_KEY_MODE_BASE 0x7000 // 32-byte * 16-entry = 512-byte
946 #define HW_SHARED_KEY_MODE_SIZE 4
947 #define SHAREDKEYTABLE 0
948 #define PAIRWISEKEYTABLE 1
949
950 typedef union _SHAREDKEY_MODE_STRUC {
951 struct {
952 UINT32 Bss0Key0CipherAlg:3;
953 UINT32 :1;
954 UINT32 Bss0Key1CipherAlg:3;
955 UINT32 :1;
956 UINT32 Bss0Key2CipherAlg:3;
957 UINT32 :1;
958 UINT32 Bss0Key3CipherAlg:3;
959 UINT32 :1;
960 UINT32 Bss1Key0CipherAlg:3;
961 UINT32 :1;
962 UINT32 Bss1Key1CipherAlg:3;
963 UINT32 :1;
964 UINT32 Bss1Key2CipherAlg:3;
965 UINT32 :1;
966 UINT32 Bss1Key3CipherAlg:3;
967 UINT32 :1;
968 } field;
969 UINT32 word;
970 } SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
971
972 // 64-entry for pairwise key table
973 typedef struct _HW_WCID_ENTRY { // 8-byte per entry
974 UCHAR Address[6];
975 UCHAR Rsv[2];
976 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
977
978
979
980 //
981 // Other on-chip shared memory space, base = 0x2000
982 //
983
984 // CIS space - base address = 0x2000
985 #define HW_CIS_BASE 0x2000
986
987 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
988 #define HW_CS_CTS_BASE 0x7700
989 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
990 #define HW_DFS_CTS_BASE 0x7780
991 #define HW_CTS_FRAME_SIZE 0x80
992
993 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
994 // to save debugging settings
995 #define HW_DEBUG_SETTING_BASE 0x77f0 // 0x77f0~0x77ff total 16 bytes
996 #define HW_DEBUG_SETTING_BASE2 0x7770 // 0x77f0~0x77ff total 16 bytes
997
998 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
999 // Three section discontinue memory segments will be used.
1000 // 1. The original region for BCN 0~3
1001 // 2. Extract memory from FCE table for BCN 4~5
1002 // 3. Extract memory from Pair-wise key table for BCN 6~7
1003 // It occupied those memory of wcid 238~253 for BCN 6
1004 // and wcid 222~237 for BCN 7
1005 #define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
1006 #define HW_BEACON_BASE0 0x7800
1007 #define HW_BEACON_BASE1 0x7A00
1008 #define HW_BEACON_BASE2 0x7C00
1009 #define HW_BEACON_BASE3 0x7E00
1010 #define HW_BEACON_BASE4 0x7200
1011 #define HW_BEACON_BASE5 0x7400
1012 #define HW_BEACON_BASE6 0x5DC0
1013 #define HW_BEACON_BASE7 0x5BC0
1014
1015 #define HW_BEACON_MAX_COUNT 8
1016 #define HW_BEACON_OFFSET 0x0200
1017 #define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
1018
1019 // HOST-MCU shared memory - base address = 0x2100
1020 #define HOST_CMD_CSR 0x404
1021 #define H2M_MAILBOX_CSR 0x7010
1022 #define H2M_MAILBOX_CID 0x7014
1023 #define H2M_MAILBOX_STATUS 0x701c
1024 #define H2M_INT_SRC 0x7024
1025 #define H2M_BBP_AGENT 0x7028
1026 #define M2H_CMD_DONE_CSR 0x000c
1027 #define MCU_TXOP_ARRAY_BASE 0x000c // TODO: to be provided by Albert
1028 #define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
1029 #define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
1030 #define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
1031 #define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
1032
1033 //
1034 // Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1035 //
1036 //
1037 // DMA RING DESCRIPTOR
1038 //
1039 #define E2PROM_CSR 0x0004
1040 #define IO_CNTL_CSR 0x77d0
1041
1042 #ifdef RT2860
1043 // 8051 firmware image for RT2860 - base address = 0x4000
1044 #define FIRMWARE_IMAGE_BASE 0x2000
1045 #define MAX_FIRMWARE_IMAGE_SIZE 0x2000 // 8kbyte
1046 #endif
1047 #ifdef RT2870
1048 // 8051 firmware image for usb - use last-half base address = 0x3000
1049 #define FIRMWARE_IMAGE_BASE 0x3000
1050 #define MAX_FIRMWARE_IMAGE_SIZE 0x1000 // 4kbyte
1051 #endif // RT2870 //
1052
1053 // ================================================================
1054 // Tx / Rx / Mgmt ring descriptor definition
1055 // ================================================================
1056
1057 // the following PID values are used to mark outgoing frame type in TXD->PID so that
1058 // proper TX statistics can be collected based on these categories
1059 // b3-2 of PID field -
1060 #define PID_MGMT 0x05
1061 #define PID_BEACON 0x0c
1062 #define PID_DATA_NORMALUCAST 0x02
1063 #define PID_DATA_AMPDU 0x04
1064 #define PID_DATA_NO_ACK 0x08
1065 #define PID_DATA_NOT_NORM_ACK 0x03
1066 // value domain of pTxD->HostQId (4-bit: 0~15)
1067 #define QID_AC_BK 1 // meet ACI definition in 802.11e
1068 #define QID_AC_BE 0 // meet ACI definition in 802.11e
1069 #define QID_AC_VI 2
1070 #define QID_AC_VO 3
1071 #define QID_HCCA 4
1072 #define NUM_OF_TX_RING 5
1073 #define QID_MGMT 13
1074 #define QID_RX 14
1075 #define QID_OTHER 15
1076
1077
1078 // ------------------------------------------------------
1079 // BBP & RF definition
1080 // ------------------------------------------------------
1081 #define BUSY 1
1082 #define IDLE 0
1083
1084 #define RF_R00 0
1085 #define RF_R01 1
1086 #define RF_R02 2
1087 #define RF_R03 3
1088 #define RF_R04 4
1089 #define RF_R05 5
1090 #define RF_R06 6
1091 #define RF_R07 7
1092 #define RF_R08 8
1093 #define RF_R09 9
1094 #define RF_R10 10
1095 #define RF_R11 11
1096 #define RF_R12 12
1097 #define RF_R13 13
1098 #define RF_R14 14
1099 #define RF_R15 15
1100 #define RF_R16 16
1101 #define RF_R17 17
1102 #define RF_R18 18
1103 #define RF_R19 19
1104 #define RF_R20 20
1105 #define RF_R21 21
1106 #define RF_R22 22
1107 #define RF_R23 23
1108 #define RF_R24 24
1109 #define RF_R25 25
1110 #define RF_R26 26
1111 #define RF_R27 27
1112 #define RF_R28 28
1113 #define RF_R29 29
1114 #define RF_R30 30
1115 #define RF_R31 31
1116
1117 #define BBP_R0 0 // version
1118 #define BBP_R1 1 // TSSI
1119 #define BBP_R2 2 // TX configure
1120 #define BBP_R3 3
1121 #define BBP_R4 4
1122 #define BBP_R5 5
1123 #define BBP_R6 6
1124 #define BBP_R14 14 // RX configure
1125 #define BBP_R16 16
1126 #define BBP_R17 17 // RX sensibility
1127 #define BBP_R18 18
1128 #define BBP_R21 21
1129 #define BBP_R22 22
1130 #define BBP_R24 24
1131 #define BBP_R25 25
1132 #define BBP_R31 31
1133 #define BBP_R49 49 //TSSI
1134 #define BBP_R50 50
1135 #define BBP_R51 51
1136 #define BBP_R52 52
1137 #define BBP_R55 55
1138 #define BBP_R62 62 // Rx SQ0 Threshold HIGH
1139 #define BBP_R63 63
1140 #define BBP_R64 64
1141 #define BBP_R65 65
1142 #define BBP_R66 66
1143 #define BBP_R67 67
1144 #define BBP_R68 68
1145 #define BBP_R69 69
1146 #define BBP_R70 70 // Rx AGC SQ CCK Xcorr threshold
1147 #define BBP_R73 73
1148 #define BBP_R75 75
1149 #define BBP_R77 77
1150 #define BBP_R79 79
1151 #define BBP_R80 80
1152 #define BBP_R81 81
1153 #define BBP_R82 82
1154 #define BBP_R83 83
1155 #define BBP_R84 84
1156 #define BBP_R86 86
1157 #define BBP_R91 91
1158 #define BBP_R92 92
1159 #define BBP_R94 94 // Tx Gain Control
1160 #define BBP_R103 103
1161 #define BBP_R105 105
1162 #define BBP_R113 113
1163 #define BBP_R114 114
1164 #define BBP_R115 115
1165 #define BBP_R116 116
1166 #define BBP_R117 117
1167 #define BBP_R118 118
1168 #define BBP_R119 119
1169 #define BBP_R120 120
1170 #define BBP_R121 121
1171 #define BBP_R122 122
1172 #define BBP_R123 123
1173 #define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
1174
1175
1176 #define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
1177
1178 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
1179 #define RSSI_FOR_LOW_SENSIBILITY -58
1180 #define RSSI_FOR_MID_LOW_SENSIBILITY -80
1181 #define RSSI_FOR_MID_SENSIBILITY -90
1182
1183 //-------------------------------------------------------------------------
1184 // EEPROM definition
1185 //-------------------------------------------------------------------------
1186 #define EEDO 0x08
1187 #define EEDI 0x04
1188 #define EECS 0x02
1189 #define EESK 0x01
1190 #define EERL 0x80
1191
1192 #define EEPROM_WRITE_OPCODE 0x05
1193 #define EEPROM_READ_OPCODE 0x06
1194 #define EEPROM_EWDS_OPCODE 0x10
1195 #define EEPROM_EWEN_OPCODE 0x13
1196
1197 #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
1198 #define NUM_EEPROM_TX_G_PARMS 7
1199 #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
1200 #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
1201 #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
1202 #define EEPROM_G_TX_PWR_OFFSET 0x52
1203 #define EEPROM_G_TX2_PWR_OFFSET 0x60
1204 #define EEPROM_LED1_OFFSET 0x3c
1205 #define EEPROM_LED2_OFFSET 0x3e
1206 #define EEPROM_LED3_OFFSET 0x40
1207 #define EEPROM_LNA_OFFSET 0x44
1208 #define EEPROM_RSSI_BG_OFFSET 0x46
1209 #define EEPROM_RSSI_A_OFFSET 0x4a
1210 #define EEPROM_DEFINE_MAX_TXPWR 0x4e
1211 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
1212 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
1213 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
1214 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
1215 #define EEPROM_A_TX_PWR_OFFSET 0x78
1216 #define EEPROM_A_TX2_PWR_OFFSET 0xa6
1217 #define EEPROM_VERSION_OFFSET 0x02
1218 #define EEPROM_FREQ_OFFSET 0x3a
1219 #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
1220 #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
1221 #define VALID_EEPROM_VERSION 1
1222
1223 // PairKeyMode definition
1224 #define PKMODE_NONE 0
1225 #define PKMODE_WEP64 1
1226 #define PKMODE_WEP128 2
1227 #define PKMODE_TKIP 3
1228 #define PKMODE_AES 4
1229 #define PKMODE_CKIP64 5
1230 #define PKMODE_CKIP128 6
1231 #define PKMODE_TKIP_NO_MIC 7 // MIC appended by driver: not a valid value in hardware key table
1232
1233 // =================================================================================
1234 // WCID format
1235 // =================================================================================
1236 //7.1 WCID ENTRY format : 8bytes
1237 typedef struct _WCID_ENTRY_STRUC {
1238 UCHAR RXBABitmap7; // bit0 for TID8, bit7 for TID 15
1239 UCHAR RXBABitmap0; // bit0 for TID0, bit7 for TID 7
1240 UCHAR MAC[6]; // 0 for shared key table. 1 for pairwise key table
1241 } WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1242
1243 //8.1.1 SECURITY KEY format : 8DW
1244 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1245 typedef struct _HW_KEY_ENTRY { // 32-byte per entry
1246 UCHAR Key[16];
1247 UCHAR TxMic[8];
1248 UCHAR RxMic[8];
1249 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1250
1251 //8.1.2 IV/EIV format : 2DW
1252
1253 //8.1.3 RX attribute entry format : 1DW
1254 typedef struct _MAC_ATTRIBUTE_STRUC {
1255 UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table
1256 UINT32 PairKeyMode:3;
1257 UINT32 BSSIDIdx:3; //multipleBSS index for the WCID
1258 UINT32 RXWIUDF:3;
1259 UINT32 rsv:22;
1260 } MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1261
1262 // =================================================================================
1263 // TX / RX ring descriptor format
1264 // =================================================================================
1265
1266 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
1267 // MAC block use this TXINFO to control the transmission behavior of this frame.
1268 #define FIFO_MGMT 0
1269 #define FIFO_HCCA 1
1270 #define FIFO_EDCA 2
1271
1272 //
1273 // TX descriptor format, Tx ring, Mgmt Ring
1274 //
1275 typedef struct PACKED _TXD_STRUC {
1276 // Word 0
1277 UINT32 SDPtr0;
1278 // Word 1
1279 UINT32 SDLen1:14;
1280 UINT32 LastSec1:1;
1281 UINT32 Burst:1;
1282 UINT32 SDLen0:14;
1283 UINT32 LastSec0:1;
1284 UINT32 DMADONE:1;
1285 //Word2
1286 UINT32 SDPtr1;
1287 //Word3
1288 UINT32 rsv2:24;
1289 UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition
1290 UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
1291 UINT32 rsv:2;
1292 UINT32 TCO:1; //
1293 UINT32 UCO:1; //
1294 UINT32 ICO:1; //
1295 } TXD_STRUC, *PTXD_STRUC;
1296
1297 //
1298 // TXD Wireless Information format for Tx ring and Mgmt Ring
1299 //
1300 //txop : for txop mode
1301 // 0:txop for the MPDU frame will be handles by ASIC by register
1302 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
1303 typedef struct PACKED _TXWI_STRUC {
1304 // Word 0
1305 UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment.
1306 UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode
1307 UINT32 CFACK:1;
1308 UINT32 TS:1;
1309
1310 UINT32 AMPDU:1;
1311 UINT32 MpduDensity:3;
1312 UINT32 txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
1313 UINT32 rsv:6;
1314
1315 UINT32 MCS:7;
1316 UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
1317 UINT32 ShortGI:1;
1318 UINT32 STBC:2; // 1: STBC support MCS =0-7, 2,3 : RESERVE
1319 UINT32 Ifs:1; //
1320 UINT32 rsv2:1;
1321 UINT32 TxBF:1; // 3*3
1322 UINT32 PHYMODE:2;
1323 // Word 1
1324 UINT32 ACK:1;
1325 UINT32 NSEQ:1;
1326 UINT32 BAWinSize:6;
1327 UINT32 WirelessCliID:8;
1328 UINT32 MPDUtotalByteCount:12;
1329 UINT32 PacketId:4;
1330 //Word2
1331 UINT32 IV;
1332 //Word3
1333 UINT32 EIV;
1334 } TXWI_STRUC, *PTXWI_STRUC;
1335
1336 //
1337 // Rx descriptor format, Rx Ring
1338 //
1339 #ifdef RT2860
1340 typedef struct PACKED _RXD_STRUC {
1341 // Word 0
1342 UINT32 SDP0;
1343 // Word 1
1344 UINT32 SDL1:14;
1345 UINT32 Rsv:2;
1346 UINT32 SDL0:14;
1347 UINT32 LS0:1;
1348 UINT32 DDONE:1;
1349 // Word 2
1350 UINT32 SDP1;
1351 // Word 3
1352 UINT32 BA:1;
1353 UINT32 DATA:1;
1354 UINT32 NULLDATA:1;
1355 UINT32 FRAG:1;
1356 UINT32 U2M:1; // 1: this RX frame is unicast to me
1357 UINT32 Mcast:1; // 1: this is a multicast frame
1358 UINT32 Bcast:1; // 1: this is a broadcast frame
1359 UINT32 MyBss:1; // 1: this frame belongs to the same BSSID
1360 UINT32 Crc:1; // 1: CRC error
1361 UINT32 CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
1362 UINT32 AMSDU:1; // rx with 802.3 header, not 802.11 header.
1363 UINT32 HTC:1;
1364 UINT32 RSSI:1;
1365 UINT32 L2PAD:1;
1366 UINT32 AMPDU:1;
1367 UINT32 Decrypted:1; // this frame is being decrypted.
1368 UINT32 PlcpSignal:1; // To be moved
1369 UINT32 PlcpRssil:1;// To be moved
1370 UINT32 Rsv1:13;
1371 } RXD_STRUC, *PRXD_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
1372 #endif /* RT2860 */
1373
1374 //
1375 // RXWI wireless information format, in PBF. invisible in driver.
1376 //
1377 typedef struct PACKED _RXWI_STRUC {
1378 // Word 0
1379 UINT32 WirelessCliID:8;
1380 UINT32 KeyIndex:2;
1381 UINT32 BSSID:3;
1382 UINT32 UDF:3;
1383 UINT32 MPDUtotalByteCount:12;
1384 UINT32 TID:4;
1385 // Word 1
1386 UINT32 FRAG:4;
1387 UINT32 SEQUENCE:12;
1388 UINT32 MCS:7;
1389 UINT32 BW:1;
1390 UINT32 ShortGI:1;
1391 UINT32 STBC:2;
1392 UINT32 rsv:3;
1393 UINT32 PHYMODE:2; // 1: this RX frame is unicast to me
1394 //Word2
1395 UINT32 RSSI0:8;
1396 UINT32 RSSI1:8;
1397 UINT32 RSSI2:8;
1398 UINT32 rsv1:8;
1399 //Word3
1400 UINT32 SNR0:8;
1401 UINT32 SNR1:8;
1402 UINT32 rsv2:16;
1403 } RXWI_STRUC, *PRXWI_STRUC;
1404
1405 // =================================================================================
1406 // HOST-MCU communication data structure
1407 // =================================================================================
1408
1409 //
1410 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
1411 //
1412 typedef union _H2M_MAILBOX_STRUC {
1413 struct {
1414 UINT32 LowByte:8;
1415 UINT32 HighByte:8;
1416 UINT32 CmdToken:8;
1417 UINT32 Owner:8;
1418 } field;
1419 UINT32 word;
1420 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1421
1422 //
1423 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
1424 //
1425 typedef union _M2H_CMD_DONE_STRUC {
1426 struct {
1427 UINT32 CmdToken0;
1428 UINT32 CmdToken1;
1429 UINT32 CmdToken2;
1430 UINT32 CmdToken3;
1431 } field;
1432 UINT32 word;
1433 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1434
1435 //
1436 // MCU_LEDCS: MCU LED Control Setting.
1437 //
1438 typedef union _MCU_LEDCS_STRUC {
1439 struct {
1440 UCHAR LedMode:7;
1441 UCHAR Polarity:1;
1442 } field;
1443 UCHAR word;
1444 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
1445
1446 // =================================================================================
1447 // Register format
1448 // =================================================================================
1449
1450
1451
1452 //NAV_TIME_CFG :NAV
1453 typedef union _NAV_TIME_CFG_STRUC {
1454 struct {
1455 UCHAR Sifs; // in unit of 1-us
1456 UCHAR SlotTime; // in unit of 1-us
1457 USHORT Eifs:9; // in unit of 1-us
1458 USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable
1459 USHORT rsv:6;
1460 } field;
1461 UINT32 word;
1462 } NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1463
1464 //
1465 // RX_FILTR_CFG: /RX configuration register
1466 //
1467 typedef union _RX_FILTR_CFG_STRUC {
1468 struct {
1469 UINT32 DropCRCErr:1; // Drop CRC error
1470 UINT32 DropPhyErr:1; // Drop physical error
1471 UINT32 DropNotToMe:1; // Drop not to me unicast frame
1472 UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true
1473
1474 UINT32 DropVerErr:1; // Drop version error frame
1475 UINT32 DropMcast:1; // Drop multicast frames
1476 UINT32 DropBcast:1; // Drop broadcast frames
1477 UINT32 DropDuplicate:1; // Drop duplicate frame
1478
1479 UINT32 DropCFEndAck:1; // Drop Ps-Poll
1480 UINT32 DropCFEnd:1; // Drop Ps-Poll
1481 UINT32 DropAck:1; // Drop Ps-Poll
1482 UINT32 DropCts:1; // Drop Ps-Poll
1483
1484 UINT32 DropRts:1; // Drop Ps-Poll
1485 UINT32 DropPsPoll:1; // Drop Ps-Poll
1486 UINT32 DropBA:1; //
1487 UINT32 DropBAR:1; //
1488
1489 UINT32 DropRsvCntlType:1;
1490 UINT32 :15;
1491 } field;
1492 UINT32 word;
1493 } RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1494
1495 //
1496 // PHY_CSR4: RF serial control register
1497 //
1498 typedef union _PHY_CSR4_STRUC {
1499 struct {
1500 UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1501 UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1502 UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program
1503 UINT32 PLL_LD:1; // RF PLL_LD status
1504 UINT32 Busy:1; // 1: ASIC is busy execute RF programming.
1505 } field;
1506 UINT32 word;
1507 } PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
1508
1509 //
1510 // SEC_CSR5: shared key table security mode register
1511 //
1512 typedef union _SEC_CSR5_STRUC {
1513 struct {
1514 UINT32 Bss2Key0CipherAlg:3;
1515 UINT32 :1;
1516 UINT32 Bss2Key1CipherAlg:3;
1517 UINT32 :1;
1518 UINT32 Bss2Key2CipherAlg:3;
1519 UINT32 :1;
1520 UINT32 Bss2Key3CipherAlg:3;
1521 UINT32 :1;
1522 UINT32 Bss3Key0CipherAlg:3;
1523 UINT32 :1;
1524 UINT32 Bss3Key1CipherAlg:3;
1525 UINT32 :1;
1526 UINT32 Bss3Key2CipherAlg:3;
1527 UINT32 :1;
1528 UINT32 Bss3Key3CipherAlg:3;
1529 UINT32 :1;
1530 } field;
1531 UINT32 word;
1532 } SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
1533
1534 //
1535 // HOST_CMD_CSR: For HOST to interrupt embedded processor
1536 //
1537 typedef union _HOST_CMD_CSR_STRUC {
1538 struct {
1539 UINT32 HostCommand:8;
1540 UINT32 Rsv:24;
1541 } field;
1542 UINT32 word;
1543 } HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
1544
1545 //
1546 // AIFSN_CSR: AIFSN for each EDCA AC
1547 //
1548
1549
1550
1551 //
1552 // E2PROM_CSR: EEPROM control register
1553 //
1554 typedef union _E2PROM_CSR_STRUC {
1555 struct {
1556 UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
1557 UINT32 EepromSK:1;
1558 UINT32 EepromCS:1;
1559 UINT32 EepromDI:1;
1560 UINT32 EepromDO:1;
1561 UINT32 Type:1; // 1: 93C46, 0:93C66
1562 UINT32 LoadStatus:1; // 1:loading, 0:done
1563 UINT32 Rsvd:25;
1564 } field;
1565 UINT32 word;
1566 } E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
1567
1568 // -------------------------------------------------------------------
1569 // E2PROM data layout
1570 // -------------------------------------------------------------------
1571
1572 //
1573 // EEPROM antenna select format
1574 //
1575 typedef union _EEPROM_ANTENNA_STRUC {
1576 struct {
1577 USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
1578 USHORT TxPath:4; // 1: 1T, 2: 2T
1579 USHORT RfIcType:4; // see E2PROM document
1580 USHORT Rsv:4;
1581 } field;
1582 USHORT word;
1583 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
1584
1585 typedef union _EEPROM_NIC_CINFIG2_STRUC {
1586 struct {
1587 USHORT HardwareRadioControl:1; // 1:enable, 0:disable
1588 USHORT DynamicTxAgcControl:1; //
1589 USHORT ExternalLNAForG:1; //
1590 USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
1591 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1592 USHORT BW40MSidebandForG:1;
1593 USHORT BW40MSidebandForA:1;
1594 USHORT EnableWPSPBC:1; // WPS PBC Control bit
1595 USHORT BW40MAvailForG:1; // 0:enable, 1:disable
1596 USHORT BW40MAvailForA:1; // 0:enable, 1:disable
1597 USHORT Rsv1:1; // must be 0
1598 USHORT AntDiversity:1; // Antenna diversity
1599 USHORT Rsv2:3; // must be 0
1600 USHORT DACTestBit:1; // control if driver should patch the DAC issue
1601 } field;
1602 USHORT word;
1603 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
1604
1605 //
1606 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
1607 //
1608 typedef union _EEPROM_TX_PWR_STRUC {
1609 struct {
1610 CHAR Byte0; // Low Byte
1611 CHAR Byte1; // High Byte
1612 } field;
1613 USHORT word;
1614 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
1615
1616 typedef union _EEPROM_VERSION_STRUC {
1617 struct {
1618 UCHAR FaeReleaseNumber; // Low Byte
1619 UCHAR Version; // High Byte
1620 } field;
1621 USHORT word;
1622 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
1623
1624 typedef union _EEPROM_LED_STRUC {
1625 struct {
1626 USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
1627 USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
1628 USHORT PolarityACT:1; // Polarity ACT setting.
1629 USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
1630 USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
1631 USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
1632 USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
1633 USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
1634 USHORT LedMode:5; // Led mode.
1635 USHORT Rsvd:3; // Reserved
1636 } field;
1637 USHORT word;
1638 } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
1639
1640 typedef union _EEPROM_TXPOWER_DELTA_STRUC {
1641 struct {
1642 UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
1643 UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
1644 UCHAR TxPowerEnable:1;// Enable
1645 } field;
1646 UCHAR value;
1647 } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
1648
1649 //
1650 // QOS_CSR0: TXOP holder address0 register
1651 //
1652 typedef union _QOS_CSR0_STRUC {
1653 struct {
1654 UCHAR Byte0; // MAC address byte 0
1655 UCHAR Byte1; // MAC address byte 1
1656 UCHAR Byte2; // MAC address byte 2
1657 UCHAR Byte3; // MAC address byte 3
1658 } field;
1659 UINT32 word;
1660 } QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
1661
1662 //
1663 // QOS_CSR1: TXOP holder address1 register
1664 //
1665 typedef union _QOS_CSR1_STRUC {
1666 struct {
1667 UCHAR Byte4; // MAC address byte 4
1668 UCHAR Byte5; // MAC address byte 5
1669 UCHAR Rsvd0;
1670 UCHAR Rsvd1;
1671 } field;
1672 UINT32 word;
1673 } QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
1674
1675 #define RF_CSR_CFG 0x500
1676 typedef union _RF_CSR_CFG_STRUC {
1677 struct {
1678 UINT RF_CSR_DATA:8; // DATA
1679 UINT TESTCSR_RFACC_REGNUM:5; // RF register ID
1680 UINT Rsvd2:3; // Reserved
1681 UINT RF_CSR_WR:1; // 0: read 1: write
1682 UINT RF_CSR_KICK:1; // kick RF register read/write
1683 UINT Rsvd1:14; // Reserved
1684 } field;
1685 UINT word;
1686 } RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
1687
1688 #endif // __RT28XX_H__
kernel source for telekom puls (alcatel/mediatek)