2 * Freescale i.MX28 LRADC driver
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
23 #include <linux/of_device.h>
24 #include <linux/sysfs.h>
25 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/spinlock.h>
30 #include <linux/wait.h>
31 #include <linux/sched.h>
32 #include <linux/stmp_device.h>
33 #include <linux/bitops.h>
34 #include <linux/completion.h>
37 #include <mach/common.h>
39 #include <linux/iio/iio.h>
40 #include <linux/iio/buffer.h>
41 #include <linux/iio/trigger.h>
42 #include <linux/iio/trigger_consumer.h>
43 #include <linux/iio/triggered_buffer.h>
45 #define DRIVER_NAME "mxs-lradc"
47 #define LRADC_MAX_DELAY_CHANS 4
48 #define LRADC_MAX_MAPPED_CHANS 8
49 #define LRADC_MAX_TOTAL_CHANS 16
51 #define LRADC_DELAY_TIMER_HZ 2000
54 * Make this runtime configurable if necessary. Currently, if the buffered mode
55 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
56 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
57 * seconds. The result is that the samples arrive every 500mS.
59 #define LRADC_DELAY_TIMER_PER 200
60 #define LRADC_DELAY_TIMER_LOOP 5
62 static const char * const mxs_lradc_irq_name
[] = {
63 "mxs-lradc-touchscreen",
78 struct mxs_lradc_chan
{
89 struct iio_trigger
*trig
;
95 struct completion completion
;
98 #define LRADC_CTRL0 0x00
99 #define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
100 #define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
102 #define LRADC_CTRL1 0x10
103 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
104 #define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff
105 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
106 #define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16)
108 #define LRADC_CTRL2 0x20
109 #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
111 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
112 #define LRADC_CH_ACCUMULATE (1 << 29)
113 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
114 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
115 #define LRADC_CH_VALUE_MASK 0x3ffff
116 #define LRADC_CH_VALUE_OFFSET 0
118 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
119 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
120 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
121 #define LRADC_DELAY_KICK (1 << 20)
122 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
123 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
124 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
125 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
126 #define LRADC_DELAY_DELAY_MASK 0x7ff
127 #define LRADC_DELAY_DELAY_OFFSET 0
129 #define LRADC_CTRL4 0x140
130 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
131 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
136 static int mxs_lradc_read_raw(struct iio_dev
*iio_dev
,
137 const struct iio_chan_spec
*chan
,
138 int *val
, int *val2
, long m
)
140 struct mxs_lradc
*lradc
= iio_priv(iio_dev
);
143 if (m
!= IIO_CHAN_INFO_RAW
)
146 /* Check for invalid channel */
147 if (chan
->channel
> LRADC_MAX_TOTAL_CHANS
)
151 * See if there is no buffered operation in progess. If there is, simply
152 * bail out. This can be improved to support both buffered and raw IO at
153 * the same time, yet the code becomes horribly complicated. Therefore I
154 * applied KISS principle here.
156 ret
= mutex_trylock(&lradc
->lock
);
160 INIT_COMPLETION(lradc
->completion
);
163 * No buffered operation in progress, map the channel and trigger it.
164 * Virtual channel 0 is always used here as the others are always not
165 * used if doing raw sampling.
167 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK
,
168 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
169 writel(0xff, lradc
->base
+ LRADC_CTRL0
+ STMP_OFFSET_REG_CLR
);
171 writel(chan
->channel
, lradc
->base
+ LRADC_CTRL4
);
172 writel(0, lradc
->base
+ LRADC_CH(0));
174 /* Enable the IRQ and start sampling the channel. */
175 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
176 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_SET
);
177 writel(1 << 0, lradc
->base
+ LRADC_CTRL0
+ STMP_OFFSET_REG_SET
);
179 /* Wait for completion on the channel, 1 second max. */
180 ret
= wait_for_completion_killable_timeout(&lradc
->completion
, HZ
);
187 *val
= readl(lradc
->base
+ LRADC_CH(0)) & LRADC_CH_VALUE_MASK
;
191 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
192 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
194 mutex_unlock(&lradc
->lock
);
199 static const struct iio_info mxs_lradc_iio_info
= {
200 .driver_module
= THIS_MODULE
,
201 .read_raw
= mxs_lradc_read_raw
,
207 static irqreturn_t
mxs_lradc_handle_irq(int irq
, void *data
)
209 struct iio_dev
*iio
= data
;
210 struct mxs_lradc
*lradc
= iio_priv(iio
);
211 unsigned long reg
= readl(lradc
->base
+ LRADC_CTRL1
);
213 if (!(reg
& LRADC_CTRL1_LRADC_IRQ_MASK
))
217 * Touchscreen IRQ handling code shall probably have priority
218 * and therefore shall be placed here.
221 if (iio_buffer_enabled(iio
))
222 iio_trigger_poll(iio
->trig
, iio_get_time_ns());
223 else if (reg
& LRADC_CTRL1_LRADC_IRQ(0))
224 complete(&lradc
->completion
);
226 writel(reg
& LRADC_CTRL1_LRADC_IRQ_MASK
,
227 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
235 static irqreturn_t
mxs_lradc_trigger_handler(int irq
, void *p
)
237 struct iio_poll_func
*pf
= p
;
238 struct iio_dev
*iio
= pf
->indio_dev
;
239 struct mxs_lradc
*lradc
= iio_priv(iio
);
240 const uint32_t chan_value
= LRADC_CH_ACCUMULATE
|
241 ((LRADC_DELAY_TIMER_LOOP
- 1) << LRADC_CH_NUM_SAMPLES_OFFSET
);
244 for_each_set_bit(i
, iio
->active_scan_mask
, iio
->masklength
) {
245 lradc
->buffer
[j
] = readl(lradc
->base
+ LRADC_CH(j
));
246 writel(chan_value
, lradc
->base
+ LRADC_CH(j
));
247 lradc
->buffer
[j
] &= LRADC_CH_VALUE_MASK
;
248 lradc
->buffer
[j
] /= LRADC_DELAY_TIMER_LOOP
;
252 if (iio
->scan_timestamp
) {
253 s64
*timestamp
= (s64
*)((u8
*)lradc
->buffer
+
254 ALIGN(j
, sizeof(s64
)));
255 *timestamp
= pf
->timestamp
;
258 iio_push_to_buffers(iio
, (u8
*)lradc
->buffer
);
260 iio_trigger_notify_done(iio
->trig
);
265 static int mxs_lradc_configure_trigger(struct iio_trigger
*trig
, bool state
)
267 struct iio_dev
*iio
= trig
->private_data
;
268 struct mxs_lradc
*lradc
= iio_priv(iio
);
269 const uint32_t st
= state
? STMP_OFFSET_REG_SET
: STMP_OFFSET_REG_CLR
;
271 writel(LRADC_DELAY_KICK
, lradc
->base
+ LRADC_DELAY(0) + st
);
276 static const struct iio_trigger_ops mxs_lradc_trigger_ops
= {
277 .owner
= THIS_MODULE
,
278 .set_trigger_state
= &mxs_lradc_configure_trigger
,
281 static int mxs_lradc_trigger_init(struct iio_dev
*iio
)
284 struct iio_trigger
*trig
;
286 trig
= iio_trigger_alloc("%s-dev%i", iio
->name
, iio
->id
);
290 trig
->dev
.parent
= iio
->dev
.parent
;
291 trig
->private_data
= iio
;
292 trig
->ops
= &mxs_lradc_trigger_ops
;
294 ret
= iio_trigger_register(trig
);
296 iio_trigger_free(trig
);
305 static void mxs_lradc_trigger_remove(struct iio_dev
*iio
)
307 iio_trigger_unregister(iio
->trig
);
308 iio_trigger_free(iio
->trig
);
311 static int mxs_lradc_buffer_preenable(struct iio_dev
*iio
)
313 struct mxs_lradc
*lradc
= iio_priv(iio
);
314 struct iio_buffer
*buffer
= iio
->buffer
;
315 int ret
= 0, chan
, ofs
= 0, enable
= 0;
317 uint32_t ctrl1_irq
= 0;
318 const uint32_t chan_value
= LRADC_CH_ACCUMULATE
|
319 ((LRADC_DELAY_TIMER_LOOP
- 1) << LRADC_CH_NUM_SAMPLES_OFFSET
);
320 const int len
= bitmap_weight(buffer
->scan_mask
, LRADC_MAX_TOTAL_CHANS
);
326 * Lock the driver so raw access can not be done during buffered
327 * operation. This simplifies the code a lot.
329 ret
= mutex_trylock(&lradc
->lock
);
333 lradc
->buffer
= kmalloc(len
* sizeof(*lradc
->buffer
), GFP_KERNEL
);
334 if (!lradc
->buffer
) {
339 ret
= iio_sw_buffer_preenable(iio
);
343 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK
,
344 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
345 writel(0xff, lradc
->base
+ LRADC_CTRL0
+ STMP_OFFSET_REG_CLR
);
347 for_each_set_bit(chan
, buffer
->scan_mask
, LRADC_MAX_TOTAL_CHANS
) {
348 ctrl4
|= chan
<< LRADC_CTRL4_LRADCSELECT_OFFSET(ofs
);
349 ctrl1_irq
|= LRADC_CTRL1_LRADC_IRQ_EN(ofs
);
350 writel(chan_value
, lradc
->base
+ LRADC_CH(ofs
));
355 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK
| LRADC_DELAY_KICK
,
356 lradc
->base
+ LRADC_DELAY(0) + STMP_OFFSET_REG_CLR
);
358 writel(ctrl4
, lradc
->base
+ LRADC_CTRL4
);
359 writel(ctrl1_irq
, lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_SET
);
361 writel(enable
<< LRADC_DELAY_TRIGGER_LRADCS_OFFSET
,
362 lradc
->base
+ LRADC_DELAY(0) + STMP_OFFSET_REG_SET
);
367 kfree(lradc
->buffer
);
369 mutex_unlock(&lradc
->lock
);
373 static int mxs_lradc_buffer_postdisable(struct iio_dev
*iio
)
375 struct mxs_lradc
*lradc
= iio_priv(iio
);
377 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK
| LRADC_DELAY_KICK
,
378 lradc
->base
+ LRADC_DELAY(0) + STMP_OFFSET_REG_CLR
);
380 writel(0xff, lradc
->base
+ LRADC_CTRL0
+ STMP_OFFSET_REG_CLR
);
381 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK
,
382 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
384 kfree(lradc
->buffer
);
385 mutex_unlock(&lradc
->lock
);
390 static bool mxs_lradc_validate_scan_mask(struct iio_dev
*iio
,
391 const unsigned long *mask
)
393 const int mw
= bitmap_weight(mask
, iio
->masklength
);
395 return mw
<= LRADC_MAX_MAPPED_CHANS
;
398 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops
= {
399 .preenable
= &mxs_lradc_buffer_preenable
,
400 .postenable
= &iio_triggered_buffer_postenable
,
401 .predisable
= &iio_triggered_buffer_predisable
,
402 .postdisable
= &mxs_lradc_buffer_postdisable
,
403 .validate_scan_mask
= &mxs_lradc_validate_scan_mask
,
407 * Driver initialization
410 #define MXS_ADC_CHAN(idx, chan_type) { \
411 .type = (chan_type), \
413 .scan_index = (idx), \
414 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
423 static const struct iio_chan_spec mxs_lradc_chan_spec
[] = {
424 MXS_ADC_CHAN(0, IIO_VOLTAGE
),
425 MXS_ADC_CHAN(1, IIO_VOLTAGE
),
426 MXS_ADC_CHAN(2, IIO_VOLTAGE
),
427 MXS_ADC_CHAN(3, IIO_VOLTAGE
),
428 MXS_ADC_CHAN(4, IIO_VOLTAGE
),
429 MXS_ADC_CHAN(5, IIO_VOLTAGE
),
430 MXS_ADC_CHAN(6, IIO_VOLTAGE
),
431 MXS_ADC_CHAN(7, IIO_VOLTAGE
), /* VBATT */
432 MXS_ADC_CHAN(8, IIO_TEMP
), /* Temp sense 0 */
433 MXS_ADC_CHAN(9, IIO_TEMP
), /* Temp sense 1 */
434 MXS_ADC_CHAN(10, IIO_VOLTAGE
), /* VDDIO */
435 MXS_ADC_CHAN(11, IIO_VOLTAGE
), /* VTH */
436 MXS_ADC_CHAN(12, IIO_VOLTAGE
), /* VDDA */
437 MXS_ADC_CHAN(13, IIO_VOLTAGE
), /* VDDD */
438 MXS_ADC_CHAN(14, IIO_VOLTAGE
), /* VBG */
439 MXS_ADC_CHAN(15, IIO_VOLTAGE
), /* VDD5V */
442 static void mxs_lradc_hw_init(struct mxs_lradc
*lradc
)
446 (LRADC_DELAY_TIMER_PER
<< LRADC_DELAY_DELAY_OFFSET
);
448 stmp_reset_block(lradc
->base
);
450 for (i
= 0; i
< LRADC_MAX_DELAY_CHANS
; i
++)
451 writel(cfg
| (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET
+ i
)),
452 lradc
->base
+ LRADC_DELAY(i
));
454 /* Start internal temperature sensing. */
455 writel(0, lradc
->base
+ LRADC_CTRL2
);
458 static void mxs_lradc_hw_stop(struct mxs_lradc
*lradc
)
462 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK
,
463 lradc
->base
+ LRADC_CTRL1
+ STMP_OFFSET_REG_CLR
);
465 for (i
= 0; i
< LRADC_MAX_DELAY_CHANS
; i
++)
466 writel(0, lradc
->base
+ LRADC_DELAY(i
));
469 static int mxs_lradc_probe(struct platform_device
*pdev
)
471 struct device
*dev
= &pdev
->dev
;
472 struct mxs_lradc
*lradc
;
474 struct resource
*iores
;
478 /* Allocate the IIO device. */
479 iio
= iio_device_alloc(sizeof(*lradc
));
481 dev_err(dev
, "Failed to allocate IIO device\n");
485 lradc
= iio_priv(iio
);
487 /* Grab the memory area */
488 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
489 lradc
->dev
= &pdev
->dev
;
490 lradc
->base
= devm_request_and_ioremap(dev
, iores
);
492 ret
= -EADDRNOTAVAIL
;
496 /* Grab all IRQ sources */
497 for (i
= 0; i
< 13; i
++) {
498 lradc
->irq
[i
] = platform_get_irq(pdev
, i
);
499 if (lradc
->irq
[i
] < 0) {
504 ret
= devm_request_irq(dev
, lradc
->irq
[i
],
505 mxs_lradc_handle_irq
, 0,
506 mxs_lradc_irq_name
[i
], iio
);
511 platform_set_drvdata(pdev
, iio
);
513 init_completion(&lradc
->completion
);
514 mutex_init(&lradc
->lock
);
516 iio
->name
= pdev
->name
;
517 iio
->dev
.parent
= &pdev
->dev
;
518 iio
->info
= &mxs_lradc_iio_info
;
519 iio
->modes
= INDIO_DIRECT_MODE
;
520 iio
->channels
= mxs_lradc_chan_spec
;
521 iio
->num_channels
= ARRAY_SIZE(mxs_lradc_chan_spec
);
523 ret
= iio_triggered_buffer_setup(iio
, &iio_pollfunc_store_time
,
524 &mxs_lradc_trigger_handler
,
525 &mxs_lradc_buffer_ops
);
529 ret
= mxs_lradc_trigger_init(iio
);
533 /* Register IIO device. */
534 ret
= iio_device_register(iio
);
536 dev_err(dev
, "Failed to register IIO device\n");
540 /* Configure the hardware. */
541 mxs_lradc_hw_init(lradc
);
546 mxs_lradc_trigger_remove(iio
);
548 iio_triggered_buffer_cleanup(iio
);
550 iio_device_free(iio
);
554 static int mxs_lradc_remove(struct platform_device
*pdev
)
556 struct iio_dev
*iio
= platform_get_drvdata(pdev
);
557 struct mxs_lradc
*lradc
= iio_priv(iio
);
559 mxs_lradc_hw_stop(lradc
);
561 iio_device_unregister(iio
);
562 iio_triggered_buffer_cleanup(iio
);
563 mxs_lradc_trigger_remove(iio
);
564 iio_device_free(iio
);
569 static const struct of_device_id mxs_lradc_dt_ids
[] = {
570 { .compatible
= "fsl,imx28-lradc", },
573 MODULE_DEVICE_TABLE(of
, mxs_lradc_dt_ids
);
575 static struct platform_driver mxs_lradc_driver
= {
578 .owner
= THIS_MODULE
,
579 .of_match_table
= mxs_lradc_dt_ids
,
581 .probe
= mxs_lradc_probe
,
582 .remove
= mxs_lradc_remove
,
585 module_platform_driver(mxs_lradc_driver
);
587 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
588 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
589 MODULE_LICENSE("GPL v2");