2 * core.h - DesignWare HS OTG Controller common declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
40 #include <linux/usb/phy.h>
43 #ifdef DWC2_LOG_WRITES
44 static inline void do_write(u32 value
, void *addr
)
47 pr_info("INFO:: wrote %08x to %p\n", value
, addr
);
51 #define writel(v, a) do_write(v, a)
54 /* Maximum number of Endpoints/HostChannels */
55 #define MAX_EPS_CHANNELS 16
58 struct dwc2_host_chan
;
62 DWC2_L0
, /* On state */
63 DWC2_L1
, /* LPM sleep state */
64 DWC2_L2
, /* USB suspend state */
65 DWC2_L3
, /* Off state */
69 * struct dwc2_core_params - Parameters for configuring the core
71 * @otg_cap: Specifies the OTG capabilities. The driver will
72 * automatically detect the value for this parameter if
74 * 0 - HNP and SRP capable (default)
75 * 1 - SRP Only capable
76 * 2 - No HNP/SRP capable
77 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
78 * the data FIFOs. The driver will automatically detect the
79 * value for this parameter if none is specified.
81 * 1 - DMA (default, if available)
82 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
83 * address DMA mode or descriptor DMA mode for accessing
84 * the data FIFOs. The driver will automatically detect the
85 * value for this if none is specified.
87 * 1 - Descriptor DMA (default, if available)
88 * @speed: Specifies the maximum speed of operation in host and
89 * device mode. The actual speed depends on the speed of
90 * the attached device and the value of phy_type.
91 * 0 - High Speed (default)
93 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
94 * when attached to a Full Speed or Low Speed device in
96 * 0 - Don't support low power mode (default)
97 * 1 - Support low power mode
98 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
99 * when connected to a Low Speed device in host mode. This
100 * parameter is applicable only if
101 * host_support_fs_ls_low_power is enabled. If phy_type is
102 * set to FS then defaults to 6 MHZ otherwise 48 MHZ.
105 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
106 * 1 - Allow dynamic FIFO sizing (default)
107 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
108 * dynamic FIFO sizing is enabled
109 * 16 to 32768 (default 1024)
110 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
111 * in host mode when dynamic FIFO sizing is enabled
112 * 16 to 32768 (default 1024)
113 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
114 * host mode when dynamic FIFO sizing is enabled
115 * 16 to 32768 (default 1024)
116 * @max_transfer_size: The maximum transfer size supported, in bytes
117 * 2047 to 65,535 (default 65,535)
118 * @max_packet_count: The maximum number of packets in a transfer
119 * 15 to 511 (default 511)
120 * @host_channels: The number of host channel registers to use
121 * 1 to 16 (default 12)
122 * @phy_type: Specifies the type of PHY interface to use. By default,
123 * the driver will automatically detect the phy_type.
124 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
125 * is applicable for a phy_type of UTMI+ or ULPI. (For a
126 * ULPI phy_type, this parameter indicates the data width
127 * between the MAC and the ULPI Wrapper.) Also, this
128 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
129 * parameter was set to "8 and 16 bits", meaning that the
130 * core has been configured to work at either data path
132 * 8 or 16 (default 16)
133 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
134 * data rate. This parameter is only applicable if phy_type
136 * 0 - single data rate ULPI interface with 8 bit wide
138 * 1 - double data rate ULPI interface with 4 bit wide
140 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
141 * external supply to drive the VBus
142 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
143 * speed PHY. This parameter is only applicable if phy_type
147 * @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only
148 * @ts_dline: True to enable Term Select Dline pulsing
149 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
151 * @reload_ctl: True to allow dynamic reloading of HFIR register during
153 * @ahb_single: This bit enables SINGLE transfers for remainder data in
154 * a transfer for DMA mode of operation.
155 * 0 - remainder data will be sent using INCR burst size
156 * 1 - remainder data will be sent using SINGLE burst size
157 * @otg_ver: OTG version supported
161 * The following parameters may be specified when starting the module. These
162 * parameters define how the DWC_otg controller should be configured.
164 struct dwc2_core_params
{
166 * Don't add any non-int members here, this will break
167 * dwc2_set_all_params!
174 int enable_dynamic_fifo
;
175 int en_multiple_tx_fifo
;
176 int host_rx_fifo_size
;
177 int host_nperio_tx_fifo_size
;
178 int host_perio_tx_fifo_size
;
179 int max_transfer_size
;
180 int max_packet_count
;
185 int phy_ulpi_ext_vbus
;
188 int host_support_fs_ls_low_power
;
189 int host_ls_low_power_phy_clk
;
196 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
197 * and periodic schedules
199 * @dev: The struct device pointer
200 * @regs: Pointer to controller regs
201 * @core_params: Parameters that define how the core should be configured
202 * @hwcfg1: Hardware Configuration - stored here for convenience
203 * @hwcfg2: Hardware Configuration - stored here for convenience
204 * @hwcfg3: Hardware Configuration - stored here for convenience
205 * @hwcfg4: Hardware Configuration - stored here for convenience
206 * @hptxfsiz: Hardware Configuration - stored here for convenience
207 * @snpsid: Value from SNPSID register
208 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
209 * @rx_fifo_size: Size of Rx FIFO (bytes)
210 * @nperio_tx_fifo_size: Size of Non-periodic Tx FIFO (Bytes)
211 * @op_state: The operational State, during transitions (a_host=>
212 * a_peripheral and b_device=>b_host) this may not match
213 * the core, but allows the software to determine
215 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
216 * transfer are in process of being queued
217 * @srp_success: Stores status of SRP request in the case of a FS PHY
218 * with an I2C interface
219 * @wq_otg: Workqueue object used for handling of some interrupts
220 * @wf_otg: Work object for handling Connector ID Status Change
222 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
223 * @lx_state: Lx state of connected device
224 * @flags: Flags for handling root port state changes
225 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
226 * Transfers associated with these QHs are not currently
227 * assigned to a host channel.
228 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
229 * Transfers associated with these QHs are currently
230 * assigned to a host channel.
231 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
232 * non-periodic schedule
233 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
234 * list of QHs for periodic transfers that are _not_
235 * scheduled for the next frame. Each QH in the list has an
236 * interval counter that determines when it needs to be
237 * scheduled for execution. This scheduling mechanism
238 * allows only a simple calculation for periodic bandwidth
239 * used (i.e. must assume that all periodic transfers may
240 * need to execute in the same frame). However, it greatly
241 * simplifies scheduling and should be sufficient for the
242 * vast majority of OTG hosts, which need to connect to a
243 * small number of peripherals at one time. Items move from
244 * this list to periodic_sched_ready when the QH interval
245 * counter is 0 at SOF.
246 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
247 * the next frame, but have not yet been assigned to host
248 * channels. Items move from this list to
249 * periodic_sched_assigned as host channels become
250 * available during the current frame.
251 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
252 * frame that are assigned to host channels. Items move
253 * from this list to periodic_sched_queued as the
254 * transactions for the QH are queued to the DWC_otg
256 * @periodic_sched_queued: List of periodic QHs that have been queued for
257 * execution. Items move from this list to either
258 * periodic_sched_inactive or periodic_sched_ready when the
259 * channel associated with the transfer is released. If the
260 * interval for the QH is 1, the item moves to
261 * periodic_sched_ready because it must be rescheduled for
262 * the next frame. Otherwise, the item moves to
263 * periodic_sched_inactive.
264 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
265 * This value is in microseconds per (micro)frame. The
266 * assumption is that all periodic transfers may occur in
267 * the same (micro)frame.
268 * @frame_number: Frame number read from the core at SOF. The value ranges
269 * from 0 to HFNUM_MAX_FRNUM.
270 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
271 * SOF enable/disable.
272 * @free_hc_list: Free host channels in the controller. This is a list of
273 * struct dwc2_host_chan items.
274 * @periodic_channels: Number of host channels assigned to periodic transfers.
275 * Currently assuming that there is a dedicated host
276 * channel for each periodic transaction and at least one
277 * host channel is available for non-periodic transactions.
278 * @non_periodic_channels: Number of host channels assigned to non-periodic
280 * @hc_ptr_array: Array of pointers to the host channel descriptors.
281 * Allows accessing a host channel descriptor given the
282 * host channel number. This is useful in interrupt
284 * @status_buf: Buffer used for data received during the status phase of
285 * a control transfer.
286 * @status_buf_dma: DMA address for status_buf
287 * @start_work: Delayed work for handling host A-cable connection
288 * @reset_work: Delayed work for handling a port reset
289 * @lock: Spinlock that protects all the driver data structures
290 * @priv: Stores a pointer to the struct usb_hcd
291 * @otg_port: OTG port number
292 * @frame_list: Frame list
293 * @frame_list_dma: Frame list DMA address
298 struct dwc2_core_params
*core_params
;
307 u16 nperio_tx_fifo_size
;
308 enum usb_otg_state op_state
;
310 unsigned int queuing_high_bandwidth
:1;
311 unsigned int srp_success
:1;
313 struct workqueue_struct
*wq_otg
;
314 struct work_struct wf_otg
;
315 struct timer_list wkp_timer
;
316 enum dwc2_lx_state lx_state
;
318 union dwc2_hcd_internal_flags
{
321 unsigned port_connect_status_change
:1;
322 unsigned port_connect_status
:1;
323 unsigned port_reset_change
:1;
324 unsigned port_enable_change
:1;
325 unsigned port_suspend_change
:1;
326 unsigned port_over_current_change
:1;
327 unsigned port_l1_change
:1;
328 unsigned reserved
:26;
332 struct list_head non_periodic_sched_inactive
;
333 struct list_head non_periodic_sched_active
;
334 struct list_head
*non_periodic_qh_ptr
;
335 struct list_head periodic_sched_inactive
;
336 struct list_head periodic_sched_ready
;
337 struct list_head periodic_sched_assigned
;
338 struct list_head periodic_sched_queued
;
341 u16 periodic_qh_count
;
343 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
344 #define FRAME_NUM_ARRAY_SIZE 1000
346 u16
*frame_num_array
;
347 u16
*last_frame_num_array
;
349 int dumped_frame_num_array
;
352 struct list_head free_hc_list
;
353 int periodic_channels
;
354 int non_periodic_channels
;
355 struct dwc2_host_chan
*hc_ptr_array
[MAX_EPS_CHANNELS
];
357 dma_addr_t status_buf_dma
;
358 #define DWC2_HCD_STATUS_BUF_SIZE 64
360 struct delayed_work start_work
;
361 struct delayed_work reset_work
;
366 dma_addr_t frame_list_dma
;
368 /* DWC OTG HW Release versions */
369 #define DWC2_CORE_REV_2_71a 0x4f54271a
370 #define DWC2_CORE_REV_2_90a 0x4f54290a
371 #define DWC2_CORE_REV_2_92a 0x4f54292a
372 #define DWC2_CORE_REV_2_94a 0x4f54294a
373 #define DWC2_CORE_REV_3_00a 0x4f54300a
379 u32 hfnum_7_samples_a
;
380 u64 hfnum_7_frrem_accum_a
;
381 u32 hfnum_0_samples_a
;
382 u64 hfnum_0_frrem_accum_a
;
383 u32 hfnum_other_samples_a
;
384 u64 hfnum_other_frrem_accum_a
;
386 u32 hfnum_7_samples_b
;
387 u64 hfnum_7_frrem_accum_b
;
388 u32 hfnum_0_samples_b
;
389 u64 hfnum_0_frrem_accum_b
;
390 u32 hfnum_other_samples_b
;
391 u64 hfnum_other_frrem_accum_b
;
395 /* Reasons for halting a host channel */
396 enum dwc2_halt_status
{
397 DWC2_HC_XFER_NO_HALT_STATUS
,
398 DWC2_HC_XFER_COMPLETE
,
399 DWC2_HC_XFER_URB_COMPLETE
,
404 DWC2_HC_XFER_XACT_ERR
,
405 DWC2_HC_XFER_FRAME_OVERRUN
,
406 DWC2_HC_XFER_BABBLE_ERR
,
407 DWC2_HC_XFER_DATA_TOGGLE_ERR
,
408 DWC2_HC_XFER_AHB_ERR
,
409 DWC2_HC_XFER_PERIODIC_INCOMPLETE
,
410 DWC2_HC_XFER_URB_DEQUEUE
,
414 * The following functions support initialization of the core driver component
415 * and the DWC_otg controller
417 extern void dwc2_core_host_init(struct dwc2_hsotg
*hsotg
);
420 * Host core Functions.
421 * The following functions support managing the DWC_otg controller in host
424 extern void dwc2_hc_init(struct dwc2_hsotg
*hsotg
, struct dwc2_host_chan
*chan
);
425 extern void dwc2_hc_halt(struct dwc2_hsotg
*hsotg
, struct dwc2_host_chan
*chan
,
426 enum dwc2_halt_status halt_status
);
427 extern void dwc2_hc_cleanup(struct dwc2_hsotg
*hsotg
,
428 struct dwc2_host_chan
*chan
);
429 extern void dwc2_hc_start_transfer(struct dwc2_hsotg
*hsotg
,
430 struct dwc2_host_chan
*chan
);
431 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg
*hsotg
,
432 struct dwc2_host_chan
*chan
);
433 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg
*hsotg
,
434 struct dwc2_host_chan
*chan
);
435 extern void dwc2_hc_do_ping(struct dwc2_hsotg
*hsotg
,
436 struct dwc2_host_chan
*chan
);
437 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg
*hsotg
);
438 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg
*hsotg
);
440 extern u32
dwc2_calc_frame_interval(struct dwc2_hsotg
*hsotg
);
441 extern int dwc2_check_core_status(struct dwc2_hsotg
*hsotg
);
444 * Common core Functions.
445 * The following functions support managing the DWC_otg controller in either
446 * device or host mode.
448 extern void dwc2_read_packet(struct dwc2_hsotg
*hsotg
, u8
*dest
, u16 bytes
);
449 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg
*hsotg
, const int num
);
450 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg
*hsotg
);
452 extern int dwc2_core_init(struct dwc2_hsotg
*hsotg
, bool select_phy
, int irq
);
453 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg
*hcd
);
454 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg
*hcd
);
456 /* This function should be called on every hardware interrupt. */
457 extern irqreturn_t
dwc2_handle_common_intr(int irq
, void *dev
);
459 /* OTG Core Parameters */
462 * Specifies the OTG capabilities. The driver will automatically
463 * detect the value for this parameter if none is specified.
464 * 0 - HNP and SRP capable (default)
465 * 1 - SRP Only capable
466 * 2 - No HNP/SRP capable
468 extern int dwc2_set_param_otg_cap(struct dwc2_hsotg
*hsotg
, int val
);
469 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
470 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
471 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
474 * Specifies whether to use slave or DMA mode for accessing the data
475 * FIFOs. The driver will automatically detect the value for this
476 * parameter if none is specified.
478 * 1 - DMA (default, if available)
480 extern int dwc2_set_param_dma_enable(struct dwc2_hsotg
*hsotg
, int val
);
483 * When DMA mode is enabled specifies whether to use
484 * address DMA or DMA Descritor mode for accessing the data
485 * FIFOs in device mode. The driver will automatically detect
486 * the value for this parameter if none is specified.
488 * 1 - DMA Descriptor(default, if available)
490 extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg
*hsotg
, int val
);
493 * Specifies the maximum speed of operation in host and device mode.
494 * The actual speed depends on the speed of the attached device and
495 * the value of phy_type. The actual speed depends on the speed of the
497 * 0 - High Speed (default)
500 extern int dwc2_set_param_speed(struct dwc2_hsotg
*hsotg
, int val
);
501 #define DWC2_SPEED_PARAM_HIGH 0
502 #define DWC2_SPEED_PARAM_FULL 1
505 * Specifies whether low power mode is supported when attached
506 * to a Full Speed or Low Speed device in host mode.
508 * 0 - Don't support low power mode (default)
509 * 1 - Support low power mode
511 extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg
*hsotg
,
515 * Specifies the PHY clock rate in low power mode when connected to a
516 * Low Speed device in host mode. This parameter is applicable only if
517 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
518 * then defaults to 6 MHZ otherwise 48 MHZ.
523 extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg
*hsotg
,
525 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
526 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
529 * 0 - Use cC FIFO size parameters
530 * 1 - Allow dynamic FIFO sizing (default)
532 extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg
*hsotg
,
536 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
537 * FIFO sizing is enabled.
538 * 16 to 32768 (default 1024)
540 extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg
*hsotg
, int val
);
543 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
544 * when Dynamic FIFO sizing is enabled in the core.
545 * 16 to 32768 (default 256)
547 extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg
*hsotg
,
551 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
552 * FIFO sizing is enabled.
553 * 16 to 32768 (default 256)
555 extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg
*hsotg
,
559 * The maximum transfer size supported in bytes.
560 * 2047 to 65,535 (default 65,535)
562 extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg
*hsotg
, int val
);
565 * The maximum number of packets in a transfer.
566 * 15 to 511 (default 511)
568 extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg
*hsotg
, int val
);
571 * The number of host channel registers to use.
572 * 1 to 16 (default 11)
573 * Note: The FPGA configuration supports a maximum of 11 host channels.
575 extern int dwc2_set_param_host_channels(struct dwc2_hsotg
*hsotg
, int val
);
578 * Specifies the type of PHY interface to use. By default, the driver
579 * will automatically detect the phy_type.
582 * 1 - UTMI+ (default)
585 extern int dwc2_set_param_phy_type(struct dwc2_hsotg
*hsotg
, int val
);
586 #define DWC2_PHY_TYPE_PARAM_FS 0
587 #define DWC2_PHY_TYPE_PARAM_UTMI 1
588 #define DWC2_PHY_TYPE_PARAM_ULPI 2
591 * Specifies the UTMI+ Data Width. This parameter is
592 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
593 * PHY_TYPE, this parameter indicates the data width between
594 * the MAC and the ULPI Wrapper.) Also, this parameter is
595 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
596 * to "8 and 16 bits", meaning that the core has been
597 * configured to work at either data path width.
599 * 8 or 16 bits (default 16)
601 extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg
*hsotg
, int val
);
604 * Specifies whether the ULPI operates at double or single
605 * data rate. This parameter is only applicable if PHY_TYPE is
608 * 0 - single data rate ULPI interface with 8 bit wide data
610 * 1 - double data rate ULPI interface with 4 bit wide data
613 extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg
*hsotg
, int val
);
616 * Specifies whether to use the internal or external supply to
617 * drive the vbus with a ULPI phy.
619 extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg
*hsotg
, int val
);
620 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
621 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
624 * Specifies whether to use the I2Cinterface for full speed PHY. This
625 * parameter is only applicable if PHY_TYPE is FS.
629 extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg
*hsotg
, int val
);
631 extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg
*hsotg
, int val
);
633 extern int dwc2_set_param_ts_dline(struct dwc2_hsotg
*hsotg
, int val
);
636 * Specifies whether dedicated transmit FIFOs are
637 * enabled for non periodic IN endpoints in device mode
641 extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg
*hsotg
,
644 extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg
*hsotg
, int val
);
646 extern int dwc2_set_param_ahb_single(struct dwc2_hsotg
*hsotg
, int val
);
648 extern int dwc2_set_param_otg_ver(struct dwc2_hsotg
*hsotg
, int val
);
651 * Dump core registers and SPRAM
653 extern void dwc2_dump_dev_registers(struct dwc2_hsotg
*hsotg
);
654 extern void dwc2_dump_host_registers(struct dwc2_hsotg
*hsotg
);
655 extern void dwc2_dump_global_registers(struct dwc2_hsotg
*hsotg
);
658 * Return OTG version - either 1.3 or 2.0
660 extern u16
dwc2_get_otg_version(struct dwc2_hsotg
*hsotg
);
662 #endif /* __DWC2_CORE_H__ */