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Staging: staging/cxt1e1: Convert bare printks to pr_<level>
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / cxt1e1 / pmcc4_drv.c
1 /*
2 * $Id: pmcc4_drv.c,v 3.1 2007/08/15 23:32:17 rickd PMCC4_3_1B $
3 */
4
5
6 /*-----------------------------------------------------------------------------
7 * pmcc4_drv.c -
8 *
9 * Copyright (C) 2007 One Stop Systems, Inc.
10 * Copyright (C) 2002-2006 SBE, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * For further information, contact via email: support@onestopsystems.com
23 * One Stop Systems, Inc. Escondido, California U.S.A.
24 *-----------------------------------------------------------------------------
25 * RCS info:
26 * RCS revision: $Revision: 3.1 $
27 * Last changed on $Date: 2007/08/15 23:32:17 $
28 * Changed by $Author: rickd $
29 *-----------------------------------------------------------------------------
30 * $Log: pmcc4_drv.c,v $
31 * Revision 3.1 2007/08/15 23:32:17 rickd
32 * Use 'if 0' instead of GNU comment delimeter to avoid line wrap induced compiler errors.
33 *
34 * Revision 3.0 2007/08/15 22:19:55 rickd
35 * Correct sizeof() castings and pi->regram to support 64bit compatibility.
36 *
37 * Revision 2.10 2006/04/21 00:56:40 rickd
38 * workqueue files now prefixed with <sbecom> prefix.
39 *
40 * Revision 2.9 2005/11/01 19:22:49 rickd
41 * Add sanity checks against max_port for ioctl functions.
42 *
43 * Revision 2.8 2005/10/27 18:59:25 rickd
44 * Code cleanup. Default channel config to HDLC_FCS16.
45 *
46 * Revision 2.7 2005/10/18 18:16:30 rickd
47 * Further NCOMM code repairs - (1) interrupt matrix usage inconsistant
48 * for indexing into nciInterrupt[][], code missing double parameters.
49 * (2) check input of ncomm interrupt registration cardID for correct
50 * boundary values.
51 *
52 * Revision 2.6 2005/10/17 23:55:28 rickd
53 * Initial port of NCOMM support patches from original work found
54 * in pmc_c4t1e1 as updated by NCOMM. Ref: CONFIG_SBE_PMCC4_NCOMM.
55 * Corrected NCOMMs wanpmcC4T1E1_getBaseAddress() to correctly handle
56 * multiple boards.
57 *
58 * Revision 2.5 2005/10/13 23:01:28 rickd
59 * Correct panic for illegal address reference w/in get_brdinfo on
60 * first_if/last_if name acquistion under Linux 2.6
61 *
62 * Revision 2.4 2005/10/13 21:20:19 rickd
63 * Correction of c4_cleanup() wherein next should be acquired before
64 * ci_t structure is free'd.
65 *
66 * Revision 2.3 2005/10/13 19:20:10 rickd
67 * Correct driver removal cleanup code for multiple boards.
68 *
69 * Revision 2.2 2005/10/11 18:34:04 rickd
70 * New routine added to determine number of ports (comets) on board.
71 *
72 * Revision 2.1 2005/10/05 00:48:13 rickd
73 * Add some RX activation trace code.
74 *
75 * Revision 2.0 2005/09/28 00:10:06 rickd
76 * Implement 2.6 workqueue for TX/RX restart. Correction to
77 * hardware register boundary checks allows expanded access of MUSYCC.
78 * Implement new musycc reg&bits namings.
79 *
80 *-----------------------------------------------------------------------------
81 */
82
83 char OSSIid_pmcc4_drvc[] =
84 "@(#)pmcc4_drv.c - $Revision: 3.1 $ (c) Copyright 2002-2007 One Stop Systems, Inc.";
85
86 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
87
88 #if defined (__FreeBSD__) || defined (__NetBSD__)
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/errno.h>
92 #else
93 #include <linux/types.h>
94 #include "pmcc4_sysdep.h"
95 #include <linux/errno.h>
96 #include <linux/kernel.h>
97 #include <linux/sched.h> /* include for timer */
98 #include <linux/timer.h> /* include for timer */
99 #include <linux/hdlc.h>
100 #include <asm/io.h>
101 #endif
102
103 #include "sbecom_inline_linux.h"
104 #include "libsbew.h"
105 #include "pmcc4_private.h"
106 #include "pmcc4.h"
107 #include "pmcc4_ioctls.h"
108 #include "musycc.h"
109 #include "comet.h"
110 #include "sbe_bid.h"
111
112 #ifdef SBE_INCLUDE_SYMBOLS
113 #define STATIC
114 #else
115 #define STATIC static
116 #endif
117
118
119 #define KERN_WARN KERN_WARNING
120
121 /* forward references */
122 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
123 status_t c4_wk_chan_init (mpi_t *, mch_t *);
124 void c4_wq_port_cleanup (mpi_t *);
125 status_t c4_wq_port_init (mpi_t *);
126
127 #endif
128 int c4_loop_port (ci_t *, int, u_int8_t);
129 status_t c4_set_port (ci_t *, int);
130 status_t musycc_chan_down (ci_t *, int);
131
132 u_int32_t musycc_chan_proto (int);
133 status_t musycc_dump_ring (ci_t *, unsigned int);
134 status_t __init musycc_init (ci_t *);
135 void musycc_init_mdt (mpi_t *);
136 void musycc_serv_req (mpi_t *, u_int32_t);
137 void musycc_update_timeslots (mpi_t *);
138
139 extern void musycc_update_tx_thp (mch_t *);
140 extern int log_level;
141 extern int max_mru;
142 extern int max_mtu;
143 extern int max_rxdesc_used, max_rxdesc_default;
144 extern int max_txdesc_used, max_txdesc_default;
145
146 #if defined (__powerpc__)
147 extern void *memset (void *s, int c, size_t n);
148
149 #endif
150
151 int drvr_state = SBE_DRVR_INIT;
152 ci_t *c4_list = 0;
153 ci_t *CI; /* dummy pointer to board ZEROE's data -
154 * DEBUG USAGE */
155
156
157 void
158 sbecom_set_loglevel (int d)
159 {
160 /*
161 * The code within the following -if- clause is a backdoor debug facility
162 * which can be used to display the state of a board's channel.
163 */
164 if (d > LOG_DEBUG)
165 {
166 unsigned int channum = d - (LOG_DEBUG + 1); /* convert to ZERO
167 * relativity */
168
169 (void) musycc_dump_ring ((ci_t *) CI, channum); /* CI implies support
170 * for card 0 only */
171 } else
172 {
173 if (log_level != d)
174 {
175 pr_info("log level changed from %d to %d\n", log_level, d);
176 log_level = d; /* set new */
177 } else
178 pr_info("log level is %d\n", log_level);
179 }
180 }
181
182
183 mch_t *
184 c4_find_chan (int channum)
185 {
186 ci_t *ci;
187 mch_t *ch;
188 int portnum, gchan;
189
190 for (ci = c4_list; ci; ci = ci->next)
191 for (portnum = 0; portnum < ci->max_port; portnum++)
192 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
193 {
194 if ((ch = ci->port[portnum].chan[gchan]))
195 {
196 if ((ch->state != UNASSIGNED) &&
197 (ch->channum == channum))
198 return (ch);
199 }
200 }
201 return 0;
202 }
203
204
205 ci_t *__init
206 c4_new (void *hi)
207 {
208 ci_t *ci;
209
210 #ifdef SBE_MAP_DEBUG
211 pr_warning("c4_new() entered, ci needs %u.\n",
212 (unsigned int) sizeof (ci_t));
213 #endif
214
215 ci = (ci_t *) OS_kmalloc (sizeof (ci_t));
216 if (ci)
217 {
218 ci->hdw_info = hi;
219 ci->state = C_INIT; /* mark as hardware not available */
220 ci->next = c4_list;
221 c4_list = ci;
222 ci->brdno = ci->next ? ci->next->brdno + 1 : 0;
223 } else
224 pr_warning("failed CI malloc, size %u.\n",
225 (unsigned int) sizeof (ci_t));
226
227 if (CI == 0)
228 CI = ci; /* DEBUG, only board 0 usage */
229 return ci;
230 }
231
232
233 /***
234 * Check port state and set LED states using watchdog or ioctl...
235 * also check for in-band SF loopback commands (& cause results if they are there)
236 *
237 * Alarm function depends on comet bits indicating change in
238 * link status (linkMask) to keep the link status indication straight.
239 *
240 * Indications are only LED and system log -- except when ioctl is invoked.
241 *
242 * "alarmed" record (a.k.a. copyVal, in some cases below) decodes as:
243 *
244 * RMAI (E1 only) 0x100
245 * alarm LED on 0x80
246 * link LED on 0x40
247 * link returned 0x20 (link was down, now it's back and 'port get' hasn't run)
248 * change in LED 0x10 (update LED register because value has changed)
249 * link is down 0x08
250 * YelAlm(RAI) 0x04
251 * RedAlm 0x02
252 * AIS(blue)Alm 0x01
253 *
254 * note "link has returned" indication is reset on read
255 * (e.g. by use of the c4_control port get command)
256 */
257
258 #define sbeLinkMask 0x41 /* change in signal status (lost/recovered) +
259 * state */
260 #define sbeLinkChange 0x40
261 #define sbeLinkDown 0x01
262 #define sbeAlarmsMask 0x07 /* red / yellow / blue alarm conditions */
263 #define sbeE1AlarmsMask 0x107 /* alarm conditions */
264
265 #define COMET_LBCMD_READ 0x80 /* read only (do not set, return read value) */
266
267 void
268 checkPorts (ci_t * ci)
269 {
270 #ifndef CONFIG_SBE_PMCC4_NCOMM
271 /*
272 * PORT POINT - NCOMM needs to avoid this code since the polling of
273 * alarms conflicts with NCOMM's interrupt servicing implementation.
274 */
275
276 comet_t *comet;
277 volatile u_int32_t value;
278 u_int32_t copyVal, LEDval;
279
280 u_int8_t portnum;
281
282 LEDval = 0;
283 for (portnum = 0; portnum < ci->max_port; portnum++)
284 {
285 copyVal = 0x12f & (ci->alarmed[portnum]); /* port's alarm record */
286 comet = ci->port[portnum].cometbase;
287 value = pci_read_32 ((u_int32_t *) &comet->cdrc_ists) & sbeLinkMask; /* link loss reg */
288
289 if (value & sbeLinkChange) /* is there a change in the link stuff */
290 {
291 /* if there's been a change (above) and yet it's the same (below) */
292 if (!(((copyVal >> 3) & sbeLinkDown) ^ (value & sbeLinkDown)))
293 {
294 if (value & sbeLinkDown)
295 pr_warning("%s: Port %d momentarily recovered.\n",
296 ci->devname, portnum);
297 else
298 pr_warning("%s: Warning: Port %d link was briefly down.\n",
299 ci->devname, portnum);
300 } else if (value & sbeLinkDown)
301 pr_warning("%s: Warning: Port %d link is down.\n",
302 ci->devname, portnum);
303 else
304 {
305 pr_warning("%s: Port %d link has recovered.\n",
306 ci->devname, portnum);
307 copyVal |= 0x20; /* record link transition to up */
308 }
309 copyVal |= 0x10; /* change (link) --> update LEDs */
310 }
311 copyVal &= 0x137; /* clear LED & link old history bits &
312 * save others */
313 if (value & sbeLinkDown)
314 copyVal |= 0x08; /* record link status (now) */
315 else
316 { /* if link is up, do this */
317 copyVal |= 0x40; /* LED indicate link is up */
318 /* Alarm things & the like ... first if E1, then if T1 */
319 if (IS_FRAME_ANY_E1 (ci->port[portnum].p.port_mode))
320 {
321 /*
322 * first check Codeword (SaX) changes & CRC and
323 * sub-multi-frame errors
324 */
325 /*
326 * note these errors are printed every time they are detected
327 * vs. alarms
328 */
329 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_nat_ists); /* codeword */
330 if (value & 0x1f)
331 { /* if errors (crc or smf only) */
332 if (value & 0x10)
333 pr_warning("%s: E1 Port %d Codeword Sa4 change detected.\n",
334 ci->devname, portnum);
335 if (value & 0x08)
336 pr_warning("%s: E1 Port %d Codeword Sa5 change detected.\n",
337 ci->devname, portnum);
338 if (value & 0x04)
339 pr_warning("%s: E1 Port %d Codeword Sa6 change detected.\n",
340 ci->devname, portnum);
341 if (value & 0x02)
342 pr_warning("%s: E1 Port %d Codeword Sa7 change detected.\n",
343 ci->devname, portnum);
344 if (value & 0x01)
345 pr_warning("%s: E1 Port %d Codeword Sa8 change detected.\n",
346 ci->devname, portnum);
347 }
348 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_mists); /* crc & smf */
349 if (value & 0x3)
350 { /* if errors (crc or smf only) */
351 if (value & sbeE1CRC)
352 pr_warning("%s: E1 Port %d CRC-4 error(s) detected.\n",
353 ci->devname, portnum);
354 if (value & sbeE1errSMF) /* error in sub-multiframe */
355 pr_warning("%s: E1 Port %d received errored SMF.\n",
356 ci->devname, portnum);
357 }
358 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_masts) & 0xcc; /* alarms */
359 /*
360 * pack alarms together (bitmiser), and construct similar to
361 * T1
362 */
363 /* RAI,RMAI,.,.,LOF,AIS,.,. ==> RMAI,.,.,.,.,.,RAI,LOF,AIS */
364 /* see 0x97 */
365 value = (value >> 2);
366 if (value & 0x30)
367 {
368 if (value & 0x20)
369 value |= 0x40; /* RAI */
370 if (value & 0x10)
371 value |= 0x100; /* RMAI */
372 value &= ~0x30;
373 } /* finished packing alarm in handy order */
374 if (value != (copyVal & sbeE1AlarmsMask))
375 { /* if alarms changed */
376 copyVal |= 0x10;/* change LED status */
377 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
378 {
379 copyVal &= ~sbeRedAlm;
380 pr_warning("%s: E1 Port %d LOF alarm ended.\n",
381 ci->devname, portnum);
382 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
383 {
384 copyVal |= sbeRedAlm;
385 pr_warning("%s: E1 Warning: Port %d LOF alarm.\n",
386 ci->devname, portnum);
387 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
388 {
389 copyVal &= ~sbeYelAlm;
390 pr_warning("%s: E1 Port %d RAI alarm ended.\n",
391 ci->devname, portnum);
392 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
393 {
394 copyVal |= sbeYelAlm;
395 pr_warning("%s: E1 Warning: Port %d RAI alarm.\n",
396 ci->devname, portnum);
397 } else if ((copyVal & sbeE1RMAI) && !(value & sbeE1RMAI))
398 {
399 copyVal &= ~sbeE1RMAI;
400 pr_warning("%s: E1 Port %d RMAI alarm ended.\n",
401 ci->devname, portnum);
402 } else if (!(copyVal & sbeE1RMAI) && (value & sbeE1RMAI))
403 {
404 copyVal |= sbeE1RMAI;
405 pr_warning("%s: E1 Warning: Port %d RMAI alarm.\n",
406 ci->devname, portnum);
407 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
408 {
409 copyVal &= ~sbeAISAlm;
410 pr_warning("%s: E1 Port %d AIS alarm ended.\n",
411 ci->devname, portnum);
412 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
413 {
414 copyVal |= sbeAISAlm;
415 pr_warning("%s: E1 Warning: Port %d AIS alarm.\n",
416 ci->devname, portnum);
417 }
418 }
419 /* end of E1 alarm code */
420 } else
421 { /* if a T1 mode */
422 value = pci_read_32 ((u_int32_t *) &comet->t1_almi_ists); /* alarms */
423 value &= sbeAlarmsMask;
424 if (value != (copyVal & sbeAlarmsMask))
425 { /* if alarms changed */
426 copyVal |= 0x10;/* change LED status */
427 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
428 {
429 copyVal &= ~sbeRedAlm;
430 pr_warning("%s: Port %d red alarm ended.\n",
431 ci->devname, portnum);
432 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
433 {
434 copyVal |= sbeRedAlm;
435 pr_warning("%s: Warning: Port %d red alarm.\n",
436 ci->devname, portnum);
437 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
438 {
439 copyVal &= ~sbeYelAlm;
440 pr_warning("%s: Port %d yellow (RAI) alarm ended.\n",
441 ci->devname, portnum);
442 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
443 {
444 copyVal |= sbeYelAlm;
445 pr_warning("%s: Warning: Port %d yellow (RAI) alarm.\n",
446 ci->devname, portnum);
447 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
448 {
449 copyVal &= ~sbeAISAlm;
450 pr_warning("%s: Port %d blue (AIS) alarm ended.\n",
451 ci->devname, portnum);
452 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
453 {
454 copyVal |= sbeAISAlm;
455 pr_warning("%s: Warning: Port %d blue (AIS) alarm.\n",
456 ci->devname, portnum);
457 }
458 }
459 } /* end T1 mode alarm checks */
460 }
461 if (copyVal & sbeAlarmsMask)
462 copyVal |= 0x80; /* if alarm turn yel LED on */
463 if (copyVal & 0x10)
464 LEDval |= 0x100; /* tag if LED values have changed */
465 LEDval |= ((copyVal & 0xc0) >> (6 - (portnum * 2)));
466
467 ci->alarmed[portnum] &= 0xfffff000; /* out with the old (it's fff
468 * ... foo) */
469 ci->alarmed[portnum] |= (copyVal); /* in with the new */
470
471 /*
472 * enough with the alarms and LED's, now let's check for loopback
473 * requests
474 */
475
476 if (IS_FRAME_ANY_T1 (ci->port[portnum].p.port_mode))
477 { /* if a T1 mode */
478 /*
479 * begin in-band (SF) loopback code detection -- start by reading
480 * command
481 */
482 value = pci_read_32 ((u_int32_t *) &comet->ibcd_ies); /* detect reg. */
483 value &= 0x3; /* trim to handy bits */
484 if (value & 0x2)
485 { /* activate loopback (sets for deactivate
486 * code length) */
487 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
488 * mode */
489 if (copyVal != COMET_MDIAG_LINELB) /* don't do it again if
490 * already in that mode */
491 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
492 * loopback mode */
493 }
494 if (value & 0x1)
495 { /* deactivate loopback (sets for activate
496 * code length) */
497 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
498 * mode */
499 if (copyVal != COMET_MDIAG_LBOFF) /* don't do it again if
500 * already in that mode */
501 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
502 * loopback mode */
503 }
504 }
505 if (IS_FRAME_ANY_T1ESF (ci->port[portnum].p.port_mode))
506 { /* if a T1 ESF mode */
507 /* begin ESF loopback code */
508 value = pci_read_32 ((u_int32_t *) &comet->t1_rboc_sts) & 0x3f; /* read command */
509 if (value == 0x07)
510 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
511 * loopback mode */
512 if (value == 0x0a)
513 c4_loop_port (ci, portnum, COMET_MDIAG_PAYLB); /* put port in payload
514 * loopbk mode */
515 if ((value == 0x1c) || (value == 0x19) || (value == 0x12))
516 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
517 * loopbk mode */
518 if (log_level >= LOG_DEBUG)
519 if (value != 0x3f)
520 pr_warning("%s: BOC value = %x on Port %d\n",
521 ci->devname, value, portnum);
522 /* end ESF loopback code */
523 }
524 }
525
526 /* if something is new, update LED's */
527 if (LEDval & 0x100)
528 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, LEDval & 0xff);
529 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
530 }
531
532
533 STATIC void
534 c4_watchdog (ci_t * ci)
535 {
536 #if 0
537 //unsigned long flags;
538 #endif
539
540 if (drvr_state != SBE_DRVR_AVAILABLE)
541 {
542 if (log_level >= LOG_MONITOR)
543 pr_info("drvr not available (%x)\n", drvr_state);
544 return;
545 }
546 #if 0
547 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
548 * board */
549 #endif
550
551 ci->wdcount++;
552 checkPorts (ci);
553 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,41)
554 if (ci->wd_notify)
555 { /* is there a state change to search for */
556 int port, gchan;
557
558 ci->wd_notify = 0; /* reset notification */
559 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
560 {
561 for (port = 0; port < ci->max_port; port++)
562 {
563 mch_t *ch = ci->port[port].chan[gchan];
564
565 if (!ch || ci->state != C_RUNNING) /* state changed while
566 * acquiring semaphore */
567 break;
568 if (ch->state == UP)/* channel must be set up */
569 {
570 #if 0
571 #ifdef RLD_TRANS_DEBUG
572 if (1 || log_level >= LOG_MONITOR)
573 #else
574 if (log_level >= LOG_MONITOR)
575 #endif
576 pr_info("%s: watchdog reviving Port %d Channel %d [%d] sts %x/%x, start_TX %x free %x start_RX %x\n",
577 ci->devname, ch->channum, port, gchan, ch->channum,
578 ch->p.status, ch->status,
579 ch->ch_start_tx, ch->txd_free, ch->ch_start_rx);
580 #endif
581
582 /**********************************/
583 /** check for RX restart request **/
584 /**********************************/
585
586 if (ch->ch_start_rx &&
587 (ch->status & RX_ENABLED)) /* requires start on
588 * enabled RX */
589 {
590 ch->ch_start_rx = 0; /* we are restarting RX... */
591 #ifdef RLD_TRANS_DEBUG
592 pr_info("++ c4_watchdog() CHAN RX ACTIVATE: chan %d\n",
593 ch->channum);
594 #endif
595 #ifdef RLD_RXACT_DEBUG
596 {
597 struct mdesc *md;
598 static int hereb4 = 7;
599
600 if (hereb4)
601 {
602 hereb4--;
603 md = &ch->mdr[ch->rxix_irq_srv];
604 pr_info("++ c4_watchdog[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
605 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status), ch->s.rx_packets);
606 musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
607 }
608 }
609 #endif
610 musycc_serv_req (ch->up, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
611 }
612 /**********************************/
613 /** check for TX restart request **/
614 /**********************************/
615
616 if (ch->ch_start_tx &&
617 (ch->status & TX_ENABLED)) /* requires start on
618 * enabled TX */
619 {
620 struct mdesc *md;
621
622 /*
623 * find next unprocessed message, then set TX thp to
624 * it
625 */
626 musycc_update_tx_thp (ch);
627
628 #if 0
629 spin_lock_irqsave (&ch->ch_txlock, flags);
630 #endif
631 md = ch->txd_irq_srv;
632 if (!md)
633 {
634 pr_info("-- c4_watchdog[%d]: WARNING, starting NULL md\n",
635 ch->channum);
636 pr_info("-- chan %d txd_irq_srv %p sts %x usr_add %p sts %x, txpkt %lu\n",
637 ch->channum, ch->txd_irq_srv, le32_to_cpu ((struct mdesc *) (ch->txd_irq_srv)->status),
638 ch->txd_usr_add, le32_to_cpu ((struct mdesc *) (ch->txd_usr_add)->status),
639 ch->s.tx_packets);
640 #if 0
641 spin_unlock_irqrestore (&ch->ch_txlock, flags);
642 #endif
643 } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
644 {
645 #ifdef RLD_TRANS_DEBUG
646 pr_info("++ c4_watchdog[%d] CHAN TX ACTIVATE: start_tx %x\n",
647 ch->channum, ch->ch_start_tx);
648 #endif
649 ch->ch_start_tx = 0; /* we are restarting
650 * TX... */
651 #if 0
652 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for
653 * service request */
654 #endif
655 musycc_serv_req (ch->up, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | gchan);
656 #ifdef RLD_TRANS_DEBUG
657 if (1 || log_level >= LOG_MONITOR)
658 #else
659 if (log_level >= LOG_MONITOR)
660 #endif
661 pr_info("++ SACK[P%d/C%d] ack'd, continuing...\n",
662 ch->up->portnum, ch->channum);
663 }
664 }
665 }
666 }
667 }
668 }
669 #else
670 ci->wd_notify = 0;
671 #endif
672 #if 0
673 SD_SEM_GIVE (&ci->sem_wdbusy);/* release per-board hold */
674 #endif
675 }
676
677
678 void
679 c4_cleanup (void)
680 {
681 ci_t *ci, *next;
682 mpi_t *pi;
683 int portnum, j;
684
685 ci = c4_list;
686 while (ci)
687 {
688 next = ci->next; /* protect <next> from upcoming <free> */
689 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
690 for (portnum = 0; portnum < ci->max_port; portnum++)
691 {
692 pi = &ci->port[portnum];
693 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
694 c4_wq_port_cleanup (pi);
695 #endif
696 for (j = 0; j < MUSYCC_NCHANS; j++)
697 {
698 if (pi->chan[j])
699 OS_kfree (pi->chan[j]); /* free mch_t struct */
700 }
701 OS_kfree (pi->regram_saved);
702 }
703 #if 0
704 /* obsolete - watchdog is now static w/in ci_t */
705 OS_free_watchdog (ci->wd);
706 #endif
707 OS_kfree (ci->iqd_p_saved);
708 OS_kfree (ci);
709 ci = next; /* cleanup next board, if any */
710 }
711 }
712
713
714 /*
715 * This function issues a write to all comet chips and expects the same data
716 * to be returned from the subsequent read. This determines the board build
717 * to be a 1-port, 2-port, or 4-port build. The value returned represents a
718 * bit-mask of the found ports. Only certain configurations are considered
719 * VALID or LEGAL builds.
720 */
721
722 int
723 c4_get_portcfg (ci_t * ci)
724 {
725 comet_t *comet;
726 int portnum, mask;
727 u_int32_t wdata, rdata;
728
729 wdata = COMET_MDIAG_LBOFF; /* take port out of any loopback mode */
730
731 mask = 0;
732 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
733 {
734 comet = ci->port[portnum].cometbase;
735 pci_write_32 ((u_int32_t *) &comet->mdiag, wdata);
736 rdata = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
737 if (wdata == rdata)
738 mask |= 1 << portnum;
739 }
740 return mask;
741 }
742
743
744 /* nothing herein should generate interrupts */
745
746 status_t __init
747 c4_init (ci_t * ci, u_char *func0, u_char *func1)
748 {
749 mpi_t *pi;
750 mch_t *ch;
751 static u_int32_t count = 0;
752 int portnum, j;
753
754 ci->state = C_INIT;
755 ci->brdno = count++;
756 ci->intlog.this_status_new = 0;
757 atomic_set (&ci->bh_pending, 0);
758
759 ci->reg = (struct musycc_globalr *) func0;
760 ci->eeprombase = (u_int32_t *) (func1 + EEPROM_OFFSET);
761 ci->cpldbase = (c4cpld_t *) ((u_int32_t *) (func1 + ISPLD_OFFSET));
762
763 /*** PORT POINT - the following is the first access of any type to the hardware ***/
764 #ifdef CONFIG_SBE_PMCC4_NCOMM
765 /* NCOMM driver uses INTB interrupt to monitor CPLD register */
766 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC);
767 #else
768 /* standard driver POLLS for INTB via CPLD register */
769 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
770 #endif
771
772 {
773 int pmsk;
774
775 /* need comet addresses available for determination of hardware build */
776 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
777 {
778 pi = &ci->port[portnum];
779 pi->cometbase = (comet_t *) ((u_int32_t *) (func1 + COMET_OFFSET (portnum)));
780 pi->reg = (struct musycc_globalr *) ((u_char *) ci->reg + (portnum * 0x800));
781 pi->portnum = portnum;
782 pi->p.portnum = portnum;
783 pi->openchans = 0;
784 #ifdef SBE_MAP_DEBUG
785 pr_info("Comet-%d: addr = %p\n", portnum, pi->cometbase);
786 #endif
787 }
788 pmsk = c4_get_portcfg (ci);
789 switch (pmsk)
790 {
791 case 0x1:
792 ci->max_port = 1;
793 break;
794 case 0x3:
795 ci->max_port = 2;
796 break;
797 #if 0
798 case 0x7: /* not built, but could be... */
799 ci->max_port = 3;
800 break;
801 #endif
802 case 0xf:
803 ci->max_port = 4;
804 break;
805 default:
806 ci->max_port = 0;
807 pr_warning("%s: illegal port configuration (%x)\n",
808 ci->devname, pmsk);
809 return SBE_DRVR_FAIL;
810 }
811 #ifdef SBE_MAP_DEBUG
812 pr_info(">> %s: c4_get_build - pmsk %x max_port %x\n",
813 ci->devname, pmsk, ci->max_port);
814 #endif
815 }
816
817 for (portnum = 0; portnum < ci->max_port; portnum++)
818 {
819 pi = &ci->port[portnum];
820 pi->up = ci;
821 pi->sr_last = 0xffffffff;
822 pi->p.port_mode = CFG_FRAME_SF; /* T1 B8ZS, the default */
823 pi->p.portP = (CFG_CLK_PORT_EXTERNAL | CFG_LBO_LH0); /* T1 defaults */
824
825 OS_sem_init (&pi->sr_sem_busy, SEM_AVAILABLE);
826 OS_sem_init (&pi->sr_sem_wait, SEM_TAKEN);
827
828 for (j = 0; j < 32; j++)
829 {
830 pi->fifomap[j] = -1;
831 pi->tsm[j] = 0; /* no assignments, all available */
832 }
833
834 /* allocate channel structures for this port */
835 for (j = 0; j < MUSYCC_NCHANS; j++)
836 {
837 ch = OS_kmalloc (sizeof (mch_t));
838 if (ch)
839 {
840 pi->chan[j] = ch;
841 ch->state = UNASSIGNED;
842 ch->up = pi;
843 ch->gchan = (-1); /* channel assignment not yet known */
844 ch->channum = (-1); /* channel assignment not yet known */
845 ch->p.card = ci->brdno;
846 ch->p.port = portnum;
847 ch->p.channum = (-1); /* channel assignment not yet known */
848 ch->p.mode_56k = 0; /* default is 64kbps mode */
849 } else
850 {
851 pr_warning("failed mch_t malloc, port %d channel %d size %u.\n",
852 portnum, j, (unsigned int) sizeof (mch_t));
853 break;
854 }
855 }
856 }
857
858
859 {
860 /*
861 * Set LEDs through their paces to supply visual proof that LEDs are
862 * functional and not burnt out nor broken.
863 *
864 * YELLOW + GREEN -> OFF.
865 */
866
867 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds,
868 PMCC4_CPLD_LED_GREEN | PMCC4_CPLD_LED_YELLOW);
869 OS_uwait (750000, "leds");
870 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
871 }
872
873 OS_init_watchdog (&ci->wd, (void (*) (void *)) c4_watchdog, ci, WATCHDOG_TIMEOUT);
874 return SBE_DRVR_SUCCESS;
875 }
876
877
878 /* better be fully setup to handle interrupts when you call this */
879
880 status_t __init
881 c4_init2 (ci_t * ci)
882 {
883 status_t ret;
884
885 /* PORT POINT: this routine generates first interrupt */
886 if ((ret = musycc_init (ci)) != SBE_DRVR_SUCCESS)
887 return ret;
888
889 #if 0
890 ci->p.framing_type = FRAMING_CBP;
891 ci->p.h110enable = 1;
892 #if 0
893 ci->p.hypersize = 0;
894 #else
895 hyperdummy = 0;
896 #endif
897 ci->p.clock = 0; /* Use internal clocking until set to
898 * external */
899 c4_card_set_params (ci, &ci->p);
900 #endif
901 OS_start_watchdog (&ci->wd);
902 return SBE_DRVR_SUCCESS;
903 }
904
905
906 /* This function sets the loopback mode (or clears it, as the case may be). */
907
908 int
909 c4_loop_port (ci_t * ci, int portnum, u_int8_t cmd)
910 {
911 comet_t *comet;
912 volatile u_int32_t loopValue;
913
914 comet = ci->port[portnum].cometbase;
915 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
916
917 if (cmd & COMET_LBCMD_READ)
918 return loopValue; /* return the read value */
919
920 if (loopValue != cmd)
921 {
922 switch (cmd)
923 {
924 case COMET_MDIAG_LINELB:
925 /* set(SF)loopback down (turn off) code length to 6 bits */
926 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x05);
927 break;
928 case COMET_MDIAG_LBOFF:
929 /* set (SF) loopback up (turn on) code length to 5 bits */
930 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x00);
931 break;
932 }
933
934 pci_write_32 ((u_int32_t *) &comet->mdiag, cmd);
935 if (log_level >= LOG_WARN)
936 pr_info("%s: loopback mode changed to %2x from %2x on Port %d\n",
937 ci->devname, cmd, loopValue, portnum);
938 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
939 if (loopValue != cmd)
940 {
941 if (log_level >= LOG_ERROR)
942 pr_info("%s: write to loop register failed, unknown state for Port %d\n",
943 ci->devname, portnum);
944 }
945 } else
946 {
947 if (log_level >= LOG_WARN)
948 pr_info("%s: loopback already in that mode (%2x)\n",
949 ci->devname, loopValue);
950 }
951 return 0;
952 }
953
954
955 /* c4_frame_rw: read or write the comet register specified
956 * (modifies use of port_param to non-standard use of struct)
957 * Specifically:
958 * pp.portnum (one guess)
959 * pp.port_mode offset of register
960 * pp.portP write (or not, i.e. read)
961 * pp.portStatus write value
962 * BTW:
963 * pp.portStatus also used to return read value
964 * pp.portP also used during write, to return old reg value
965 */
966
967 status_t
968 c4_frame_rw (ci_t * ci, struct sbecom_port_param * pp)
969 {
970 comet_t *comet;
971 volatile u_int32_t data;
972
973 if (pp->portnum >= ci->max_port)/* sanity check */
974 return ENXIO;
975
976 comet = ci->port[pp->portnum].cometbase;
977 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
978
979 if (pp->portP)
980 { /* control says this is a register
981 * _write_ */
982 if (pp->portStatus == data)
983 pr_info("%s: Port %d already that value! Writing again anyhow.\n",
984 ci->devname, pp->portnum);
985 pp->portP = (u_int8_t) data;
986 pci_write_32 ((u_int32_t *) comet + pp->port_mode,
987 pp->portStatus);
988 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
989 }
990 pp->portStatus = (u_int8_t) data;
991 return 0;
992 }
993
994
995 /* c4_pld_rw: read or write the pld register specified
996 * (modifies use of port_param to non-standard use of struct)
997 * Specifically:
998 * pp.port_mode offset of register
999 * pp.portP write (or not, i.e. read)
1000 * pp.portStatus write value
1001 * BTW:
1002 * pp.portStatus also used to return read value
1003 * pp.portP also used during write, to return old reg value
1004 */
1005
1006 status_t
1007 c4_pld_rw (ci_t * ci, struct sbecom_port_param * pp)
1008 {
1009 volatile u_int32_t *regaddr;
1010 volatile u_int32_t data;
1011 int regnum = pp->port_mode;
1012
1013 regaddr = (u_int32_t *) ci->cpldbase + regnum;
1014 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
1015
1016 if (pp->portP)
1017 { /* control says this is a register
1018 * _write_ */
1019 pp->portP = (u_int8_t) data;
1020 pci_write_32 ((u_int32_t *) regaddr, pp->portStatus);
1021 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
1022 }
1023 pp->portStatus = (u_int8_t) data;
1024 return 0;
1025 }
1026
1027 /* c4_musycc_rw: read or write the musycc register specified
1028 * (modifies use of port_param to non-standard use of struct)
1029 * Specifically:
1030 * mcp.RWportnum port number and write indication bit (0x80)
1031 * mcp.offset offset of register
1032 * mcp.value write value going in and read value returning
1033 */
1034
1035 /* PORT POINT: TX Subchannel Map registers are write-only
1036 * areas within the MUSYCC and always return FF */
1037 /* PORT POINT: regram and reg structures are minorly different and <offset> ioctl
1038 * settings are aligned with the <reg> struct musycc_globalr{} usage.
1039 * Also, regram is separately allocated shared memory, allocated for each port.
1040 * PORT POINT: access offsets of 0x6000 for Msg Cfg Desc Tbl are for 4-port MUSYCC
1041 * only. (An 8-port MUSYCC has 0x16000 offsets for accessing its upper 4 tables.)
1042 */
1043
1044 status_t
1045 c4_musycc_rw (ci_t * ci, struct c4_musycc_param * mcp)
1046 {
1047 mpi_t *pi;
1048 volatile u_int32_t *dph; /* hardware implemented register */
1049 u_int32_t *dpr = 0; /* RAM image of registers for group command
1050 * usage */
1051 int offset = mcp->offset % 0x800; /* group relative address
1052 * offset, mcp->portnum is
1053 * not used */
1054 int portnum, ramread = 0;
1055 volatile u_int32_t data;
1056
1057 /*
1058 * Sanity check hardware accessibility. The 0x6000 portion handles port
1059 * numbers associated with Msg Descr Tbl decoding.
1060 */
1061 portnum = (mcp->offset % 0x6000) / 0x800;
1062 if (portnum >= ci->max_port)
1063 return ENXIO;
1064 pi = &ci->port[portnum];
1065 if (mcp->offset >= 0x6000)
1066 offset += 0x6000; /* put back in MsgCfgDesc address offset */
1067 dph = (u_int32_t *) ((u_long) pi->reg + offset);
1068
1069 /* read of TX are from RAM image, since hardware returns FF */
1070 dpr = (u_int32_t *) ((u_long) pi->regram + offset);
1071 if (mcp->offset < 0x6000) /* non MsgDesc Tbl accesses might require
1072 * RAM access */
1073 {
1074 if (offset >= 0x200 && offset < 0x380)
1075 ramread = 1;
1076 if (offset >= 0x10 && offset < 0x200)
1077 ramread = 1;
1078 }
1079 /* read register from RAM or hardware, depending... */
1080 if (ramread)
1081 {
1082 data = *dpr;
1083 //pr_info("c4_musycc_rw: RAM addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dpr, data, portnum, offset, ramread); /* RLD DEBUG */
1084 } else
1085 {
1086 data = pci_read_32 ((u_int32_t *) dph);
1087 //pr_info("c4_musycc_rw: REG addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dph, data, portnum, offset, ramread); /* RLD DEBUG */
1088 }
1089
1090
1091 if (mcp->RWportnum & 0x80)
1092 { /* control says this is a register
1093 * _write_ */
1094 if (mcp->value == data)
1095 pr_info("%s: musycc grp%d already that value! writing again anyhow.\n",
1096 ci->devname, (mcp->RWportnum & 0x7));
1097 /* write register RAM */
1098 if (ramread)
1099 *dpr = mcp->value;
1100 /* write hardware register */
1101 pci_write_32 ((u_int32_t *) dph, mcp->value);
1102 }
1103 mcp->value = data; /* return the read value (or the 'old
1104 * value', if is write) */
1105 return 0;
1106 }
1107
1108 status_t
1109 c4_get_port (ci_t * ci, int portnum)
1110 {
1111 if (portnum >= ci->max_port) /* sanity check */
1112 return ENXIO;
1113
1114 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
1115 * board */
1116 checkPorts (ci);
1117 ci->port[portnum].p.portStatus = (u_int8_t) ci->alarmed[portnum];
1118 ci->alarmed[portnum] &= 0xdf;
1119 SD_SEM_GIVE (&ci->sem_wdbusy); /* release per-board hold */
1120 return 0;
1121 }
1122
1123 status_t
1124 c4_set_port (ci_t * ci, int portnum)
1125 {
1126 mpi_t *pi;
1127 struct sbecom_port_param *pp;
1128 int e1mode;
1129 u_int8_t clck;
1130 int i;
1131
1132 if (portnum >= ci->max_port) /* sanity check */
1133 return ENXIO;
1134
1135 pi = &ci->port[portnum];
1136 pp = &ci->port[portnum].p;
1137 e1mode = IS_FRAME_ANY_E1 (pp->port_mode);
1138 if (log_level >= LOG_MONITOR2)
1139 {
1140 pr_info("%s: c4_set_port[%d]: entered, e1mode = %x, openchans %d.\n",
1141 ci->devname,
1142 portnum, e1mode, pi->openchans);
1143 }
1144 if (pi->openchans)
1145 return EBUSY; /* group needs initialization only for
1146 * first channel of a group */
1147
1148 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
1149 {
1150 status_t ret;
1151
1152 if ((ret = c4_wq_port_init (pi))) /* create/init
1153 * workqueue_struct */
1154 return (ret);
1155 }
1156 #endif
1157
1158 init_comet (ci, pi->cometbase, pp->port_mode, 1 /* clockmaster == true */ , pp->portP);
1159 clck = pci_read_32 ((u_int32_t *) &ci->cpldbase->mclk) & PMCC4_CPLD_MCLK_MASK;
1160 if (e1mode)
1161 clck |= 1 << portnum;
1162 else
1163 clck &= 0xf ^ (1 << portnum);
1164
1165 pci_write_32 ((u_int32_t *) &ci->cpldbase->mclk, clck);
1166 pci_write_32 ((u_int32_t *) &ci->cpldbase->mcsr, PMCC4_CPLD_MCSR_IND);
1167 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
1168
1169 /*********************************************************************/
1170 /* ERRATA: If transparent mode is used, do not set OOFMP_DISABLE bit */
1171 /*********************************************************************/
1172
1173 pi->regram->grcd =
1174 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
1175 MUSYCC_GRCD_TX_ENABLE |
1176 MUSYCC_GRCD_OOFMP_DISABLE |
1177 MUSYCC_GRCD_SF_ALIGN | /* per MUSYCC ERRATA,
1178 * for T1 * fix */
1179 MUSYCC_GRCD_COFAIRQ_DISABLE |
1180 MUSYCC_GRCD_MC_ENABLE |
1181 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
1182
1183 pi->regram->pcd =
1184 __constant_cpu_to_le32 ((e1mode ? 1 : 0) |
1185 MUSYCC_PCD_TXSYNC_RISING |
1186 MUSYCC_PCD_RXSYNC_RISING |
1187 MUSYCC_PCD_RXDATA_RISING);
1188
1189 /* Message length descriptor */
1190 pi->regram->mld = __constant_cpu_to_le32 (max_mru | (max_mru << 16));
1191
1192 /* tsm algorithm */
1193 for (i = 0; i < 32; i++)
1194 {
1195
1196 /*** ASSIGNMENT NOTES: ***/
1197 /*** Group's channel ZERO unavailable if E1. ***/
1198 /*** Group's channel 16 unavailable if E1 CAS. ***/
1199 /*** Group's channels 24-31 unavailable if T1. ***/
1200
1201 if (((i == 0) && e1mode) ||
1202 ((i == 16) && ((pp->port_mode == CFG_FRAME_E1CRC_CAS) || (pp->port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
1203 || ((i > 23) && (!e1mode)))
1204 {
1205 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
1206 } else
1207 {
1208 pi->tsm[i] = 0x00; /* make tslot available for assignment */
1209 }
1210 }
1211 for (i = 0; i < MUSYCC_NCHANS; i++)
1212 {
1213 pi->regram->ttsm[i] = 0;
1214 pi->regram->rtsm[i] = 0;
1215 }
1216 FLUSH_MEM_WRITE ();
1217 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
1218 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
1219
1220 musycc_init_mdt (pi);
1221
1222 pi->group_is_set = 1;
1223 pi->p = *pp;
1224 return 0;
1225 }
1226
1227
1228 unsigned int max_int = 0;
1229
1230 status_t
1231 c4_new_chan (ci_t * ci, int portnum, int channum, void *user)
1232 {
1233 mpi_t *pi;
1234 mch_t *ch;
1235 int gchan;
1236
1237 if (c4_find_chan (channum)) /* a new channel shouldn't already exist */
1238 return EEXIST;
1239
1240 if (portnum >= ci->max_port) /* sanity check */
1241 return ENXIO;
1242
1243 pi = &(ci->port[portnum]);
1244 /* find any available channel within this port */
1245 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
1246 {
1247 ch = pi->chan[gchan];
1248 if (ch && ch->state == UNASSIGNED) /* no assignment is good! */
1249 break;
1250 }
1251 if (gchan == MUSYCC_NCHANS) /* exhausted table, all were assigned */
1252 return ENFILE;
1253
1254 ch->up = pi;
1255
1256 /* NOTE: mch_t already cleared during OS_kmalloc() */
1257 ch->state = DOWN;
1258 ch->user = user;
1259 ch->gchan = gchan;
1260 ch->channum = channum; /* mark our channel assignment */
1261 ch->p.channum = channum;
1262 #if 1
1263 ch->p.card = ci->brdno;
1264 ch->p.port = portnum;
1265 #endif
1266 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1267 ch->p.idlecode = CFG_CH_FLAG_7E;
1268 ch->p.pad_fill_count = 2;
1269 spin_lock_init (&ch->ch_rxlock);
1270 spin_lock_init (&ch->ch_txlock);
1271
1272 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
1273 {
1274 status_t ret;
1275
1276 if ((ret = c4_wk_chan_init (pi, ch)))
1277 return ret;
1278 }
1279 #endif
1280
1281 /* save off interface assignments which bound a board */
1282 if (ci->first_if == 0) /* first channel registered is assumed to
1283 * be the lowest channel */
1284 {
1285 ci->first_if = ci->last_if = user;
1286 ci->first_channum = ci->last_channum = channum;
1287 } else
1288 {
1289 ci->last_if = user;
1290 if (ci->last_channum < channum) /* higher number channel found */
1291 ci->last_channum = channum;
1292 }
1293 return 0;
1294 }
1295
1296 status_t
1297 c4_del_chan (int channum)
1298 {
1299 mch_t *ch;
1300
1301 if (!(ch = c4_find_chan (channum)))
1302 return ENOENT;
1303 if (ch->state == UP)
1304 musycc_chan_down ((ci_t *) 0, channum);
1305 ch->state = UNASSIGNED;
1306 ch->gchan = (-1);
1307 ch->channum = (-1);
1308 ch->p.channum = (-1);
1309 return 0;
1310 }
1311
1312 status_t
1313 c4_del_chan_stats (int channum)
1314 {
1315 mch_t *ch;
1316
1317 if (!(ch = c4_find_chan (channum)))
1318 return ENOENT;
1319
1320 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1321 return 0;
1322 }
1323
1324
1325 status_t
1326 c4_set_chan (int channum, struct sbecom_chan_param * p)
1327 {
1328 mch_t *ch;
1329 int i, x = 0;
1330
1331 if (!(ch = c4_find_chan (channum)))
1332 return ENOENT;
1333
1334 #if 1
1335 if (ch->p.card != p->card ||
1336 ch->p.port != p->port ||
1337 ch->p.channum != p->channum)
1338 return EINVAL;
1339 #endif
1340
1341 if (!(ch->up->group_is_set))
1342 {
1343 return EIO; /* out of order, SET_PORT command
1344 * required prior to first group's
1345 * SET_CHAN command */
1346 }
1347 /*
1348 * Check for change of parameter settings in order to invoke closing of
1349 * channel prior to hardware poking.
1350 */
1351
1352 if (ch->p.status != p->status || ch->p.chan_mode != p->chan_mode ||
1353 ch->p.data_inv != p->data_inv || ch->p.intr_mask != p->intr_mask ||
1354 ch->txd_free < ch->txd_num) /* to clear out queued messages */
1355 x = 1; /* we have a change requested */
1356 for (i = 0; i < 32; i++) /* check for timeslot mapping changes */
1357 if (ch->p.bitmask[i] != p->bitmask[i])
1358 x = 1; /* we have a change requested */
1359 ch->p = *p;
1360 if (x && (ch->state == UP)) /* if change request and channel is
1361 * open... */
1362 {
1363 status_t ret;
1364
1365 if ((ret = musycc_chan_down ((ci_t *) 0, channum)))
1366 return ret;
1367 if ((ret = c4_chan_up (ch->up->up, channum)))
1368 return ret;
1369 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1370 * channel */
1371 }
1372 return 0;
1373 }
1374
1375
1376 status_t
1377 c4_get_chan (int channum, struct sbecom_chan_param * p)
1378 {
1379 mch_t *ch;
1380
1381 if (!(ch = c4_find_chan (channum)))
1382 return ENOENT;
1383 *p = ch->p;
1384 return 0;
1385 }
1386
1387 status_t
1388 c4_get_chan_stats (int channum, struct sbecom_chan_stats * p)
1389 {
1390 mch_t *ch;
1391
1392 if (!(ch = c4_find_chan (channum)))
1393 return ENOENT;
1394 *p = ch->s;
1395 p->tx_pending = atomic_read (&ch->tx_pending);
1396 return 0;
1397 }
1398
1399 STATIC int
1400 c4_fifo_alloc (mpi_t * pi, int chan, int *len)
1401 {
1402 int i, l = 0, start = 0, max = 0, maxstart = 0;
1403
1404 for (i = 0; i < 32; i++)
1405 {
1406 if (pi->fifomap[i] != -1)
1407 {
1408 l = 0;
1409 start = i + 1;
1410 continue;
1411 }
1412 ++l;
1413 if (l > max)
1414 {
1415 max = l;
1416 maxstart = start;
1417 }
1418 if (max == *len)
1419 break;
1420 }
1421 if (max != *len)
1422 {
1423 if (log_level >= LOG_WARN)
1424 pr_info("%s: wanted to allocate %d fifo space, but got only %d\n",
1425 pi->up->devname, *len, max);
1426 *len = max;
1427 }
1428 if (log_level >= LOG_DEBUG)
1429 pr_info("%s: allocated %d fifo at %d for channel %d/%d\n",
1430 pi->up->devname, max, start, chan, pi->p.portnum);
1431 for (i = maxstart; i < (maxstart + max); i++)
1432 pi->fifomap[i] = chan;
1433 return start;
1434 }
1435
1436 void
1437 c4_fifo_free (mpi_t * pi, int chan)
1438 {
1439 int i;
1440
1441 if (log_level >= LOG_DEBUG)
1442 pr_info("%s: deallocated fifo for channel %d/%d\n",
1443 pi->up->devname, chan, pi->p.portnum);
1444 for (i = 0; i < 32; i++)
1445 if (pi->fifomap[i] == chan)
1446 pi->fifomap[i] = -1;
1447 }
1448
1449
1450 status_t
1451 c4_chan_up (ci_t * ci, int channum)
1452 {
1453 mpi_t *pi;
1454 mch_t *ch;
1455 struct mbuf *m;
1456 struct mdesc *md;
1457 int nts, nbuf, txnum, rxnum;
1458 int addr, i, j, gchan;
1459 u_int32_t tmp; /* for optimizing conversion across BE
1460 * platform */
1461
1462 if (!(ch = c4_find_chan (channum)))
1463 return ENOENT;
1464 if (ch->state == UP)
1465 {
1466 if (log_level >= LOG_MONITOR)
1467 pr_info("%s: channel already UP, graceful early exit\n",
1468 ci->devname);
1469 return 0;
1470 }
1471 pi = ch->up;
1472 gchan = ch->gchan;
1473 /* find nts ('number of timeslots') */
1474 nts = 0;
1475 for (i = 0; i < 32; i++)
1476 {
1477 if (ch->p.bitmask[i] & pi->tsm[i])
1478 {
1479 if (1 || log_level >= LOG_WARN)
1480 {
1481 pr_info("%s: c4_chan_up[%d] EINVAL (attempt to cfg in-use or unavailable TimeSlot[%d])\n",
1482 ci->devname, channum, i);
1483 pr_info("+ ask4 %x, currently %x\n",
1484 ch->p.bitmask[i], pi->tsm[i]);
1485 }
1486 return EINVAL;
1487 }
1488 for (j = 0; j < 8; j++)
1489 if (ch->p.bitmask[i] & (1 << j))
1490 nts++;
1491 }
1492
1493 nbuf = nts / 8 ? nts / 8 : 1;
1494 if (!nbuf)
1495 {
1496 /* if( log_level >= LOG_WARN) */
1497 pr_info("%s: c4_chan_up[%d] ENOBUFS (no TimeSlots assigned)\n",
1498 ci->devname, channum);
1499 return ENOBUFS; /* this should not happen */
1500 }
1501 addr = c4_fifo_alloc (pi, gchan, &nbuf);
1502 ch->state = UP;
1503
1504 /* Setup the Time Slot Map */
1505 musycc_update_timeslots (pi);
1506
1507 /* ch->tx_limit = nts; */
1508 ch->s.tx_pending = 0;
1509
1510 /* Set Channel Configuration Descriptors */
1511 {
1512 u_int32_t ccd;
1513
1514 ccd = musycc_chan_proto (ch->p.chan_mode) << MUSYCC_CCD_PROTO_SHIFT;
1515 if ((ch->p.chan_mode == CFG_CH_PROTO_ISLP_MODE) ||
1516 (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1517 {
1518 ccd |= MUSYCC_CCD_FCS_XFER; /* Non FSC Mode */
1519 }
1520 ccd |= 2 << MUSYCC_CCD_MAX_LENGTH; /* Select second MTU */
1521 ccd |= ch->p.intr_mask;
1522 ccd |= addr << MUSYCC_CCD_BUFFER_LOC;
1523 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1524 ccd |= (nbuf) << MUSYCC_CCD_BUFFER_LENGTH;
1525 else
1526 ccd |= (nbuf - 1) << MUSYCC_CCD_BUFFER_LENGTH;
1527
1528 if (ch->p.data_inv & CFG_CH_DINV_TX)
1529 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1530 pi->regram->tcct[gchan] = cpu_to_le32 (ccd);
1531
1532 if (ch->p.data_inv & CFG_CH_DINV_RX)
1533 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1534 else
1535 ccd &= ~MUSYCC_CCD_INVERT_DATA; /* take away data inversion */
1536 pi->regram->rcct[gchan] = cpu_to_le32 (ccd);
1537 FLUSH_MEM_WRITE ();
1538 }
1539
1540 /* Reread the Channel Configuration Descriptor for this channel */
1541 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_RX_DIRECTION | gchan);
1542 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_TX_DIRECTION | gchan);
1543
1544 /*
1545 * Figure out how many buffers we want. If the customer has changed from
1546 * the defaults, then use the changed values. Otherwise, use Transparent
1547 * mode's specific minimum default settings.
1548 */
1549 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1550 {
1551 if (max_rxdesc_used == max_rxdesc_default) /* use default setting */
1552 max_rxdesc_used = MUSYCC_RXDESC_TRANS;
1553 if (max_txdesc_used == max_txdesc_default) /* use default setting */
1554 max_txdesc_used = MUSYCC_TXDESC_TRANS;
1555 }
1556 /*
1557 * Increase counts when hyperchanneling, since this implies an increase
1558 * in throughput per channel
1559 */
1560 rxnum = max_rxdesc_used + (nts / 4);
1561 txnum = max_txdesc_used + (nts / 4);
1562
1563 #if 0
1564 /* DEBUG INFO */
1565 if (log_level >= LOG_MONITOR)
1566 pr_info("%s: mode %x rxnum %d (rxused %d def %d) txnum %d (txused %d def %d)\n",
1567 ci->devname, ch->p.chan_mode,
1568 rxnum, max_rxdesc_used, max_rxdesc_default,
1569 txnum, max_txdesc_used, max_txdesc_default);
1570 #endif
1571
1572 ch->rxd_num = rxnum;
1573 ch->txd_num = txnum;
1574 ch->rxix_irq_srv = 0;
1575
1576 ch->mdr = OS_kmalloc (sizeof (struct mdesc) * rxnum);
1577 ch->mdt = OS_kmalloc (sizeof (struct mdesc) * txnum);
1578 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1579 tmp = __constant_cpu_to_le32 (max_mru | EOBIRQ_ENABLE);
1580 else
1581 tmp = __constant_cpu_to_le32 (max_mru);
1582
1583 for (i = 0, md = ch->mdr; i < rxnum; i++, md++)
1584 {
1585 if (i == (rxnum - 1))
1586 {
1587 md->snext = &ch->mdr[0];/* wrapness */
1588 } else
1589 {
1590 md->snext = &ch->mdr[i + 1];
1591 }
1592 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1593
1594 if (!(m = OS_mem_token_alloc (max_mru)))
1595 {
1596 if (log_level >= LOG_MONITOR)
1597 pr_info("%s: c4_chan_up[%d] - token alloc failure, size = %d.\n",
1598 ci->devname, channum, max_mru);
1599 goto errfree;
1600 }
1601 md->mem_token = m;
1602 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m)));
1603 md->status = tmp | MUSYCC_RX_OWNED; /* MUSYCC owns RX descriptor **
1604 * CODING NOTE:
1605 * MUSYCC_RX_OWNED = 0 so no
1606 * need to byteSwap */
1607 }
1608
1609 for (i = 0, md = ch->mdt; i < txnum; i++, md++)
1610 {
1611 md->status = HOST_TX_OWNED; /* Host owns TX descriptor ** CODING
1612 * NOTE: HOST_TX_OWNED = 0 so no need to
1613 * byteSwap */
1614 md->mem_token = 0;
1615 md->data = 0;
1616 if (i == (txnum - 1))
1617 {
1618 md->snext = &ch->mdt[0];/* wrapness */
1619 } else
1620 {
1621 md->snext = &ch->mdt[i + 1];
1622 }
1623 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1624 }
1625 ch->txd_irq_srv = ch->txd_usr_add = &ch->mdt[0];
1626 ch->txd_free = txnum;
1627 ch->tx_full = 0;
1628 ch->txd_required = 0;
1629
1630 /* Configure it into the chip */
1631 tmp = cpu_to_le32 (OS_vtophys (&ch->mdt[0]));
1632 pi->regram->thp[gchan] = tmp;
1633 pi->regram->tmp[gchan] = tmp;
1634
1635 tmp = cpu_to_le32 (OS_vtophys (&ch->mdr[0]));
1636 pi->regram->rhp[gchan] = tmp;
1637 pi->regram->rmp[gchan] = tmp;
1638
1639 /* Activate the Channel */
1640 FLUSH_MEM_WRITE ();
1641 if (ch->p.status & RX_ENABLED)
1642 {
1643 #ifdef RLD_TRANS_DEBUG
1644 pr_info("++ c4_chan_up() CHAN RX ACTIVATE: chan %d\n", ch->channum);
1645 #endif
1646 ch->ch_start_rx = 0; /* we are restarting RX... */
1647 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
1648 }
1649 if (ch->p.status & TX_ENABLED)
1650 {
1651 #ifdef RLD_TRANS_DEBUG
1652 pr_info("++ c4_chan_up() CHAN TX ACTIVATE: chan %d <delayed>\n", ch->channum);
1653 #endif
1654 ch->ch_start_tx = CH_START_TX_1ST; /* we are delaying start
1655 * until receipt from user of
1656 * first packet to transmit. */
1657 }
1658 ch->status = ch->p.status;
1659 pi->openchans++;
1660 return 0;
1661
1662 errfree:
1663 while (i > 0)
1664 {
1665 /* Don't leak all the previously allocated mbufs in this loop */
1666 i--;
1667 OS_mem_token_free (ch->mdr[i].mem_token);
1668 }
1669 OS_kfree (ch->mdt);
1670 ch->mdt = 0;
1671 ch->txd_num = 0;
1672 OS_kfree (ch->mdr);
1673 ch->mdr = 0;
1674 ch->rxd_num = 0;
1675 ch->state = DOWN;
1676 return ENOBUFS;
1677 }
1678
1679 /* stop the hardware from servicing & interrupting */
1680
1681 void
1682 c4_stopwd (ci_t * ci)
1683 {
1684 OS_stop_watchdog (&ci->wd);
1685 SD_SEM_TAKE (&ci->sem_wdbusy, "_stop_"); /* ensure WD not running */
1686 SD_SEM_GIVE (&ci->sem_wdbusy);
1687 }
1688
1689
1690 void
1691 sbecom_get_brdinfo (ci_t * ci, struct sbe_brd_info * bip, u_int8_t *bsn)
1692 {
1693 char *np;
1694 u_int32_t sn = 0;
1695 int i;
1696
1697 bip->brdno = ci->brdno; /* our board number */
1698 bip->brd_id = ci->brd_id;
1699 bip->brd_hdw_id = ci->hdw_bid;
1700 bip->brd_chan_cnt = MUSYCC_NCHANS * ci->max_port; /* number of channels
1701 * being used */
1702 bip->brd_port_cnt = ci->max_port; /* number of ports being used */
1703 bip->brd_pci_speed = BINFO_PCI_SPEED_unk; /* PCI speed not yet
1704 * determinable */
1705
1706 if (ci->first_if)
1707 {
1708 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1709 np = (char *) hdlc_to_name (ci->first_if);
1710 #else
1711 {
1712 struct net_device *dev;
1713
1714 dev = (struct net_device *) ci->first_if;
1715 np = (char *) dev->name;
1716 }
1717 #endif
1718 strncpy (bip->first_iname, np, CHNM_STRLEN - 1);
1719 } else
1720 strcpy (bip->first_iname, "<NULL>");
1721 if (ci->last_if)
1722 {
1723 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1724 np = (char *) hdlc_to_name (ci->last_if);
1725 #else
1726 {
1727 struct net_device *dev;
1728
1729 dev = (struct net_device *) ci->last_if;
1730 np = (char *) dev->name;
1731 }
1732 #endif
1733 strncpy (bip->last_iname, np, CHNM_STRLEN - 1);
1734 } else
1735 strcpy (bip->last_iname, "<NULL>");
1736
1737 if (bsn)
1738 {
1739 for (i = 0; i < 3; i++)
1740 {
1741 bip->brd_mac_addr[i] = *bsn++;
1742 }
1743 for (; i < 6; i++)
1744 {
1745 bip->brd_mac_addr[i] = *bsn;
1746 sn = (sn << 8) | *bsn++;
1747 }
1748 } else
1749 {
1750 for (i = 0; i < 6; i++)
1751 bip->brd_mac_addr[i] = 0;
1752 }
1753 bip->brd_sn = sn;
1754 }
1755
1756
1757 status_t
1758 c4_get_iidinfo (ci_t * ci, struct sbe_iid_info * iip)
1759 {
1760 struct net_device *dev;
1761 char *np;
1762
1763 if (!(dev = getuserbychan (iip->channum)))
1764 return ENOENT;
1765
1766 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1767 np = (char *) hdlc_to_name (dev_to_hdlc (dev));
1768 #else
1769 np = dev->name;
1770 #endif
1771 strncpy (iip->iname, np, CHNM_STRLEN - 1);
1772 return 0;
1773 }
1774
1775
1776 #ifdef CONFIG_SBE_PMCC4_NCOMM
1777 void (*nciInterrupt[MAX_BOARDS][4]) (void);
1778 extern void wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler);
1779
1780 void
1781 wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler)
1782 {
1783 if (cardID < MAX_BOARDS) /* sanity check */
1784 nciInterrupt[cardID][deviceID] = handler;
1785 }
1786
1787 irqreturn_t
1788 c4_ebus_intr_th_handler (void *devp)
1789 {
1790 ci_t *ci = (ci_t *) devp;
1791 volatile u_int32_t ists;
1792 int handled = 0;
1793 int brdno;
1794
1795 /* which COMET caused the interrupt */
1796 brdno = ci->brdno;
1797 ists = pci_read_32 ((u_int32_t *) &ci->cpldbase->intr);
1798 if (ists & PMCC4_CPLD_INTR_CMT_1)
1799 {
1800 handled = 0x1;
1801 if (nciInterrupt[brdno][0] != NULL)
1802 (*nciInterrupt[brdno][0]) ();
1803 }
1804 if (ists & PMCC4_CPLD_INTR_CMT_2)
1805 {
1806 handled |= 0x2;
1807 if (nciInterrupt[brdno][1] != NULL)
1808 (*nciInterrupt[brdno][1]) ();
1809 }
1810 if (ists & PMCC4_CPLD_INTR_CMT_3)
1811 {
1812 handled |= 0x4;
1813 if (nciInterrupt[brdno][2] != NULL)
1814 (*nciInterrupt[brdno][2]) ();
1815 }
1816 if (ists & PMCC4_CPLD_INTR_CMT_4)
1817 {
1818 handled |= 0x8;
1819 if (nciInterrupt[brdno][3] != NULL)
1820 (*nciInterrupt[brdno][3]) ();
1821 }
1822 #if 0
1823 /*** Test code just de-implements the asserted interrupt. Alternate
1824 vendor will supply COMET interrupt handling code herein or such.
1825 ***/
1826 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
1827 #endif
1828
1829 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,20)
1830 return;
1831 #else
1832 return IRQ_RETVAL (handled);
1833 #endif
1834 }
1835
1836
1837 unsigned long
1838 wanpmcC4T1E1_getBaseAddress (int cardID, int deviceID)
1839 {
1840 ci_t *ci;
1841 unsigned long base = 0;
1842
1843 ci = c4_list;
1844 while (ci)
1845 {
1846 if (ci->brdno == cardID) /* found valid device */
1847 {
1848 if (deviceID < ci->max_port) /* comet is supported */
1849 base = ((unsigned long) ci->port[deviceID].cometbase);
1850 break;
1851 }
1852 ci = ci->next; /* next board, if any */
1853 }
1854 return (base);
1855 }
1856
1857 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
1858
1859
1860 /*** End-of-File ***/
kernel source for telekom puls (alcatel/mediatek)